WO2022133729A1 - 移位寄存器、栅极驱动电路、显示面板及其驱动方法 - Google Patents

移位寄存器、栅极驱动电路、显示面板及其驱动方法 Download PDF

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Publication number
WO2022133729A1
WO2022133729A1 PCT/CN2020/138322 CN2020138322W WO2022133729A1 WO 2022133729 A1 WO2022133729 A1 WO 2022133729A1 CN 2020138322 W CN2020138322 W CN 2020138322W WO 2022133729 A1 WO2022133729 A1 WO 2022133729A1
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Prior art keywords
signal terminal
shift register
pull
transistor
control
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PCT/CN2020/138322
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English (en)
French (fr)
Inventor
王珍
张健
孙建
闫伟
王德帅
秦文文
王继国
张寒
山岳
杨小艳
张亚东
王世君
刘建涛
Original Assignee
京东方科技集团股份有限公司
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Priority to PCT/CN2020/138322 priority Critical patent/WO2022133729A1/zh
Priority to CN202080003514.6A priority patent/CN115244603A/zh
Priority to US17/593,953 priority patent/US11875727B2/en
Priority to DE112020007346.7T priority patent/DE112020007346T5/de
Publication of WO2022133729A1 publication Critical patent/WO2022133729A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register, a gate driving circuit, a display panel and a driving method thereof.
  • a gate driving circuit is usually used to drive a plurality of sub-pixels for display.
  • the gate driving circuit in the display device is powered on, so that the gate driving circuit generates a gate driving signal, and the gate driving signal is provided to a plurality of sub-pixels, so that the sub-pixels are turned on for display.
  • the gate driving circuit is powered off, and the gate driving circuit usually includes a plurality of shift registers connected in cascade to generate a plurality of output signals shifted in sequence as gate driving signals.
  • the conventional gate drive circuit is prone to display abnormality when powered on.
  • an input circuit connected to the input signal terminal, the input control terminal and the pull-up node of the shift register, and configured to input the potential of the input signal terminal to the pull-up node under the control of the signal of the input control terminal;
  • an output circuit connected to the pull-up node, the clock signal terminal and the output signal terminal, and configured to provide a signal of the clock signal terminal to the output signal terminal under the control of the potential of the pull-up node;
  • a first control circuit connected to a first control signal terminal, the pull-up node, a pull-down node of the shift register, and a reference signal terminal, and configured to supply a potential of the first control signal terminal to the pull-down node, and supplying the potential of the reference signal terminal to the pull-down node according to the potential of the pull-up node;
  • a second control circuit is connected to the pull-down node, the second control signal terminal, the output signal terminal and the reference signal terminal, and is configured to control the potential of the pull-down node and the second control signal terminal In the down stage, the potential of the output signal terminal is pulled down in the display stage, and the potential of the output signal terminal is pulled up in the power down stage.
  • the second control circuit includes:
  • a pull-down subcircuit connected to the pull-down node, the output signal terminal, and the reference signal terminal, and configured to provide the potential of the reference signal terminal to the output signal under the control of the potential of the pull-down node end;
  • a lower electronic circuit is connected to the second control signal terminal, the pull-down node, the output signal terminal and the reference signal terminal, and is configured to, under the control of the signal of the second control signal terminal, convert the The potential of the second control signal terminal is supplied to the output signal terminal and the potential of the reference signal terminal is supplied to the pull-down node.
  • the lower electronic circuit includes a first transistor and a second transistor, wherein,
  • the gate and first electrode of the first transistor are connected to the second control signal terminal, and the second electrode of the first transistor is connected to the output signal terminal;
  • the gate of the second transistor is connected to the second control signal terminal, the first terminal of the second transistor is connected to the reference signal terminal, and the second terminal of the second transistor is connected to the pull-down node .
  • the pull-down subcircuit includes a third transistor and a first capacitor, wherein,
  • a gate of the third transistor is connected to the pull-down node, a first electrode of the third transistor is connected to the reference signal terminal, and a second electrode of the third transistor is connected to the output signal terminal;
  • a first terminal of the first capacitor is connected to the pull-down node, and a second terminal of the first capacitor is connected to the reference signal terminal.
  • the pull-down sub-circuit further includes a fourth transistor, the gate of the fourth transistor is connected to the output signal terminal, the first electrode of the fourth transistor is connected to the reference signal terminal, and the fourth transistor is connected to the reference signal terminal.
  • the second pole of the transistor is connected to the pull-down node.
  • the second control circuit includes a fifth transistor and a second capacitor, wherein,
  • the gate of the fifth transistor is connected to the pull-down node, the first electrode of the fifth transistor is connected to the second control signal terminal, and the second electrode of the fifth transistor is connected to the output signal terminal ;
  • the first terminal of the second capacitor is connected to the pull-down node, and the second terminal of the second capacitor is connected to the reference signal terminal.
  • the shift register further includes a noise reduction circuit connected to the input control terminal, the pull-down node and the reference signal terminal, and configured to convert the input control terminal under the control of the signal of the input control terminal The potential of the reference signal terminal is supplied to the pull-down node.
  • the noise reduction circuit includes a sixth transistor, the gate of the sixth transistor is connected to the input control terminal, the first electrode of the sixth transistor is connected to the reference signal terminal, and the sixth transistor The second pole of is connected to the pull-down node.
  • the shift register further includes a reset circuit connected to the reset control terminal, the reset signal terminal and the pull-up node, and configured to change the potential of the reset signal terminal under the control of the signal of the reset control terminal supplied to the pull-up node.
  • the pull-up node includes a first pull-up node connected to the input circuit and a second pull-up node connected to the output circuit
  • the first control circuit includes a seventh transistor, an eighth transistor, a third Nine transistors and tenth transistors, where,
  • a gate and a first electrode of the seventh transistor are connected to the first control signal terminal, and a second electrode of the seventh transistor is connected to the pull-down node;
  • the gate of the eighth transistor is connected to the pull-down node, the first electrode of the eighth transistor is connected to the reference signal terminal, and the second electrode of the eighth transistor is connected to the first pull-up node ;
  • the gate of the ninth transistor is connected to the first pull-up node, the first electrode of the ninth transistor is connected to the reference signal terminal, and the second electrode of the ninth transistor is connected to the pull-down node ;and
  • the gate of the tenth transistor is connected to the power signal terminal, the first pole of the tenth transistor is connected to the first pull-up node, and the second pole of the tenth transistor is connected to the second pull-up node node.
  • the input circuit includes an eleventh transistor, a gate of the eleventh transistor is connected to the input control terminal, a first pole of the eleventh transistor is connected to the input signal terminal, and the first pole is connected to the input signal terminal.
  • the second pole of the eleven transistors is connected to the pull-up node.
  • the output circuit includes a twelfth transistor and a third capacitor, wherein,
  • the gate of the twelfth transistor is connected to the pull-up node, the first electrode of the twelfth transistor is connected to the clock signal terminal, and the second electrode of the twelfth transistor is connected to the output signal terminal;
  • the first terminal of the third capacitor is connected to the pull-up node, and the second terminal of the third capacitor is connected to the output signal terminal.
  • the reset circuit includes a thirteenth transistor, a gate of the thirteenth transistor is connected to the reset control terminal, a first pole of the thirteenth transistor is connected to the reset signal terminal, and the thirteenth transistor is connected to the reset signal terminal.
  • the second pole of the thirteen transistors is connected to the pull-up node.
  • the shift register further includes a general reset circuit connected to the general reset signal terminal, the pull-up node and the reference signal terminal, and configured to reset the general reset signal terminal under the control of the signal of the general reset signal terminal.
  • the potential of the reference signal terminal is supplied to the pull-up node.
  • the total reset circuit includes a fourteenth transistor, the gate of the fourteenth transistor is connected to the total reset signal terminal, the first electrode of the fourteenth transistor is connected to the reference signal terminal, so The second electrode of the fourteenth transistor is connected to the pull-up node.
  • Embodiments of the present disclosure also provide a gate drive circuit, comprising N-stage cascaded shift registers, each shift register being the above-mentioned shift register, wherein,
  • each shift register is connected to receive the input signal
  • the reset signal terminal is connected to receive the reset signal
  • the second control signal terminal is connected to receive the second control signal
  • the input control terminal of the nth stage shift register is connected to the output signal terminal of the n-ith stage shift register, and the reset control terminal of the nth stage shift register is connected to the output signal terminal of the n+jth stage shift register;
  • the N-level cascaded shift registers are divided into at least one group, each group includes K-level cascaded shift registers, and the clock signal terminals of the K-level cascaded shift registers are respectively connected to receive K clock signals , the first control signal terminals of the K-stage cascaded shift registers are respectively connected to receive the K clock signals, wherein N, K, n, i and j are all integers, 1 ⁇ n ⁇ N, 1 ⁇ K ⁇ N.
  • the K clock signals include a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a Seven clock signals and eighth clock signals, in each set of shift registers:
  • the clock signal terminal of the first-stage shift register is connected to receive the first clock signal, and the first control signal terminal of the first-stage shift register is connected to receive the fifth clock signal;
  • the clock signal terminal of the second stage shift register is connected to receive the second clock signal, and the first control signal terminal of the second stage shift register is connected to receive the sixth clock signal;
  • the clock signal terminal of the third-stage shift register is connected to receive the third clock signal, and the first control signal terminal of the third-stage shift register is connected to receive the seventh clock signal;
  • the clock signal terminal of the fourth-stage shift register is connected to receive the fourth clock signal, and the first control signal terminal of the fourth-stage shift register is connected to receive the eighth clock signal;
  • the clock signal terminal of the fifth-stage shift register is connected to receive the fifth clock signal, and the first control signal terminal of the fifth-stage shift register is connected to receive the first clock signal;
  • the clock signal terminal of the sixth-stage shift register is connected to receive the sixth clock signal, and the first control signal terminal of the sixth-stage shift register is connected to receive the second clock signal;
  • the clock signal terminal of the seventh-stage shift register is connected to receive the seventh clock signal, and the first control signal terminal of the seventh-stage shift register is connected to receive the third clock signal;
  • the clock signal terminal of the eighth-stage shift register is connected to receive the eighth clock signal
  • the first control signal terminal of the eighth-stage shift register is connected to receive the fourth clock signal
  • the K clock signals include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, in each group of shift registers:
  • the clock signal terminal of the first-stage shift register is connected to receive the first clock signal, and the first control signal terminal of the first-stage shift register is connected to receive the third clock signal;
  • the clock signal terminal of the second stage shift register is connected to receive the second clock signal, and the first control signal terminal of the second stage shift register is connected to receive the fourth clock signal;
  • the clock signal terminal of the third-stage shift register is connected to receive the third clock signal, and the first control signal terminal of the third-stage shift register is connected to receive the first clock signal;
  • the clock signal terminal of the fourth-stage shift register is connected to receive the fourth clock signal
  • the first control signal terminal of the fourth-stage shift register is connected to receive the second clock signal
  • Embodiments of the present disclosure also provide a display panel, including:
  • At least one of the above-mentioned gate driving circuits, the N-stage shift registers in the gate driving circuit are respectively connected to a plurality of rows of sub-pixels in the array.
  • the display panel includes two of the gate driving circuits, and the two gate driving circuits are respectively located on both sides of the array of the plurality of sub-pixels along a first direction, wherein the first direction is the The row direction of the array.
  • the shift register includes an input circuit, a first control circuit, a second control circuit and an output circuit, the input circuit, the first control circuit, the second control circuit and the output circuit are sequentially arranged in the first direction, and all the The size of each of the input circuit, the first control circuit, the second control circuit and the output circuit in the second direction is 0.8-1.4 times the size of the sub-pixel in the second direction, wherein the first direction is the size of the sub-pixel in the second direction.
  • the row direction of the array, the second direction is perpendicular to the first direction.
  • the display panel further includes a multiplexing circuit, the multiplexing circuit is connected to the M columns of sub-pixels in the array, and the multiplexing circuit is configured to select between the first selection signal and the second Under the control of the selection signal, the received m input data signals are multiplexed into M output data signals, which are respectively provided to the M columns of sub-pixels, wherein m and M are integers greater than 1, and M is an integer multiple of m.
  • Embodiments of the present disclosure also provide a driving method for the above gate driving circuit, including:
  • an input signal of a first level is provided to the gate driving circuit, and each shift register outputs a gate drive at a respective output signal terminal based on the input signal under the control of the potential of the respective input control terminal Signal;
  • a second control signal of a first level and an input signal of a second level are provided to the gate driving circuit, and each shift register provides the second control signal of the first level to its respective and each shift register provides the input signal of the second level to the respective pull-up node under the control of the potential of the respective input control terminal.
  • the second control circuit of each shift register includes a pull-down sub-circuit and a lower electronic circuit, wherein,
  • the pull-down subcircuit of each shift register provides the potential of the reference signal terminal of the shift register to the output signal of the shift register under the control of the potential of the pull-down node of the shift register end;
  • each shift register provides a second control signal of a first level at the second control signal terminal of the shift register to the output signal terminal of the shift register and The potential of the reference signal terminal of the shift register is supplied to the pull-down node of the shift register.
  • the second control circuit of each shift register includes a fifth transistor and a second capacitor, wherein,
  • a second control signal of a second level is provided to the gate drive circuit, and the second control circuit of each shift register switches all the shift registers under the control of the potential of the pull-down node of the shift register.
  • the second control signal of the second level is provided to the output signal terminal of the shift register;
  • K clock signals maintaining a first level are provided to the gate driving circuit, and the first control circuit of each shift register receives the first control signal terminal of the shift register
  • the clock signal of the first level is provided to the pull-down node of the shift register, and the potential of the pull-down node causes the second control circuit of the shift register to provide the second control signal of the first level to the output signal terminal of the shift register.
  • each shift register is based on the input signals and the received clock under the control of the potential of the respective input control terminal
  • the signals output gate drive signals at respective output signal terminals, wherein the k+1th clock signal is shifted by a unit scan time relative to the kth clock signal, where k is an integer, 1 ⁇ k ⁇ K-1, the unit scan time The time required for the gate drive circuit to scan a row of pixels.
  • the K clock signals are periodic signals with a duty ratio of 25% and a pulse width of twice the unit scan time .
  • the K clock signals are periodic signals with a duty ratio of 50% and a pulse width of twice the unit scan time .
  • the K clock signals are periodic signals with a duty ratio of 12.5% and a pulse width of a unit scan time.
  • the K clock signals are periodic signals with a duty ratio of 25% and a pulse width of a unit scan time.
  • FIG. 1 shows a block diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 2A shows a circuit diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 2B shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 2C shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 2D shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 3 shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 4 shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure.
  • FIG. 7A shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 7B shows a schematic diagram of the layout of the display panel of FIG. 7A .
  • Figure 7C shows a schematic diagram of the layout of the shift register in Figure 7B.
  • FIG. 8 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 9 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 12 shows a circuit diagram of a multiplexing circuit according to an embodiment of the present disclosure.
  • FIG. 13 shows a signal timing diagram of a shift register in a display phase according to an embodiment of the present disclosure.
  • FIG. 14 shows a signal timing diagram of a gate driving circuit in a display stage according to an embodiment of the present disclosure.
  • FIG. 15 shows a signal timing diagram of a gate driving circuit in a display stage according to another embodiment of the present disclosure.
  • FIG. 16 shows an operation timing diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 17 shows an operation timing diagram of a gate driving circuit according to another embodiment of the present disclosure.
  • FIG. 18 shows a timing diagram of a gate driving circuit in a power-up phase according to another embodiment of the present disclosure.
  • 19A illustrates a signal timing diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 19B shows a schematic diagram of signal waveforms of a display panel according to an embodiment of the present disclosure.
  • 19C illustrates a simulation diagram of signal waveforms of a display panel according to an embodiment of the present disclosure.
  • FIG. 20 illustrates a signal timing diagram of a display panel according to another embodiment of the present disclosure.
  • 21A to 21C show signal simulation diagrams of the embodiment of FIG. 20 .
  • FIG. 22 shows a signal waveform diagram of a display panel according to another embodiment of the present disclosure.
  • 23A to 23C show signal simulation diagrams of the embodiment of FIG. 22 .
  • FIG. 24 shows a flowchart of a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • connection may mean that two components are directly connected, or may mean that two components are connected via one or more other components.
  • the two components may be connected or coupled by wired or wireless means.
  • first level and “second level” are only used to distinguish the amplitudes of the two levels from being different.
  • first level is a high level
  • second level is a low level as an example for description.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the thin film transistor used in the embodiments of the present disclosure may be an oxide semiconductor transistor or a low temperature polysilicon (LTPS, Low Temperature Poly-silicon) thin film transistor. Since the source electrode and the drain electrode of the thin film transistor used here are symmetrical, the source electrode and the drain electrode can be interchanged. In the embodiments of the present disclosure, one of the source electrode and the drain electrode is referred to as the first electrode, and the other of the source electrode and the drain electrode is referred to as the second electrode. In the following examples, an N-type thin film transistor is used as an example for description. Those skilled in the art can understand that the embodiments of the present disclosure can obviously be applied to the case of P-type thin film transistors.
  • FIG. 1 shows a block diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register 100 includes an input circuit 110 , an output circuit 120 , a first control circuit 130 and a second control circuit 140 .
  • the input circuit 110 is connected to the input signal terminal CN, the input control terminal STV and the pull-up node PU.
  • the input circuit 110 can input the potential of the input signal terminal CN to the pull-up node PU under the control of the signal of the input control terminal STV.
  • the output circuit 120 is connected to the pull-up node PU, the clock signal terminal CK and the output signal terminal OUT.
  • the output circuit 120 may provide the signal of the clock signal terminal CK to the output signal terminal OUT under the control of the potential of the pull-up node PU.
  • the first control circuit 130 is connected to the first control signal terminal CKB, the pull-up node PU, the pull-down node PD and the reference signal terminal VGL.
  • the first control circuit 130 may provide the potential of the first control signal terminal CKB to the pull-down node PD, and provide the potential of the reference signal terminal VGL to the pull-down node PD according to the potential of the pull-up node PU.
  • the second control circuit 140 is connected to the pull-down node PD, the second control signal terminal EN, the output signal terminal OUT and the reference signal terminal VGL.
  • the second control circuit 140 can pull down the potential of the output signal terminal OUT in the display stage and pull up the potential of the output signal terminal OUT in the power-down stage under the control of the potentials of the pull-down node PD and the second control signal terminal EN.
  • the pull-up and pull-down of the potential of the output signal terminal can be controlled based on the signal of the second control signal terminal, so that when the shift register is powered off Charge discharge can be achieved without putting all signal terminals at an active level (eg, a high level).
  • the level of the pull-up node can be set as required during the power-down stage, for example, the pull-up node can be set to an inactive level (such as a low level), so that When the shift register is powered up again, there will be no undesired outputs during power-up due to the fact that the power-up process does not support the reset of the pull-up node.
  • FIG. 2A shows a circuit diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register 200A includes an input circuit 210 , an output circuit 220 , a first control circuit 230 and a second control circuit 240 .
  • the input circuit 210 includes an eleventh transistor T11, the gate of the eleventh transistor T11 is connected to the input control terminal STV, the first pole of the eleventh transistor T11 is connected to the input signal terminal CN, and the second pole of the eleventh transistor T11 Connect to the pull-up node PU.
  • the output circuit 220 includes a twelfth transistor T12 and a third capacitor C3.
  • the gate of the twelfth transistor T12 is connected to the pull-up node PU, the first pole of the twelfth transistor T12 is connected to the clock signal terminal CK, and the second pole of the twelfth transistor T12 is connected to the output signal terminal OUT.
  • the first terminal of the third capacitor C3 is connected to the pull-up node PU, and the second terminal of the third capacitor C3 is connected to the output signal terminal OUT.
  • the first control circuit 230 includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9.
  • the gate and first electrode of the seventh transistor T7 are connected to the first control signal terminal CKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD.
  • the gate of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is connected to the reference signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the pull-up node PU.
  • the gate of the ninth transistor T9 is connected to the pull-up node PU, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the pull-down node PD.
  • the shift register 200A also includes a reset circuit 250 .
  • the reset circuit 250 includes a thirteenth transistor T13, the gate of the thirteenth transistor T13 is connected to the reset control terminal RST, the first pole of the thirteenth transistor T13 is connected to the reset signal terminal CNB, and the second pole of the thirteenth transistor T13 Connect to the pull-up node PU.
  • the reset circuit 250 and the input circuit 210 can be used interchangeably to achieve forward and reverse scans.
  • a high-level signal is applied to the input signal terminal CN, and a low-level signal is applied to the reset signal terminal CNB, and the input circuit 210 provides a high power to the pull-up node PU based on the high level of the input signal terminal CN If the input is flat, the reset circuit 250 resets the pull-up node PU to a low level based on the low level of the reset signal terminal CNB.
  • a low-level signal is applied to the input signal terminal CN, and a high-level signal is applied to the reset signal terminal CNB, and the reset circuit 250 provides a high-level input to the pull-up node PU based on the high level of the reset signal terminal CNB , the input circuit 210 resets the pull-up node PU to a low level based on the low level of the input signal terminal CN.
  • FIG. 2B shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • the shift register 200B of FIG. 2B is similar to the above-mentioned shift register 200A, and for the sake of brevity, the different parts are mainly described in detail below.
  • the shift register 200B includes an input circuit 210, an output circuit 220, a first control circuit 230' and a reset circuit 250.
  • the shift register 200B has two pull-up nodes, which are a first pull-up node PU1 and a second pull-up node PU2 .
  • the first pull-up node PU1 is connected to the input circuit 210
  • the second pull-up node PU2 is connected to the output circuit 220 .
  • the first control circuit 230' further includes a tenth transistor T10 connected between the first pull-up node PU1 and the second pull-up node PU2.
  • the gate of the tenth transistor T10 is connected to the power supply signal terminal VGH
  • the first electrode of the tenth transistor T10 is connected to the first pull-up node PU1
  • the second electrode of the tenth transistor T10 is connected to the second pull-up node PU1.
  • the gate and first electrode of the seventh transistor T7 are connected to the first control signal terminal CKB
  • the second electrode of the seventh transistor T7 is connected to the pull-down node PD.
  • the gate of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is connected to the reference signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the first pull-up node PU1.
  • the gate of the ninth transistor T9 is connected to the first pull-up node PU1, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the pull-down node PD.
  • the tenth transistor T10 When the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, thereby electrically connecting the first pull-up node PU1 and the second pull-up node PU2; when the power signal terminal VGH is at a low level, the tenth transistor T10 is turned off
  • the first pull-up node PU1 and the second pull-up node PU2 are electrically isolated.
  • the first pull-up node PU1 and the second pull-up node PU2 can be electrically isolated or electrically connected as required, so as to avoid the potential of the second pull-up node PU2 for controlling the output circuit 320 when necessary. affected by other circuits.
  • the second control circuit includes a pull-down sub-circuit 2401 and a lower electronic circuit 2402 .
  • the pull-down subcircuit 2401 is connected to the pull-down node PD, the output signal terminal OUT and the reference signal terminal VGL.
  • the pull-down sub-circuit 2401 may provide the potential of the reference signal terminal VGL to the output signal terminal OUT under the control of the potential of the pull-down node PD.
  • the pull-down sub-circuit 2401 includes a third transistor T3 and a first capacitor C1.
  • the gate of the third transistor T3 is connected to the pull-down node PD, the first electrode of the third transistor T3 is connected to the reference signal terminal VGL, and the second electrode of the third transistor T3 is connected to the output signal terminal OUT.
  • the first terminal of the first capacitor C1 is connected to the pull-down node PD, and the second terminal of the first capacitor C1 is connected to the reference signal terminal VGL.
  • the lower electronic circuit 2402 is connected to the second control signal terminal EN, the pull-down node PD, the output signal terminal OUT and the reference signal terminal VGL.
  • the lower electronic circuit 2402 can provide the potential of the second control signal terminal EN to the output signal terminal OUT and the potential of the reference signal terminal VGL to the pull-down node PD under the control of the signal of the second control signal terminal EN.
  • the lower electronic circuit 2402 may include a first transistor T1 and a second transistor T2.
  • the gate and first pole of the first transistor T1 are connected to the second control signal terminal EN, and the second pole of the first transistor T1 is connected to the output signal terminal OUT.
  • the gate of the second transistor T2 is connected to the second control signal terminal EN, the first terminal of the second transistor T2 is connected to the reference signal terminal VGL, and the second terminal of the second transistor T2 is connected to the pull-down node PD.
  • the pull-down sub-circuit 2401 may further include a fourth transistor T4, the gate of the fourth transistor T4 is connected to the output signal terminal OUT, and the first electrode of the fourth transistor T4 is connected to the reference signal The terminal VGL, the second pole of the fourth transistor T4 is connected to the pull-down node PD.
  • the fourth transistor T4 When the output signal terminal OUT is at a high level, the fourth transistor T4 is turned on, thereby pulling down the pull-down node PD to the low level of the reference signal terminal VGL.
  • the fourth transistor T4 functions to further stabilize the potential of the pull-down node PD.
  • the shift register 200B also includes a general reset circuit 270, as shown in FIG. 2B.
  • the total reset circuit 270 is connected to the total reset signal terminal RESET, the first pull-up node PU1 and the reference signal terminal VGL.
  • the general reset circuit 370 may provide the potential of the reference signal terminal VGL to the first pull-up node PU1 under the control of the signal of the general reset signal terminal RESET.
  • the total reset circuit 270 includes a fourteenth transistor T14, the gate of the fourteenth transistor T14 is connected to the total reset signal terminal RESET, the first electrode of the fourteenth transistor T14 is connected to the reference signal terminal VGL, and the tenth transistor T14 is connected to the reference signal terminal VGL.
  • the second pole of the quad transistor T14 is connected to the first pull-up node PU1.
  • the fourteenth transistor T14 is turned on, thereby resetting the first pull-up node PU1 to a low level at the reference signal terminal VGL.
  • FIG. 2C shows a circuit diagram of a shift register according to another embodiment of the present disclosure. Similar to the shift register 200B, the shift register 200C includes an input circuit 210, an output circuit 220, a first control circuit 230', a reset circuit 250, and a total reset circuit 270.
  • the second control circuit 240' of the shift register 200C includes a fifth transistor T5 and a second capacitor C2.
  • the gate of the fifth transistor T5 is connected to the pull-down node PD, the first pole of the fifth transistor T5 is connected to the second control signal terminal EN, and the second pole of the fifth transistor T5 is connected to the output signal terminal OUT.
  • the first terminal of the second capacitor C2 is connected to the pull-down node PD, and the second terminal of the second capacitor C2 is connected to the reference signal terminal VGL.
  • FIG. 2D shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • the shift register 200D of FIG. 2D is similar to the shift register 200B, and the difference is at least in the structure of the second control circuit 240 ′′ and the noise reduction circuit 260 is further included.
  • the noise reduction circuit 260 is connected to the input control terminal STV, the pull-down node PD and the reference signal terminal VGL.
  • the noise reduction circuit 260 may provide the potential of the reference signal terminal VGL to the pull-down node PD under the control of the signal input to the control terminal STV.
  • the noise reduction circuit 260 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the input control terminal STV, the first pole of the sixth transistor T6 is connected to the reference signal terminal VGL, and the sixth transistor T6 The diode is connected to the pull-down node PD.
  • the second control circuit 240" includes a third transistor T3, a fourth transistor T4 and a first capacitor C1.
  • the gate of the third transistor T3 is connected to the pull-down node PD, and the first electrode of the third transistor T3 is connected to The second control signal terminal EN, the second pole of the third transistor T3 is connected to the output signal terminal OUT.
  • the first terminal of the first capacitor C1 is connected to the pull-down node PD, and the second terminal of the first capacitor C1 is connected to the reference signal terminal VGL
  • the gate of the fourth transistor T4 is connected to the output signal terminal OUT, the first pole of the fourth transistor T4 is connected to the reference signal terminal VGL, and the second pole of the fourth transistor T4 is connected to the pull-down node PD.
  • the first electrode of the third transistor T3 may be connected to the reference signal terminal VGL instead of the second control signal terminal EN.
  • FIG. 3 shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • the shift register 300 of FIG. 3 is similar to the above-mentioned shift register 200A.
  • the different parts are mainly described in detail below.
  • shift register 300 includes input circuit 310, output circuit 320, first control circuit 330, and reset circuit 350, above for input circuit 210, output circuit 220, first control circuit 230, and reset circuit 250 The description of the same applies to the input circuit 310 , the output circuit 320 , the first control circuit 330 and the reset circuit 350 .
  • the shift register 300 has two pull-up nodes, which are a first pull-up node PU1 and a second pull-up node PU2 .
  • the first pull-up node PU1 is connected to the input circuit 310
  • the second pull-up node PU2 is connected to the output circuit 320 .
  • the first control circuit further includes a tenth transistor T10 connected between the first pull-up node PU1 and the second pull-up node PU2. As shown in FIG.
  • the gate of the tenth transistor T10 is connected to the power signal terminal VGH, the first electrode of the tenth transistor T10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor T10 is connected to the second pull-up node PU1.
  • the gate and first electrode of the seventh transistor T7 are connected to the first control signal terminal CKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD.
  • the gate of the eighth transistor T8 is connected to the pull-down node PD, the first electrode of the eighth transistor T8 is connected to the reference signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the first pull-up node PU1.
  • the gate of the ninth transistor T9 is connected to the first pull-up node PU1, the first electrode of the ninth transistor T9 is connected to the reference signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the pull-down node PD.
  • the tenth transistor T10 When the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, thereby electrically connecting the first pull-up node PU1 and the second pull-up node PU2; when the power signal terminal VGH is at a low level, the tenth transistor T10 is turned off
  • the first pull-up node PU1 and the second pull-up node PU2 are electrically isolated.
  • the first pull-up node PU1 and the second pull-up node PU2 can be electrically isolated or electrically connected as required, so as to avoid the potential of the second pull-up node PU2 for controlling the output circuit 320 when necessary. affected by other circuits.
  • the second control circuit includes a pull-down sub-circuit 3401 and a lower electronic circuit 3402 .
  • the pull-down subcircuit 3401 is connected to the pull-down node PD, the output signal terminal OUT and the reference signal terminal VGL.
  • the pull-down sub-circuit 3401 may provide the potential of the reference signal terminal VGL to the output signal terminal OUT under the control of the potential of the pull-down node PD.
  • the pull-down sub-circuit 3401 includes a third transistor T3 and a first capacitor C1.
  • the gate of the third transistor T3 is connected to the pull-down node PD, the first electrode of the third transistor T3 is connected to the reference signal terminal VGL, and the second electrode of the third transistor T3 is connected to the output signal terminal OUT.
  • the first terminal of the first capacitor C1 is connected to the pull-down node PD, and the second terminal of the first capacitor C1 is connected to the reference signal terminal VGL.
  • the lower electronic circuit 3402 is connected to the second control signal terminal EN, the pull-down node PD, the output signal terminal OUT and the reference signal terminal VGL.
  • the lower electronic circuit 3402 can provide the potential of the second control signal terminal EN to the output signal terminal OUT and the potential of the reference signal terminal VGL to the pull-down node PD under the control of the signal of the second control signal terminal EN.
  • the lower electronic circuit 3402 may include a first transistor T1 and a second transistor T2.
  • the gate and first pole of the first transistor T1 are connected to the second control signal terminal EN, and the second pole of the first transistor T1 is connected to the output signal terminal OUT.
  • the gate of the second transistor T2 is connected to the second control signal terminal EN, the first terminal of the second transistor T2 is connected to the reference signal terminal VGL, and the second terminal of the second transistor T2 is connected to the pull-down node PD.
  • the pull-down sub-circuit 3401 may further include a fourth transistor T4, the gate of the fourth transistor T4 is connected to the output signal terminal OUT, and the first electrode of the fourth transistor T4 is connected to the reference signal The terminal VGL, the second pole of the fourth transistor T4 is connected to the pull-down node PD.
  • the fourth transistor T4 When the output signal terminal OUT is at a high level, the fourth transistor T4 is turned on, thereby pulling down the pull-down node PD to the low level of the reference signal terminal VGL.
  • the fourth transistor T4 functions to further stabilize the potential of the pull-down node PD.
  • the shift register also includes noise reduction circuitry 360 .
  • the noise reduction circuit 360 is connected to the input control terminal STV, the pull-down node PD and the reference signal terminal VGL.
  • the noise reduction circuit 360 may provide the potential of the reference signal terminal VGL to the pull-down node PD under the control of the signal input to the control terminal STV.
  • the noise reduction circuit includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the input control terminal STV, the first pole of the sixth transistor T6 is connected to the reference signal terminal VGL, and the second terminal of the sixth transistor T6 pole is connected to the pull-down node PD.
  • the eleventh transistor T11 is turned on, and the high level at the input signal terminal CN is input to the first pull-up node PU1, so that the Nine transistors T9 are turned on.
  • the high level at the first control signal terminal CKB makes the seventh transistor T7 in a conducting state, and the seventh transistor T7 and the ninth transistor T9 form a direct current path.
  • the channel width to length ratio W/L of the ninth transistor T9 is at least twice the channel width to length ratio W/L of the seventh transistor, the resistance of the seventh transistor T7 is greater than the resistance of the ninth transistor T9, and the pull-down node PD is at Under the action of the resistor divider, it is at an intermediate level, which is close to but greater than the low level at the reference signal terminal VGL.
  • the intermediate level at the pull-down node PD causes the eighth transistor T8 to be turned on, thereby pulling down the potential of the first pull-up node PU1.
  • the sixth transistor T6 is turned on, so that the low level of the reference signal terminal VGL is used to further pull down the potential of the pull-down node PD, thereby alleviating or avoiding the above-mentioned due to pull-down
  • the problem that the potential of the node PD is not low enough to affect the potential of the first pull-up node PU1 improves the competition between the pull-up node PU and the pull-down node PD.
  • the shift register 300 also includes a general reset circuit 370 .
  • the total reset circuit 370 is connected to the total reset signal terminal RESET, the first pull-up node PU1 and the reference signal terminal VGL.
  • the general reset circuit 370 may provide the potential of the reference signal terminal VGL to the first pull-up node PU1 under the control of the signal of the general reset signal terminal RESET.
  • the total reset circuit 370 includes a fourteenth transistor T14, the gate of the fourteenth transistor T14 is connected to the total reset signal terminal RESET, the first electrode of the fourteenth transistor T14 is connected to the reference signal terminal VGL, and the tenth transistor T14 is connected to the reference signal terminal VGL.
  • the second pole of the quad transistor T14 is connected to the first pull-up node PU1.
  • the fourteenth transistor T14 is turned on, thereby resetting the first pull-up node PU1 to a low level at the reference signal terminal VGL.
  • FIG. 4 shows a circuit diagram of a shift register according to another embodiment of the present disclosure.
  • the shift register 400 of FIG. 4 is similar to the shift register 300 of FIG. 3 , except for at least the second control circuit 440 .
  • the following will mainly describe the different parts in detail.
  • the shift register 400 includes an input circuit 410, an output circuit 420, a first control circuit 430, a reset circuit 450, a noise reduction circuit 460, and a total reset circuit 470, above for the input circuit 310, the output circuit 320 , the description of the first control circuit 330, the reset circuit 350, the noise reduction circuit 360, and the overall reset circuit 370 apply equally to the input circuit 410, the output circuit 420, the first control circuit 430, the reset circuit 450, the noise reduction circuit 460, and the overall reset circuit 470.
  • the second control circuit 440 of the shift register 400 includes a fifth transistor T5 and a second capacitor C2.
  • the gate of the fifth transistor T5 is connected to the pull-down node PD, the first pole of the fifth transistor T5 is connected to the second control signal terminal EN, and the second pole of the fifth transistor T5 is connected to the output signal terminal OUT.
  • the first terminal of the second capacitor C2 is connected to the pull-down node PD, and the second terminal of the second capacitor C2 is connected to the reference signal terminal VGL.
  • FIG. 5 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit 500 includes N cascaded shift registers.
  • N cascaded shift registers.
  • 8 shift registers GOA1 to GOA8 are shown in FIG. 5 .
  • the number of shift registers can be set as required.
  • Each of the shift registers GOA1 to GOA8 may be implemented by a shift register of any of the above-described embodiments, such as shift registers 100 , 200A, 200B, 200C, 200D, 300 or 400 .
  • the respective input signal terminals CN of the shift registers GOA1 to GOA8 are connected to receive the input signal CN, the reset signal terminal CNB is connected to receive the reset signal CNB, and the second control signal terminal EN is connected to receive the second control signal EN.
  • the input signal terminal CN of each shift register receives the same input signal, in order to simplify the description, the input signal and the input signal terminal are denoted by the same reference numeral CN.
  • the reset signal Both the terminal and the reset signal are represented by CNB, and both the second control signal terminal EN and the second control signal are represented by EN.
  • the input control terminal STV of the nth stage shift register is connected to the output signal terminal OUT of the n-ith stage shift register, and the reset control terminal RST of the nth stage shift register is connected to the n+jth stage The output signal terminal OUT of the shift register.
  • the input control terminal STV of the n-th stage shift register is connected to the output signal terminal OUT of the n-4th stage shift register, and the reset control terminal RST of the n-th stage shift register is connected to To the output signal terminal OUT of the n+4th stage shift register, for example, the output signal terminal OUT of the first stage shift register GOA1 is connected to the input control terminal STV of the fifth stage shift register GOA5, and the second stage shift register GOA2 The output signal terminal OUT of is connected to the input control terminal STV of the sixth-stage shift register GOA6, and so on.
  • the reset control terminal RST of the first-stage shift register GOA1 is connected to the output signal terminal OUT of the fifth-stage shift register GOA5, and the reset control terminal RST of the second-stage shift register GOA2 is connected to the output of the sixth-stage shift register GOA6 Signal terminal OUT, and so on.
  • the input signal terminals STV of the first to fourth stage shift registers GOA1 to GOA4 are respectively connected to receive enable signals STV1 to STV4.
  • the N-stage cascaded shift registers are divided into at least one group, each group includes K-stage cascaded shift registers, and clock signal terminals CK of the K-stage cascaded shift registers are respectively connected to
  • the first control signal terminals CKB of the K-stage cascaded shift registers are respectively connected to receive the K clock signals, wherein N, K, n, i and j are all integers, 1 ⁇ n ⁇ N, 1 ⁇ K ⁇ N.
  • K 8
  • each group of shift registers includes 8 shift registers, for example, the first to eighth shift registers GOA1 to GOA8 are a group, and are respectively connected to 8 clock signals CK1 to CK8.
  • the clock signal terminal CK of the first-stage shift register GOA1 is connected to receive the first clock signal CK1, and the first control signal terminal of the first-stage shift register GOA1 is connected to CKB is connected to receive the fifth clock signal CK5;
  • the clock signal terminal CK of the second-stage shift register GOA2 is connected to receive the second clock signal CK2, and the first control signal terminal CKB of the second-stage shift register GOA2 is connected to receive the sixth The clock signal CK6;
  • the clock signal terminal CK of the third-stage shift register GOA3 is connected to receive the third clock signal CK3, and the first control signal terminal CKB of the third-stage shift register GOA3 is connected to receive the seventh clock signal CK7;
  • the fourth The clock signal terminal CK of the stage shift register GOA4 is connected to receive the fourth clock signal CK4, and the first control signal terminal CKB of the fourth stage shift register GOA4 is connected to receive the eighth clock signal CK8;
  • the clock signal terminal CK of the stage shift register GOA4 is
  • the other signal terminals (if any) of the shift registers GOA1 to GOA8 of the gate driving circuit 500 are respectively connected to receive signals for the signal terminals, for example, the power signal terminals VGH of the shift registers GOA1 to GOA8 of each stage are connected to receive power
  • the reference signal terminal VGL is connected to receive the reference signal
  • the total reset signal terminal RESET is connected to receive the total reset signal.
  • FIG. 6 shows a schematic diagram of a gate driving circuit according to another embodiment of the present disclosure.
  • the input control terminal STV of the n-th stage shift register is connected to the output signal terminal OUT of the n-2-th stage shift register, and the reset control terminal RST of the n-th stage shift register is connected to the n+2-th stage
  • the output signal terminal OUT of the stage shift register for example, the output signal terminal OUT of the first stage shift register GOA1 is connected to the input control terminal STV of the third stage shift register GOA3, and the output signal terminal OUT of the second stage shift register GOA2 Connect to the input control terminal STV of the 4th stage shift register GOA4, and so on.
  • the reset control terminal RST of the first-stage shift register GOA1 is connected to the output signal terminal OUT of the third-stage shift register GOA3, and the reset control terminal RST of the second-stage shift register GOA2 is connected to the output of the fourth-stage shift register GOA4 Signal terminal OUT, and so on.
  • the input signal terminals STV of the first-stage shift register GOA1 and the second-stage shift register GOA2 are respectively connected to receive enable signals STV1 and STV2.
  • the gate driving circuit 600 is controlled by four clock signals CK1 to CK4, and adjacent four-stage shift registers are connected as a group to receive the clock signals CK1 to CK4 respectively.
  • the clock signal terminal CK of the first-stage shift register GOA1 is connected to receive the first clock signal CK1
  • the first control signal terminal CKB of the first-stage shift register GOA1 is connected to In order to receive the third clock signal CK3
  • the clock signal terminal CK of the second stage shift register GOA2 is connected to receive the second clock signal CK2
  • the first control signal terminal CKB of the second stage shift register GOA2 is connected to receive the fourth clock signal CK4
  • the clock signal terminal CK of the third-stage shift register GOA3 is connected to receive the third clock signal CK3, and the first control signal terminal CKB of the third-stage shift register GOA3 is connected to receive the first clock signal CK1
  • the clock signal terminal CK of the bit register GOA4 is connected to receive the fourth
  • FIG. 7A shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 700 includes a plurality of sub-pixels Pix arranged in an array and a gate driving circuit 710 .
  • the gate driving circuit 710 may be implemented by the gate driving circuit of any of the above-mentioned embodiments, and the multi-stage shift registers in the gate driving circuit 710 are respectively connected to the sub-pixels Pix in the rows of the array.
  • FIG. 7A the display panel 700 includes a plurality of sub-pixels Pix arranged in an array and a gate driving circuit 710 .
  • the gate driving circuit 710 may be implemented by the gate driving circuit of any of the above-mentioned embodiments, and the multi-stage shift registers in the gate driving circuit 710 are respectively connected to the sub-pixels Pix in the rows of the array.
  • a plurality of sub-pixels Pix are located in the display area 720 , the plurality of sub-pixels Pix are arranged in an N ⁇ M array, N rows of sub-pixels Pix are respectively connected to N gate signal lines G1 to GN, and M columns of sub-pixels Pix are respectively connected to To the M data lines D1 to DM, N output signals generated by the N-stage shift registers in the gate driving circuit 710 are supplied to the gate lines G1 to GN, respectively.
  • the embodiments of the present disclosure are not limited thereto, the sub-pixels Pix can be arranged in other forms of arrays as required, the rows and columns of the sub-pixels Pix can be connected to the gate lines and data lines in different ways, and the output of the gate driving circuit 710
  • the signal terminals can be connected to the gate lines in different ways.
  • one gate line may connect two rows of sub-pixels, or two gate lines may connect one row of sub-pixels.
  • each output signal terminal in the gate driving circuit 710 may be connected to one gate line or multiple gate lines, and so on.
  • FIG. 7B shows a schematic diagram of the layout of the display panel of FIG. 7A .
  • the gate driving circuit 710 can be composed of the gate driving circuit described above.
  • the N shift registers GOA1 to GOAN in the gate driving circuit 710 move along the y direction (the column direction of the sub-pixel array, also referred to as the second direction, the vertical direction in FIG. 7B ) is arranged and connected to the gate lines G1 to GN in a one-to-one correspondence, so as to be connected to the sub-pixels Pix in the display area 720 .
  • the y direction the column direction of the sub-pixel array, also referred to as the second direction, the vertical direction in FIG. 7B
  • the size of each of the shift registers GOA1 to GOAN in the y direction may be 0.8-1.4 times the size of the sub-pixel Pix in the y direction.
  • each of the shift registers GOA1 to GOAN is in the y direction.
  • the size in the direction is substantially the same as the size of the sub-pixel Pix in the y direction (both denoted by d in FIG. 7B ).
  • the so-called size here may refer to the size of the projection on the base substrate of the display panel. For example, in FIG.
  • the distance spanned in the y direction by the projection of each of the shift registers GOA1 to GOAN on the base substrate of the display panel may represent the dimension d of the shift registers in the y direction.
  • the distance spanned by the projection of the sub-pixel Pix on the base substrate in the y-direction may represent the dimension d of the sub-pixel Pix in the y-direction.
  • Figure 7C shows a schematic diagram of the layout of the shift register in Figure 7B.
  • the shift register may be implemented by the shift register of any of the above-mentioned embodiments, for example, including the above-mentioned input circuit 110 , the first control circuit 130 , the second control circuit 140 and the output circuit 120 .
  • the input circuit 110 , the first control circuit 130 , the second control circuit 140 and the output circuit 120 are sequentially arranged along the x direction (the row direction of the sub-pixel array, also referred to as the first direction, which is perpendicular to the y direction).
  • the x direction the row direction of the sub-pixel array, also referred to as the first direction, which is perpendicular to the y direction.
  • each of the input circuit 110 , the first control circuit 130 , the second control circuit 140 and the output circuit 120 has a size d in the y direction, which is the same as the size d of the subpixel in the y direction.
  • the shift register set on the left side of the display area 720 is used as an example for illustration.
  • the input circuit 110 , the first control circuit 130 , the second control circuit 140 and the output circuit 120 are arranged from left to right, so that the This sequence gradually approaches the display area 720 .
  • the input circuit 110, the first control circuit 130, the second control circuit 140 and the output circuit 120 are arranged from right to left so as to gradually approach the display area in this order 720.
  • the arrangement size of each shift register unit in the y-direction can be reduced as much as possible in the y-direction.
  • the number of shift register units in the y-direction can be increased, thereby helping to improve the resolution of the display panel and the narrow border of the display panel in the y-direction.
  • the projection of the shift register and the input circuit 110, the first control circuit 130, the second control circuit 140, and the output circuit 120 it includes on the base substrate is shown as a substantially rectangular shape, which The size in the y direction is represented by the side length of the rectangle in the y direction.
  • the embodiments of the present disclosure are not limited thereto, and the shift register and the projection of the input circuit, the first control circuit, the second control circuit and the output circuit in the shift register on the base substrate can be designed into other shapes, even irregular shapes as required , as long as its size in the y direction is substantially the same as the size of the subpixel in the y direction.
  • FIG. 8 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel 800 of FIG. 8 is similar to the display panel 700 of FIG. 7A, and the difference is at least that the display panel 800 includes two gate driving circuits 810A and 810B.
  • the display panel 800 includes a display area 820 , and the above description about the display area 720 is also applicable to the display area 820 .
  • the gate driving circuits 810A and 810B are respectively located on both sides of the array of the plurality of sub-pixels along the x-direction (row direction of the sub-pixel array, also referred to as the first direction, horizontal direction in FIG.
  • the gate driving circuits 810A and 810B are each implemented by the gate driving circuit 500 described above.
  • the gate driving circuit 500 described above.
  • FIG. 8 only the cascade connection between the respective shift registers GOA1 to GOAN is shown in FIG. 8 , omitting such as clock signals and other Connection between control signal and shift register. As shown in FIG.
  • the output signal terminal of the first-stage shift register GOA1 in the gate driving circuit 810A is connected to the gate line G1 for the first row of sub-pixels from the left, and the first-stage shift register GOA1 in the gate driving circuit 810B
  • the output signal terminal of the stage shift register GOA1 is connected from the right to the gate line G1 for the sub-pixels in the first row; in a similar manner, the respective second stage shift registers GOA2 of the gate drive circuits 810A and 810B are connected from the left and right, respectively. Both sides are connected to the gate line G1, and so on. In this way, gate driving signals can be applied to the gate lines from both sides, and for large-size display panels, signal attenuation caused by excessively long gate lines can be alleviated.
  • FIG. 9 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel 900 of FIG. 9 is similar to the display panel 800 of FIG. 8 , and includes a display area 920 and gate driving circuits 910A and 910B respectively located on both sides of the display area 920 .
  • the gate driving circuits 910A and 910B in the display panel 900 are each implemented by the gate driving circuit 600 described above.
  • the cascade connection between the respective shift registers GOA1 to GOAN is shown in FIG. 9, and connections such as clock signals and other control signals and the shift registers are omitted. Similar to FIG.
  • the shift registers GOA1 to GOAN of the gate driving circuit 910A in FIG. 9 are respectively connected to the gate lines G1 to GN from the left, and the shift registers GOA1 to GOAN of the gate driving circuit 910B are respectively connected from the right to gate lines G1 to GN.
  • FIG. 10 shows a schematic diagram of a display panel according to another embodiment of the present disclosure. Similar to the display panel 700 of FIG. 7A , the display panel 1000 of FIG. 10 includes a gate driving circuit and a plurality of sub-pixels located in the display area 1020 .
  • the gate driving circuit adopts the structure of the gate driving circuit 500 , wherein an odd-numbered stage shift register is used.
  • GOA1, GOA3, . . . GOA(N-1) (represented by the dotted box 1010A in FIG. 10 ) are arranged on one side (left side in FIG. 10 ) of the display area 1020 along the x direction, the even-numbered stage shift registers GOA2, GOA4, . . .
  • GOAN (indicated by dashed box 1010B in FIG. 10 ) is disposed on the other side (right side in FIG. 10 ) of the display area 1020 in the x-direction.
  • the cascade connections between the respective shift registers GOA1 to GOAN are shown in FIG. 10 , and connections such as clock signals and other control signals and the shift registers are omitted.
  • the odd-numbered shift registers GOA1, GOA3, ... GOA(N-1) are respectively connected to the gate lines G1, G3, ... G(N-1) from the left
  • the even-numbered shift registers GOA2, GOA4, . . . GOAN are connected to the gate lines G2, G4, . . . GN from the right side, respectively.
  • FIG. 11 shows a schematic diagram of a display panel according to another embodiment of the present disclosure. Similar to FIG. 10 , the display panel 1100 of FIG. 11 includes a plurality of sub-pixels Pix located in the display area 1120 and a gate driving circuit 1110 connected to the plurality of sub-pixels Pix. The gate driving circuit 1100 may adopt the above reference to FIG. 8 to Any way described in FIG. 10 is connected to the sub-pixel Pix. In FIG. 11 , the display panel 1100 further includes a multiplexing circuit 1130 . The multiplexing circuit 1130 is connected to M columns of subpixels in the subpixel array through M data lines D1 to DM.
  • the multiplexing circuit 1130 is, for example, connected to a data driving circuit (eg, a driving IC) to receive m input data signals Data1 to Datam, and the multiplexing circuit 1130 may be under the control of the first selection signal MUX1 and the second selection signal MUX2
  • the received m input data signals Data1 to Datam are multiplexed into M output data signals, which are respectively provided to the data lines D1 to DM, and then provided to M columns of sub-pixels Pix.
  • m and M are integers greater than 1, and M is an integer multiple of m, such as twice.
  • the multiplexing circuit includes a plurality of multiplexing units M1 , M2 . . . , two of which are shown in FIG. 12 for simplicity.
  • M/m 2
  • each multiplexing unit of the multiplexing circuit 1130 can multiplex a received input data signal into two output data signals and provide them to the two data lines respectively, Thereby, the multiplexing of one-to-two is realized.
  • the multiplexing unit M1 multiplexes the received input data signal Data1 into two output data signals, which are respectively provided to the data lines D1 and D2, and the multiplexing unit M2 will The received input data signal Data2 is multiplexed into two output data signals and provided to the data lines D3 and D4 respectively.
  • the multiplexing unit M1 multiplexes the received input data signal Data1 into two output data signals, which are respectively provided to the data lines D1 and D2, and the multiplexing unit M2 will The received input data signal Data2 is multiplexed into two output data signals and provided to the data lines D3 and D4 respectively.
  • each multiplexing unit includes transistors Tm1 and Tm2, for example in the multiplexing unit M1, the gate of the transistor Tm1 is connected to the first selection signal line to receive the first selection signal MUX1, the first The pole is connected to receive the input data signal Data1, the second pole is connected to the data line D1; the gate of the transistor Tm2 is connected to the second selection signal line to receive the second selection signal MUX2, the first pole is connected to receive the input data signal Data1, and the first pole is connected to the second selection signal MUX2.
  • the diode is connected to the data line D2.
  • the transistor Tm1 When the first selection signal MUX1 is at a high level, the transistor Tm1 is turned on, thereby providing the received input data signal Data1 to the data line D1; when the second selection signal MUX2 is at a high level, the transistor Tm2 is turned on, thereby turning the input The data signal Data1 is supplied to the data line D2.
  • Other multiplexing units work in a similar manner and will not be described here.
  • FIG. 13 shows a signal timing diagram of a shift register in a display phase according to an embodiment of the present disclosure.
  • the signal timing of FIG. 13 is applicable to the shift register of any of the above-mentioned embodiments.
  • the following will take the shift register 300 of FIG. 3 as an example to describe the signal timing of FIG. 13 .
  • the input signal terminal CN and the power signal terminal VGH maintain a high level
  • the reset signal terminal RST and the reference signal terminal RST maintain a low level.
  • the input control terminal STV is at a high level, and the eleventh transistor T11 is turned on, thereby inputting the high level of the input signal terminal CN to the first pull-up node PU1.
  • the high level of the power signal terminal VGH makes the tenth transistor T10 turn on, so that the second pull-up node PU2 is at a high level.
  • the high level of the second pull-up node PU2 turns on the twelfth transistor T12.
  • the output signal terminal OUT is at a low level.
  • the first control signal terminal CKB is at a high level, the seventh transistor T7 is turned on, and the high level of the first pull-up node PU1 turns on the ninth transistor T9, so that the low level of the reference signal terminal VGL is used to pull down the node PD. potential is pulled down.
  • the potential at the pull-down node PD represented by "PD (no noise reduction)" in FIG. 13
  • it is in an on state and cannot reach a desired low level value, thereby affecting the potential of the first pull-up node PU1.
  • the noise reduction circuit 360 By setting the noise reduction circuit 360, the high level of the input control terminal STV can make the sixth transistor T6 turn on, so that the potential of the pull-down node PD is further pulled down by the potential of the reference signal terminal VGL (as shown in the “PD (with drop)” in FIG. 13 . It can be seen from FIG. 13 that, compared with the case without the noise reduction circuit 360, the potential of the pull-down node PD is reduced.
  • the input control terminal STV and the first control signal terminal CKB become low level
  • the eleventh transistor T11 and the seventh transistor T7 are turned off
  • the first pull-up node PU1 and the second pull-up node PU2 are due to the third
  • the presence of capacitor C3 remains high.
  • the seventh transistor T7 is turned off and the ninth transistor T9 is turned on, the potential of the pull-down node PD is further lowered.
  • the clock signal terminal CK is at a high level.
  • the twelfth transistor T12 since the twelfth transistor T12 is in a conducting state, the high level of the clock signal terminal CK is provided to the output signal terminal OUT.
  • the bootstrap effect of the third capacitor C3 further increases the potential of the second pull-up node PU2.
  • the clock signal terminal CK becomes the low level, and the twelfth transistor T12 in the on-state causes the output signal terminal OUT to also become the low level.
  • the bootstrap effect of the third capacitor C3 reduces the potential of the second pull-up node PU2.
  • the reset control terminal RST is at a high level, thereby providing a low level at the reset signal terminal CNB to the first pull-up node PU1, and the tenth transistor T10 being turned on makes the second pull-up node PU2 also become low level.
  • the first control signal terminal CKB is at a high level, and the seventh transistor T7 is turned on, so that the pull-down node PD becomes a high level.
  • the high level of the pull-down node PD turns on the third transistor T3, thereby pulling down the output signal terminal OUT to the low level of the reference signal terminal VGL.
  • the second control signal terminal EN is kept at a low level, and the first transistor T1 and the second transistor are in an off state.
  • the shift register 300 is used as an example to describe the signal timing sequence above, the above signal timing sequence is also applicable to other shift registers in the embodiments of the present disclosure.
  • the shift register 400 can operate in a similar manner to the above based on the signal timing of FIG. 13, the difference is that, in the period P5, the second control signal terminal is at a low level, and the high level of the pull-down node PD makes the first The five transistors T5 are turned on, thereby pulling down the output signal terminal OUT to the low level of the reference signal terminal VGL.
  • FIG. 14 shows a signal timing diagram of a gate driving circuit in a display stage according to an embodiment of the present disclosure.
  • the signal timing of FIG. 14 is applicable to the gate driving circuit 500 described above.
  • sequentially shifted 8 clock signals CK1 to CK8 are provided to the gate driving circuit 500 , and each shift register GOA1 to GOAN in the gate driving circuit 500 may be, for example, in the manner described above with reference to FIG. 13 . It operates so as to output gate driving signals at the respective output signal terminals OUT based on the clock signals at the respective clock signal terminals CK under the control of the potentials of the respective input control terminals STV.
  • the N gate driving signals generated by the shift registers GOA1 to GOAN are respectively supplied to the gate lines G1 to GN connected thereto.
  • the clock signals CK1 to CK8 are periodic signals with a duty ratio of 12.5% and a pulse width of a unit scan time, where the k+1th clock signal is shifted by a unit scan time relative to the kth clock signal, where k is Integer, 1 ⁇ k ⁇ 7.
  • the so-called unit scan time refers to the time required for the gate driving circuit to scan a row of pixels. Taking a display panel with 8K resolution as an example, the sub-pixels in the display area of the display panel are arranged in a 7680 ⁇ 4320 array.
  • the scanning time of one frame is 1/60 second, that is, 4320 lines of sub-pixels are scanned.
  • the unit scan time H is about 1.85 ⁇ s.
  • FIG. 15 shows a signal timing diagram of a gate driving circuit in a display stage according to another embodiment of the present disclosure.
  • the signal timings of FIG. 15 are applicable to the gate driving circuit 600 described above.
  • the sequentially shifted 4 clock signals CK1 to CK4 are provided to the gate driving circuit 600 , and each shift register GOA1 to GOAN in the gate driving circuit 600 may be, for example, in the manner described above with reference to FIG. 13 . It operates so as to output gate driving signals at the respective output signal terminals OUT based on the clock signals at the respective clock signal terminals CK under the control of the potentials of the respective input control terminals STV.
  • the N gate driving signals generated by the shift registers GOA1 to GOAN are respectively supplied to the gate lines G1 to GN connected thereto.
  • the clock signals CK1 to CK4 are periodic signals with a duty ratio of 25% and a pulse width of a unit scan time, where the k+1th clock signal is shifted by a unit scan time relative to the kth clock signal, where k is Integer, 1 ⁇ k ⁇ 3.
  • FIG. 16 shows an operation timing diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the operation timing diagram of FIG. 16 is applicable to the gate driving circuit of any of the above-mentioned embodiments, and the above-mentioned shift register 300 is used in the gate driving circuit.
  • the operating sequence of Figure 16 covers the power-on phase, the display phase, and the power-off phase. For example, when the gate drive circuit is turned on, it enters the power-on stage; after the power-on is completed, it enters the display stage, and each shift register in the gate drive circuit works in the manner described above with reference to FIG. 13 to drive the sub-pixels for display; The power-down phase is entered when the gate drive circuit is turned off.
  • the second control signal is at a low level, so that the second control signal terminal EN of each shift register is at a low level.
  • the low level of the second control signal terminal EN turns off the first transistor T1 and the second transistor T2, and thus does not affect the display operation of the shift register.
  • the second control signal and the power supply signal provided to the gate driving circuit are at a high level, so that the second control signal terminal EN and the power supply signal terminal VGH of each shift register are at a high level, respectively.
  • Other signals provided to the gate drive circuit such as total reset signal, input signal, reset signal, enable signals STV1 to STVx (eg STV1 to STV4 in Figure 5, or STV1 and STV2 in Figure 6), K clock signals and the reference signal are both low level, so that the total reset signal terminal RESET, the input signal terminal CN, the reset signal terminal CNB, the clock signal terminal CK, the first control signal terminal CKB and the reference signal terminal VGL of each shift register are all low level.
  • each shift register referring to FIG.
  • the high level of the second control signal terminal EN makes the first transistor T1 and the second transistor T2 conductive, so that the high level at the second control signal terminal EN is provided to The output signal terminal thus outputs a high level output signal, and the low level at the reference signal terminal VGL is supplied to the pull-down node PD. Since each of the shift registers GOA1 to GOAN in the gate drive circuit outputs a high level, the cascade connection makes the input control terminal STV and the reset control terminal RST of each shift register are both high level, and the eleventh transistor T11 and the thirteenth transistor T13 are turned on, thereby supplying the low level at the input signal terminal CN and the reset signal terminal CNB to the pull-up node PU1.
  • the tenth transistor T10 Since the power signal terminal VGH is at a high level, the tenth transistor T10 is turned on, so that the second pull-up node PU2 is also at a low level.
  • the gate drive circuit is powered off, so that the output signal terminal OUT of each shift register is at a high level, the first pull-up node PU1 and the second pull-up node PU2 are at a high level, and the pull-down node is at a high level. to low level.
  • the power-on operation may not be required, and the gate driving circuit may enter the display stage to perform display driving after being started.
  • the embodiments of the present disclosure are not limited to this, and other signal timing sequences may be used to perform the power-on operation in the power-on phase, which will be described in further detail below.
  • FIG. 17 shows an operation timing diagram of a gate driving circuit according to another embodiment of the present disclosure.
  • the operation timing diagram of FIG. 17 is applicable to the gate driving circuit of any of the above-mentioned embodiments, and the above-mentioned shift register 400 is used in the gate driving circuit.
  • the working sequence of Fig. 17 is similar to that of Fig. 16, the difference is at least in the power-off phase. In order to simplify the description, the different parts will be mainly described in detail below.
  • the second control signal is at a low level, so that the second control signal terminal EN of each shift register is at a low level.
  • the pull-down node PD is at a high level
  • the fifth transistor T5 is turned on, and the low level of the second control signal terminal EN is provided to the output signal terminal OUT to pull down the potential of the output signal terminal OUT. .
  • the second control signal, power supply signal and K clock signals provided to the gate driving circuit are at high level, respectively making the second control signal terminal EN, power supply signal terminal VGH, and clock signal of each shift register.
  • the terminal CK and the first control signal terminal CKB are at a high level.
  • Other signals supplied to the gate drive circuit such as overall reset signal, input signal, reset signal, enable signals STV1 to STVx (eg STV1 to STV4 in Figure 5, or STV1 and STV2 in Figure 6) and reference signals are all Low level, so that the total reset signal terminal RESET, the input signal terminal CN, the reset signal terminal CNB and the reference signal terminal VGL of each shift register are all low level.
  • STV1 to STVx eg STV1 to STV4 in Figure 5, or STV1 and STV2 in Figure 6
  • reference signals are all Low level, so that the total reset signal terminal RESET, the input signal terminal CN, the reset signal terminal CNB and the reference signal terminal VGL of each shift register are all low level.
  • the high level of the first control signal terminal CKB causes the seventh transistor T7 to be turned on, so that the pull-down node PD is at a high level. Pulling down the high level of the node PD turns on the fifth transistor T5, thereby providing the high level at the second control signal terminal EN to the output signal terminal OUT. Since the output signal terminal OUT of each shift register outputs a high level, the cascade connection makes the input control terminal STV and reset control terminal RST of each shift register both high level, so that the input signal terminal CN and the reset signal are connected to the high level.
  • the low level of the terminal CNB is supplied to the first pull-up node PU1.
  • the tenth transistor T10 is turned on, and the second pull-up node PU2 is also at a low level.
  • the pull-up nodes PU1 and PU2 of each shift register are at a low level, and the pull-down node PD is at a high level.
  • FIG. 18 shows a timing diagram of a gate driving circuit in a power-up phase according to another embodiment of the present disclosure.
  • the total reset signal, K clock signals and power supply signals provided to the gate drive circuit are at high level, so that the total reset signal terminal RESET and the clock signal terminal of each shift register are at a high level.
  • CK, the first control signal terminal CKB and the power signal terminal VGH are at high level.
  • the high level of the first control signal terminal CKB turns on the seventh transistor T7, so that the pull-down node PD is at a high level.
  • the pull-up node can be reset to a low level, and the pull-down node can be reset to a high level, so that the pull-up node is pulled down again before entering the display stage, which further alleviates the influence of the display due to the abnormal potential of the pull-up node.
  • 19A illustrates a signal timing diagram of a display panel according to an embodiment of the present disclosure.
  • the signal timing of FIG. 19 is applicable to the display panel of any of the above embodiments, such as the display panel 1100 described above with reference to FIG. 11 .
  • the signal timing of 19A will be described below with reference to the display panel 1100 of FIG. 11 .
  • the gate driving circuit 1110 provides gate driving signals to a plurality of rows of sub-pixels in the array through a plurality of gate lines G1 to GN under the control of K clock signals, so as to connect the sub-pixels in the plurality of rows of pixels with gate driving signals. At least one row of subpixels is turned on.
  • the multiplexing circuit 1130 multiplexes the received m input data signals into M output data signals under the control of the first selection signal MUX1 and the second selection signal MUX2, and provides them to the data lines D1 to DM, respectively, so as to be provided to the data lines D1 to DM.
  • M columns of sub-pixels in the array make the at least one row of sub-pixels turned on emit light based on the received output data signal, wherein m and M are integers greater than 1, and M is an integer multiple of m.
  • the gate line G1 is at a high level, and the sub-pixels in the first row are turned on.
  • the first selection signal line MUX1 is at a high level, and the multiplexing circuit 1130 provides the received m input data signals to the m odd-numbered columns of data lines D_o (including D1, D3 , D5 .
  • the high level of the second selection signal line MUX2 comes, and the multiplexing circuit 1130 provides the received m input data signals to the m even-numbered columns of data lines D_e (including D2, D4, D6, .
  • the gate line G2 of the sub-pixels in the second row is at a high level
  • the sub-pixels in the second row are turned on, and the first selection signal MUX1 and the second selection signal MUX2 are successively at a high level, so that the first selection signal MUX1 and the second selection signal MUX2 are at a high level.
  • Data is written to the sub-pixels located in the odd-numbered columns in the sub-pixels of the second row, and then data is written to the sub-pixels located in the even-numbered columns of the sub-pixels of the second column, and so on.
  • FIG. 19B shows a schematic diagram of signal waveforms of a display panel according to an embodiment of the present disclosure.
  • the pulse width of the gate driving signal GATE ie, from the start point of the rising edge of the gate driving signal GATE to the end point of the falling edge
  • the time length is H
  • H represents the unit scan time.
  • the gate driving signal GATE may represent any gate driving signal in the gate driving circuit, for example, any one of the above-mentioned G1 to GN.
  • first time interval GAP1 between the starting point of the rising edge of the gate driving signal GATE and the starting point of the rising edge of the first selection signal MUX1
  • second selection signal There is a second time interval GAP2 between the ending point of the falling edge of MUX2 and the starting point of the falling edge of the gate driving signal GATE, and the ending point of the falling edge of the first selection signal MUX1 and the starting point of the rising edge of the second selection signal MUX2
  • third time interval GAP3 between the starting points.
  • the rise time Tr of the gate driving signal GATE is relatively large, so that a certain period of time after the first selection signal MUX1 becomes a high level
  • the gate driving signal GATE has not reached the expected high level within the time, resulting in incomplete turn-on of the sub-pixels.
  • FIG. 20 illustrates a signal timing diagram of a display panel according to another embodiment of the present disclosure.
  • the signal timing diagram of FIG. 20 is applicable to the above-mentioned gate driving circuit using four clock signals, such as the gate driving circuit 600 .
  • the signal timing of FIG. 20 is similar to that of FIG. 15 , except that the four clock signals CK1 to CK4 are periodic signals with a duty ratio of 50% and a pulse width of 2H.
  • the first selection signal MUX1 and the second selection signal MUX2 are periodic signals with a duty ratio of 50% and a pulse width smaller than m/M*H.
  • M 2m
  • the pulse widths of the first selection signal MUX1 and the second selection signal MUX2 are smaller than 1/2*H.
  • the gate driving signal G1 is at a high level, and the sub-pixels in the first row are turned on. This process is also referred to as a precharge phase.
  • the gate driving circuit G1 maintains a high level, and the first selection signal MUX1 and the second selection signal MUX2 successively become a high level, so that the data signals for the first row are written into the first row of sub-pixels that are turned on. .
  • the gate driving signal G2 is also high to precharge the sub-pixels in the second row. The data signal for the first row is written.
  • the precharging process does not substantially affect the normal display of the sub-pixels in the second row, because in the period P3 after the period P2, the sub-pixels in the second row are written in a similar manner to the above for the second row. data signal.
  • the above precharging scheme may have some problems, which will be analyzed and explained below with reference to Figures 21A to 21C.
  • 21A-21C show signal simulation diagrams of the embodiment of FIG. 20 .
  • the output signal terminal OUT of the third-stage shift register GOA3 when the output signal terminal OUT of the third-stage shift register GOA3 is at a high level, it discharges the pull-up node PU of the first-stage shift register GOA1, so that the first-stage shift register GOA1 has a high level.
  • the three transistors T3 are turned off, and at the same time, the CKB of the first-stage shift register GOA1 charges the pull-down node PD, so that the fourth transistor T4 is turned on.
  • the output signal terminal OUT is in a floating state, and at this time the output signal terminal OUT is connected to the pull-down node PD
  • the potential rise occurs due to the effect of the coupling capacitance of , as shown by the dotted line in Figure 21A.
  • the potential of the output signal terminal OUT continues to drop.
  • the discharge capacity is weak, so that the The discharge time of the output signal terminal OUT is relatively long, so the falling period Tf of the generated gate driving signal G1 is relatively long, as shown in FIG. 21A .
  • each clock signal drives 1080 rows of pixels. In this case, as shown in the charging simulation waveform of FIG.
  • the shift register which is farther from the clock signal line
  • the rising edge of the gate driving signal on the gate line of the shift register for example, the gate line Gx connected to the output signal terminal of the last stage of the shift register controlled by CK1
  • the shift closer to the clock signal line There is a large difference between the rising edges of the gate lines of the registers (eg, the gate line G1 connected to the output signal terminal of the first-stage shift register controlled by CK1 ). If the signal line width and signal line material film thickness in the process fluctuate, the RC load on the gate line will fluctuate greatly, and the difference may be larger, and may even cause the product to display different screen splits.
  • the charging rate of the sub-pixels realized in the driving scheme of FIG. 20 is less than 95%.
  • FIG. 22 shows a signal waveform diagram of a display panel according to another embodiment of the present disclosure.
  • the signal timing diagram of FIG. 20 is applicable to the above-mentioned gate driving circuit 500 using 8 clock signals, for example, the gate driving circuit 600 .
  • the signal timing of FIG. 22 is similar to that of FIG. 22 , with the difference at least that the eight clock signals are periodic signals with a duty cycle of 25% and a pulse width of 2H.
  • the first selection signal MUX1 and the second selection signal MUX2 are periodic signals with a duty ratio of 50% and a pulse width of less than 1/2*H.
  • FIG. 23A to 23C show signal simulation diagrams of the embodiment of FIG. 22 .
  • the falling edge of the gate driving signal G1 controlled by the clock signal CK1 and the rising edge of the gate driving signal G5 controlled by the clock signal CK5 do not have Overlap, the falling period Tf of the gate driving signals G1 to GN is smaller than that in FIG. 21A .
  • FIG. 23B shows that, for the above-mentioned 8K display products, if a cascade scheme of 8 clock signals is used, each clock signal drives 540 rows of pixels.
  • the signal waveforms described above with reference to FIGS. 19A to 23 are the signal waveforms of the display panel in the display phase.
  • the signal waveforms of the display panel in the power-on phase and the power-off phase can be selected according to needs.
  • the above reference to FIGS. 16 to 18 can be used.
  • FIG. 24 shows a flowchart of a driving method of a gate driving circuit according to an embodiment of the present disclosure. This method is applicable to the gate driving circuit of any of the above embodiments.
  • step S2401 in the display stage, an input signal of a first level is provided to the gate driving circuit, and each shift register is controlled by the potential of the respective input control terminal STV based on the input signal at the respective output
  • the signal terminal OUT outputs a gate driving signal.
  • step S2402 in the power-off phase, the gate driving circuit is provided with a second control signal of a first level and an input signal of a second level, and each shift register converts the second control signal of the first level to The signal is supplied to the respective output signal terminal OUT, and each shift register supplies the input signal of the second level to the respective pull-up node PU under the control of the potential of the respective input control terminal STV.
  • the pull-down sub-circuit of each shift register is Under the control of the potential of the pull-down node PD of the shift register, the potential of the reference signal terminal VGL of the shift register is provided to the output signal terminal OUT of the shift register;
  • the lower electronic circuit of the bit register provides the second control signal of the first level at the second control signal terminal EN of the shift register to the output signal terminal OUT of the shift register and the reference of the shift register is The potential of the signal terminal VGL is supplied to the pull-down node PD of the shift register.
  • the gate drive circuit is provided with A second control signal of a second level
  • the second control circuit of each shift register provides the second control signal of the second level to all the shift registers under the control of the potential of the pull-down node PD of the shift register
  • the output signal terminal OUT of the shift register; in the power-off stage, K clock signals maintaining the first level are provided to the gate drive circuit, and the first control circuit of each shift register
  • the clock signal of the first level received at the first control signal terminal CKB is provided to the pull-down node PD of the shift register, and the potential of the pull-down node PD causes the second control circuit of the shift register to
  • the second control signal of the first level is provided to the output signal terminal OUT of the shift register.
  • each shift register is based on the input signals and the potential of the respective input control terminal STV under the control of the The received clock signals output gate drive signals at respective output signal terminals OUT, wherein the k+1th clock signal is shifted by the unit scan time relative to the kth clock signal, where k is an integer, 1 ⁇ k ⁇ K- 1.
  • the unit scan time is the time required for the gate driving circuit to scan a row of pixels.

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Abstract

一种移位寄存器、栅极驱动电路、显示面板及其驱动方法。移位寄存器（100）包括：输入电路（110），被配置为在输入控制端（STV）的信号的控制下将输入信号端（CN）的电位输入至上拉节点（PU）；输出电路（120），被配置为在上拉节点（PU）的电位的控制下将时钟信号端（CK）的信号提供至输出信号端（OUT）；第一控制电路（130），被配置为将第一控制信号端（CKB）的电位提供至下拉节点（PD），以及根据上拉节点（PU）的电位将参考信号端（VGL）的电位提供至下拉节点（PD）；以及第二控制电路（140），连接至下拉节点（PD）、第二控制信号端（EN）、输出信号端（OUT）和参考信号端（VGL），并且被配置为在下拉节点（PD）和第二控制信号端（EN）的电位的控制下，在显示阶段下拉输出信号端（OUT）的电位，在下电阶段上拉输出信号端（OUT）的电位。

Description

移位寄存器、栅极驱动电路、显示面板及其驱动方法 技术领域
本公开涉及显示技术领域，具体涉及一种移位寄存器、栅极驱动电路、显示面板及其驱动方法。
背景技术
在显示设备中，通常利用栅极驱动电路来驱动多个子像素进行显示。例如在显示设备开启时，将显示设备中的栅极驱动电路上电，使得栅极驱动电路产生栅极驱动信号，栅极驱动信号被提供给多个子像素，使得子像素开启以便进行显示。在显示设备关闭时，将栅极驱动电路下电，栅极驱动电路通常包括级联连接的多个移位寄存器，以产生顺次移位的多个输出信号作为栅极驱动信号。然而，传统的栅极驱动电路在上电时容易发生显示异常。
发明内容
本公开的实施例提供了一种移位寄存器，包括：
输入电路，连接至输入信号端、输入控制端和所述移位寄存器的上拉节点，并且被配置为在所述输入控制端的信号的控制下将输入信号端的电位输入至所述上拉节点；
输出电路，连接至所述上拉节点、时钟信号端和输出信号端，并且被配置为在所述上拉节点的电位的控制下将时钟信号端的信号提供至所述输出信号端；
第一控制电路，连接至第一控制信号端、所述上拉节点、所述移位寄存器的下拉节点和参考信号端，并且被配置为将所述第一控制信号端的电位提供至所述下拉节点，以及根据所述上拉节点的电位将所述参考信号端的电位提供至所述下拉节点；以及
第二控制电路，连接至所述下拉节点、第二控制信号端、所述输出信号端和所述参考信号端，并且被配置为在所述下拉节点和所述第二控制信号端的电位的控制下，在显示阶段下拉所述输出信号端的电位，在下电阶段上拉所述输出信号端的电位。
例如，所述第二控制电路包括：
下拉子电路，连接至所述下拉节点、所述输出信号端和所述参考信号端，并且被配置为在所述下拉节点的电位的控制下将所述参考信号端的电位提供至所述输出信号端； 以及
下电子电路，连接至所述第二控制信号端、所述下拉节点、所述输出信号端和所述参考信号端，并且被配置为在所述第二控制信号端的信号的控制下，将所述第二控制信号端的电位提供至所述输出信号端并且将所述参考信号端的电位提供至所述下拉节点。
例如，所述下电子电路包括第一晶体管和第二晶体管，其中，
所述第一晶体管的栅极和第一极连接至所述第二控制信号端，所述第一晶体管的第二极连接至所述输出信号端；并且
所述第二晶体管的栅极连接至所述第二控制信号端，所述第二晶体管的第一极连接至所述参考信号端，所述第二晶体管的第二极连接至所述下拉节点。
例如，所述下拉子电路包括第三晶体管和第一电容，其中，
所述第三晶体管的栅极连接至所述下拉节点，所述第三晶体管的第一极连接至所述参考信号端，所述第三晶体管的第二极连接至所述输出信号端；并且
所述第一电容的第一端连接至所述下拉节点，所述第一电容的第二端连接至所述参考信号端。
例如，所述下拉子电路还包括第四晶体管，所述第四晶体管的栅极连接至所述输出信号端，所述第四晶体管的第一极连接至所述参考信号端，所述第四晶体管的第二极连接至所述下拉节点。
例如，所述第二控制电路包括第五晶体管和第二电容，其中，
所述第五晶体管的栅极连接至所述下拉节点，所述第五晶体管的第一极连接至所述第二控制信号端，所述第五晶体管的第二极连接至所述输出信号端；并且
所述第二电容的第一端连接至所述下拉节点，所述第二电容的第二端连接至所述参考信号端。
例如，所述移位寄存器还包括：降噪电路，连接至所述输入控制端、所述下拉节点和所述参考信号端，并且被配置为在所述输入控制端的信号的控制下将所述参考信号端的电位提供至所述下拉节点。
例如，所述降噪电路包括第六晶体管，所述第六晶体管的栅极连接至所述输入控制端，所述第六晶体管的第一极连接至所述参考信号端，所述第六晶体管的第二极连接至所述下拉节点。
例如，所述移位寄存器还包括：复位电路，连接至复位控制端、复位信号端和所述上拉节点，并且被配置为在所述复位控制端的信号的控制下将所述复位信号端的电位提 供至所述上拉节点。
例如，所述上拉节点包括与所述输入电路连接的第一上拉节点以及与所述输出电路连接的第二上拉节点，所述第一控制电路包括第七晶体管、第八晶体管、第九晶体管和第十晶体管，其中，
所述第七晶体管的栅极和第一极连接至所述第一控制信号端，所述第七晶体管的第二极连接至所述下拉节点；
所述第八晶体管的栅极连接至所述下拉节点，所述第八晶体管的第一极连接至所述参考信号端，所述第八晶体管的第二极连接至所述第一上拉节点；
所述第九晶体管的栅极连接至所述第一上拉节点，所述第九晶体管的第一极连接至所述参考信号端，所述第九晶体管的第二极连接至所述下拉节点；并且
所述第十晶体管的栅极连接至电源信号端，所述第十晶体管的第一极连接至所述第一上拉节点，所述第十晶体管的第二极连接至所述第二上拉节点。
例如，所述输入电路包括第十一晶体管，所述第十一晶体管的栅极连接至所述输入控制端，所述第十一晶体管的第一极连接至所述输入信号端，所述第十一晶体管的第二极连接至所述上拉节点。
例如，所述输出电路包括第十二晶体管和第三电容，其中，
所述第十二晶体管的栅极连接至所述上拉节点，所述第十二晶体管的第一极连接至所述时钟信号端，所述第十二晶体管的第二极连接至所述输出信号端；并且
所述第三电容的第一端连接至所述上拉节点，所述第三电容的第二端连接至所述输出信号端。
例如，所述复位电路包括第十三晶体管，所述第十三晶体管的栅极连接至所述复位控制端，所述第十三晶体管的第一极连接至所述复位信号端，所述第十三晶体管的第二极连接至所述上拉节点。
例如，所述移位寄存器还包括总复位电路，连接至总复位信号端、所述上拉节点和所述参考信号端，并且被配置为在所述总复位信号端的信号的控制下将所述参考信号端的电位提供至所述上拉节点。
例如，所述总复位电路包括第十四晶体管，所述第十四晶体管的栅极连接至所述总复位信号端，所述第十四晶体管的第一极连接至所述参考信号端，所述第十四晶体管的第二极连接至所述上拉节点。
本公开的实施例还提供了一种栅极驱动电路，包括N级级联的移位寄存器，每个移 位寄存器为上述移位寄存器，其中，
每个移位寄存器的输入信号端连接为接收输入信号，复位信号端连接为接收复位信号，第二控制信号端连接为接收第二控制信号；
第n级移位寄存器的输入控制端连接至第n-i级移位寄存器的输出信号端，第n级移位寄存器的复位控制端连接至第n+j级移位寄存器的输出信号端；并且
所述N级级联的移位寄存器分为至少一组，每组包括K级级联的移位寄存器，所述K级级联的移位寄存器的时钟信号端分别连接为接收K个时钟信号，所述K级级联的移位寄存器的第一控制信号端分别连接为接收所述K个时钟信号，其中N、K、n、i和j均为整数，1≤n≤N，1＜K≤N。
例如，i＝j＝4，K＝8，所述K个时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号和第八时钟信号，在每组移位寄存器中：
第一级移位寄存器的时钟信号端连接为接收第一时钟信号，第一级移位寄存器的第一控制信号端连接为接收第五时钟信号；
第二级移位寄存器的时钟信号端连接为接收第二时钟信号，第二级移位寄存器的第一控制信号端连接为接收第六时钟信号；
第三级移位寄存器的时钟信号端连接为接收第三时钟信号，第三级移位寄存器的第一控制信号端连接为接收第七时钟信号；
第四级移位寄存器的时钟信号端连接为接收第四时钟信号，第四级移位寄存器的第一控制信号端连接为接收第八时钟信号；
第五级移位寄存器的时钟信号端连接为接收第五时钟信号，第五级移位寄存器的第一控制信号端连接为接收第一时钟信号；
第六级移位寄存器的时钟信号端连接为接收第六时钟信号，第六级移位寄存器的第一控制信号端连接为接收第二时钟信号；
第七级移位寄存器的时钟信号端连接为接收第七时钟信号，第七级移位寄存器的第一控制信号端连接为接收第三时钟信号；
第八级移位寄存器的时钟信号端连接为接收第八时钟信号，第八级移位寄存器的第一控制信号端连接为接收第四时钟信号。
例如，i＝j＝2，K＝4，所述K个时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，在每组移位寄存器中：
第一级移位寄存器的时钟信号端连接为接收第一时钟信号，第一级移位寄存器的第一控制信号端连接为接收第三时钟信号；
第二级移位寄存器的时钟信号端连接为接收第二时钟信号，第二级移位寄存器的第一控制信号端连接为接收第四时钟信号；
第三级移位寄存器的时钟信号端连接为接收第三时钟信号，第三级移位寄存器的第一控制信号端连接为接收第一时钟信号；
第四级移位寄存器的时钟信号端连接为接收第四时钟信号，第四级移位寄存器的第一控制信号端连接为接收第二时钟信号。
本公开的实施例还提供了一种显示面板，包括：
布置成阵列的多个子像素；以及
至少一个上述栅极驱动电路，所述栅极驱动电路中的N级移位寄存器分别连接至所述阵列中的多行子像素。
例如，所述显示面板包括两个所述栅极驱动电路，所述两个栅极驱动电路沿第一方向分别位于所述多个子像素的阵列的两侧，其中所述第一方向为所述阵列的行方向。
例如，所述显示面板包括一个所述栅极驱动电路，其中i＝j＝2，K＝4，所述栅极驱动电路中的奇数级移位寄存器和偶数级移位寄存器沿第一方向分别位于所述多个子像素的阵列的两侧。
例如，所述移位寄存器包括输入电路、第一控制电路、第二控制电路和输出电路，所述输入电路、第一控制电路、第二控制电路和输出电路依次沿第一方向排列，并且所述输入电路、第一控制电路、第二控制电路和输出电路各自在第二方向上的尺寸为所述子像素在第二方向上的尺寸的0.8-1.4倍，其中所述第一方向为所述阵列的行方向，所述第二方向垂直于所述第一方向。
例如，所述显示面板还包括多路复用电路，所述多路复用电路与所述阵列中的M列子像素连接，所述多路复用电路被配置为在第一选择信号和第二选择信号的控制下将接收到的m个输入数据信号复用为M个输出数据信号分别提供给所述M列子像素，其中m和M为大于1的整数，M是m的整数倍。
本公开的实施例还提供了一种上述栅极驱动电路的驱动方法，包括：
在显示阶段，向所述栅极驱动电路提供第一电平的输入信号，每个移位寄存器在各自的输入控制端的电位的控制下基于所述输入信号在各自的输出信号端输出栅极驱动信号；
在下电阶段，向所述栅极驱动电路提供第一电平的第二控制信号和第二电平的输入信号，每个移位寄存器将所述第一电平的第二控制信号提供至各自的输出信号端，并且每个移位寄存器在各自的输入控制端的电位的控制下将所述第二电平的输入信号提供至各自的上拉节点。
例如，每个移位寄存器的第二控制电路包括下拉子电路和下电子电路，其中，
在所述显示阶段，每个移位寄存器的下拉子电路在所述移位寄存器的下拉节点的电位的控制下将所述移位寄存器的参考信号端的电位提供至所述移位寄存器的输出信号端；以及
在所述下电阶段，每个移位寄存器的下电子电路将所述移位寄存器的第二控制信号端处第一电平的第二控制信号提供至所述移位寄存器的输出信号端并且将所述移位寄存器的参考信号端的电位提供至所述移位寄存器的下拉节点。
例如，每个移位寄存器的第二控制电路包括第五晶体管和第二电容，其中，
在所述显示阶段，向所述栅极驱动电路提供第二电平的第二控制信号，每个移位寄存器的第二控制电路在所述移位寄存器的下拉节点的电位的控制下将所述第二电平的第二控制信号提供至所述移位寄存器的输出信号端；
在所述下电阶段，向所述栅极驱动电路提供保持第一电平的K个时钟信号，每个移位寄存器的第一控制电路将所述移位寄存器的第一控制信号端处接收到的第一电平的时钟信号提供至所述移位寄存器的下拉节点，所述下拉节点的电位使所述移位寄存器的第二控制电路将所述第一电平的第二控制信号提供至所述移位寄存器的输出信号端。
例如，在所述显示阶段，向所述栅极驱动电路提供顺序移位的K个时钟信号，每个移位寄存器在各自的输入控制端的电位的控制下基于所述输入信号和接收到的时钟信号在各自的输出信号端输出栅极驱动信号，其中第k+1时钟信号相对于第k时钟信号移位单位扫描时间，其中k为整数，1≤k≤K-1，所述单位扫描时间为所述栅极驱动电路扫描一行像素所需的时间。
例如，所述栅极驱动电路中i＝j＝4且K＝8，在所述显示时段，所述K个时钟信号是占空比为25％且脉冲宽度为2倍单位扫描时间的周期信号。
例如，所述栅极驱动电路中i＝j＝2且K＝4，在所述显示时段，所述K个时钟信号是占空比为50％且脉冲宽度为2倍单位扫描时间的周期信号。
例如，所述栅极驱动电路中i＝j＝4且K＝8，在所述显示时段，所述K个时钟信号是占空比为12.5％且脉冲宽度为单位扫描时间的周期信号。
例如，所述栅极驱动电路中i＝j＝2且K＝4，在所述显示时段，所述K个时钟信号是占空比为25％且脉冲宽度为单位扫描时间的周期信号。
附图说明
图1示出了根据本公开实施例的移位寄存器的框图。
图2A示出了根据本公开一实施例的移位寄存器的电路图。
图2B示出了根据本公开另一实施例的移位寄存器的电路图。
图2C示出了根据本公开另一实施例的移位寄存器的电路图。
图2D示出了根据本公开另一实施例的移位寄存器的电路图。
图3示出了根据本公开另一实施例的移位寄存器的电路图。
图4示出了根据本公开另一实施例的移位寄存器的电路图。
图5示出了根据本公开一实施例的栅极驱动电路的示意图。
图6示出了根据本公开另一实施例的栅极驱动电路的示意图。
图7A示出了根据本公开一实施例的显示面板的示意图。
图7B示出了图7A的显示面板的布局的示意图。
图7C示出了图7B中的移位寄存器的布局的示意图。
图8示出了根据本公开另一实施例的显示面板的示意图。
图9示出了根据本公开另一实施例的显示面板的示意图。
图10示出了根据本公开另一实施例的显示面板的示意图。
图11示出了根据本公开另一实施例的显示面板的示意图。
图12示出了根据本公开实施例的多路复用电路的电路图。
图13示出了根据本公开实施例的移位寄存器在显示阶段的信号时序图。
图14示出了根据本公开实施例的栅极驱动电路在显示阶段的信号时序图。
图15示出了根据本公开另一实施例的栅极驱动电路在显示阶段的信号时序图。
图16示出了根据本公开实施例的栅极驱动电路的工作时序图。
图17示出了根据本公开另一实施例的栅极驱动电路的工作时序图。
图18示出了根据本公开另一实施例的栅极驱动电路在上电阶段的时序图。
图19A示出了根据本公开实施例的显示面板的信号时序图。
图19B示出了根据本公开实施例的显示面板的信号波形的示意图。
图19C示出了根据本公开实施例的显示面板的信号波形的仿真图。
图20示出了根据本公开另一实施例的显示面板的信号时序图。
图21A至21C示出了图20的实施例的信号仿真图。
图22示出了根据本公开另一实施例的显示面板的信号波形图。
图23A至23C示出了图22的实施例的信号仿真图。
图24示出了根据本公开实施例的栅极驱动电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。例如，下文中以“第一电平”为高电平、“第二电平”为低电平为例进行描述。本领域技术人员可以理解，本公开不局限于此。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。优选地，本公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管或低温多晶硅(LTPS，Low Temperature Poly-silicon)薄膜晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。在以下示例中以N型薄膜晶体管为例进行描述。本领域技术人员可以理解，本公开实施例显然可以应用于P型薄 膜晶体管的情况。
图1示出了根据本公开实施例的移位寄存器的框图。
如图1所示，移位寄存器100包括输入电路110、输出电路120、第一控制电路130和第二控制电路140。
输入电路110连接至输入信号端CN、输入控制端STV和上拉节点PU。输入电路110可以在输入控制端STV的信号的控制下将输入信号端CN的电位输入至上拉节点PU。
输出电路120连接至上拉节点PU、时钟信号端CK和输出信号端OUT。输出电路120可以在上拉节点PU的电位的控制下将时钟信号端CK的信号提供至输出信号端OUT。
第一控制电路130连接至第一控制信号端CKB、上拉节点PU、下拉节点PD和参考信号端VGL。第一控制电路130可以将第一控制信号端CKB的电位提供至下拉节点PD，以及根据上拉节点PU的电位将参考信号端VGL的电位提供至所述下拉节点PD。
第二控制电路140连接至下拉节点PD、第二控制信号端EN、输出信号端OUT和参考信号端VGL。第二控制电路140可以在下拉节点PD和第二控制信号端EN的电位的控制下，在显示阶段下拉输出信号端OUT的电位，在下电阶段上拉输出信号端OUT的电位。
通常，移位寄存器在下电过程中将所有信号端(例如输入控制端、输入信号端、第一控制信号端、时钟信号端和参考信号端等等)均置于有效电平(例如高电平)，使得在输出信号端输出高电平，从而实现电荷释放。
本公开的实施例通过设置与单独的第二控制信号端连接的第二控制电路，可以基于该第二控制信号端的信号来控制输出信号端的电位的上拉和下拉，使得移位寄存器在下电时无需将所有信号端都置于有效电平(例如高电平)即可实现电荷释放。而由于在下电时无需所有信号端都置于有效电平，在下电阶段可以根据需要来设置上拉节点的电平，例如可以将上拉节点设置为无效电平(例如低电平)，这样当移位寄存器再次上电时，不会由于上电过程不支持上拉节点的复位而导致上电期间产生不期望的输出。
图2A示出了根据本公开一实施例的移位寄存器的电路图。
如图2A所示，移位寄存器200A包括输入电路210、输出电路220、第一控制电路230和第二控制电路240。以上对于输入电路110、输出电路120、第一控制电路130和第二控制电路140同样分别适用于输入电路210、输出电路220、第一控制电路230和第 二控制电路240。
输入电路210包括第十一晶体管T11，第十一晶体管T11的栅极连接至输入控制端STV，第十一晶体管T11的第一极连接至输入信号端CN，第十一晶体管T11的第二极连接至上拉节点PU。
输出电路220包括第十二晶体管T12和第三电容C3。第十二晶体管T12的栅极连接至上拉节点PU，第十二晶体管T12的第一极连接至时钟信号端CK，第十二晶体管T12的第二极连接至输出信号端OUT。第三电容C3的第一端连接至上拉节点PU，第三电容C3的第二端连接至输出信号端OUT。
第一控制电路230包括第七晶体管T7、第八晶体管T8和第九晶体管T9。第七晶体管T7的栅极和第一极连接至第一控制信号端CKB，第七晶体管T7的第二极连接至下拉节点PD。第八晶体管T8的栅极连接至下拉节点PD，第八晶体管T8的第一极连接至参考信号端VGL，第八晶体管T8的第二极连接至上拉节点PU。第九晶体管T9的栅极连接至上拉节点PU，第九晶体管T9的第一极连接至参考信号端VGL，第九晶体管T9的第二极连接至下拉节点PD。
在图2A中，移位寄存器200A还包括复位电路250。复位电路250包括第十三晶体管T13，第十三晶体管T13的栅极连接至复位控制端RST，第十三晶体管T13的第一极连接至复位信号端CNB，第十三晶体管T13的第二极连接至上拉节点PU。复位电路250和输入电路210可以互换使用，以实现正扫和反扫。例如，在正扫的情况下，在输入信号端CN施加高电平信号，在复位信号端CNB施加低电平信号，输入电路210基于输入信号端CN的高电平向上拉节点PU提供高电平输入，复位电路250基于复位信号端CNB的低电平将上拉节点PU复位至低电平。在反扫的情况下，在输入信号端CN施加低电平信号，在复位信号端CNB施加高电平信号，复位电路250基于复位信号端CNB的高电平向上拉节点PU提供高电平输入，输入电路210基于输入信号端CN的低电平将上拉节点PU复位至低电平。
图2B示出了根据本公开另一实施例的移位寄存器的电路图。图2B的移位寄存器200B与上述移位寄存器200A类似，为了简明起见，下面主要对区别部分进行详细说明。
与移位寄存器200A类似，移位寄存器200B包括输入电路210、输出电路220、第一控制电路230’和复位电路250。与图2A的移位寄存器200A不同，移位寄存器200B的上拉节点有两个，分别是第一上拉节点PU1和第二上拉节点PU2。第一上拉节点PU1与输入电路210连接，第二上拉节点PU2与输出电路220连接。第一控制电路230’除 了包括第七晶体管T7、第八晶体管T8和第九晶体管T9之外，还包括连接在第一上拉节点PU1和第二上拉节点PU2之间的第十晶体管T10。如图2B所示，第十晶体管T10的栅极连接至电源信号端VGH，第十晶体管T10的第一极连接至第一上拉节点PU1，第十晶体管T10的第二极连接至第二上拉节点PU2。第七晶体管T7的栅极和第一极连接至第一控制信号端CKB，第七晶体管T7的第二极连接至下拉节点PD。第八晶体管T8的栅极连接至下拉节点PD，第八晶体管T8的第一极连接至参考信号端VGL，第八晶体管T8的第二极连接至第一上拉节点PU1。第九晶体管T9的栅极连接至第一上拉节点PU1，第九晶体管T9的第一极连接至参考信号端VGL，第九晶体管T9的第二极连接至下拉节点PD。当电源信号端VGH为高电平时，第十晶体管T10导通，从而将第一上拉节点PU1与第二上拉节点PU2电连接；当电源信号端VGH为低电平时，第十晶体管T10关断，从而将第一上拉节点PU1和第二上拉节点PU2电隔离。通过设置第十晶体管T10，可以根据需要将第一上拉节点PU1和第二上拉节点PU2电隔离或电连接，从而在需要时避免用于控制输出电路320的第二上拉节点PU2的电位受到其他电路的影响。
在图2B的移位寄存器200B中，第二控制电路包括下拉子电路2401和下电子电路2402。
下拉子电路2401连接至下拉节点PD、输出信号端OUT和参考信号端VGL。下拉子电路2401可以在下拉节点PD的电位的控制下将参考信号端VGL的电位提供至输出信号端OUT。在图2B中，下拉子电路2401包括第三晶体管T3和第一电容C1。第三晶体管T3的栅极连接至下拉节点PD，第三晶体管T3的第一极连接至参考信号端VGL，第三晶体管T3的第二极连接至输出信号端OUT。第一电容C1的第一端连接至下拉节点PD，第一电容C1的第二端连接至参考信号端VGL。
下电子电路2402连接至第二控制信号端EN、下拉节点PD、输出信号端OUT和参考信号端VGL。下电子电路2402可以在第二控制信号端EN的信号的控制下，将第二控制信号端EN的电位提供至输出信号端OUT并且将参考信号端VGL的电位提供至下拉节点PD。在图2B中，下电子电路2402可以包括第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极和第一极连接至第二控制信号端EN，第一晶体管T1的第二极连接至输出信号端OUT。第二晶体管T2的栅极连接至第二控制信号端EN，第二晶体管T2的第一极连接至参考信号端VGL，第二晶体管T2的第二极连接至下拉节点PD。
在一些实施例中，如图2B所示，下拉子电路2401还可以包括第四晶体管T4，第 四晶体管T4的栅极连接至输出信号端OUT，第四晶体管T4的第一极连接至参考信号端VGL，第四晶体管T4的第二极连接至下拉节点PD。当输出信号端OUT为高电平时，第四晶体管T4导通，从而将下拉节点PD下拉至参考信号端VGL的低电平。第四晶体管T4起到了进一步稳定下拉节点PD的电位的作用。
在一些实施例中，如图2B所示，移位寄存器200B还包括总复位电路270。总复位电路270连接至总复位信号端RESET、第一上拉节点PU1和参考信号端VGL。总复位电路370可以在总复位信号端RESET的信号的控制下将参考信号端VGL的电位提供至第一上拉节点PU1。在图2B中，总复位电路270包括第十四晶体管T14，第十四晶体管T14的栅极连接至总复位信号端RESET，第十四晶体管T14的第一极连接至参考信号端VGL，第十四晶体管T14的第二极连接至第一上拉节点PU1。当总复位信号端RESET为高电平时，第十四晶体管T14导通，从而将第一上拉节点PU1复位至参考信号端VGL处的低电平。
图2C示出了根据本公开另一实施例的移位寄存器的电路图。与移位寄存器200B类似，移位寄存器200C包括输入电路210、输出电路220、第一控制电路230’、复位电路250和总复位电路270。
与移位寄存器200B不同，移位寄存器200C的第二控制电路240’包括第五晶体管T5和第二电容C2。第五晶体管T5的栅极连接至下拉节点PD，第五晶体管T5的第一极连接至第二控制信号端EN，第五晶体管T5的第二极连接至输出信号端OUT。第二电容C2的第一端连接至下拉节点PD，第二电容C2的第二端连接至参考信号端VGL。
图2D示出了根据本公开另一实施例的移位寄存器的电路图。图2D的移位寄存器200D与移位寄存器200B类似，区别至少在于第二控制电路240”的结构以及还包括降噪电路260。
如图2D所示，降噪电路260连接至输入控制端STV、下拉节点PD和参考信号端VGL。降噪电路260可以在输入控制端STV的信号的控制下将参考信号端VGL的电位提供至下拉节点PD。在图2D中，降噪电路260包括第六晶体管T6，第六晶体管T6的栅极连接至输入控制端STV，第六晶体管T6的第一极连接至参考信号端VGL，第六晶体管T6的第二极连接至下拉节点PD。
在图2D中，第二控制电路240”包括第三晶体管T3、第四晶体管T4和第一电容C1。第三晶体管T3的栅极连接至下拉节点PD，第三晶体管T3的第一极连接至第二控制信号端EN，第三晶体管T3的第二极连接至输出信号端OUT。第一电容C1的第一端 连接至下拉节点PD，第一电容C1的第二端连接至参考信号端VGL。第四晶体管T4的栅极连接至输出信号端OUT，第四晶体管T4的第一极连接至参考信号端VGL，第四晶体管T4的第二极连接至下拉节点PD。当然本公开的实施例不限于此，在一些实施例中，第三晶体管T3的第一极可以连接至参考信号端VGL，而非第二控制信号端EN。
图3示出了根据本公开另一实施例的移位寄存器的电路图。图3的移位寄存器300与上述移位寄存器200A类似，为了简明起见，下面主要对区别部分进行详细说明。
与移位寄存器200A类似，移位寄存器300包括输入电路310、输出电路320、第一控制电路330和复位电路350，上文中对于输入电路210、输出电路220、第一控制电路230和复位电路250的描述同样适用于输入电路310、输出电路320、第一控制电路330和复位电路350。
与图2A的移位寄存器200A不同，移位寄存器300的上拉节点有两个，分别是第一上拉节点PU1和第二上拉节点PU2。第一上拉节点PU1与输入电路310连接，第二上拉节点PU2与输出电路320连接。第一控制电路除了包括第七晶体管T7、第八晶体管T8和第九晶体管T9之外，还包括连接在第一上拉节点PU1和第二上拉节点PU2之间的第十晶体管T10。如图3所示，第十晶体管T10的栅极连接至电源信号端VGH，第十晶体管T10的第一极连接至第一上拉节点PU1，第十晶体管T10的第二极连接至第二上拉节点PU2。第七晶体管T7的栅极和第一极连接至第一控制信号端CKB，第七晶体管T7的第二极连接至下拉节点PD。第八晶体管T8的栅极连接至下拉节点PD，第八晶体管T8的第一极连接至参考信号端VGL，第八晶体管T8的第二极连接至第一上拉节点PU1。第九晶体管T9的栅极连接至第一上拉节点PU1，第九晶体管T9的第一极连接至参考信号端VGL，第九晶体管T9的第二极连接至下拉节点PD。当电源信号端VGH为高电平时，第十晶体管T10导通，从而将第一上拉节点PU1与第二上拉节点PU2电连接；当电源信号端VGH为低电平时，第十晶体管T10关断，从而将第一上拉节点PU1和第二上拉节点PU2电隔离。通过设置第十晶体管T10，可以根据需要将第一上拉节点PU1和第二上拉节点PU2电隔离或电连接，从而在需要时避免用于控制输出电路320的第二上拉节点PU2的电位受到其他电路的影响。
在图3中，第二控制电路包括下拉子电路3401和下电子电路3402。
下拉子电路3401连接至下拉节点PD、输出信号端OUT和参考信号端VGL。下拉子电路3401可以在下拉节点PD的电位的控制下将参考信号端VGL的电位提供至输出信号端OUT。在图3中，下拉子电路3401包括第三晶体管T3和第一电容C1。第三晶 体管T3的栅极连接至下拉节点PD，第三晶体管T3的第一极连接至参考信号端VGL，第三晶体管T3的第二极连接至输出信号端OUT。第一电容C1的第一端连接至下拉节点PD，第一电容C1的第二端连接至参考信号端VGL。
下电子电路3402连接至第二控制信号端EN、下拉节点PD、输出信号端OUT和参考信号端VGL。下电子电路3402可以在第二控制信号端EN的信号的控制下，将第二控制信号端EN的电位提供至输出信号端OUT并且将参考信号端VGL的电位提供至下拉节点PD。在图3中，下电子电路3402可以包括第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极和第一极连接至第二控制信号端EN，第一晶体管T1的第二极连接至输出信号端OUT。第二晶体管T2的栅极连接至第二控制信号端EN，第二晶体管T2的第一极连接至参考信号端VGL，第二晶体管T2的第二极连接至下拉节点PD。
在一些实施例中，如图3所示，下拉子电路3401还可以包括第四晶体管T4，第四晶体管T4的栅极连接至输出信号端OUT，第四晶体管T4的第一极连接至参考信号端VGL，第四晶体管T4的第二极连接至下拉节点PD。当输出信号端OUT为高电平时，第四晶体管T4导通，从而将下拉节点PD下拉至参考信号端VGL的低电平。第四晶体管T4起到了进一步稳定下拉节点PD的电位的作用。
在一些实施例中，如图3所示，移位寄存器还包括降噪电路360。降噪电路360连接至输入控制端STV、下拉节点PD和参考信号端VGL。降噪电路360可以在输入控制端STV的信号的控制下将参考信号端VGL的电位提供至下拉节点PD。在图3中，降噪电路包括第六晶体管T6，第六晶体管T6的栅极连接至输入控制端STV，第六晶体管T6的第一极连接至参考信号端VGL，第六晶体管T6的第二极连接至下拉节点PD。
在没有降噪电路360的情况下，在输入控制端STV处于高电平时，第十一晶体管T11导通，输入信号端CN处的高电平被输入至第一上拉节点PU1，从而使第九晶体管T9导通。在此期间，第一控制信号端CKB处的高电平使第七晶体管T7处于导通状态，第七晶体管T7与第九晶体管T9形成了直流通路。由于第九晶体管T9的沟道宽长比W/L是第七晶体管的沟道宽长比W/L的至少两倍，第七晶体管T7的电阻大于第九晶体管T9的电阻，下拉节点PD在电阻分压的作用下处于一个中间电平，该中间电平接近但是大于参考信号端VGL处的低电平。下拉节点PD处的中间电平会导致第八晶体管T8导通，从而拉低第一上拉节点PU1的电位。
通过设置降噪电路360，当输入控制端STV处于高电平时，第六晶体管T6导通，从而利用参考信号端VGL的低电平来进一步下拉下拉节点PD的电位，进而缓解或避 免上述由于下拉节点PD的电位不够低而影响第一上拉节点PU1的电位的问题，改善了上拉节点PU与下拉节点PD的竞争关系。
在一些实施例中，如图3所示，移位寄存器300还包括总复位电路370。总复位电路370连接至总复位信号端RESET、第一上拉节点PU1和参考信号端VGL。总复位电路370可以在总复位信号端RESET的信号的控制下将参考信号端VGL的电位提供至第一上拉节点PU1。在图3中，总复位电路370包括第十四晶体管T14，第十四晶体管T14的栅极连接至总复位信号端RESET，第十四晶体管T14的第一极连接至参考信号端VGL，第十四晶体管T14的第二极连接至第一上拉节点PU1。当总复位信号端RESET为高电平时，第十四晶体管T14导通，从而将第一上拉节点PU1复位至参考信号端VGL处的低电平。
图4示出了根据本公开另一实施例的移位寄存器的电路图。图4的移位寄存器400与图3的移位寄存器300类似，区别至少在于第二控制电路440。为了简明起见，下面将主要对区别部分进行详细描述。
与移位寄存器300类似，移位寄存器400包括输入电路410、输出电路420、第一控制电路430、复位电路450、降噪电路460和总复位电路470，上文中对于输入电路310、输出电路320、第一控制电路330、复位电路350、降噪电路360和总复位电路370的描述同样适用于输入电路410、输出电路420、第一控制电路430、复位电路450、降噪电路460和总复位电路470。
与移位寄存器300不同，移位寄存器400的第二控制电路440包括第五晶体管T5和第二电容C2。第五晶体管T5的栅极连接至下拉节点PD，第五晶体管T5的第一极连接至第二控制信号端EN，第五晶体管T5的第二极连接至输出信号端OUT。第二电容C2的第一端连接至下拉节点PD，第二电容C2的第二端连接至参考信号端VGL。
图5示出了根据本公开一实施例的栅极驱动电路的示意图。
如图5所示，栅极驱动电路500包括N级级联的移位寄存器，为了便于描述，图5中示出了8个移位寄存器GOA1至GOA8，然而本公开的实施例不限于此，移位寄存器的数量可以根据需要设置。每个移位寄存器GOA1至GOA8可以由上述任意实施例的移位寄存器来实现，例如移位寄存器100、200A、200B、200C、200D、300或400。
移位寄存器GOA1至GOA8各自的输入信号端CN连接为接收输入信号CN，复位信号端CNB连接为接收复位信号CNB，第二控制信号端EN连接为接收第二控制信号EN。这里需要说明的是，由于各个移位寄存器的输入信号端CN接收同一输入信号， 为了简化描述，本文将输入信号与输入信号端用同一附图标记CN来表示，出于同样的原因，复位信号端和复位信号均由CNB表示，第二控制信号端EN和第二控制信号均由EN表示。
根据本公开的实施例，第n级移位寄存器的输入控制端STV连接至第n-i级移位寄存器的输出信号端OUT，第n级移位寄存器的复位控制端RST连接至第n+j级移位寄存器的输出信号端OUT。
在图5中，i＝j＝4，第n级移位寄存器的输入控制端STV连接至第n-4级移位寄存器的输出信号端OUT，第n级移位寄存器的复位控制端RST连接至第n+4级移位寄存器的输出信号端OUT，例如第1级移位寄存器GOA1的输出信号端OUT连接至第5级移位寄存器GOA5的输入控制端STV，第2级移位寄存器GOA2的输出信号端OUT连接至第6级移位寄存器GOA6的输入控制端STV，以此类推。第1级移位寄存器GOA1的复位控制端RST连接至第5级移位寄存器GOA5的输出信号端OUT，第2级移位寄存器GOA2的复位控制端RST连接至第6级移位寄存器GOA6的输出信号端OUT，以此类推。第一级至第四级移位寄存器GOA1至GOA4的输入信号端STV分别连接为接收启动信号STV1至STV4。
根据本公开的实施例，N级级联的移位寄存器分为至少一组，每组包括K级级联的移位寄存器，所述K级级联的移位寄存器的时钟信号端CK分别连接为接收K个时钟信号，所述K级级联的移位寄存器的第一控制信号端CKB分别连接为接收所述K个时钟信号，其中N、K、n、i和j均为整数，1≤n≤N，1＜K≤N。在图5中，K＝8，每组移位寄存器包括8个移位寄存器，例如第一级至第八级移位寄存器GOA1至GOA8作为一组，分别连接8个时钟信号CK1至CK8。
在图5所示的一组移位寄存器GOA1至GOA8中，第一级移位寄存器GOA1的时钟信号端CK连接为接收第一时钟信号CK1，第一级移位寄存器GOA1的第一控制信号端CKB连接为接收第五时钟信号CK5；第二级移位寄存器GOA2的时钟信号端CK连接为接收第二时钟信号CK2，第二级移位寄存器GOA2的第一控制信号端CKB连接为接收第六时钟信号CK6；第三级移位寄存器GOA3的时钟信号端CK连接为接收第三时钟信号CK3，第三级移位寄存器GOA3的第一控制信号端CKB连接为接收第七时钟信号CK7；第四级移位寄存器GOA4的时钟信号端CK连接为接收第四时钟信号CK4，第四级移位寄存器GOA4的第一控制信号端CKB连接为接收第八时钟信号CK8；第五级移位寄存器GOA5的时钟信号端CK连接为接收第五时钟信号CK5，第五级移位寄存器 GOA5的第一控制信号端CKB连接为接收第一时钟信号CK1；第六级移位寄存器GOA6的时钟信号端CK连接为接收第六时钟信号CK6，第六级移位寄存器GOA6的第一控制信号端CKB连接为接收第二时钟信号CK2；第七级移位寄存器GOA7的时钟信号端CK连接为接收第七时钟信号CK7，第七级移位寄存器GOA7的第一控制信号端CKB连接为接收第三时钟信号CK3；第八级移位寄存器GOA8的时钟信号端CK连接为接收第八时钟信号CK8，第八级移位寄存器GOA8的第一控制信号端CKB连接为接收第四时钟信号CK4。第二组移位寄存器GOA9至GOA16分别以类似于GOA1至GOA8的方式连接为接收时钟信号CK1至CK8，以此类推。
栅极驱动电路500的移位寄存器GOA1至GOA8的其他信号端(如果有的话)分别连接为接收针对该信号端的信号，例如各级移位寄存器GOA1至GOA8的电源信号端VGH连接为接收电源信号，参考信号端VGL连接为接收参考信号，总复位信号端RESET连接为接收总复位信号。
图6示出了根据本公开另一实施例的栅极驱动电路的示意图。图6的栅极驱动电路600与图5的栅极驱动电路500类似，区别至少在于i＝j＝2，K＝4。为了简化描述，下面将主要对区别部分进行详细说明。
如图6所示，第n级移位寄存器的输入控制端STV连接至第n-2级移位寄存器的输出信号端OUT，第n级移位寄存器的复位控制端RST连接至第n+2级移位寄存器的输出信号端OUT，例如第1级移位寄存器GOA1的输出信号端OUT连接至第3级移位寄存器GOA3的输入控制端STV，第2级移位寄存器GOA2的输出信号端OUT连接至第4级移位寄存器GOA4的输入控制端STV，以此类推。第1级移位寄存器GOA1的复位控制端RST连接至第3级移位寄存器GOA3的输出信号端OUT，第2级移位寄存器GOA2的复位控制端RST连接至第4级移位寄存器GOA4的输出信号端OUT，以此类推。第一级移位寄存器GOA1和第二级移位寄存器GOA2的输入信号端STV分别连接为接收启动信号STV1和STV2。
栅极驱动电路600受控于4个时钟信号CK1至CK4，相邻的四级移位寄存器作为一组分别连接为接收时钟信号CK1至CK4。例如，在第一组移位寄存器GOA1至GOA4中，第一级移位寄存器GOA1的时钟信号端CK连接为接收第一时钟信号CK1，第一级移位寄存器GOA1的第一控制信号端CKB连接为接收第三时钟信号CK3；第二级移位寄存器GOA2的时钟信号端CK连接为接收第二时钟信号CK2，第二级移位寄存器GOA2的第一控制信号端CKB连接为接收第四时钟信号CK4；第三级移位寄存器GOA3 的时钟信号端CK连接为接收第三时钟信号CK3，第三级移位寄存器GOA3的第一控制信号端CKB连接为接收第一时钟信号CK1；第四级移位寄存器GOA4的时钟信号端CK连接为接收第四时钟信号CK4，第四级移位寄存器GOA4的第一控制信号端CKB连接为接收第二时钟信号CK2。第二组移位寄存器GOA2至GOA8以类似于第一组移位寄存器GOA1至GOA4的方式分别连接为接收时钟信号CK1至CK4。
图7A示出了根据本公开一实施例的显示面板的示意图。
如图7A所示，显示面板700包括布置成阵列的多个子像素Pix和栅极驱动电路710。栅极驱动电路710可以由上述任意实施例的栅极驱动电路来实现，栅极驱动电路710中的多级移位寄存器分别连接至阵列中的多行子像素Pix。在图7A中，多个子像素Pix位于显示区720中，多个子像素Pix布置成N×M阵列，N行子像素Pix分别连接至N条栅极信号线G1至GN，M列子像素Pix分别连接至M条数据线D1至DM，栅极驱动电路710中的N级移位寄存器产生的N个输出信号分别被提供给栅极线G1至GN。当然本公开的实施例不限于此，子像素Pix可以根据需要布置成其他形式的阵列，子像素Pix的行和列可以以不同方式与栅极线和数据线连接，栅极驱动电路710的输出信号端可以以不同方式连接栅极线。例如可以一条栅极线连接两行子像素，或则两条栅极线连接一行子像素。又例如栅极驱动电路710中的每个输出信号端可以连接一条栅极线或多条栅极线，等等。
图7B示出了图7A的显示面板的布局的示意图。如图7B所示，栅极驱动电路710可以由上述栅极驱动电路，栅极驱动电路710中的N个移位寄存器GOA1至GOAN沿y方向(子像素阵列的列方向，也称作第二方向，在图7B中为竖直方向)排列，并且与栅极线G1至GN一一对应地连接，从而连接至显示区720中的子像素Pix。如图7B所示，每个移位寄存器GOA1至GOAN在y方向上的尺寸可为子像素Pix在y方向上的尺寸的0.8-1.4倍，优选地，每个移位寄存器GOA1至GOAN在y方向上的尺寸与子像素Pix在y方向上的尺寸基本相同(在图7B中均由d来表示)。这里所谓尺寸可以指的是在显示面板的衬底基板上的投影的尺寸。例如在图7B中，每个移位寄存器GOA1至GOAN在显示面板的衬底基板上的投影在y方向上跨越的距离可以表示移位寄存器在y方向上的尺寸d。同样，如图7B所示，子像素Pix在衬底基板上的投影在y方向上跨越的距离可以表示子像素Pix在y方向上的尺寸d。
图7C示出了图7B中的移位寄存器的布局的示意图。如图7C所示，移位寄存器可以由上述任意实施例的移位寄存器来实现，例如包括上述输入电路110、第一控制电路 130、第二控制电路140和输出电路120。输入电路110、第一控制电路130、第二控制电路140和输出电路120依次沿x方向(子像素阵列的行方向，也称作第一方向，其与y方向垂直)排列。在图7C中，输入电路110、第一控制电路130、第二控制电路140和输出电路120各自在y方向上的尺寸均为d，与子像素在y方向上的尺寸d相同。在图7C中，以设置在显示区720左侧的移位寄存器为例进行了示意，输入电路110、第一控制电路130、第二控制电路140和输出电路120从左到右排列，从而以此顺序逐渐靠近显示区720。类似地，在移位寄存器位于显示区720右侧的情况下，输入电路110、第一控制电路130、第二控制电路140和输出电路120从右至左排列，从而以此顺序逐渐靠近显示区720。通过沿x方向依次排布输入子电路110、第一控制电路130、第二控制电路140和输出电路120，可以在y方向上尽量缩小每个移位寄存器单元在y方向的排布尺寸，在保证移位寄存器中各TFT的宽长比的前提下，可以增加y方向上移位寄存器单元的数量，进而有利于提高显示面板的分辨率，以及显示面板在y方向的窄边框。
在图7B和图7C中，移位寄存器及其包括的输入电路110、第一控制电路130、第二控制电路140和输出电路120在衬底基板上的投影被示为大致矩形的形状，其在y方向上的尺寸由矩形在y方向上的边长来表示。然而本公开的实施例不限于此，移位寄存器及其中的输入电路、第一控制电路、第二控制电路和输出电路在衬底基板上的投影可以根据需要设计成其他形状，甚至不规则形状，只要其在y方向上的尺寸与子像素在y方向上的尺寸基本相同。
图8示出了根据本公开另一实施例的显示面板的示意图。图8的显示面板800与图7A的显示面板700类似，区别至少在于显示面板800包括两个栅极驱动电路810A和810B。为了简化描述，下面将主要对区别部分进行详细说明。如图8所示，显示面板800包括显示区820，以上关于显示区720的描述同样适用于显示区820。栅极驱动电路810A和810B沿x方向(子像素阵列的行方向，也称作第一方向，在图8中为水平方向)分别位于所述多个子像素的阵列的两侧。栅极驱动电路810A和810B各自由上述栅极驱动电路500来实现，为了简明起见，图8中仅示出了各个移位寄存器GOA1至GOAN之间的级联连接，省略了诸如时钟信号和其他控制信号与移位寄存器之间的连接。如图8所示，栅极驱动电路810A中的第一级移位寄存器GOA1的输出信号端从左侧连接至针对第一行子像素的栅极线G1，栅极驱动电路810B中的第一级移位寄存器GOA1的输出信号端从右侧连接至针对第一行子像素的栅极线G1；以类似的方式，栅极驱动电路810A和810B各自的第二级移位寄存器GOA2分别从左右两侧连接至栅极线G1，以此类推。 通过这种方式，可以实现从两侧向栅极线施加栅极驱动信号，对于大尺寸显示面板来说，可以缓解由于栅极线走线过长而导致的信号衰减。
图9示出了根据本公开另一实施例的显示面板的示意图。图9的显示面板900与图8的显示面板800类似，包括显示区920以及分别位于显示区920两侧的栅极驱动电路910A和910B。与显示面板800不同，显示面板900中的栅极驱动电路910A和910B各自由上述栅极驱动电路600来实现。为了简明起见，图9中仅示出了各个移位寄存器GOA1至GOAN之间的级联连接，省略了诸如时钟信号和其他控制信号与移位寄存器之间的连接。类似于图8，图9中栅极驱动电路910A的移位寄存器GOA1至GOAN从左侧分别连接至栅极线G1至GN，栅极驱动电路910B的移位寄存器GOA1至GOAN从右侧分别连接至栅极线G1至GN。
图10示出了根据本公开另一实施例的显示面板的示意图。图7A的显示面板700类似，图10的显示面板1000包括栅极驱动电路和位于显示区1020的多个子像素，所述栅极驱动电路采用栅极驱动电路500的结构，其中奇数级移位寄存器GOA1，GOA3，…GOA(N-1)(图10中由虚线框1010A表示)沿x方向设置在显示区1020的一侧(图10中为左侧)，偶数级移位寄存器GOA2，GOA4，…GOAN(图10中由虚线框1010B表示)沿x方向设置在显示区1020的另一侧(图10中为右侧)。为了简明起见，图10中仅示出了各个移位寄存器GOA1至GOAN之间的级联连接，省略了诸如时钟信号和其他控制信号与移位寄存器之间的连接。如图10所示，奇数级移位寄存器GOA1，GOA3，…GOA(N-1)从左侧分别连接至栅极线G1，G3，…G(N-1)，偶数级移位寄存器GOA2，GOA4，…GOAN从右侧分别连接至栅极线G2，G4，…GN。
图11示出了根据本公开另一实施例的显示面板的示意图。类似于图10，图11的显示面板1100包括位于显示区1120中的多个子像素Pix和与所述多个子像素Pix连接的栅极驱动电路1110，栅极驱动电路1100可以采用以上参考图8至图10描述的任意方式与子像素Pix连接。在图11中，显示面板1100还包括多路复用电路1130。多路复用电路1130通过M条数据线D1至DM与子像素阵列中的M列子像素连接。多路复用电路1130例如连接至数据驱动电路(例如驱动IC)以接收m个输入数据信号Data1至Datam，多路复用电路1130可以在第一选择信号MUX1和第二选择信号MUX2的控制下将接收到的m个输入数据信号Data1至Datam复用为M个输出数据信号分别提供给数据线D1至DM，进而提供给M列子像素Pix。m和M为大于1的整数，M是m的整数倍，例如两倍。
图12示出了根据本公开实施例的多路复用电路的电路图。如图12所示，多路复用电路包括多个多路复用单元M1、M2……，图12中为了简明起见示出了其中两个多路复用单元M1和M2。在图12中，M/m＝2，多路复用电路1130的每个多路复用单元可以将接收到的一个输入数据信号复用为两个输出数据信号分别提供给两条数据线，从而实现一分二的多路复用，例如多路复用单元M1将接收到的输入数据信号Data1复用为两个输出数据信号分别提供给数据线D1和D2，多路复用单元M2将接收到的输入数据信号Data2复用为两个输出数据信号分别提供给数据线D3和D4。在图12中，每个多路复用单元包括晶体管Tm1和Tm2，例如在多路复用单元M1中，晶体管Tm1的栅极连接至第一选择信号线以接收第一选择信号MUX1，第一极连接为接收输入数据信号Data1，第二极连接至数据线D1；晶体管Tm2的栅极连接至第二选择信号线以接收第二选择信号MUX2，第一极连接为接收输入数据信号Data1，第二极连接至数据线D2。当第一选择信号MUX1为高电平时，晶体管Tm1导通，从而将接收到的输入数据信号Data1提供至数据线D1；当第二选择信号MUX2为高电平时，晶体管Tm2导通，从而将输入数据信号Data1提供至数据线D2。其他多路复用单元以类似的方式工作，这里不再赘述。
图13示出了根据本公开实施例的移位寄存器在显示阶段的信号时序图。图13的信号时序适用于上述任意实施例的移位寄存器，下面将以图3的移位寄存器300为例来对图13的信号时序进行说明。在显示阶段，输入信号端CN和电源信号端VGH保持高电平，复位信号端RST和参考信号端RST保持低电平。
在时段P1，输入控制端STV为高电平，第十一晶体管T11导通，从而将输入信号端CN的高电平输入至第一上拉节点PU1。电源信号端VGH的高电平使第十晶体管T10导通，使得第二上拉节点PU2为高电平。第二上拉节点PU2的高电平使第十二晶体管T12导通，此时由于时钟信号端CK处的时钟信号为低电平，因此输出信号端OUT为低电平。第一控制信号端CKB为高电平，第七晶体管T7导通，第一上拉节点PU1的高电平使第九晶体管T9导通，从而利用参考信号端VGL的低电平将下拉节点PD的电位拉低。此时，若没有降噪电路360，如上文分析的，下拉节点PD处的电位(如图13中的“PD(无降噪)”所表示的)会由于第七晶体管T7和第九晶体管T9同时处于导通状态而无法达到期望的低电平值，从而影响第一上拉节点PU1的电位。通过设置降噪电路360，输入控制端STV的高电平可以使第六晶体管T6导通，从而利用参考信号端VGL的电位进一步下拉下拉节点PD的电位(如图13中的“PD(有降噪)”所表示的)，从 图13可以看出，相比于没有降噪电路360的情况，下拉节点PD的电位有所降低。
在时段P2，输入控制端STV和第一控制信号端CKB变为低电平，第十一晶体管T11和第七晶体管T7关断，第一上拉节点PU1和第二上拉节点PU2由于第三电容C3的存在而保持高电平。此时由于第七晶体管T7关断而第九晶体管T9导通，下拉节点PD的电位进一步变低。
在时段P3，时钟信号端CK为高电平，此时由于第十二晶体管T12处于导通状态，将时钟信号端CK的高电平提供至输出信号端OUT。第三电容C3的自举作用使第二上拉节点PU2的电位进一步升高。
在时段P4，时钟信号端CK变为低电平，导通状态的第十二晶体管T12使输出信号端OUT也变为低电平。第三电容C3的自举作用使第二上拉节点PU2的电位降低。
在时段P5，复位控制端RST为高电平，从而将复位信号端CNB处的低电平提供至第一上拉节点PU1，导通的第十晶体管T10使第二上拉节点PU2也变为低电平。第一控制信号端CKB为高电平，第七晶体管T7导通，从而使下拉节点PD变为高电平。下拉节点PD的高电平使第三晶体管T3导通，从而将输出信号端OUT下拉至参考信号端VGL的低电平。
在上述过程中，第二控制信号端EN保持低电平，第一晶体管T1和第二晶体管处于关断状态。
上文虽然以移位寄存器300为例对信号时序进行了说明，然而上述信号时序同样适用于本公开实施例的其他移位寄存器。例如对于移位寄存器400来说，可以基于图13的信号时序以类似于上述方式来工作，区别在于，在时段P5，第二控制信号端为低电平，下拉节点PD的高电平使第五晶体管T5导通，从而将输出信号端OUT下拉至参考信号端VGL的低电平。
图14示出了根据本公开实施例的栅极驱动电路在显示阶段的信号时序图。图14的信号时序适用于上述栅极驱动电路500。如图14所示，向栅极驱动电路500提供顺序移位的8个时钟信号CK1至CK8，栅极驱动电路500中的每个移位寄存器GOA1至GOAN例如可以按照以上参考图13描述的方式工作，从而在各自的输入控制端STV的电位的控制下基于各自时钟信号端CK处的时钟信号在各自的输出信号端OUT输出栅极驱动信号。移位寄存器GOA1至GOAN产生的N个栅极驱动信号分别被提供至与其连接的栅极线G1至GN。在图14中，时钟信号CK1至CK8是占空比为12.5％且脉冲宽度为单位扫描时间的周期信号，其中第k+1时钟信号相对于第k时钟信号移位单位扫描时间， 其中k为整数，1≤k≤7。这里所谓单位扫描时间是指所述栅极驱动电路扫描一行像素所需的时间。以8K分辨率的显示面板为例，显示面板的显示区的子像素布置成7680×4320阵列，在刷新频率为60Hz的情况下，1帧是扫描时间是1/60秒，即扫描4320行子像素花费的时间是1/60秒，那么扫描每一行子像素花费的时间(即单位扫描时间)H＝1/60÷4320≈3.7μs。同理，在刷新率为120Hz的情况下，单位扫描时间H为大约1.85μs。
图15示出了根据本公开另一实施例的栅极驱动电路在显示阶段的信号时序图。图15的信号时序适用于上述栅极驱动电路600。如图15所示，向栅极驱动电路600提供顺序移位的4个时钟信号CK1至CK4，栅极驱动电路600中的每个移位寄存器GOA1至GOAN例如可以按照以上参考图13描述的方式工作，从而在各自的输入控制端STV的电位的控制下基于各自时钟信号端CK处的时钟信号在各自的输出信号端OUT输出栅极驱动信号。移位寄存器GOA1至GOAN产生的N个栅极驱动信号分别被提供至与其连接的栅极线G1至GN。在图15中，时钟信号CK1至CK4是占空比为25％且脉冲宽度为单位扫描时间的周期信号，其中第k+1时钟信号相对于第k时钟信号移位单位扫描时间，其中k为整数，1≤k≤3。
图16示出了根据本公开实施例的栅极驱动电路的工作时序图。图16的工作时序图适用于上述任意实施例的栅极驱动电路，栅极驱动电路中采用上述移位寄存器300。图16的工作时序涵盖了上电阶段、显示阶段和下电阶段。例如在栅极驱动电路开启时进入上电阶段；在上电完成后进入显示阶段，栅极驱动电路中的各个移位寄存器按照以上参考图13描述的方式工作以驱动子像素进行显示；在需要关闭栅极驱动电路关闭时进入下电阶段。
在显示阶段，第二控制信号为低电平，使得每个移位寄存器的第二控制信号端EN为低电平。参考图3，第二控制信号端EN的低电平使第一晶体管T1和第二晶体管T2关断，因此不影响移位寄存器的显示操作。
在下电阶段，提供给栅极驱动电路的第二控制信号和电源信号为高电平，分别使得每个移位寄存器的第二控制信号端EN和电源信号端VGH为高电平。提供给栅极驱动电路的其他信号，例如总复位信号、输入信号、复位信号、启动信号STV1至STVx(例如图5中的STV1至STV4，或者图6中的STV1和STV2)、K个时钟信号和参考信号均为低电平，使得每个移位寄存器的总复位信号端RESET、输入信号端CN、复位信号端CNB、时钟信号端CK、第一控制信号端CKB和参考信号端VGL均为低电平。在每个 移位寄存器中，参考图3，第二控制信号端EN的高电平使得第一晶体管T1和第二晶体管T2导通，从而第二控制信号端EN处的高电平被提供给输出信号端从而输出高电平的输出信号，参考信号端VGL处的低电平被提供给下拉节点PD。由于栅极驱动电路中的各个移位寄存器GOA1至GOAN均输出高电平，级联连接使得每个移位寄存器的输入控制端STV和复位控制端RST均为高电平，第十一晶体管T11和第十三晶体管T13导通，从而将输入信号端CN和复位信号端CNB处的低电平提供至上拉节点PU1。由于电源信号端VGH为高电平，第十晶体管T10导通，使得第二上拉节点PU2也为低电平。通过上述方式，实现了栅极驱动电路的下电，使得每个移位寄存器的输出信号端OUT为高电平，第一上拉节点PU1和第二上拉节点PU2为高电平，下拉节点为低电平。
通过在下电阶段将上拉节点(例如第一上拉节点PU1和第二上拉节点PU2)设置为低电平，使得当栅极驱动电路再次上电时，不会由于上电过程无法将上拉节点置低而导致不期望的输出。通过这种方式，使得上电过程不必须具备将上拉节点拉低的功能，放宽了对上电的限制。例如，在图16中，在上电阶段提供给栅极驱动电路的所有信号都处于地电平，例如介于高电平和低电平之间的中间电平，使得每个移位寄存器的各个信号端均处于地电平。换言之，在图16的实施例中可以不需要上电操作，栅极驱动电路可以启动后即进入显示阶段进行显示驱动。当然本公开的实施例不限于此，在上电阶段可以采用其他信号时序来进行上电操作，下文将对此进一步详细说明。
图17示出了根据本公开另一实施例的栅极驱动电路的工作时序图。图17的工作时序图适用于上述任意实施例的栅极驱动电路，栅极驱动电路中采用上述移位寄存器400。图17的工作时序与图16类似，区别至少在于下电阶段。为了简化描述，下面将主要对区别部分进行详细说明。
在显示阶段，类似于图16，第二控制信号为低电平，使得每个移位寄存器的第二控制信号端EN为低电平。参考图4，当下拉节点PD为高电平时，第五晶体管T5导通，第二控制信号端EN的低电平被提供至输出信号端OUT，以起到下拉输出信号端OUT的电位的作用。
在下电阶段，提供给栅极驱动电路的第二控制信号和电源信号和K个时钟信号为高电平，分别使得每个移位寄存器的第二控制信号端EN、电源信号端VGH、时钟信号端CK和第一控制信号端CKB为高电平。提供给栅极驱动电路的其他信号，例如总复位信号、输入信号、复位信号、启动信号STV1至STVx(例如图5中的STV1至STV4，或者图6中的STV1和STV2)和参考信号均为低电平，使得每个移位寄存器的总复位信号 端RESET、输入信号端CN、复位信号端CNB和参考信号端VGL均为低电平。在每个移位寄存器中，参考图4，第一控制信号端CKB的高电平使得第七晶体管T7导通，从而下拉节点PD为高电平。下拉节点PD的高电平使第五晶体管T5导通，从而将第二控制信号端EN处的高电平提供至输出信号端OUT。由于各个移位寄存器的输出信号端OUT均输出高电平，级联连接使得每个移位寄存器的输入控制端STV和复位控制端RST均为高电平，从而将输入信号端CN和复位信号端CNB的低电平提供至第一上拉节点PU1。由于电源信号端VGH为高电平，第十晶体管T10导通，第二上拉节点PU2也为低电平。通过图17的下电过程，使得每个移位寄存器的上拉节点PU1和PU2为低电平，下拉节点PD为高电平。
虽然以上参考图16和图17描述了特定的上电时序，然而本公开的实施例不限于此，上电阶段可以根据需要采用其他信号时序，例如图18的上电时序。
图18示出了根据本公开另一实施例的栅极驱动电路在上电阶段的时序图。如图18所示，在上电阶段，提供给栅极驱动电路的总复位信号、K个时钟信号和电源信号为高电平，使得每个移位寄存器的总复位信号端RESET、时钟信号端CK、第一控制信号端CKB和电源信号端VGH为高电平。提供给栅极驱动电路的其他信号，例如输入信号、第二控制信号、复位信号、启动信号STV1至STVx(x等于2或4)、参考信号为低电平，使得每个移位寄存器的输入信号端CN、第二控制信号端EN、复位信号端CNB和参考信号端VGL为低电平。参考图3和图4，总复位信号端RESET的高电平使第十四晶体管T14导通，从而将第一上拉节点PU1下拉至参考信号端VGL的低电平。由于电源信号端VGH为高电平，第十晶体管T10导通，使得第二上拉节点PU2也为低电平。第一控制信号端CKB的高电平使第七晶体管T7导通，使得下拉节点PD为高电平。通过该上电过程，可以将上拉节点复位至低电平，下拉节点复位至高电平，从而在进入显示阶段之前将上拉节点再次拉低，进一步缓解由于上拉节点的电位异常而影响显示阶段的信号输出的问题。
图19A示出了根据本公开实施例的显示面板的信号时序图。图19的信号时序适用于上述任意实施例的显示面板，例如以上参考图11描述的显示面板1100。下面将结合图11的显示面板1100来对于19A的信号时序进行说明。
参考图11，栅极驱动电路1110在K个时钟信号的控制下通过多条栅极线G1至GN向阵列中的多行子像素提供栅极驱动信号，以将所述多行子像素中的至少一行子像素开启。多路复用电路1130在第一选择信号MUX1和第二选择信号MUX2的控制下将接收 到的m个输入数据信号复用为M个输出数据信号分别提供给数据线D1至DM，从而提供给阵列中的M列子像素，使得开启的所述至少一行子像素基于接收到的输出数据信号而发光，其中m和M为大于1的整数，M是m的整数倍。在图19A的实施例中，M＝2m，即，多路复用电路1130的每个多路复用单元将一个输入数据信号复用为两个输出数据信号分别提供给两条数据线。
如图19A所示，在时段P1，栅极线G1为高电平，，第一行子像素开启。在时段P1的第一子时段，第一选择信号线MUX1为高电平，多路复用电路1130将接收到的m个输入数据信号提供给m个奇数列的数据线D_o(包括D1、D3、D5……)，使得所开启的第一行子像素中位于奇数列的m子像素发光。然后，在时段P1的第二子时段，第二选择信号线MUX2的高电平到来，多路复用电路1130将接收到的m个输入数据信号提供给m个偶数列的数据线D_e(包括D2、D4、D6……)，使得所开启的第一行子像素中位于偶数列的m子像素发光。以类似的方式，在时段P2，第二行子像素的栅极线G2为高电平，第二行子像素开启，第一选择信号MUX1和第二选择信号MUX2先后为高电平，从而先向第二行子像素中位于奇数列的子像素写入数据，再向第二列子像素中位于偶数列的子像素写入数据，以此类推。
图19B示出了根据本公开实施例的显示面板的信号波形的示意图。如图19B所示，在以上参考图13至图15描述的信号时序下，栅极驱动信号GATE的脉冲宽度(即从栅极驱动信号GATE的上升沿的起始点到下降沿的结束点之间的时间长度)为H，H表示单位扫描时间。栅极驱动信号GATE可以表示栅极驱动电路中的任一级栅极驱动信号，例如上述G1至GN中的任意一个。在栅极驱动信号GATE的一个高电平脉冲内，栅极驱动信号GATE的上升沿的起始点与第一选择信号MUX1的上升沿的起始点之间具有第一时间间隔GAP1，第二选择信号MUX2的下降沿的结束点与栅极驱动信号GATE的下降沿的起始点之间具有第二时间间隔GAP2，第一选择信号MUX1的下降沿的结束点与第二选择信号MUX2的上升沿的起始点之间具有第三时间间隔GAP3。
通常，第一选择信号MUX1和第二选择信号MUX2的高电平时间越长，留给子像素充电的时间越长。因此一行子像素开启的时间内，即，在栅极驱动信号GATE为高电平期间，期望尽可能减小GAP1、GAP2以及栅极驱动信号GATE的上升时长Tr(上升沿的起始点到结束点的时间)和下降时长Tf(下降沿的起始点到结束点的时间)。
然而在采用图13至图15描述的信号时序下，如图19C的信号仿真图所示，栅极驱动信号GATE的上升时长Tr较大，使得第一选择信号MUX1变为高电平之后的一定时 间内栅极驱动信号GATE尚未达到期望的高电平，导致子像素开启不完全。这使得第一选择信号MUX1对应的子像素充电率低于第二选择信号MUX2对应的子像素充电率，这里所谓充电率是子像素实际达到的数据电压与期望的数据电压的比值。
图20示出了根据本公开另一实施例的显示面板的信号时序图。图20的信号时序图适用于上述采用4个时钟信号的栅极驱动电路，例如栅极驱动电路600。图20的信号时序与图15类似，区别至少在于，4个时钟信号CK1至CK4是占空比为50％且脉冲宽度为2H的周期信号。第一选择信号MUX1和第二选择信号MUX2是占空比为50％且脉冲宽度小于m/M*H的周期信号。在本实施例中M＝2m，第一选择信号MUX1和第二选择信号MUX2的脉冲宽度小于1/2*H。
在时段P1，栅极驱动信号G1为高电平，第一行子像素开启，该过程也称作预充电阶段。
在时段P2，栅极驱动电路G1保持高电平，第一选择信号MUX1和第二选择信号MUX2先后变为高电平，从而向开启的第一行子像素写入针对第一行的数据信号。在时段P2期间，栅极驱动信号G2也为高电平，给第二行子像素预充电，在此期间第一选择信号MUX1和第二选择信号MUX2的高电平使得向第二行子像素写入了针对第一行的数据信号。然而该预充电过程并不会对第二行子像素的正常显示造成实质影响，因为在时段P2之后的时段P3，会以类似于上述的方式给第二行子像素写入针对第二行的数据信号。
通过上述预充电，增加了栅极驱动信号的高电平持续时间，从而使第一选择信号MUX1和第二选择信号MUX2对应的子像素充电率一致。但对于更大尺寸更高分辨率的产品，比如31.5 8K产品，上述预充电方案可能存在一些问题，下面将参考图21A至21C来对此进行分析说明。
图21A至图21C示出了图20的实施例的信号仿真图。
参考栅极驱动电路600的结构，第三级移位寄存器GOA3的输出信号端OUT高电平时，给第一级移位寄存器GOA1的上拉节点PU放电，使第一级移位寄存器GOA1的第三晶体管T3关断，同时第一级移位寄存器GOA1的CKB给下拉节点PD充电，使第四晶体管T4导通。在第一级移位寄存器GOA1中，当第三晶体管T3已经关断但是第四晶体管T4尚未导通时，输出信号端OUT处于浮置状态，此时输出信号端OUT受到与下拉节点PD之间的耦合电容作用而出现电位升高，如图21A中的虚线所示。在第一级移位寄存器GOA1中，当第四晶体管T4导通之后，输出信号端OUT的电位继续 下降，由于第四晶体管T4的沟道宽长比W/L较小，放电能力弱，使得输出信号端OUT的放电时间较长，所以产生的栅极驱动信号G1的下降时长Tf较大，如图21A所示。
另外，对于分辨率为7680×4320的8K显示面板来说，如采用图6的4个时钟信号的级联方案，每个时钟信号驱动1080行像素。在这种情况下，如图21B的充电仿真波形所示，在同一个时钟信号线(例如提供时钟信号CK1的时钟信号线)控制的多个移位寄存器当中，距离该时钟信号线较远的移位寄存器的栅极线(例如CK1控制的最后一级移位寄存器的输出信号端所连接的栅极线Gx)上的栅极驱动信号的上升沿和距离该时钟信号线较近的移位寄存器的栅极线(例如CK1控制的第一级移位寄存器的输出信号端所连接的栅极线G1)的上升沿之间存在较大差异。若经历工艺上的信号线线宽和信号线材料膜厚的制程波动，导致的栅极线上的RC负载波动较大，该差异可能会更大，甚至可能导致产品分屏异显。
如图21C的仿真波形图所示，对于8K显示产品来说，在图20的驱动方案实现的子像素的充电率小于95％。
图22示出了根据本公开另一实施例的显示面板的信号波形图。图20的信号时序图适用于上述采用8个时钟信号的栅极驱动电路500，例如栅极驱动电路600。图22的信号时序与图22类似，区别至少在于，8个时钟信号是占空比为25％且脉冲宽度为2H的周期信号。第一选择信号MUX1和第二选择信号MUX2是占空比为50％且脉冲宽度小于1/2*H的周期信号。
图23A至23C示出了图22的实施例的信号仿真图。从图23A可以看出，通过采用图5的8个时钟信号的级联方案，如时钟信号CK1控制的栅极驱动信号G1的下降沿与时钟信号CK5控制的栅极驱动信号G5的上升沿没有交叠，相比于图21A，栅极驱动信号G1至GN的下降时长Tf较小。从图23B可以看出，同样对于上述8K显示产品来说，如采用8个时钟信号的级联方案，每个时钟信号驱动540行像素，相比于图21B，同一时钟信号线控制的不同栅极线(例如G1和Gx)上的栅极驱动信号的上升沿差异减小。从图23C可以看出，采用图22的驱动方法，子像素充电率可以达到96％。
以上参考图19A至图23描述的信号波形是显示面板在显示阶段的信号波形，显示面板在上电阶段和下电阶段的信号波形可以根据需要来选择，例如可以采用以上参考图16至图18中的任意实施例中的上电时序和下电时序。
图24示出了根据本公开实施例的栅极驱动电路的驱动方法的流程图。该方法适用于上述任意实施例的栅极驱动电路。
在步骤S2401，在显示阶段，向所述栅极驱动电路提供第一电平的输入信号，每个移位寄存器在各自的输入控制端STV的电位的控制下基于所述输入信号在各自的输出信号端OUT输出栅极驱动信号。
在步骤S2402，在下电阶段，向所述栅极驱动电路提供第一电平的第二控制信号和第二电平的输入信号，每个移位寄存器将所述第一电平的第二控制信号提供至各自的输出信号端OUT，并且每个移位寄存器在各自的输入控制端STV的电位的控制下将所述第二电平的输入信号提供至各自的上拉节点PU。
例如，在每个移位寄存器的第二控制电路包括下拉子电路和下电子电路的情况下，例如在采用移位寄存器300的情况下，在显示阶段，每个移位寄存器的下拉子电路在所述移位寄存器的下拉节点PD的电位的控制下将所述移位寄存器的参考信号端VGL的电位提供至所述移位寄存器的输出信号端OUT；在所述下电阶段，每个移位寄存器的下电子电路将所述移位寄存器的第二控制信号端EN处第一电平的第二控制信号提供至所述移位寄存器的输出信号端OUT并且将所述移位寄存器的参考信号端VGL的电位提供至所述移位寄存器的下拉节点PD。
例如，在每个移位寄存器的第二控制电路包括第五晶体管T5和第二电容C2的情况下，例如在采用移位寄存器400的情况下，在显示阶段，向所述栅极驱动电路提供第二电平的第二控制信号，每个移位寄存器的第二控制电路在所述移位寄存器的下拉节点PD的电位的控制下将所述第二电平的第二控制信号提供至所述移位寄存器的输出信号端OUT；在下电阶段，向所述栅极驱动电路提供保持第一电平的K个时钟信号，每个移位寄存器的第一控制电路将所述移位寄存器的第一控制信号端CKB处接收到的第一电平的时钟信号提供至所述移位寄存器的下拉节点PD，所述下拉节点PD的电位使所述移位寄存器的第二控制电路将所述第一电平的第二控制信号提供至所述移位寄存器的输出信号端OUT。
在一些实施例中，在显示阶段，向所述栅极驱动电路提供顺序移位的K个时钟信号，每个移位寄存器在各自的输入控制端STV的电位的控制下基于所述输入信号和接收到的时钟信号在各自的输出信号端OUT输出栅极驱动信号，其中第k+1时钟信号相对于第k时钟信号移位所述单位扫描时间，其中k为整数，1≤k≤K-1，所述单位扫描时间为为所述栅极驱动电路扫描一行像素所需的时间。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲 突的情况下可以进行自由组合。
在详细说明本公开的较佳实施例之后，熟悉本领域的技术人员可清楚的了解，在不脱离随附权利要求的保护范围与精神下可进行各种变化与改变，且本公开亦不受限于说明书中所举示例性实施例的实施方式。

Claims (31)

  1. 一种移位寄存器，包括：
    输入电路，连接至输入信号端、输入控制端和所述移位寄存器的上拉节点，并且被配置为在所述输入控制端的信号的控制下将输入信号端的电位输入至所述上拉节点；
    输出电路，连接至所述上拉节点、时钟信号端和输出信号端，并且被配置为在所述上拉节点的电位的控制下将时钟信号端的信号提供至所述输出信号端；
    第一控制电路，连接至第一控制信号端、所述上拉节点、所述移位寄存器的下拉节点和参考信号端，并且被配置为将所述第一控制信号端的电位提供至所述下拉节点，以及根据所述上拉节点的电位将所述参考信号端的电位提供至所述下拉节点；以及
    第二控制电路，连接至所述下拉节点、第二控制信号端、所述输出信号端和所述参考信号端，并且被配置为在所述下拉节点和所述第二控制信号端的电位的控制下，在显示阶段下拉所述输出信号端的电位，在下电阶段上拉所述输出信号端的电位。
  2. 根据权利要求1所述的移位寄存器，其中，所述第二控制电路包括：
    下拉子电路，连接至所述下拉节点、所述输出信号端和所述参考信号端，并且被配置为在所述下拉节点的电位的控制下将所述参考信号端的电位提供至所述输出信号端；以及
    下电子电路，连接至所述第二控制信号端、所述下拉节点、所述输出信号端和所述参考信号端，并且被配置为在所述第二控制信号端的信号的控制下，将所述第二控制信号端的电位提供至所述输出信号端并且将所述参考信号端的电位提供至所述下拉节点。
  3. 根据权利要求2所述的移位寄存器，其中，所述下电子电路包括第一晶体管和第二晶体管，其中，
    所述第一晶体管的栅极和第一极连接至所述第二控制信号端，所述第一晶体管的第二极连接至所述输出信号端；并且
    所述第二晶体管的栅极连接至所述第二控制信号端，所述第二晶体管的第一极连接至所述参考信号端，所述第二晶体管的第二极连接至所述下拉节点。
  4. 根据权利要求2所述的移位寄存器，其中，所述下拉子电路包括第三晶体管和第一电容，其中，
    所述第三晶体管的栅极连接至所述下拉节点，所述第三晶体管的第一极连接至所 述参考信号端，所述第三晶体管的第二极连接至所述输出信号端；并且
    所述第一电容的第一端连接至所述下拉节点，所述第一电容的第二端连接至所述参考信号端。
  5. 根据权利要求4所述的移位寄存器，其中，所述下拉子电路还包括第四晶体管，所述第四晶体管的栅极连接至所述输出信号端，所述第四晶体管的第一极连接至所述参考信号端，所述第四晶体管的第二极连接至所述下拉节点。
  6. 根据权利要求1所述的移位寄存器，其中，所述第二控制电路包括第五晶体管和第二电容，其中，
    所述第五晶体管的栅极连接至所述下拉节点，所述第五晶体管的第一极连接至所述第二控制信号端，所述第五晶体管的第二极连接至所述输出信号端；并且
    所述第二电容的第一端连接至所述下拉节点，所述第二电容的第二端连接至所述参考信号端。
  7. 根据权利要求1所述的移位寄存器，还包括：降噪电路，连接至所述输入控制端、所述下拉节点和所述参考信号端，并且被配置为在所述输入控制端的信号的控制下将所述参考信号端的电位提供至所述下拉节点。
  8. 根据权利要求7所述的移位寄存器，其中，所述降噪电路包括第六晶体管，所述第六晶体管的栅极连接至所述输入控制端，所述第六晶体管的第一极连接至所述参考信号端，所述第六晶体管的第二极连接至所述下拉节点。
  9. 根据权利要求1所述的移位寄存器，还包括：复位电路，连接至复位控制端、复位信号端和所述上拉节点，并且被配置为在所述复位控制端的信号的控制下将所述复位信号端的电位提供至所述上拉节点。
  10. 根据权利要求1所述的移位寄存器，其中，所述上拉节点包括与所述输入电路连接的第一上拉节点以及与所述输出电路连接的第二上拉节点，所述第一控制电路包括第七晶体管、第八晶体管、第九晶体管和第十晶体管，其中，
    所述第七晶体管的栅极和第一极连接至所述第一控制信号端，所述第七晶体管的第二极连接至所述下拉节点；
    所述第八晶体管的栅极连接至所述下拉节点，所述第八晶体管的第一极连接至所述参考信号端，所述第八晶体管的第二极连接至所述第一上拉节点；
    所述第九晶体管的栅极连接至所述第一上拉节点，所述第九晶体管的第一极连接至所述参考信号端，所述第九晶体管的第二极连接至所述下拉节点；并且
    所述第十晶体管的栅极连接至电源信号端，所述第十晶体管的第一极连接至所述第一上拉节点，所述第十晶体管的第二极连接至所述第二上拉节点。
  11. 根据权利要求1所述的移位寄存器，其中，所述输入电路包括第十一晶体管，所述第十一晶体管的栅极连接至所述输入控制端，所述第十一晶体管的第一极连接至所述输入信号端，所述第十一晶体管的第二极连接至所述上拉节点。
  12. 根据权利要求1所述的移位寄存器，其中，所述输出电路包括第十二晶体管和第三电容，其中，
    所述第十二晶体管的栅极连接至所述上拉节点，所述第十二晶体管的第一极连接至所述时钟信号端，所述第十二晶体管的第二极连接至所述输出信号端；并且
    所述第三电容的第一端连接至所述上拉节点，所述第三电容的第二端连接至所述输出信号端。
  13. 根据权利要求9所述的移位寄存器，其中，所述复位电路包括第十三晶体管，所述第十三晶体管的栅极连接至所述复位控制端，所述第十三晶体管的第一极连接至所述复位信号端，所述第十三晶体管的第二极连接至所述上拉节点。
  14. 根据权利要求1所述的移位寄存器，还包括总复位电路，连接至总复位信号端、所述上拉节点和所述参考信号端，并且被配置为在所述总复位信号端的信号的控制下将所述参考信号端的电位提供至所述上拉节点。
  15. 根据权利要求14所述的移位寄存器，其中，所述总复位电路包括第十四晶体管，所述第十四晶体管的栅极连接至所述总复位信号端，所述第十四晶体管的第一极连接至所述参考信号端，所述第十四晶体管的第二极连接至所述上拉节点。
  16. 一种栅极驱动电路，包括N级级联的移位寄存器，每个移位寄存器为根据权利要求1至15中任一项权利要求所述的移位寄存器，其中，
    每个移位寄存器的输入信号端连接为接收输入信号，复位信号端连接为接收复位信号，第二控制信号端连接为接收第二控制信号；
    第n级移位寄存器的输入控制端连接至第n-i级移位寄存器的输出信号端，第n级移位寄存器的复位控制端连接至第n+j级移位寄存器的输出信号端；并且
    所述N级级联的移位寄存器分为至少一组，每组包括K级级联的移位寄存器，所述K级级联的移位寄存器的时钟信号端分别连接为接收K个时钟信号，所述K级级联的移位寄存器的第一控制信号端分别连接为接收所述K个时钟信号，其中N、K、n、i和j均为整数，1≤n≤N，1＜K≤N。
  17. 根据权利要求16所述的栅极驱动电路，其中，i＝j＝4，K＝8，所述K个时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号和第八时钟信号，在每组移位寄存器中：
    第一级移位寄存器的时钟信号端连接为接收第一时钟信号，第一级移位寄存器的第一控制信号端连接为接收第五时钟信号；
    第二级移位寄存器的时钟信号端连接为接收第二时钟信号，第二级移位寄存器的第一控制信号端连接为接收第六时钟信号；
    第三级移位寄存器的时钟信号端连接为接收第三时钟信号，第三级移位寄存器的第一控制信号端连接为接收第七时钟信号；
    第四级移位寄存器的时钟信号端连接为接收第四时钟信号，第四级移位寄存器的第一控制信号端连接为接收第八时钟信号；
    第五级移位寄存器的时钟信号端连接为接收第五时钟信号，第五级移位寄存器的第一控制信号端连接为接收第一时钟信号；
    第六级移位寄存器的时钟信号端连接为接收第六时钟信号，第六级移位寄存器的第一控制信号端连接为接收第二时钟信号；
    第七级移位寄存器的时钟信号端连接为接收第七时钟信号，第七级移位寄存器的第一控制信号端连接为接收第三时钟信号；
    第八级移位寄存器的时钟信号端连接为接收第八时钟信号，第八级移位寄存器的第一控制信号端连接为接收第四时钟信号。
  18. 根据权利要求16所述的栅极驱动电路，其中，i＝j＝2，K＝4，所述K个时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，在每组移位寄存器中：
    第一级移位寄存器的时钟信号端连接为接收第一时钟信号，第一级移位寄存器的第一控制信号端连接为接收第三时钟信号；
    第二级移位寄存器的时钟信号端连接为接收第二时钟信号，第二级移位寄存器的第一控制信号端连接为接收第四时钟信号；
    第三级移位寄存器的时钟信号端连接为接收第三时钟信号，第三级移位寄存器的第一控制信号端连接为接收第一时钟信号；
    第四级移位寄存器的时钟信号端连接为接收第四时钟信号，第四级移位寄存器的第一控制信号端连接为接收第二时钟信号。
  19. 一种显示面板，包括：
    布置成阵列的多个子像素；以及
    至少一个如权利要求16至18中任一项所述的栅极驱动电路，所述栅极驱动电路中的N级移位寄存器分别连接至所述阵列中的多行子像素。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板包括两个所述栅极驱动电路，所述两个栅极驱动电路沿第一方向分别位于所述多个子像素的阵列的两侧，其中所述第一方向为所述阵列的行方向。
  21. 根据权利要求19所述的显示面板，其中，所述显示面板包括一个所述栅极驱动电路，其中i＝j＝2，K＝4，所述栅极驱动电路中的奇数级移位寄存器和偶数级移位寄存器沿第一方向分别位于所述多个子像素的阵列的两侧。
  22. 根据权利要求19至21中任一项所述的显示面板，其中，所述移位寄存器包括输入电路、第一控制电路、第二控制电路和输出电路，所述输入电路、第一控制电路、第二控制电路和输出电路依次沿第一方向排列，并且所述输入电路、第一控制电路、第二控制电路和输出电路各自在第二方向上的尺寸为所述子像素在第二方向上的尺寸的0.8-1.4倍，其中所述第一方向为所述阵列的行方向，所述第二方向垂直于所述第一方向。
  23. 根据权利要求19至21中任一项所述的显示面板，还包括多路复用电路，所述多路复用电路与所述阵列中的M列子像素连接，所述多路复用电路被配置为在第一选择信号和第二选择信号的控制下将接收到的m个输入数据信号复用为M个输出数据信号分别提供给所述M列子像素，其中m和M为大于1的整数，M是m的整数倍。
  24. 一种根据权利要求16至18中任一项权利要求所述的栅极驱动电路的驱动方法，包括：
    在显示阶段，向所述栅极驱动电路提供第一电平的输入信号，每个移位寄存器在各自的输入控制端的电位的控制下基于所述输入信号在各自的输出信号端输出栅极驱动信号；
    在下电阶段，向所述栅极驱动电路提供第一电平的第二控制信号和第二电平的输入信号，每个移位寄存器将所述第一电平的第二控制信号提供至各自的输出信号端，并且每个移位寄存器在各自的输入控制端的电位的控制下将所述第二电平的输入信号提供至各自的上拉节点。
  25. 根据权利要求24所述的驱动方法，其中，每个移位寄存器的第二控制电路包 括下拉子电路和下电子电路，其中，
    在所述显示阶段，每个移位寄存器的下拉子电路在所述移位寄存器的下拉节点的电位的控制下将所述移位寄存器的参考信号端的电位提供至所述移位寄存器的输出信号端；以及
    在所述下电阶段，每个移位寄存器的下电子电路将所述移位寄存器的第二控制信号端处第一电平的第二控制信号提供至所述移位寄存器的输出信号端并且将所述移位寄存器的参考信号端的电位提供至所述移位寄存器的下拉节点。
  26. 根据权利要求24所述的驱动方法，其中，每个移位寄存器的第二控制电路包括第五晶体管和第二电容，其中，
    在所述显示阶段，向所述栅极驱动电路提供第二电平的第二控制信号，每个移位寄存器的第二控制电路在所述移位寄存器的下拉节点的电位的控制下将所述第二电平的第二控制信号提供至所述移位寄存器的输出信号端；
    在所述下电阶段，向所述栅极驱动电路提供保持第一电平的K个时钟信号，每个移位寄存器的第一控制电路将所述移位寄存器的第一控制信号端处接收到的第一电平的时钟信号提供至所述移位寄存器的下拉节点，所述下拉节点的电位使所述移位寄存器的第二控制电路将所述第一电平的第二控制信号提供至所述移位寄存器的输出信号端。
  27. 根据权利要求24所述的驱动方法，其中，在所述显示阶段，向所述栅极驱动电路提供顺序移位的K个时钟信号，每个移位寄存器在各自的输入控制端的电位的控制下基于所述输入信号和接收到的时钟信号在各自的输出信号端输出栅极驱动信号，其中第k+1时钟信号相对于第k时钟信号移位单位扫描时间，其中k为整数，1≤k≤K-1，所述单位扫描时间为所述栅极驱动电路扫描一行像素所需的时间。
  28. 根据权利要求27所述的驱动方法，其中，所述栅极驱动电路中i＝j＝4且K＝8，在所述显示时段，所述K个时钟信号是占空比为25％且脉冲宽度为2倍单位扫描时间的周期信号。
  29. 根据权利要求27所述的驱动方法，其中，所述栅极驱动电路中i＝j＝2且K＝4，在所述显示时段，所述K个时钟信号是占空比为50％且脉冲宽度为2倍单位扫描时间的周期信号。
  30. 根据权利要求27所述的驱动方法，其中，所述栅极驱动电路中i＝j＝4且K＝8，在所述显示时段，所述K个时钟信号是占空比为12.5％且脉冲宽度为单位扫描时间的 周期信号。
  31. 根据权利要求27所述的驱动方法，其中，所述栅极驱动电路中i＝j＝2且K＝4，在所述显示时段，所述K个时钟信号是占空比为25％且脉冲宽度为单位扫描时间的周期信号。
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