WO2024040432A1 - 显示面板、显示设备和显示面板的控制方法 - Google Patents

显示面板、显示设备和显示面板的控制方法 Download PDF

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Publication number
WO2024040432A1
WO2024040432A1 PCT/CN2022/114229 CN2022114229W WO2024040432A1 WO 2024040432 A1 WO2024040432 A1 WO 2024040432A1 CN 2022114229 W CN2022114229 W CN 2022114229W WO 2024040432 A1 WO2024040432 A1 WO 2024040432A1
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Prior art keywords
gate line
shift register
auxiliary circuit
transistor
auxiliary
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PCT/CN2022/114229
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English (en)
French (fr)
Inventor
文娜
邹佳滨
尹晓峰
闫岩
栗峰
郑翠翠
桑琦
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002767.0A priority Critical patent/CN117918028A/zh
Priority to PCT/CN2022/114229 priority patent/WO2024040432A1/zh
Publication of WO2024040432A1 publication Critical patent/WO2024040432A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a display device and a control method of the display panel.
  • a display panel is usually provided with multiple sub-pixels, multiple gate lines and gate driving circuits.
  • the multiple sub-pixels can receive scanning signals provided by the gate driving circuit through the gate lines.
  • Embodiments of the present disclosure provide a display panel, a display device, and a control method of the display panel.
  • a display panel including:
  • the base substrate including a display area and a peripheral area surrounding the display area;
  • a plurality of sub-pixels located in the display area and arranged in multiple rows along the first direction;
  • a plurality of gate lines located in the display area, the plurality of gate lines extending along a first direction and arranged along a second direction crossing the first direction, each gate line being connected to at least one row of sub-pixels;
  • a plurality of shift registers located in the peripheral area and configured to provide scanning signals
  • a plurality of auxiliary circuits are located in the peripheral area, wherein a first end of at least one gate line is connected to at least one of the shift registers and is configured to receive a scan signal provided by the at least one shift register, and the at least one gate line
  • the second end of the pole line is connected to at least one of the auxiliary circuits, wherein the control end of the auxiliary circuit is configured to receive an auxiliary signal, the input end of the auxiliary circuit is configured to receive a reference signal, and the output end of the auxiliary circuit is connected to At the second end of the gate line, the auxiliary circuit is configured to provide the reference signal at the input end of the auxiliary circuit to the output end of the auxiliary circuit under the control of the auxiliary signal.
  • control end of the auxiliary circuit connected to the i-th gate line among the plurality of gate lines is connected to receive the scan signal provided by the shift register connected to the i+k-th gate line as the auxiliary signal, where i and k are integers greater than or equal to 1.
  • the plurality of shift registers include a plurality of first shift registers located on a first side of the display area along the first direction and connected in cascade;
  • the plurality of auxiliary circuits include a plurality of first auxiliary circuits located along the first direction on a second side of the display area opposite to the first side;
  • the at least one gate line includes a plurality of first gate lines, a first end of the first gate line is located on a first side of the display area and is connected to the first shift register, and the first gate line The second end of the gate line is located on the second side of the display area and connected to the first auxiliary circuit.
  • control terminal of the i-th first auxiliary circuit is connected to the second terminal of the i+k-th first gate line, and the output terminal of the i-th first auxiliary circuit is connected to the second terminal of the i-th first gate line. end.
  • the plurality of shift registers further include a plurality of second shift registers located on the second side of the display area and connected in cascade;
  • the plurality of auxiliary circuits also include a plurality of second auxiliary circuits located on the first side of the display area;
  • the at least one gate line also includes a plurality of second gate lines alternately arranged with the plurality of first gate lines, and a first end of the second gate line is located on the second side of the display area. And connected to the second shift register, the second end of the second gate line is located on the first side of the display area and connected to the second auxiliary circuit.
  • the first gate line is connected to odd-numbered rows of sub-pixels
  • the second gate line is connected to even-numbered rows of sub-pixels.
  • the control end of the first auxiliary circuit connected to each first gate line is connected to the second gate line connected to the second gate line spaced three gate lines away from the first gate line.
  • the output signal terminal of the shift register; the control terminal of the second auxiliary circuit connected to each second gate line is connected to the first gate line separated from the second gate line by three gate lines. The output signal terminal of the first shift register.
  • the first auxiliary circuit is located between the display area and the second shift register
  • the second auxiliary circuit is located between the display area and the first shift register.
  • the size of each of the first auxiliary circuit and the second auxiliary circuit in the second direction is equal to the sum of the sizes of the two rows of sub-pixels in the second direction.
  • the plurality of shift registers further include a plurality of third shift registers located on the second side of the display area;
  • the plurality of auxiliary circuits also include a plurality of third auxiliary circuits located on the first side of the display area;
  • the first end of the first gate line is also connected to the third auxiliary circuit, and the second end of the first gate line is also connected to the third shift register.
  • the first auxiliary circuit is located between the display area and the third shift register
  • the third auxiliary circuit is located between the display area and the first shift register.
  • control terminal of the i-th first auxiliary circuit is connected to the output signal terminal of the i+k-th stage third shift register, and the output terminal of the i-th first auxiliary circuit is connected to the second terminal of the i-th first gate line. end;
  • the control end of the i-th third auxiliary circuit is connected to the output signal end of the i+k-th stage first shift register, and the output end of the i-th third auxiliary circuit is connected to the first end of the i-th first gate line.
  • the auxiliary circuit includes a first transistor, the gate of the first transistor serves as the control terminal of the auxiliary circuit, the first pole of the first transistor serves as the input terminal of the auxiliary circuit, and the first The second pole of the transistor serves as the output of the auxiliary circuit.
  • the shift register includes:
  • An input circuit connected to an input signal terminal of the shift register and a pull-up node of the shift register, and configured to provide a signal from the input signal terminal to the pull-up node;
  • An output circuit is connected to the pull-up node, the clock signal terminal of the shift register, and the output signal terminal of the shift register, and is configured to provide the signal of the clock signal terminal under the control of the pull-up node. to the output signal terminal to output a scanning signal;
  • control circuit connected to the pull-up node of the shift register and the pull-down node of the shift register, and configured to control the potential of the pull-down node according to the potential of the pull-up node;
  • a pull-down circuit is connected to the output signal terminal of the shift register and the pull-down node, and is configured to pull down the potential of the output signal terminal of the shift register under the control of the pull-down node.
  • the output circuit includes:
  • a second transistor The gate of the second transistor is connected to the pull-up node.
  • the first electrode of the second transistor is connected to the clock signal terminal.
  • the second electrode of the second transistor is connected to the shift register. The output signal terminal;
  • a capacitor, a first pole of the capacitor is connected to the pull-up node, and a second pole of the capacitor is connected to the output signal terminal of the shift register.
  • the auxiliary circuit includes a first transistor, the gate of the first transistor serves as the control terminal of the auxiliary circuit, the first pole of the first transistor serves as the input terminal of the auxiliary circuit, and the first The second pole of the transistor serves as the output terminal of the auxiliary circuit;
  • the first transistor is a thin film transistor, and the channel width of the first transistor is in the range of 1000 ⁇ m to 3000 ⁇ m.
  • the second transistor is a thin film transistor, and the channel width of the second transistor is in the range of 5000 ⁇ m to 7000 ⁇ m. Within, the channel length of the first transistor and the second transistor is in the range of 3 ⁇ m to 6 ⁇ m.
  • the shift register further includes: a reset circuit, the reset circuit is connected to the pull-up node and a reset signal terminal of the shift register, and is configured to switch the pull-up node under the control of the reset signal terminal. Pull node to reset.
  • a display device including the above-mentioned display panel.
  • a method for controlling the above-mentioned display panel including a plurality of shift registers providing scanning signals to multiple rows of sub-pixels in multiple scanning periods, each scanning period including a first period and The second period includes:
  • At least one shift register among the plurality of shift registers provides a scan signal to at least one row of sub-pixels among the plurality of sub-pixels through at least one gate line;
  • At least one auxiliary circuit among the plurality of auxiliary circuits provides a reference signal to the gate line under the control of the auxiliary signal.
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 2 shows a timing diagram of a scan signal according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 7 shows a circuit diagram of a shift register in a display panel according to an embodiment of the present disclosure.
  • FIG. 8 shows a signal timing diagram of the shift register of FIG. 7 .
  • FIG. 9 shows a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 shows a schematic plan view of a display panel according to another embodiment of the present disclosure.
  • FIG. 11 shows a schematic plan view of a display panel according to another embodiment of the present disclosure.
  • FIG. 12 shows a partial layout diagram of the display panel of FIG. 9 .
  • 13 to 17 illustrate comparison results of the fall time of signals at both ends of the gate line when transistors of different sizes are used according to embodiments of the present disclosure.
  • a gate driving circuit is usually connected to one end of the gate line, referred to as the near end herein, to apply a scanning signal to it.
  • the end of the gate line opposite to the near end is called the distal end in this article.
  • the signal at the far end of the gate line is affected by various factors, such as the length and electrical characteristics of the gate line (such as resistance, capacitance, etc.), the size of the screen, etc., which results in a signal at the far end of the gate line.
  • a horizontal screen with a long gate line that is, a display panel with a horizontal size larger than a vertical size
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes a plurality of sub-pixels P, which are arranged in multiple rows. For example, they may be arranged in an N ⁇ M array, where N and M are both integers greater than 1.
  • the display panel may further include a gate driving circuit 10 connected to the plurality of sub-pixels P.
  • the gate driving circuit 10 can be respectively connected to the N rows of sub-pixels through a plurality of gate lines G1, G2,...GN extending along the first direction (the x direction in FIG. 1).
  • the gate line G1 is used to connect the Nth row of sub-pixels.
  • One row of sub-pixels P is used to provide scanning signals to the first row of sub-pixels P, and a second row of sub-pixels P is connected to the second row of sub-pixels P through the gate line G2 to provide scanning signals to the second row of sub-pixels P, and so on.
  • the first row of sub-pixels P is turned on in response to the scanning signal on the gate line G1
  • the second row of sub-pixels P is turned on in response to the scanning signal on the gate line G2, and so on.
  • the gate driving circuit 10 may scan N rows of sub-pixels P one row by one or multiple rows. For example, as shown in FIG. 2 , the gate driving circuit 10 can apply N sequentially shifted scanning signals to the gate lines G1, G2, ...GN to sequentially turn on the first row of sub-pixels P, the second row of sub-pixels P, and the second row of sub-pixels. Row sub-pixel P...Nth row sub-pixel P. In some embodiments, the gate driving circuit 10 can scan each row of sub-pixels sequentially from the last row to the first row, for example, applying scanning to the N gate lines in the order of GN, G(N-1),...G1. Signal.
  • the gate driving circuit 10 may also scan two or more rows of sub-pixels P at a time. For example, the gate driving circuit 10 can apply scanning signals to the gate lines G1 and G2 at the same time to turn on the sub-pixels P in the first row and the sub-pixels P in the second row at the same time. Then the gate driving circuit 10 can simultaneously Lines G3 and G4 apply scan signals to turn on the third row of sub-pixels P and the fourth row of sub-pixels P at the same time, and so on. In some embodiments, the gate driving circuit 10 may scan the N rows of sub-pixels P at least one row apart to sequentially turn on the sub-pixels P in some rows.
  • the gate driving circuit 10 can sequentially scan the odd rows of sub-pixels P (for example, sequentially turn on the first row of sub-pixels P, the third row of sub-pixels P, the fifth row of sub-pixels P, and so on), or sequentially scan the even-numbered rows of sub-pixels.
  • P for example, the second row of sub-pixels P, the fourth row of sub-pixels P, the sixth row of sub-pixels P are turned on in sequence, and so on).
  • the display panel may further include a source driving circuit 20 connected to the plurality of sub-pixels P.
  • the source driving circuit 20 may be connected to M columns of sub-pixels P respectively through a plurality of data lines extending along the second direction (the y direction in FIG. 1 ).
  • the source driving circuit 20 can be connected to the first column of sub-pixels P through the first data line to provide the first data signal D1 to the first column of sub-pixels P, and to the second column of sub-pixels P through the second data line and the second column of sub-pixels P.
  • a second data signal D2 is provided, and so on.
  • the source driving circuit 20 can provide M data signals D11, D12, for the first row of sub-pixels to the M sub-pixels P of the first row through M data lines respectively. .., D1M; when the second row of sub-pixels P is turned on, the source driving circuit 20 can respectively provide M data signals D21, D22 for the second row to the M sub-pixels P of the second row through multiple data lines. ,...,D2M, and so on.
  • the embodiments of the present disclosure are not limited thereto, which will be described in further detail below.
  • the display panel may further include a timing controller 30 , which is connected to the gate driving circuit 10 and the source driving circuit 20 , and may provide relevant information to the gate driving circuit 10 and the source driving circuit 20 control signal.
  • the timing controller 30 may provide the data control signal TP to the source driving circuit 20 , and the source driving circuit 20 may output data signals for each row under the control of the data control signal TP.
  • the timing controller 30 can also provide other control signals to the source driving circuit 20, including but not limited to row data start signals, data synchronization signals, data inversion signals, and so on.
  • the timing controller 30 can also provide various control signals to the gate driving circuit 10 , including but not limited to startup signals, clock signals, etc. required by the gate driving circuit 10 .
  • FIG. 3 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 100 includes a base substrate 101 that includes a display area AA and a peripheral area surrounding the display area.
  • the plurality of sub-pixels P are located in the display area AA and are arranged in multiple rows along the first direction (x direction in FIG. 3).
  • the plurality of gate lines G1, G2, ..., GN are located in the display area AA, extend along the first direction and are arranged along the second direction (y direction in FIG. 3) crossing the first direction.
  • Each gate line G1, G2, ..., GN is connected to at least one row of sub-pixels P.
  • multiple gate lines are connected to multiple rows of sub-pixels in a one-to-one correspondence, that is, the gate line G1 is connected to the first row of sub-pixels P, and the gate line G2 is connected to the second row of sub-pixels P.
  • one gate line may connect multiple rows of sub-pixels, or multiple gate lines may connect one row of sub-pixels. This disclosure is not limiting.
  • a plurality of shift registers GOA1, GOA2,..., GOAN are located in the peripheral area and are respectively connected to a plurality of gate lines G1, G2,..., GN to provide scanning signals to these gate lines.
  • they can be provided Scan signal as shown in Figure 2.
  • the embodiments of the present disclosure are not limited to this.
  • the timing of the scanning signal can be set as needed, and the present disclosure does not limit this.
  • multiple shift registers are connected to multiple gate lines in a one-to-one correspondence, that is, the shift register GOA1 is connected to the gate line G1, the shift register GOA2 is connected to the gate line G2, and so on.
  • one shift register can be connected to multiple gate lines, or one gate line can be connected to multiple shift registers, which the present disclosure is not limited to.
  • a plurality of auxiliary circuits A1, A2, ..., AN are located in the peripheral area.
  • One end of at least one gate line is connected to at least one shift register to receive a scan signal provided by the at least one shift register, and the other end is connected to at least one auxiliary circuit.
  • both ends of each gate line are connected to a shift register and an auxiliary circuit.
  • one end of the gate line G1 (the left end in Figure 3) is connected to the shift register GOA1, and the other end (the left end in Figure 3) is connected to the shift register GOA1.
  • the right end is connected to the auxiliary circuit A1; one end of the gate line G1 is connected to the shift register GOA2, the other end is connected to the auxiliary circuit A2, and so on.
  • the number of shift registers and auxiliary circuits connected to both ends of the gate line can be set as needed, which will not be described again here.
  • each auxiliary circuit A1, A2, ..., AN can be connected to receive the corresponding auxiliary signal (as shown by the arrow line).
  • the auxiliary signal can be an auxiliary signal provided separately, or the scanning signal provided by the lower-level shift register can be used as an auxiliary signal.
  • the control terminal of the auxiliary circuit connected to the i-th gate line is connected to receive the scan signal provided by the shift register connected to the i+k-th gate line as an auxiliary signal, where i and k are greater than or An integer equal to 1.
  • the control terminal of the auxiliary circuit A1 connected to the first gate line G1 can receive the scanning signal provided by the shift register GOA2 connected to the second gate line G2 as an auxiliary signal.
  • the control end of A2 can receive the scanning signal provided by the shift register GOA3 as an auxiliary signal, and so on.
  • the control end of the auxiliary circuit is shown as being connected to the gate line of the next row in Figure 3, this only indicates that the two are electrically connected and not necessarily physically connected.
  • the control end of the auxiliary circuit can receive signals from the auxiliary circuit in various ways. Other auxiliary signals provided by the shift register are described in detail below.
  • each auxiliary circuit A1, A2, ..., AN are connected to receive the reference signal, for example, connected to the reference signal terminal VGL that provides the reference signal.
  • the output end of each auxiliary circuit A1, A2, ..., AN is connected to the other end of the corresponding gate line (the right end in Figure 3).
  • the auxiliary circuits A1, A2, ..., AN can provide the reference signals at the respective input terminals to the respective output terminals under the control of the auxiliary signals at the respective control terminals.
  • the auxiliary circuit A1 can receive the scan signal provided by the shift register GOA2 as an auxiliary signal, and under its control, provide the reference signal at the reference signal terminal VGL to the scan line G1.
  • the auxiliary circuit A2 can receive the scan signal provided by the shift register GOA3. The scan signal is used as an auxiliary signal, and under its control, the reference signal at the reference signal terminal VGL is provided to the scan line G2, and so on.
  • k 1
  • the embodiments of the present disclosure are not limited thereto.
  • the value of k can be set as needed.
  • k can be 2 or other values.
  • the row of sub-pixels located at the top along the y direction is regarded as the first row of sub-pixels and the row of sub-pixels located at the bottom is regarded as the last row of sub-pixels in FIG. 3 , this is only for schematic illustration.
  • the so-called first row and the last row are defined according to the order of scanning.
  • the first row scanned is defined as the first row
  • the last row scanned is defined as the last row.
  • rows of pixels may be scanned from bottom to top, in which case the bottom row may be the first row and the top row may be the last row.
  • shift registers are shown as being located on one side (left side) of the display area in Figure 3, this is only for ease of illustration.
  • the shift registers can be distributed in other locations in the peripheral area as needed, for example, in the display area. on both sides, which will be explained in further detail below.
  • the display panel may also include other components such as a source driver and a timing controller, such as the source driver and timing controller described above with reference to FIG. 1 , which will not be described again here.
  • a source driver and a timing controller such as the source driver and timing controller described above with reference to FIG. 1 , which will not be described again here.
  • an end of the gate line connected to the shift register may be called a proximal end of the gate line, and an end of the gate line opposite to the proximal end may be called a distal end.
  • an auxiliary circuit at the far end of the gate line, embodiments of the present disclosure can complete the output of the scan signal after the shift register at the near end of the gate line, for example, after the scan signal starts to decrease from high level to low level. , pulling down the potential at the far end of the gate line, thereby reducing the fall time of the signal at the far end of the gate line.
  • the so-called fall time here refers to the time it takes for the signal to fall from a high level to the desired low level. Since the existence of the auxiliary circuit reduces the signal fall time at the far end of the gate line, the difference in signal fall time between the far end and the near end of the gate line can be reduced, thereby improving display quality.
  • FIG. 4 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel 200 includes a plurality of sub-pixels P located on a substrate, a plurality of gate lines G1, G2, ..., GN, and a plurality of shift registers GOA1, GOA2, ..., GOAN. and a plurality of auxiliary circuits A1, A2,..., AN.
  • the shift registers GOA1, GOA2,..., GOA1200 are distributed on opposite sides of the display area AA. For the convenience of description, they will be located on the first side of the display area AA along the first direction (in Figure 4
  • the shift registers GOA1, GOA3, GOA5...GOA1199 on the left side) are called the first shift register
  • the shift register GOA2 located on the second side of the display area AA along the first direction (the right side in Figure 4) , GOA4, GOA6... GOA1200 is called the second shift register.
  • the first shift registers GOA1, GOA3, GOA5...GOA1199 are connected in cascade
  • the second shift registers GOA2, GOA4, GOA6...GOA1200 are connected in cascade.
  • the so-called cascade connection here refers to the output end of the current shift register serving as the input end of the subsequent stage shift register.
  • the output end of the i-th stage shift register can be connected to the input end of the i+d-th stage shift register.
  • i and d are positive integers.
  • the output terminal of shift register GOA1 is connected to the input terminal of shift register GOA3
  • the output terminal of shift register GOA3 is connected to the input terminal of shift register GOA5, and so on.
  • Each shift register responds to an input signal at its respective input end and generates an output signal shifted relative to the input signal at its output end. Through this cascade connection, the output signal of the subsequent stage shift register is relative to the previous stage.
  • the output signal of the shift register is shifted, thereby realizing the shift register.
  • the shift register on the right can also be connected in a cascade manner.
  • the above description takes the step-by-step cascade as an example, that is, the output terminal of the current stage shift register is connected to the output terminal of the next stage shift register, however, the embodiment of the present disclosure is not limited to this, and the value of d can Set as desired.
  • the auxiliary circuits A1, A2, ..., GOA1200 are also distributed on the opposite sides of the display area AA.
  • the auxiliary circuits A1, A1, A2,..., and GOA1200 located on the second side (right side) of the display area AA will be described here.
  • A3, A5...A1199 are called the first auxiliary circuit
  • the auxiliary circuits A2, A4, A6...A1200 located on the first side (left side) of the display area AA are called the second auxiliary circuit.
  • the plurality of gate lines G1, G2,..., G1200 may include a plurality of alternately arranged first gate lines G1, G3, G5...G1199 and a plurality of second gate lines G2, G4, G6...G1200 .
  • the first ends of the first gate lines G1, G3, G5...G1199 are located on the first side of the display area and are connected to the corresponding first shift registers GOA1, GOA3, GOA5...GOA1199.
  • the two ends are located on the second side of the display area AA and are connected to the corresponding first auxiliary circuits A1, A3, A5...A1199.
  • the first end (left end) of the first gate line G1 is connected to the first shift register GOA1, and the second end (right end) is connected to the first auxiliary circuit A1; the first end (left end) of the first gate line G3 is connected to The second end (right end) of the first shift register GOA3 is connected to the first auxiliary circuit A3, and so on.
  • the first ends of the plurality of second gate lines G2, G4, G6...G1200 are located on the second side of the display area AA and are connected to the corresponding second shift registers GOA2, GOA4, GOA6...GOA1200, and the second ends are located on the second side of the display area AA
  • the first side of the display area AA is connected to the corresponding second auxiliary circuits A2, A4, A6...A1200.
  • the second end (left end) of the second gate line G2 is connected to the second auxiliary circuit A2, and the first end (right end) is connected to the second shift register GOA2; the second end (left end) of the second gate line G4 is connected to The first end (right end) of the second auxiliary circuit A4 is connected to the second shift register GOA4, and so on.
  • the first gate lines G1, G3, G5...G1199 are gate lines connecting odd-numbered rows of sub-pixels
  • the second gate lines G2, G4, G6...G1200 are connecting even-numbered rows of sub-pixels. gate line.
  • the first gate lines and the second gate lines may be alternately arranged in other ways, for example, two or more second gate lines may be arranged between two adjacent first gate lines. gate lines, or two or more first gate lines are provided between two adjacent second gate lines, and so on.
  • the control end of the first auxiliary circuit connected to each first gate line is connected to the second gate connected to the second gate line adjacent to the first gate line.
  • the output signal terminal of the shift register for example, the control terminal of the first auxiliary circuit A1 connected to the first gate line G1 is connected to the output signal terminal of the second shift register GOA2 connected to the first gate line G2.
  • the control terminal of an auxiliary circuit A3 is connected to the output signal terminal of the second shift register GOA4, and so on.
  • control terminal of the second auxiliary circuit connected to each second gate line is connected to the output signal terminal of the first shift register connected to the first gate line adjacent to the second gate line
  • control terminal of the second auxiliary circuit A2 is connected to the output signal terminal of the first shift register GOA3
  • control terminal of the second auxiliary circuit A4 is connected to the output signal terminal of the first shift register GOA5, and so on.
  • multiple shift registers GOA1, GOA2,..., GOA1200 can sequentially apply scanning signals to multiple gate lines G1, G2,..., G1200.
  • the shift register GOA1 on the left first generates a first scan signal and provides it to the gate line G1 to apply a scan signal
  • the shift register GOA2 on the right generates a second scan signal and provides it to the gate line G2 to apply a scan signal.
  • bilateral staggered driving is achieved.
  • the shift register GOA1 outputs the first scanning signal to the gate line G1
  • the second scanning signal generated by the shift register GOA2 turns on the auxiliary circuit A1 connected to it, thereby turning on the reference signal terminal VGL.
  • the signal is provided to the gate line G1, thereby shortening the signal fall time at the right end of the gate line G1.
  • the third scan signal generated by the shift register GOA3 causes the auxiliary circuit A2 to provide the reference signal to the left end of the gate line G2, thereby shortening the signal fall time at the left end of the gate line G2. , and so on. In this way, the difference in signal fall time at both ends of each gate line is reduced, which is beneficial to improving display quality.
  • FIG. 5 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel 500 of FIG. 5 is similar to the above-mentioned display panel 400, and the difference lies in at least the arrangement and connection mode of the auxiliary circuit and the shift register. For the sake of simplicity, the differences will mainly be explained in detail below.
  • the display panel 300 also includes a plurality of gate lines G1, G2, ..., G1200, which are also called first gate lines in this embodiment. Different from the above embodiment, shift registers and auxiliary circuits are connected to both sides of the gate line.
  • the display panel 300 includes a plurality of first shift registers GOA1_L, GOA2_L, .
  • the display panel 300 also includes a plurality of first auxiliary circuits A1_R, A2_R, ..., A1200_R on the second side (right side) of the display area AA, and a plurality of third auxiliary circuits located on the first side (left side) of the display area AA. Circuits A1_L, A2_L, ..., A1200_L.
  • the first end (left end) of the gate line G1 is connected to the first shift register GOA1_L, and the second end (right end) is connected to the third shift register GOA1_R.
  • the first end of the gate line G2 is connected to the first shift register GOA2_L, the second end is connected to the third shift register GOA2_R, and so on.
  • the first end (left end) of the gate line G1 is also connected to the third auxiliary circuit A1_L, and the second end (right end) is also connected to the first auxiliary circuit A1_R; the first end (left end) of the gate line G2 is also connected to the third auxiliary circuit A1_L.
  • Three auxiliary circuits A2_L, the second end (right end) is also connected to the first auxiliary circuit A2_R.
  • control terminal of the i-th first auxiliary circuit is connected to the output signal terminal of the i+k-th stage third shift register, and the output terminal of the i-th first auxiliary circuit is connected to the i-th first gate.
  • the second end of the line; the control terminal of the i-th third auxiliary circuit is connected to the output signal terminal of the i+k-th stage first shift register, and the output terminal of the i-th third auxiliary circuit is connected to the i-th first gate. the first end of the line.
  • the control terminal of the third auxiliary circuit A1_L is connected to the output signal terminal of the first shift register GOA2_L, and the control terminal of the third auxiliary circuit A2_L The terminal is connected to the output signal terminal of the first shift register GOA3_L, and so on.
  • the control terminal of the first auxiliary circuit A1_R is connected to the output signal terminal of the third shift register GOA2_R, and the control terminal of the first auxiliary circuit A2_L is connected to the output signal terminal of the third shift register GOA3_L. And so on.
  • the shift registers GOA1_L and GOA1_R apply scanning signals to the gate line G1 at the same time, and then the shift registers GOA2_L and GOA2_R apply the scanning signals to the gate line G2 at the same time, and so on, thereby sequentially applying scanning signals to multiple gate lines.
  • G1, G2,...,G1200 apply scanning signals. In this way, simultaneous driving on both sides is achieved.
  • the scanning signal generated by the third shift register GOA2_R on the right turns on the first auxiliary circuit A1_R connected to it. , thereby providing the reference signal to the right end of the gate line G1.
  • the signal fall time at the right end of the gate line G1 is shortened, making it closer to the signal fall time at the left end of the gate line G1.
  • the scanning signal generated by the first shift register GOA2_L on the left turns on the third auxiliary circuit A1_L connected thereto, thereby The reference signal is provided to the left end of the gate line G1.
  • the signal fall time at the left end of the gate line G1 is shortened, making it closer to the signal fall time at the right end of the gate line G1.
  • Other shift registers and auxiliary circuits work in a similar manner and will not be described again here.
  • FIG. 6 shows a schematic diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel 400 of FIG. 6 is similar to the above-mentioned display panel 400, and the difference lies in at least the arrangement and connection mode of the auxiliary circuit and the shift register. For the sake of simplicity, the differences will mainly be explained in detail below.
  • the display panel 400 also includes a plurality of gate lines G1, G2, ..., G1200, which are also called first gate lines in this embodiment.
  • multiple shift registers are arranged on one side of the display area AA, and multiple auxiliary circuits are arranged on the other side of the display area AA.
  • the plurality of shift registers include a plurality of first shift registers GOA1, GOA2, ..., GOA1200 located on the first side (left side) of the display area AA along the first direction and connected in cascade.
  • the plurality of auxiliary circuits include a plurality of first auxiliary circuits A1, A2, ..., A1200 located on a second side (right side) of the display area AA opposite to the first side along the first direction.
  • the first end of the gate line G1 is located on the first side of the display area AA and is connected to the first shift register GOA1, and the second end of the gate line G1 is located on the second side of the display area AA and is connected to the first auxiliary circuit A1;
  • the first end of the gate line G2 is located on the first side of the display area AA and is connected to the first shift register GOA2.
  • the second end of the gate line G2 is located on the second side of the display area AA and is connected to the first auxiliary circuit A2. analogy.
  • control end of the i-th first auxiliary circuit is connected to the second end of the i+k-th first gate line, and the output end of the i-th first auxiliary circuit is connected to the i-th first gate line. the second end of the line.
  • the control terminal of the first auxiliary circuit A1 ie, the first first auxiliary circuit
  • the gate line G2 ie, the second first gate line
  • the second end of the first auxiliary circuit A1 is connected to the second end of the gate line G1 (ie, the first first gate line);
  • the first auxiliary circuit A2 ie, the second first auxiliary circuit
  • the gate line G3 ie, the third first gate line
  • the output end of the first auxiliary circuit A2 is connected to the second end of the gate line G2, and so on.
  • the shift register GOA1 applies a scanning signal to the gate line G1, and then the shift register GOA2 applies a scanning signal to the gate line G2, and so on, thereby sequentially applying the scanning signal to the multiple gate lines G1, G2, .. ., G1200 applies scan signal.
  • the scanning signal provided by the first shift register GOA2 to the gate line G2 is provided via the right end of the gate line G2 to the first auxiliary circuit A1, so that the first auxiliary circuit A1 is turned on, thereby providing the reference signal to the right end of the gate line G1.
  • the signal fall time at the right end of the gate line G1 is shortened, making it closer to the signal fall time at the left end of the gate line G1.
  • Other shift registers and auxiliary circuits work in a similar manner and will not be described again here.
  • the size of the display panel can be arbitrarily selected according to needs, for example but not limited to within the range of 8 inches to 15 inches.
  • the resolution of the display panel can be set as needed, such as but not limited to 2160 ⁇ 1440.
  • the material of the gate lines may be metal, including but not limited to aluminum or copper.
  • the length of the gate line can be set according to the size of the display panel, for example, it can be in the range of 200mm-300mm, for example, it can be about 265mm, and in some embodiments, it can be 265.68mm.
  • the resistance of the gate line may be approximately in the range of 4.5 k ⁇ to 5.5 k ⁇ , for example, may be 5 k ⁇ , and in some embodiments may be 4.95 k ⁇ .
  • the capacitance of the gate line may be in the range of 250 pf to 350 pf, may be approximately 300 pf, for example, and may be 284.3 pf in some embodiments.
  • FIG. 7 shows a circuit diagram of a shift register in a display panel according to an embodiment of the present disclosure.
  • the structure of the shift register is applicable to the display panel of any of the above embodiments.
  • FIG. 7 takes the first gate line G1 as an example for illustration.
  • one end of the gate line G1 is connected to the shift register GOA1, and the other end is connected to the auxiliary circuit A1.
  • One end of the gate line G1 connected to the shift register GOA1 is also called a near end (indicated by NE), and the end opposite to the near end is also called a far end (indicated by FE).
  • NE near end
  • FE far end
  • the shift register GOA1 and the auxiliary circuit A1 are shown as being located at the left end and the right end of the gate line G1 respectively in FIG. 7 , this is only for illustration, and the positions of the two can be interchanged.
  • the auxiliary circuit A1 includes a transistor M1 (first transistor).
  • the gate of the transistor M1 serves as the control terminal of the auxiliary circuit A1 and is connected to receive the auxiliary signal CTR.
  • the auxiliary signal CTR may come from the output signal terminal of other shift registers or from other gate lines.
  • the first pole of the transistor M1 serves as the input terminal of the auxiliary circuit A1 and is connected to the reference signal terminal VGL1 for providing the reference signal.
  • the second pole of the transistor M1 serves as the output terminal of the auxiliary circuit A and is connected to the other end FE of the gate line G1.
  • the shift register GOA1 may include an input circuit 510, an output circuit 520, a control circuit 530, and a pull-down circuit.
  • the pull-down circuit may include a first pull-down circuit 5401 and a second pull-down circuit 5402 , collectively referred to as pull-down circuit 540 .
  • the input circuit 510 connects the input signal terminal INPUT of the shift register GOA1 and the pull-up node PU of the shift register GOA1.
  • the input circuit 510 may provide the signal of the input signal terminal INPUT to the pull-up node PU.
  • the output circuit 520 is connected to the pull-up node PU, the clock signal terminal CLK of the shift register GOA1 and the output signal terminal OUTPUT of the shift register GOA1.
  • the output circuit 520 may provide the signal of the clock signal terminal CLK to the output signal terminal OUTPUT under the control of the pull-up node PU to output the scan signal.
  • the control circuit 530 connects the pull-up node PU and the pull-down node of the shift register GOA1.
  • the shift register may include one of the above two pull-down nodes.
  • the control circuit 530 is used to control the potential of the pull-down node PD according to the potential of the pull-up node PU.
  • the pull-down circuit 540 connects the output signal terminal OUTPUT and the pull-down node PD.
  • the pull-down circuit 540 can pull down the potential of the output signal terminal OUTPUT under the control of the pull-down node PD.
  • the first pull-down circuit 5401 is connected to the pull-down nodes PD1 and PD2, and can pull down the potential of the output signal terminal OUTPUT under the control of the pull-down nodes PD1 and PD2.
  • the second pull-down circuit 5402 is connected to the pull-down nodes PD1 and PD2, and pulls down the potential of the pull-up node PU under the control of the pull-down nodes PD1 and PD2.
  • shift register GOA1 may also include a reset circuit 550 .
  • the reset circuit 550 is connected to the pull-up node PU and the reset signal terminal of the shift register GOA1.
  • the reset signal terminal may include a first reset signal terminal RESET, which is used to receive a reset signal for resetting the shift register of this stage.
  • the reset signal terminal may also include a second reset signal terminal TRST, which is used to receive a total reset signal for resetting multi-stage shift registers including the current stage shift register.
  • the reset circuit 550 can reset the pull-up node PU under the control of the reset signal terminal RESET.
  • the reset circuit 550 may also reset the pull-up node PU under the control of the reset signal terminal TRST.
  • shift register GOA1 may also include a noise reduction circuit 560 .
  • the noise reduction circuit 560 is connected to the input signal terminal INPUT and the pull-down nodes PD1 and PD2, and can perform noise reduction on the pull-down nodes PD1 and PD2 under the control of the input signal terminal INPUT.
  • the output circuit 520 may include a transistor M2 and a capacitor C.
  • the gate of the transistor M2 is connected to the pull-up node PU, the first electrode of the transistor M2 is connected to the clock signal terminal CLK, and the second electrode of the transistor M2 is connected to the output signal terminal OUTPUT.
  • the first pole of the capacitor C is connected to the pull-up node PU, and the second pole of the capacitor C is connected to the output signal terminal OUTPUT.
  • the input circuit 510 may include a transistor M3, a gate electrode and a first electrode of the transistor M3 are connected to the input signal terminal INPUT, and a second electrode of the transistor M3 is connected to the pull-up node PU.
  • the control circuit 530 may include at least one of a first control circuit and a second control circuit.
  • the first control circuit includes transistors M4, M5, M6 and M7.
  • the gate and first electrode of the transistor M4 are connected to the power signal terminal VDDO, and the second electrode of the transistor M4 is connected to the gate of the transistor M5.
  • the first electrode of the transistor M5 is connected to the power signal terminal VDDO, and the second electrode of the transistor M5 is connected to the pull-down node PD1.
  • the gates of the transistors M6 and M7 are both connected to the pull-up node PU, and the first electrodes of the transistors M6 and M7 are both connected to the reference signal terminal VGL2.
  • the second electrode of the transistor M6 is connected to the gate of the transistor M5, and the second electrode of the transistor M7 is connected to the pull-down node PD1.
  • the second control circuit includes transistors M8, M9, M10 and M11.
  • the gate and first electrode of the transistor M8 are connected to the power signal terminal VDDE, and the second electrode of the transistor M8 is connected to the gate of the transistor M9.
  • the first electrode of the transistor M9 is connected to the power signal terminal VDDE, and the second electrode of the transistor M9 is connected to the pull-down node PD2.
  • the gates of the transistors M10 and M11 are both connected to the pull-up node PU, and the first electrodes of the transistors M10 and M11 are both connected to the reference signal terminal VGL2.
  • the second electrode of the transistor M10 is connected to the gate of the transistor M9, and the second electrode of the transistor M11 is connected to the pull-down node PD2.
  • the power signal terminals VDDO and VDDE may be at a high level alternately, for example, during a period when the power signal terminal VDDO receives a high-level power signal, the power signal terminal VDDE receives a low-level power signal, and vice versa. In this way, the first control circuit and the second control circuit can be made to work alternately to avoid device loss caused by the transistors in the control circuit 530 being turned on for a long time.
  • the first pull-down circuit 5401 may include at least one of the transistors M12 and M13.
  • the second pull-down circuit 5402 may include at least one of transistors M14 and M15. As shown in FIG. 7 , the gate of the transistor M12 is connected to the pull-down node PD1, and the gate of the transistor M13 is connected to the pull-down node PD2. The first poles of the transistors M12 and M13 are both connected to the reference signal terminal VGL2, and the first poles of the transistors M12 and M13 are both connected to the output signal terminal OUTPUT. Similarly, the gate of the transistor M14 is connected to the pull-down node PD1, and the gate of the transistor M15 is connected to the pull-down node PD2. The first poles of the transistors M14 and M15 are both connected to the reference signal terminal VGL2, and the first poles of the transistors M14 and M15 are both connected to the pull-up node PU.
  • Reset circuit 550 may include transistor M16.
  • reset circuit 550 may also include transistors M17 and M18. As shown in Figure 7, the gate of the transistor M16 is connected to the reset signal terminal RESET, the first electrode is connected to the reference signal terminal VGL2, and the second electrode is connected to the pull-up node PU. The gates of the transistors M17 and M18 are both connected to the reset signal terminal TRST, and the first electrodes of the transistors M17 and M18 are both connected to the reference signal terminal VGL2. The second electrode of the transistor M17 is connected to the pull-up node PU, and the second electrode of the transistor M8 is connected to the output signal terminal OUTPUT.
  • the noise reduction circuit 560 may include at least one of the transistors M19 and M20. As shown in Figure 7, the gates of transistors M19 and M20 are both connected to the input signal terminal INPUT. The first poles of the transistors M19 and M20 are both connected to the reference signal terminal VGL2. The second electrode of the transistor M19 is connected to the pull-down node PD1, and the second electrode of the transistor M20 is connected to the pull-down node PD2.
  • At least one of the transistors M1 to M20 is a thin film transistor.
  • at least one of the transistors M1 and M2 may be a thin film transistor.
  • the above-mentioned transistors M1 to M20 may all be thin film transistors.
  • the channel width of each thin film transistor can be set according to needs, for example, according to the size of the display panel, the material, length and electrical characteristics of the gate line, and so on.
  • the size of the transistors M1 and M2 can be designed by comprehensively considering the length and material of the gate line within the size range of the reserved space. , to optimize the reduction effect on the signal fall time on the gate line.
  • transistor M1 may be in the range of 1800 ⁇ m to 2200 ⁇ m, and may be approximately 2000 ⁇ m, for example.
  • the channel width of the transistor M2 may be in the range of 5800 ⁇ m to 6200 ⁇ m, and may be approximately 6000 ⁇ m, for example.
  • the channel length of each transistor can be set in the range of 3um to 6um, for example, it can be 4.0um.
  • the above embodiment takes two reference signal terminals VGL1 and VGL2 as an example for description, the embodiments of the present disclosure are not limited thereto, and the reference signal terminals VGL1 and VGL2 can be implemented as the same reference signal terminal.
  • FIG. 8 shows a signal timing diagram of the shift register of FIG. 7 .
  • the power signal terminal VDDO is at a high level and the power signal terminal VDDE is at a low level during a certain period of time as an example for explanation. Therefore, during the scanning period shown in FIG. 8 , the first control circuit controlled by the power signal terminal VDDO is in the working state, and the second control circuit controlled by the power signal terminal VDDE is in the non-working state.
  • the clock signal terminal CLK of the shift register GOA1 can receive the clock signal CLK1, and the clock signal terminal of the next-level shift register (such as GOA2) can receive the clock signal CLK2, so that the output is relative to the shift register
  • the output signal of GOA1 is the shifted output signal.
  • the shift register connected to the odd-numbered gate lines may receive the clock signal CLK1
  • the shift register connected to the even-numbered gate lines may receive the clock signal CLK2 and receive the clock signal CLK2.
  • More (for example, 4, 8, 12 or 16) clock signals can be set as needed and provided to each shift register in a manner adapted to the shift register cascade structure. bit register.
  • the input signal terminal INPUT receives a high-level input signal, causing the transistor M3 to turn on, so that the pull-up node PU point becomes a high level.
  • the high level of the pull-up node PU charges the capacitor C and turns on the transistor M2.
  • the output signal terminal OUTPUT remains at a low level.
  • the high level of the pull-up node PU also turns on the transistors M6 and M7, thereby providing the low level of the reference signal terminal VGL2 to the pull-down node PD1.
  • the high level of the input signal terminal INPUT also turns on the transistors M19 and M20, thereby stabilizing the pull-down nodes PD1 and PD2 at a low level, and the noise reduction circuit 560 plays a role in reducing noise on the pull-down nodes PD1 and PD2.
  • the clock signal CLK1 received by the clock signal terminal CLK changes from low level to high level.
  • the transistor M2 since the transistor M2 is in the on state, the high level of the clock signal CLK1 is provided to the output signal terminal OUTPUT. Thereby outputting a high level scanning signal.
  • the potential of the pull-up node PU increases again on the original basis.
  • the reset signal terminal RESET receives a high-level reset signal.
  • the scan signal output by the next-level shift register is as a reset signal.
  • the high level of the reset signal terminal RESET turns on the transistor M16, thereby pulling the potential of the pull-up node PU down to a low level.
  • the low level of the pull-up node PU turns off the transistors M6 and M7 in the control circuit 530, and the transistor M5 turns on, thereby providing the high level of the power signal terminal VDDO to the pull-down node PD1.
  • the high level of the pull-down node PD1 turns on the transistor M12, thereby pulling the output signal terminal OUTPUT down to the low level of the reference signal terminal VGL2.
  • the auxiliary signal CTR received by the auxiliary circuit A1 is at a high level.
  • the auxiliary signal is at a high level.
  • the high level of the auxiliary signal CTR turns on the transistor M1, thereby providing the low level of the reference signal terminal VGL1 to the output signal terminal OUTPUT. In this way, the signal drop at the output signal terminal OUTPUT is accelerated, thereby reducing the difference in signal drop time at both ends of the gate line G1.
  • the high level of the pull-down node PD1 also turns on the transistor M14, thereby further pulling down the potential of the pull-up node PU.
  • this period including t1, t2, and t3 is also called a scan period.
  • Periods t1 and t2 may be referred to as the first period of the scanning period, and period t3 may be referred to as the second period of the scanning period.
  • the output of the scan signal is completed in the first period, and the reset and accelerated decline of the scan signal is completed in the second period.
  • the scanning periods of each gate line may overlap. For example, periods t2 and t3 of the previous scanning period may overlap with t1 and t2 of the following scanning period.
  • the embodiments of the present disclosure are not limited thereto.
  • the display panel of the embodiment of the present disclosure can adopt any suitable shift register circuit structure, such as but not limited to 9T1C, 11T1C, 19T1C and other shift register structures.
  • FIG. 9 shows a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • the plan layout of FIG. 9 can be applied to, for example, the circuit structure of FIG. 4 described above, so the layout of FIG. 9 will be described below in conjunction with FIG. 4 .
  • the connection wiring between the gate line, the auxiliary circuit and the shift register is omitted.
  • the first auxiliary circuit A1 connected to the gate line G1 and the second shift register GOA2 connected to the gate line G2 are located on the second side (right side) of the display area AA.
  • the first auxiliary circuit A1 is located between the display area AA and the second shift register GOA2.
  • the transistor M1 in the first auxiliary circuit A1 is located between the transistor M2 in the second shift register GOA2 and the display area AA, so that the second ends of the gate lines G1 and G2 in the display area AA are located in the auxiliary circuit A1.
  • Transistor M1 in circuit A1 is on the side facing away from transistor M2 in first shift register GOA1.
  • first shift register GOA1 connected to the gate line G1 and the second auxiliary circuit A2 connected to the gate line G2 are located on the first side (left side) of the display area AA, where the second auxiliary circuit A2 is located on the display area AA.
  • first auxiliary circuit A3, the second auxiliary circuit A4, the first shift register GOA3 and the second shift register GOA4 connected to the gate lines G3 and G4 are laid out in a similar manner, and so on.
  • the size of each of the first auxiliary circuits A1, A3, A5... and the second auxiliary circuits A2, A4, A6... in the second direction is substantially equal to the size of the two rows of sub-pixels P in the second direction ( In Figure 9, it is the sum of the dimensions in the longitudinal direction, that is, the y direction).
  • the size of the auxiliary circuit here can be characterized by the projected size of the transistors in the auxiliary circuit on the base substrate.
  • the size of the projection of each transistor M1 and M2 on the base substrate in the longitudinal direction is substantially equal to the size of the projection of two adjacent rows of sub-pixels on the base substrate in the longitudinal direction.
  • FIG. 10 shows a schematic plan view of a display panel according to another embodiment of the present disclosure.
  • the plan layout of FIG. 10 may be applicable to, for example, the circuit structure of FIG. 5 described above, so the layout of FIG. 10 will be described below in conjunction with FIG. 5 .
  • the first auxiliary circuit A1_R is located between the display area AA and the third shift register GOA1_R
  • the third auxiliary circuit A1_L is located between the display area AA and the first shift register GOA1_L.
  • the transistor M1 in the first auxiliary circuit A1_R is located between the second end (right end) of the gate line G1 and the transistor M2 of the third shift register GOA1_R
  • the transistor M1 in the third auxiliary circuit A1_L is located between the gate line Between the first end (left end) of G1 and the transistor M2 of the first shift register GOA1_L.
  • each auxiliary circuit including the first auxiliary circuit and the third auxiliary circuit has a size in the second direction that is substantially equal to a row of sub-pixels P in the second direction (vertical direction). ) on the size.
  • FIG. 11 shows a schematic plan view of a display panel according to another embodiment of the present disclosure.
  • the plan layout of FIG. 11 can be applied to, for example, the circuit structure of FIG. 6 described above, so the layout of FIG. 11 will be described below in conjunction with FIG. 6 .
  • each auxiliary circuit ie, the transistor therein
  • the first auxiliary circuit and the third auxiliary circuit has a size in the second direction that is substantially equal to one row of sub-pixels P in the second direction (vertical direction). size of.
  • FIG. 12 shows a partial layout diagram of the display panel of FIG. 9 .
  • the display area AA is provided with a plurality of gate lines extending along the first direction (only gate lines G5 and G6 are marked in FIG. 12 ), and a plurality of data lines extending along the second direction ( Only data lines D1 and D2 are shown in Figure 12).
  • a plurality of sub-pixels arranged in an array are also provided in the display area AA, and each sub-pixel may include one or more transistors TFT.
  • each row of sub-pixels is connected to the same gate line, and each column of sub-pixels is connected to a data line.
  • the fifth row of sub-pixels is connected to the gate line G5, and the sixth row of sub-pixels is connected to the gate line G6; the first column of sub-pixels is connected to the gate line G5.
  • the pixel is connected to the data line D1, the second column of sub-pixels is connected to the data line D2, and so on.
  • a plurality of common electrodes Ecom and a plurality of common electrode lines Vcom extending along the first direction and arranged in the second direction are also provided in the display area AA.
  • the common electrode Ecom may have a hollow pattern and be connected to the common electrode line Vcom.
  • the common electrode line Vcom is connected to the common electrode bus line Vcom_bus located in the peripheral area outside the display area AA.
  • the transistor M2 of the shift register GOA5 and the transistor M1 of the auxiliary circuit A6 are located in the peripheral area outside the display area AA, and each has a source S, a drain D, and a gate G.
  • the first end of the gate line G5 is connected to the drain D of the transistor M2 of the shift register GOA5 through the wiring W1.
  • the first end of the gate line G5 is connected to the trace W1 through the crossover hole H1, and is further connected to the drain D of the transistor M2 of the shift register GOA5.
  • the gate G of the transistor M2 in the shift register GOA5 is connected to the first electrode plate E1 of the capacitor C.
  • the first electrode plate E1 of the capacitor C can be connected to the relevant structure in the GOA5 through the crossover hole Vc to receive the control signal.
  • the first electrode plate E1 of the capacitor C may be disposed in the same layer as the gate G of the transistor M2.
  • the second electrode plate E2 of the capacitor C may be electrically connected to one of the source S and the drain D of the transistor M2 in the shift register GOA5.
  • the second electrode plate E2 of the capacitor C may be arranged in the same layer as the source S and drain D of the transistor M2 in the shift register GOA5 and be connected to the drain D.
  • the second end of the gate line G6 is connected to the drain D of the transistor M1 of the auxiliary circuit A6 through the trace W2.
  • the first end of the gate line G6 is connected to the trace W2 through the crossover hole H2, and is further connected to the drain D of the transistor M1 of the auxiliary circuit A6.
  • the trace W1 may include a first portion W1_1 extending along the first direction and a second portion W1_2 extending along the second direction.
  • the trace W2 may also include a first portion W2_1 extending along the first direction and a second portion W2_2 extending along the second direction.
  • the first portion W1_1 of trace W1 is substantially parallel to the first portion W2_1 of trace W2.
  • the second portion W1_2 of the trace W1 is substantially parallel to the second portion W2_2 of the trace W2.
  • the second portion W1_2 of the trace W1 is located between the second portion W2_2 of the trace W2 and the display area AA.
  • the second end of the gate line G6 is also connected to the gate G of the transistor M1 in the auxiliary circuit A2 through the wiring W3, wherein the drain D of the transistor M1 of the auxiliary circuit A2 is connected to the first end of the gate line G2 .
  • the first end of the gate line G6 is connected to the trace W2 through the crossover hole H2
  • the trace W2 is connected to the trace W3 through the crossover hole H3
  • the trace W3 is connected to the gate of the transistor M1 in the auxiliary circuit A2 G. In this way, an electrical connection is achieved between the first end of the gate line G6 and the gate G of the transistor M1 in the auxiliary circuit A2.
  • the trace W3 may extend along the second direction, for example, extend along the second direction across one transistor M1 and be located between the second portion W22 of the trace W2 connected to the transistor M1 and the transistor M1 .
  • the respective source S and drain D of the transistors M1 and M2 are arranged in a comb-like pattern, and the patterns of the source S and drain D of each transistor mesh with each other.
  • embodiments of the present disclosure are not limited thereto, and the sources S and drains D of the transistors M and M2 may be arranged in any suitable pattern as needed.
  • embodiments of the present disclosure can pull down the output signal at the far end of the gate line and reduce the signal fall time of the entire gate line, especially the fall time of the far end signal. , reducing the difference in signal fall time between the near end and the far end of the gate line, and improving the display uniformity of the entire display panel.
  • the function and effect of the auxiliary circuit will be explained below with reference to Figures 13 to 17.
  • 13 to 17 illustrate comparison results of the fall time of signals at both ends of the gate line when transistors of different sizes are used according to embodiments of the present disclosure.
  • the signal fall time Near Tf at the near end of the gate line and the signal fall time at the far end when the auxiliary circuit (transistor M1) is provided Far Tf is significantly shorter.
  • the channel width of transistor M2 is 4900 ⁇ m
  • the signal fall time at the near end of the gate line can be reduced from 4.056 ⁇ s to 3.361 ⁇ s, and the signal fall time at the far end of the gate line can be reduced.
  • the signal fall time is reduced from 4.547 ⁇ s to 3.227 ⁇ s.
  • the channel width of transistor M2 is 4900 ⁇ m
  • the greater the channel width of transistor M1 the shorter the near-end signal fall time Near Tf and the far-end signal fall time Far Tf of the gate line.
  • the space occupied by each transistor is limited.
  • the transistor M2 in the shift register plays a major role in the signal drop at the near end of the gate line
  • the transistor M1 in the auxiliary circuit plays a major role in the signal drop at the far end of the gate line, that is to say , compared with transistor M1, transistor M2 has a greater effect on the near-end signal fall time; compared with M2, transistor M1 has a greater effect on the far-end signal fall time of the gate line.
  • the transistor M1 can be weighed and M2 sizes to achieve optimized size allocation. As shown in Figures 16 and 17, when the sum of the channel widths of transistors M1 and M2 is fixed at 8000um, the transistor M2 is increased successively and the transistor M1 is decreased successively. It can be seen from FIGS.
  • the channel width of the transistor M1 may be in the range of 1000 ⁇ m to 3000 ⁇ m, and the channel width of the transistor M2 may be in the range of 5000 ⁇ m to 7000 ⁇ m.
  • the transistor M1 and The channel length of M2 can be in the range of 3 ⁇ m to 6 ⁇ m.
  • the ratio of the channel widths of the transistors M1 and M2 can be set so that the signal fall time at the near end and the far end of the gate line and the difference between the two tend to be minimized, for example, the difference is less than 0.1us. .
  • the ratio of the channel width of the transistor M1 to the channel width of the transistor M2 may be set between 0.23 and 0.45, for example, may be set to approximately 0.33. It can be seen from Figures 16 and 17 that when the channel width of transistor M2 is approximately 6000um and the channel width of transistor M1 is approximately 2000um, the signal fall time at the near end and far end of the gate line is generally small and the difference is minimal.
  • An embodiment of the present disclosure also provides a display device, including the display panel of any of the above embodiments.
  • Examples of display devices include, but are not limited to, various electronic devices with display functions, such as tablets, televisions, mobile phones, and so on.
  • a method for controlling the display panel of any of the above embodiments including multiple shift registers providing scanning signals to multiple rows of sub-pixels in multiple scanning periods, each scanning period including a first period and the second period.
  • At least one shift register among the plurality of shift registers provides a scan signal to at least one row of subpixels among the plurality of subpixels through at least one gate line.
  • At least one auxiliary circuit among the plurality of auxiliary circuits provides a reference signal to the gate line under the control of the auxiliary signal.

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Abstract

本公开的实施例提供了一种显示面板、显示设备和显示面板的控制方法。显示面板包括：衬底基板；多个子像素；多条栅极线，沿第一方向延伸且沿与第一方向交叉的第二方向排列，每条栅极线与至少一行子像素连接；多个移位寄存器；多个辅助电路，位于衬底基板的周边区，其中栅极线的第一端连接移位寄存器，栅极线的第二端连接辅助电路，其中辅助电路的控制端连接为接收辅助信号，辅助电路的输入端连接为接收参考信号，辅助电路的输出端连接至栅极线的第二端，辅助电路被配置为在所述辅助电路的控制端处辅助信号的控制下将所述辅助电路的输入端处的参考信号提供至所述辅助电路的输出端。

Description

显示面板、显示设备和显示面板的控制方法 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板、显示设备和显示面板的控制方法。
背景技术
显示面板上的通常设置有多个子像素、多条栅极线和栅极驱动电路，多个子像素可以通过栅极线来接收由栅极驱动电路提供的扫描信号。然而随着技术的发展，对显示面板的显示质量要求越来越高，目前的显示面板设计无法满足高质量显示需求。
发明内容
本公开的实施例提供了一种显示面板、显示设备和显示面板的控制方法。
根据本公开的一方面，提供了一种显示面板，包括：
衬底基板，所述衬底基板包括显示区和围绕显示区的周边区；
多个子像素，位于所述显示区，且沿第一方向布置成多行；
多条栅极线，位于所述显示区，所述多条栅极线沿第一方向延伸且沿与第一方向交叉的第二方向排列，每条栅极线与至少一行子像素连接；
多个移位寄存器，位于所述周边区，并配置为提供扫描信号；
多个辅助电路，位于所述周边区，其中至少一条栅极线的第一端连接至少一个所述移位寄存器并配置为接收所述至少一个移位寄存器提供的扫描信号，所述至少一条栅极线的第二端连接至少一个所述辅助电路，其中所述辅助电路的控制端配置为接收辅助信号，所述辅助电路的输入端配置为接收参考信号，所述辅助电路的输出端连接至所述栅极线的第二端，所述辅助电路配置为在所述辅助信号的控制下将所述辅助电路的输入端处的参考信号提供至所述辅助电路的输出端。
例如，与所述多条栅极线中的第i条栅极线连接的辅助电路的控制端连接为接收与第i+k条栅极线连接的移位寄存器提供的扫描信号作为辅助信号，其中i和k为大于或等于1的整数。
例如，所述多个移位寄存器包括沿所述第一方向位于所述显示区第一侧且级联连 接的多个第一移位寄存器；
所述多个辅助电路包括沿所述第一方向位于所述显示区与所述第一侧相对的第二侧的多个第一辅助电路；
所述至少一条栅极线包括多条第一栅极线，所述第一栅极线的第一端位于所述显示区的第一侧且连接所述第一移位寄存器，所述第一栅极线的第二端位于所述显示区的第二侧且连接所述第一辅助电路。
例如，第i个第一辅助电路的控制端连接第i+k条第一栅极线的第二端，第i个第一辅助电路的输出端连接第i条第一栅极线的第二端。
例如，所述多个移位寄存器还包括位于所述显示区第二侧且级联连接的多个第二移位寄存器；
所述多个辅助电路还包括位于所述显示区第一侧的多个第二辅助电路；
所述至少一条栅极线还包括与所述多条第一栅极线交替设置的多条第二栅极线，所述第二栅极线的第一端位于所述显示区的第二侧且连接所述第二移位寄存器，所述第二栅极线的第二端位于所述显示区的第一侧且连接所述第二辅助电路。
例如，所述第一栅极线连接奇数行子像素、所述第二栅极线连接偶数行子像素。
例如，k＝4，与每条第一栅极线连接的第一辅助电路的控制端连接至与该第一栅极线间隔三条所述栅极线的第二栅极线所连接的第二移位寄存器的输出信号端；与每条第二栅极线连接的第二辅助电路的控制端连接至与该第二栅极线间隔三条所述栅极线的第一栅极线所连接的第一移位寄存器的输出信号端。
例如，第一辅助电路位于所述显示区与所述第二移位寄存器之间，所述第二辅助电路位于所述显示区与所述第一移位寄存器之间。
例如，所述第一辅助电路和所述第二辅助电路各自在第二方向上的尺寸等于两行子像素在第二方向上的尺寸之和。
例如，所述多个移位寄存器还包括位于所述显示区第二侧的多个第三移位寄存器；
所述多个辅助电路还包括位于所述显示区第一侧的多个第三辅助电路；
所述第一栅极线的第一端还连接所述第三辅助电路，所述第一栅极线的第二端还连接所述第三移位寄存器。
例如，所述第一辅助电路位于所述显示区与所述第三移位寄存器之间，所述第三辅助电路位于所述显示区与所述第一移位寄存器之间。
例如，第i个第一辅助电路的控制端连接第i+k级第三移位寄存器的输出信号端， 第i个第一辅助电路的输出端连接第i条第一栅极线的第二端；
第i个第三辅助电路的控制端连接第i+k级第一移位寄存器的输出信号端，第i个第三辅助电路的输出端连接第i条第一栅极线的第一端。
例如，所述辅助电路包括第一晶体管，所述第一晶体管的栅极作为所述辅助电路的控制端，所述第一晶体管的第一极作为所述辅助电路的输入端，所述第一晶体管的第二极作为所述辅助电路的输出端。
例如，所述移位寄存器包括：
输入电路，连接所述移位寄存器的输入信号端和所述移位寄存器的上拉节点，并配置为将所述输入信号端的信号提供至所述上拉节点；
输出电路，连接所述上拉节点、所述移位寄存器的时钟信号端以及所述移位寄存器的输出信号端，并配置为在所述上拉节点的控制下将所述时钟信号端的信号提供至所述输出信号端，以输出扫描信号；
控制电路，连接所述移位寄存器的上拉节点和所述移位寄存器的下拉节点，并配置为根据所述上拉节点的电位来控制所述下拉节点的电位；
下拉电路，连接所述移位寄存器的输出信号端和所述下拉节点，并配置为在所述下拉节点的控制下，下拉所述移位寄存器的输出信号端的电位。
例如，所述输出电路包括：
第二晶体管，所述第二晶体管的栅极连接所述上拉节点，所述第二晶体管的第一极连接所述时钟信号端，所述第二晶体管的第二极连接所述移位寄存器的输出信号端；以及
电容，所述电容的第一极连接所述上拉节点，所述电容的第二极连接所述移位寄存器的输出信号端。
例如，所述辅助电路包括第一晶体管，所述第一晶体管的栅极作为所述辅助电路的控制端，所述第一晶体管的第一极作为所述辅助电路的输入端，所述第一晶体管的第二极作为所述辅助电路的输出端；
所述第一晶体管为薄膜晶体管，所述第一晶体管的沟道宽度在1000μm至3000μm的范围内，所述第二晶体管为薄膜晶体管，所述第二晶体管的沟道宽度在5000μm至7000μm的范围内，所述第一晶体管和所述第二晶体管的沟道长度在3μm至6μm的范围内。
例如，所述移位寄存器还包括：复位电路，所述复位电路连接至所述上拉节点和 所述移位寄存器的复位信号端，并配置为在所述复位信号端的控制下将所述上拉节点复位。
根据本公开的另一方面，还提供了一种显示设备，包括上述显示面板。
根据本公开的另一方面，还提供了一种上述显示面板的控制方法，包括多个移位寄存器在多个扫描时段分别向多行子像素提供扫描信号，每个扫描时段包括第一时段和第二时段，其中：
在第一时段，多个移位寄存器中的至少一个移位寄存器通过至少一条栅极线向多个子像素中的至少一行子像素提供扫描信号；
在第二时段，多个辅助电路中的至少一个辅助电路在辅助信号的控制下将参考信号提供至所述栅极线。
附图说明
图1示出了根据本公开实施例的一种显示面板的示意图。
图2示出了根据本公开实施例的扫描信号的时序图。
图3示出了根据本公开实施例的显示面板的示意图。
图4示出了根据本公开另一实施例的显示面板的示意图。
图5示出了根据本公开另一实施例的显示面板的示意图。
图6示出了根据本公开另一实施例的显示面板的示意图。
图7示出了根据本公开实施例的显示面板中的移位寄存器的电路图。
图8示出了图7的移位寄存器的信号时序图。
图9示出了根据本公开实施例的显示面板的平面示意图。
图10示出了根据本公开另一实施例的显示面板的平面示意图。
图11示出了根据本公开另一实施例的显示面板的平面示意图。
图12示出了图9的显示面板的局部布局图。
图13至图17示出了根据本公开实施例的在采用不同尺寸的晶体管的情况下栅极线两端信号的下降时间的比较结果图。
具体实施方式
虽然将参照含有本公开的较佳实施例的附图充分描述本公开，但在此描述之前应了解本领域的普通技术人员可修改本文中所描述的公开，同时获得本公开的技术效果。因 此，须了解以上的描述对本领域的普通技术人员而言为一广泛的揭示，且其内容不在于限制本公开所描述的示例性实施例。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
显示面板中，通常栅极驱动电路连接在栅极线的一端，本文称作近端，以向其施加扫描信号。栅极线的与近端相对端，本文称作远端。在实践中，栅极线远端的信号受各种因素的影响，例如栅极线的长度和电学特性(例如电阻、电容等)、屏幕的尺寸等等，这导致栅极线远端的信号与栅极线近端的信号存在一定差异。特别是对于栅极线较长的横屏(即横向尺寸大于纵向尺寸的显示面板)，栅极线的近端的信号时延与远端的信号时延之间存在较大的差异。
图1示出了根据本公开实施例的一种显示面板的示意图。
如图1所示，显示面板包括多个子像素P，所述多个子像素P布置成多行，例如可以布置成N×M阵列，其中N和M均为大于1的整数。
显示面板还可以包括栅极驱动电路10，栅极驱动电路10与所述多个子像素P连接。栅极驱动电路10可以通过沿第一方向(图1中为x方向)延伸的多条栅极线G1，G2，...GN分别与N行子像素连接，例如通过栅极线G1连接第一行子像素P，以向所述第一行子像素P提供扫描信号，在通过栅极线G2连接第二行子像素P以向第二行子像素P提供扫描信号，以此类推。第一行子像素P响应于栅极线G1的扫描信号而开启，第二行子像素P响应于栅极线G2上的扫描信号而开启，以此类推。
在一些实施例中，栅极驱动电路10可以逐一行或多行扫描N行子像素P。例如，如图2所示，栅极驱动电路10可以分别向栅极线G1，G2，...GN施加N个顺次移位的扫描信号，以依次开启第一行子像素P、第二行子像素P……第N行子像素P。在一些实施例中，栅极驱动电路10可以从最后一行向第一行依次扫描各行子像素，例如按照GN，G(N-1)，...G1的顺序向N条栅极线施加扫描信号。栅极驱动电路10也可以每次扫描两行或更多行子像素P。例如，栅极驱动电路10可以同时向栅极线G1和G2施加扫描信号，以将第一行子像素P和第二行子像素P同时开启，接下来栅极驱动电路10可以同时向栅极线G3和G4施加扫描信号，以将第三行子像素P和第四行子像素P同时开启，以此类推。在一些实施例中，栅极驱动电路10可以每间隔至少一行来扫描所述N行子像素P，以依次开启部分行的子像素P。例如栅极驱动电路10可以依次扫描奇数行子像 素P(例如依次开启第一行子像素P、第三行子像素P、第五行子像素P，以此类推)，或者依次扫描偶数行子像素P(例如依次开启第二行子像素P、第四行子像素P、第六行子像素P，以此类推)。
显示面板还可以包括源极驱动电路20，源极驱动电路20与所述多个子像素P连接。例如源极驱动电路20可以通过沿第二方向(图1中为y方向)延伸的多条数据线分别与M列子像素P连接。例如源极驱动电路20可以通过第一数据线与第一列子像素P连接以向第一列子像素P提供第一数据信号D1，通过第二数据线与第二列子像素P向第二列子像素P提供第二数据信号D2，以此类推。
例如，当第一行子像素P开启时，源极驱动电路20可以通过M条数据线分别向第一行的M个子像素P提供针对第一行子像素的M个数据信号D11，D12，...，D1M；当第二行子像素P开启时，源极驱动电路20可以通过多条数据线分别向第二行的M个子像素P分别提供针对第二行的M个数据信号D21，D22，...，D2M，以此类推。当然本公开的实施例不限于此，下文将对此进一步详细说明。
在一些实施例中，显示面板还可以包括时序控制器30，时序控制器30与栅极驱动电路10和源极驱动电路20连接，可以向栅极驱动电路10和源极驱动电路20提供相关的控制信号。例如，时序控制器30可以向源极驱动电路20提供数据控制信号TP，源极驱动电路20可以在数据控制信号TP的控制下输出针对各行的数据信号。时序控制器30还可以向源极驱动电路20提供其他控制信号，包括但不限于行数据起始信号、数据同步信号、数据反转信号等等。时序控制器30还可以向栅极驱动电路10提供各种控制信号，包括但不限于栅极驱动电路10所需的启动信号、时钟信号等等。
图3示出了根据本公开实施例的显示面板的示意图。
如图3所示，显示面板100包括衬底基板101，衬底基板101包括显示区AA和围绕显示区的周边区。多个子像素P位于显示区AA中，且沿第一方向(图3中是x方向)布置成多行。
多条栅极线G1，G2，...，GN位于显示区AA中，沿第一方向延伸且沿与第一方向交叉的第二方向(图3中为y方向)排列。每条栅极线G1，G2，...，GN与至少一行子像素P连接。例如在图3中多条栅极线与多行子像素一一对应地连接，即栅极线G1连接第一行子像素P，栅极线G2连接第二行子像素P。然而本公开的实施例不限于此，在一些实施例中一条栅极线可以连接多行子像素，或者多条栅极线连接一行子像素，本公开对此不作限制。
多个移位寄存器GOA1，GOA2，...，GOAN位于所述周边区，分别与多条栅极线G1，G2，...，GN连接以向这些栅极线提供扫描信号，例如可以提供如图2所示的扫描信号。当然本公开的实施例不限于此，扫描信号的时序可以根据需要来设置，本公开对此不作限制。在图3中，多个移位寄存器与多条栅极线一一对应地连接，即，移位寄存器GOA1连接栅极线G1，移位寄存器GOA2连接栅极线G2，以此类推。然而本公开的实施例不限于此，在一些实施例中，一个移位寄存器可以连接多条栅极线，或者一条栅极线可以连接多个移位寄存器，本公开对此不作限制。
多个辅助电路A1，A2，...，AN位于周边区。至少一条栅极线的一端连接至少一个移位寄存器以接收所述至少一个移位寄存器提供的扫描信号，另一端连接至少一个辅助电路。在图3中，每条栅极线两端分别连接一个移位寄存器和一个辅助电路，例如栅极线G1的一端(图3中为左端)连接移位寄存器GOA1，另一端(图3中为右侧端部)连接辅助电路A1；栅极线G1的一端连接移位寄存器GOA2，另一端连接辅助电路A2，以此类推。然而本公开的实施例不限于此，栅极线两端连接的移位寄存器和辅助电路的数量可以根据需要来设置，这里不再赘述。
如图3所示，各个辅助电路A1，A2，...，AN的控制端可以连接为接收相应的辅助信号(如箭头线所示)。辅助信号可以是单独提供的辅助信号，也可以将下级移位寄存器提供的扫描信号作为辅助信号。在图3中，第i条栅极线连接的辅助电路的控制端连接为接收与第i+k条栅极线连接的移位寄存器提供的扫描信号作为辅助信号，其中i和k为大于或等于1的整数。例如在k＝1的情况下，与第一栅极线G1连接的辅助电路A1的控制端可以接收由与第二栅极线G2连接的移位寄存器GOA2提供的扫描信号作为辅助信号，辅助电路A2的控制端可以接收由移位寄存器GOA3提供的扫描信号作为辅助信号，以此类推。虽然在图3中将辅助电路的控制端示为连接至下一行的栅极线，然而这仅仅表示二者电学连接，而不必须为物理连接，辅助电路的控制端可以通过各种方式接收由其他移位寄存器提供的辅助信号，下文将对此进行详细说明。
各个辅助电路A1，A2，...，AN的输入端连接为接收参考信号，例如连接至提供参考信号的参考信号端VGL。各辅助电路A1，A2，...，AN的输出端连接至对应栅极线的另一端(在图3中为右端)。辅助电路A1，A2，...，AN可以在各自的控制端处辅助信号的控制下将各自输入端处的参考信号提供至各自输出端。例如辅助电路A1可以接收移位寄存器GOA2提供的扫描信号作为辅助信号，并在其控制下将参考信号端VGL处的参考信号提供至扫描线G1，相应地辅助电路A2可以接收移位寄存器GOA3提供的扫 描信号作为辅助信号，并在其控制下将参考信号端VGL处的参考信号提供至扫描线G2，以此类推。
虽然上述实施例以k＝1为例进行了说明，然而本公开的实施例不限于此，k的值是可以根据需要来设置的，例如k可以为2或其他数值。
虽然在图3中将沿着y方向位于顶部的一行子像素作为第一行子像素，位于底部的一行子像素作为最后一行子像素，然而这仅仅是为了示意说明。在本公开的实施例中，所谓第一行和最后一行是按照扫描的先后顺序来定义的，例如最先扫描的一行定义为第一行，最后扫描的一行定义为最后一行。在一些实施例中，可以从下向上扫描各行像素，在这种情况下可以将底部的一行作为第一行，将顶部的一行作为最后一行。
虽然图3中将移位寄存器均示为位于显示区的一侧(左侧)，然而这仅仅是为了便于说明，移位寄存器可以根据需要分布在周边区的其他位置，例如可以分布在显示区的两侧，下文将对此进一步详细说明。
在一些实施例中，显示面板还可以包括源极驱动器、时序控制器等其他部件，例如具有以上参考图1描述的源极驱动器和时序控制器等等，这里不在赘述。
在本公开的实施例中，可以将栅极线的与移位寄存器相连的一端称作栅极线的近端，将栅极线的与近端相对的一端称为远端。本公开的实施例通过在栅极线的远端设置辅助电路，可以在栅极线近端的移位寄存器完成扫描信号的输出之后，例如在扫描信号开始从高电平向低电平下降之后，下拉栅极线远端的电位，从而减小栅极线远端信号的下降时间。这里所谓下降时间指的是信号从高电平下降至期望的低电平所花费的时间。由于辅助电路的存在减小了栅极线远端的信号下降时间，能够降低栅极线远端与近端的信号下降时间的差异，从而提高显示质量。
图4示出了根据本公开另一实施例的显示面板的示意图。
如图4所示，显示面板200包括位于衬底基板上的多个子像素P、多条栅极线G1，G2，...，GN、多个移位寄存器GOA1，GOA2，...，GOAN和多个辅助电路A1，A2，...，AN，以上对于显示面板各个部件的描述同样适用于本实施例。在图4的示例中，以N＝1200为例进行了说明，然而本公开的实施例不限于此，N的值可以根据需要来进行设置。
如图4所示，移位寄存器GOA1，GOA2，...，GOA1200分布在显示区AA的相对两侧，为了便于描述，这里将沿第一方向位于显示区AA第一侧(图4中为左侧)的移位寄存器GOA1、GOA3、GOA5……GOA1199称作第一移位寄存器，将位于沿第一方向位于显示区AA的第二侧(图4中为右侧)的移位寄存器GOA2、GOA4、GOA6…… GOA1200称作第二移位寄存器。第一移位寄存器GOA1、GOA3、GOA5……GOA1199级联连接，第二移位寄存器GOA2、GOA4、GOA6……GOA1200级联连接。这里所谓级联连接指的是当前移位寄存器的输出端作为后级移位寄存器的输入端，例如第i级移位寄存器的输出端可以连接至第i+d级移位寄存器的输入端，i和d为正整数。以左侧的移位寄存器为例，移位寄存器GOA1的输出端连接移位寄存器GOA3的输入端，移位寄存器GOA3的输出端连接移位寄存器GOA5的输入端，以此类推。每个移位寄存器响应于各自输入端处的输入信号在其输出端产生相对于输入信号而移位的输出信号，通过这种级联连接，使得后级移位寄存器的输出信号相对于前级移位寄存器的输出信号而移位，从而实现移位寄存。类似地，右侧的移位寄存器也可以采用级联的方式连接。虽然上文以逐级级联为例进行了说明，即当前级移位寄存器的输出端连接至其下一级移位寄存器的输出端，然而本公开的实施例不限于此，d的值可以根据需要任意设置。
继续参考图4，辅助电路A1，A2，...，GOA1200也分布在显示区AA的相对两侧，为了便于描述，这里将将位于显示区AA第二侧(右侧)的辅助电路A1、A3、A5……A1199称作第一辅助电路，位于显示区AA第一侧(左侧)的辅助电路A2、A4、A6……A1200称作第二辅助电路。
多条栅极线G1，G2，...，G1200可以包括交替设置的多条第一栅极线G1、G3、G5……G1199和多条第二栅极线G2、G4、G6……G1200。在本实施例中，第一栅极线G1、G3、G5……G1199各自的第一端位于显示区的第一侧且连接相应的第一移位寄存器GOA1、GOA3、GOA5……GOA1199，第二端位于显示区AA的第二侧且连接相应的第一辅助电路A1、A3、A5……A1199。例如，第一栅极线G1的第一端(左端)连接第一移位寄存器GOA1，第二端(右端)连接第一辅助电路A1；第一栅极线G3的第一端(左端)连接第一移位寄存器GOA3，第二端(右端)连接第一辅助电路A3，以此类推。多条第二栅极线G2、G4、G6……G1200各自的第一端位于显示区AA的第二侧且连接相应的第二移位寄存器GOA2、GOA4、GOA6……GOA1200，第二端位于显示区AA的第一侧且连接相应的第二辅助电路A2、A4、A6……A1200。例如，第二栅极线G2的第二端(左端)连接第二辅助电路A2，第一端(右端)连接第二移位寄存器GOA2；第二栅极线G4的第二端(左端)连接第二辅助电路A4，第一端(右端)连接第二移位寄存器GOA4，以此类推。
在图4的示例中，第一栅极线G1、G3、G5……G1199是连接奇数行子像素的栅 极线，第二栅极线G2、G4、G6……G1200是连接偶数行子像素的栅极线。然而本公开的实施例不限于此，第一栅极线和第二栅极线可以按照其他方式交替设置，例如相邻两条第一栅极线之间设置两条或更多条第二栅极线，或者相邻两条第二栅极线之间设置两条或更多条第一栅极线，等等。
在图4的示例中，k＝1，与每条第一栅极线连接的第一辅助电路的控制端连接至与该第一栅极线相邻的第二栅极线所连接的第二移位寄存器的输出信号端，例如与第一栅极线G1连接的第一辅助电路A1的控制端与第一栅极线G2所连接的第二移位寄存器GOA2的输出信号端相连接，第一辅助电路A3的控制端连接至第二移位寄存器GOA4的输出信号端，以此类推。类似地，与每条第二栅极线连接的第二辅助电路的控制端连接至与该第二栅极线相邻的第一栅极线所连接的第一移位寄存器的输出信号端，例如第二辅助电路A2的控制端连接第一移位寄存器GOA3的输出信号端，第二辅助电路A4的控制端连接第一移位寄存器GOA5的输出信号端，以此类推。然而本公开的实施例不限于此，k的值可以根据需要来设置，例如k＝2的情况下，辅助电路A1的控制端可以连接至移位寄存器GOA4的输出信号端，这里不再赘述。
在工作过程中，多个移位寄存器GOA1，GOA2，...，GOA1200可以向多条栅极线G1，G2，...，G1200顺序地施加扫描信号。例如左侧的移位寄存器GOA1首先产生第一扫描信号并提供至栅极线G1施加扫描信号，然后右侧的移位寄存器GOA2产生第二扫描信号并提供至栅极线G2施加扫描信号，以此类推，从而实现双侧交错驱动。在这过程中，在移位寄存器GOA1向栅极线G1输出第一扫描信号之后，移位寄存器GOA2产生的第二扫描信号使得与其连接的辅助电路A1导通，从而将参考信号端VGL的参考信号提供至栅极线G1，进而缩短栅极线G1右端的信号下降时间。类似地，移位寄存器GOA2产生第二扫描信号之后，移位寄存器GOA3产生的第三扫描信号使辅助电路A2将参考信号提供至栅极线G2左端，进而缩短栅极线G2左端的信号下降时间，以此类推。通过这种方式，使得每条栅极线两端的信号下降时间的差异减小，有利于提高显示质量。
图5示出了根据本公开另一实施例的显示面板的示意图。图5的显示面板500与上述显示面板400类似，区别至少在于辅助电路和移位寄存器的排布和连接方式。为了简要，下文将主要对区别部分进行详细说明。
如图5所示，显示面板300同样包括多条栅极线G1，G2，...，G1200，在本实施例中也称作第一栅极线。与上述实施例不同的是，栅极线两侧均连接有移位寄存器和辅助电 路。例如，显示面板300包括位于显示区AA第一侧(左侧)的多个第一移位寄存器GOA1_L，GOA2_L，...，GOA1200_L，以及位于显示区AA第二侧(右侧)的多个第三移位寄存器GOA1_R，GOA2_R，...，GOA1200_R。显示面板300还包括显示区AA第二侧(右侧)的多个第一辅助电路A1_R，A2_R，...，A1200_R，以及位于显示区AA第一侧(左侧)的多个第三辅助电路A1_L，A2_L，...，A1200_L。
栅极线G1的第一端(左端)连接第一移位寄存器GOA1_L，第二端(右端)连接第三移位寄存器GOA1_R。类似地，栅极线G2的第一端连接第一移位寄存器GOA2_L，第二端连接第三移位寄存器GOA2_R，以此类推。相应地，栅极线G1的第一端(左端)还连接第三辅助电路A1_L，第二端(右端)还连接第一辅助电路A1_R；栅极线G2的第一端(左端)还连接第三辅助电路A2_L，第二端(右端)还连接第一辅助电路A2_R。
在本实施例中，第i个第一辅助电路的控制端连接第i+k级第三移位寄存器的输出信号端，第i个第一辅助电路的输出端连接第i条第一栅极线的第二端；第i个第三辅助电路的控制端连接第i+k级第一移位寄存器的输出信号端，第i个第三辅助电路的输出端连接第i条第一栅极线的第一端。如图5所示，在k＝1的情况下，在显示区AA的第一侧，第三辅助电路A1_L的控制端连接第一移位寄存器GOA2_L的输出信号端，第三辅助电路A2_L的控制端连接第一移位寄存器GOA3_L的输出信号端，以此类推。在显示区AA的第二侧，第一辅助电路A1_R的控制端连接第三移位寄存器GOA2_R的输出信号端，第一辅助电路A2_L的控制端连接第三移位寄存器GOA3_L的输出信号端，以此类推。
在工作时，移位寄存器GOA1_L和GOA1_R同时向栅极线G1施加扫描信号，然后移位寄存器GOA2_L和GOA2_R同时向栅极线G2施加扫描信号，以此类推，从而顺序地向多条栅极线G1，G2，...，G1200施加扫描信号。通过这种方式，实现了双侧同时驱动。在扫描过程中，当左侧的第一移位寄存器GOA1_L向栅极线G1施加扫描信号之后，右侧的第三移位寄存器GOA2_R产生的扫描信号使得与之连接的第一辅助电路A1_R导通，从而将参考信号提供至栅极线G1的右端。通过这种方式，缩短了栅极线G1右端的信号下降时间，使之更接近栅极线G1左端的信号下降时间。类似地，当右侧的第三移位寄存器GOA1_R向栅极线G1施加扫描信号之后，左侧的第一移位寄存器GOA2_L产生的扫描信号使得与之连接的第三辅助电路A1_L导通，从而将参考信号提供至栅极线G1的左端。通过这种方式，缩短了栅极线G1左端的信号下降时间， 使之更接近栅极线G1右端的信号下降时间。其他移位寄存器和辅助电路以类似的方式工作，这里不再赘述。
图6示出了根据本公开另一实施例的显示面板的示意图。图6的显示面板400与上述显示面板400类似，区别至少在于辅助电路和移位寄存器的排布和连接方式。为了简要，下文将主要对区别部分进行详细说明。
如图6所示，显示面板400同样包括多条栅极线G1，G2，...，G1200，在本实施例中也称作第一栅极线。与上述实施例不同的是，多个移位寄存器均设置在显示区AA的一侧，多个辅助电路设置在显示区AA的另一侧。如图6所示，多个移位寄存器包括沿第一方向位于显示区AA第一侧(左侧)且级联连接的多个第一移位寄存器GOA1，GOA2，...，GOA1200。多个辅助电路包括沿第一方向位于显示区AA与第一侧相对的第二侧(右侧)的多个第一辅助电路A1，A2，...，A1200。
栅极线G1的第一端位于显示区AA的第一侧且连接第一移位寄存器GOA1，栅极线G1的第二端位于显示区AA的第二侧且连接第一辅助电路A1；栅极线G2的第一端位于显示区AA的第一侧且连接第一移位寄存器GOA2，栅极线G2的第二端位于显示区AA的第二侧且连接第一辅助电路A2，以此类推。
在本实施例中，第i个第一辅助电路的控制端连接第i+k条第一栅极线的第二端，第i个第一辅助电路的输出端连接第i条第一栅极线的第二端。如图6所示，在k＝1的情况下，第一辅助电路A1(即，第一个第一辅助电路)的控制端连接栅极线G2(即，第二条第一栅极线)的第二端，第一辅助电路A1的输出端连接栅极线G1(即，第一条第一栅极线)的第二端；第一辅助电路A2(即，第二个第一辅助电路)的控制端连接栅极线G3(即，第三条第一栅极线)的第二端，第一辅助电路A2的输出端连接栅极线G2的第二端，以此类推。
在工作时，移位寄存器GOA1向栅极线G1施加扫描信号，然后移位寄存器GOA2向栅极线G2施加扫描信号，以此类推，从而顺序地向多条栅极线G1，G2，...，G1200施加扫描信号。通过这种方式，实现了单侧驱动。在扫描过程中，当第一移位寄存器GOA1向栅极线G1的左端施加扫描信号之后，由第一移位寄存器GOA2提供到栅极线G2上的扫描信号经由栅极线G2的右端被提供至第一辅助电路A1，使得第一辅助电路A1导通，从而将参考信号提供至栅极线G1的右端。通过这种方式，缩短了栅极线G1右端的信号下降时间，使之更接近栅极线G1左端的信号下降时间。其他移位寄存器和辅助电路以类似的方式工作，这里不再赘述。
以上结合各个实施例描述了显示面板的结构和布局。根据本公开的实施例，显示面板的尺寸可以根据需要任意选择，例如但不限于在8英寸至15英寸范围内。显示面板的分辨率可以根据需要来设置，例如但不限于2160×1440。在一些实施例中，栅极线的材料可以为金属，包括但不限于铝或铜。栅极线的长度可以根据显示面板的尺寸来设置，例如可以在200mm-300mm的范围内，例如可以为大约265mm，在一些实施例中可以为265.68mm。栅极线的电阻可以大约在4.5kΩ至5.5kΩ的范围内，例如可以为5kΩ，在一些实施例中可以为4.95kΩ。栅极线的电容可以在250pf至350pf的范围内，例如可以大约为300pf，在一些实施例中可以为284.3pf。
下面将参考图7和图8来说明本公开实施例的显示面板中的移位寄存器的结构和工作原理。
图7示出了根据本公开实施例的显示面板中的移位寄存器的电路图。该移位寄存器的结构适用于上述任意实施例的显示面板。为了便于描述，图7中以第一条栅极线G1为例进行了说明。如图7所示，栅极线G1的一端连接移位寄存器GOA1，另一端连接辅助电路A1。栅极线G1的与移位寄存器GOA1连接的一端也称作近端(由NE表示)，与近端相对的一端也称作远端(由FE表示)。虽然在图7中移位寄存器GOA1和辅助电路A1被示为分别位于栅极线G1的左端和右端，然而这仅仅是为了示意，二者的位置可以互换。
如图7所示，辅助电路A1包括晶体管M1(第一晶体管)。晶体管M1的栅极作为辅助电路A1的控制端连接为接收辅助信号CTR。根据上述不同的实施例，辅助信号CTR可以来自于其他移位寄存器的输出信号端，或者来自于其他栅极线。晶体管M1的第一极作为辅助电路A1的输入端连接至用于提供所述参考信号的参考信号端VGL1。晶体管M1的第二极作为辅助电路A的输出端连接至栅极线G1的另一端FE。
如图7所示，移位寄存器GOA1可以包括输入电路510、输出电路520、控制电路530和下拉电路。在图7的示例中，下拉电路可以包括第一下拉电路5401和第二下拉电路5402，统称下拉电路540。
输入电路510连接移位寄存器GOA1的输入信号端INPUT和移位寄存器GOA1的上拉节点PU。输入电路510可以将输入信号端INPUT的信号提供至上拉节点PU。
输出电路520连接上拉节点PU、移位寄存器GOA1的时钟信号端CLK以及移位寄存器GOA1的输出信号端OUTPUT。输出电路520可以在上拉节点PU的控制下将时钟信号端CLK的信号提供至输出信号端OUTPUT，以输出扫描信号。
控制电路530连接上拉节点PU和移位寄存器GOA1的下拉节点。在本实施例中下拉节点有两个，分别为PD1和PD2，统称下拉节点PD。然而本公开的实施例不限于此，在一些实施例中移位寄存器可以包括上述两个下拉节点之一。控制电路530用于根据上拉节点PU的电位来控制下拉节点PD的电位。
下拉电路540连接输出信号端OUTPUT和下拉节点PD。下拉电路540可以在下拉节点PD的控制下，下拉输出信号端OUTPUT的电位。例如，第一下拉电路5401连接下拉节点PD1和PD2，并且可以在下拉节点PD1和PD2的控制下，下拉输出信号端OUTPUT的电位。第二下拉电路5402连接下拉节点PD1和PD2，并且在下拉节点PD1和PD2的控制下，对上拉节点PU的电位进行下拉。
在一些实施例中，移位寄存器GOA1还可以包括复位电路550。复位电路550连接至上拉节点PU和移位寄存器GOA1的复位信号端。在一些实施例中，复位信号端可以包括第一复位信号端RESET，其用于接收给本级移位寄存器复位的复位信号。在另一些实施例中，复位信号端还可以包括第二复位信号端TRST，其用于接收给包括本级移位寄存器在内的多级移位寄存器复位的总复位信号。复位电路550可以在复位信号端RESET的控制下将上拉节点PU复位。复位电路550也可以在复位信号端TRST的控制下将上拉节点PU复位。
在一些实施例中，移位寄存器GOA1还可以包括降噪电路560。降噪电路560连接输入信号端INPUT和下拉节点PD1和PD2，可以在输入信号端INPUT的控制下对下拉节点PD1和PD2进行降噪。
在一些实施例中，如图7所示，输出电路520可以包括晶体管M2和电容C。晶体管M2的栅极连接上拉节点PU，晶体管M2的第一极连接时钟信号端CLK，晶体管的第二极连接输出信号端OUTPUT。电容C的第一极连接上拉节点PU，电容C的第二极连接输出信号端OUTPUT。
输入电路510可以包括晶体管M3，晶体管M3的栅极和第一极连接至输入信号端INPUT，晶体管M3的第二极连接上拉节点PU。
控制电路530可以包括第一控制电路和第二控制电路中的至少之一。例如在图7中，第一控制电路包括晶体管M4、M5、M6和M7。晶体管M4的栅极和第一极连接至电源信号端VDDO，晶体管M4的第二极与晶体管M5的栅极相连接。晶体管M5的第一极连接电源信号端VDDO，晶体管M5的第二极连接至下拉节点PD1。晶体管M6和M7的栅极均连接上拉节点PU，晶体管M6和M7的第一极均连接至参考信号 端VGL2。晶体管M6的第二极连接晶体管M5的栅极，晶体管M7的第二极连接下拉节点PD1。类似地，第二控制电路包括晶体管M8、M9、M10和M11。晶体管M8的栅极和第一极连接至电源信号端VDDE，晶体管M8的第二极与晶体管M9的栅极相连接。晶体管M9的第一极连接电源信号端VDDE，晶体管M9的第二极连接至下拉节点PD2。晶体管M10和M11的栅极均连接上拉节点PU，晶体管M10和M11的第一极均连接至参考信号端VGL2。晶体管M10的第二极连接晶体管M9的栅极，晶体管M11的第二极连接下拉节点PD2。根据本公开的实施例，电源信号端VDDO和VDDE可以交替地为高电平，例如在电源信号端VDDO接收高电平电源信号期间，电源信号端VDDE接收低电平电源信号，反之亦然。通过这种方式，可以使第一控制电路和第二控制电路交替工作，以避免控制电路530中的晶体管长时间导通造成器件损耗。
第一下拉电路5401可以包括晶体管M12和M13中的至少之一。第二下拉电路5402可以包括晶体管M14和M15中的至少之一。如图7所示，晶体管M12的栅极连接下拉节点PD1，晶体管M13的栅极连接下拉节点PD2。晶体管M12和M13的第一极均连接参考信号端VGL2，晶体管M12和13的第一极均连接输出信号端OUTPUT。类似地，晶体管M14的栅极连接下拉节点PD1，晶体管M15的栅极连接下拉节点PD2。晶体管M14和M15的第一极均连接参考信号端VGL2，晶体管M14和15的第一极均连接上拉节点PU。
复位电路550可以包括晶体管M16。在一些实施例中，复位电路550还可以包括晶体管M17和M18。如图7所示，晶体管M16的栅极连接复位信号端RESET，第一极连接参考信号端VGL2，第二极连接上拉节点PU。晶体管M17和M18的栅极均连接复位信号端TRST，晶体管M17和M18的第一极均连接参考信号端VGL2。晶体管M17的第二极连接上拉节点PU，晶体管M8的第二极连接输出信号端OUTPUT。
降噪电路560可以包括晶体管M19和M20中的至少一个。如图7所示，晶体管M19和M20的栅极均连接至输入信号端INPUT。晶体管M19和M20的第一极均连接至参考信号端VGL2。晶体管M19的第二极连接下拉节点PD1，晶体管M20的第二极连接下拉节点PD2。
上述晶体管M1至M20中的至少一个是薄膜晶体管，例如晶体管M1和M2中的至少之一可以为薄膜晶体管。在一些实施例中，上述晶体管M1至M20可以均为薄膜晶体管。各个薄膜晶体管的沟道宽度可以根据需要来设置，例如根据显示面板的尺寸、栅极线的材料、长度和电学特性等等来设置。在一些实施例中，显示面板中给晶体管 M1和M2预留的空间有限的情况下，可以在该预留空间的尺寸范围内综合考虑栅极线的长度和材料来设计晶体管M1和M2的尺寸，以优化对栅极线上的信号下降时间的缩减效果。例如，晶体管M1可以在1800μm至2200μm的范围内，例如可以大约为2000μm。晶体管M2的沟道宽度可以在5800μm至6200μm的范围内，例如可以为大约6000μm。各个晶体管的沟道长度可以设置在3um至6um的范围内，例如可以为4.0um。
虽然上述实施例中以两个参考信号端VGL1和VGL2为例来进行了说明，然而本公开的实施例不限于此，参考信号端VGL1和VGL2可以实现为同一个参考信号端。
图8示出了图7的移位寄存器的信号时序图。
考虑到电源信号端VDDO和VDDE交替工作，本实施例中以某一时段内电源信号端VDDO为高电平且电源信号端VDDE为低电平为例来进行说明。因此在图8所示的扫描时段，受控于电源信号端VDDO的第一控制电路处于工作状态，受控于电源信号端VDDE的第二控制电路处于非工作状态。结合图7和图8，移位寄存器GOA1的时钟信号端CLK可以接收时钟信号CLK1，其下一级移位寄存器(例如GOA2)的时钟信号端可以接收时钟信号CLK2，以便输出相对于移位寄存器GOA1的输出信号而移位的输出信号。在一些实施例中，可以使连接奇数栅极线的移位寄存器接收时钟信号CLK1，连接偶数栅极线的移位寄存器接收时钟信号CLK2接收时钟信号CLK2。当然本公开的实施例不限于此，可以根据需要设置更多个(例如4个、8个、12个或16个)时钟信号并按照适配于移位寄存器级联结构的方式提供给各个移位寄存器。
在时段t1，输入信号端INPUT接收到高电平的输入信号，使得晶体管M3导通，从而上拉节点PU点变为高电平。上拉节点PU的高电平给电容C充电，并且使晶体管M2导通。此时由于时钟信号端CLK接收的第一时钟信号CLK1尚且为低电平，因此虽然晶体管M2导通，但是输出信号端OUTPUT保持低电平。上拉节点PU的高电平还使晶体管M6和M7导通，从而将参考信号端VGL2的低电平提供至下拉节点PD1。另外，输入信号端INPUT的高电平还将晶体管M19和M20导通，从而将下拉节点PD1和PD2稳定在低电平，进而降噪电路560对下拉节点PD1和PD2起到降噪的作用。
在时段t2，时钟信号端CLK接收到的时钟信号CLK1由低电平变为高电平，此时由于晶体管M2处于导通状态，因此时钟信号CLK1的高电平被提供至输出信号端OUTPUT，从而输出高电平的扫描信号。在这过程中，由于电容C自举，上拉节点PU的电位在原来的基础上再次增加。
在时段t3，复位信号端RESET接收到高电平的复位信号，例如在复位信号端RESET 连接下一级移位寄存器的输出信号端的情况下，该下一级移位寄存器输出的扫描信号即被作为复位信号。复位信号端RESET的高电平使晶体管M16导通，从而将上拉节点PU的电位下拉至低电平。上拉节点PU的低电平使控制电路530中的晶体管M6和M7关断，晶体管M5导通，从而将电源信号端VDDO的高电平提供至下拉节点PD1。下拉节点PD1的高电平使晶体管M12导通，从而将输出信号端OUTPUT下拉至参考信号端VGL2的低电平。在这过程中，辅助电路A1接收到的辅助信号CTR为高电平，例如在接收下一级移位寄存器输出的扫描信号作为辅助信号的情况下，辅助信号即为高电平。辅助信号CTR的高电平使晶体管M1导通，从而将参考信号端VGL1的低电平提供至输出信号端OUTPUT。通过这种方式，加快了输出信号端OUTPUT的信号下降，进而减小栅极线G1两端信号下降时间的差异。另外在该时段，下拉节点PD1的高电平还使晶体管M14导通，从而进一步下拉上拉节点PU的电位。
至此实现了一次扫描，即完成了向一条栅极线G1施加扫描信号，因此这段包含t1、t2和t3的时间段也称作扫描时段。可以将时段t1和t2称作扫描时段的第一时段，将时段t3称作扫描时段的第二时段。在第一时段完成扫描信号的输出，在第二时段完成扫描信号的复位和加速下降。针对各个栅极线重复上述操作，即可完成全部栅极线的扫描。各个栅极线的扫描时段可以存在重叠，例如前一个扫描时段的时段t2和t3可以与后一个扫描时段的t1和t2存在重叠。
上述实施例虽然以特定的移位寄存器电路结构为例进行了说明，然而本公开的实施例不限于此。本公开实施例的显示面板可以采用任何合适的移位寄存器电路结构，例如但不限于9T1C、11T1C、19T1C等移位寄存器结构。
图9示出了根据本公开实施例的显示面板的平面示意图。图9的平面布局可以适用于例如上述图4的电路结构，因此下文将结合图4对图9的布局进行说明。在图9中为了便于示意，省略了栅极线与辅助电路和移位寄存器之间的连接走线。
如图9所示，与栅极线G1连接的第一辅助电路A1和与栅极线G2连接的第二移位寄存器GOA2位于显示区AA的第二侧(右侧)。第一辅助电路A1位于显示区AA与第二移位寄存器GOA2之间。在图9中，第一辅助电路A1中的晶体管M1位于第二移位寄存器GOA2中的晶体管M2与显示区AA之间，使得显示区AA内的栅极线G1和G2的第二端位于辅助电路A1中的晶体管M1背离第一移位寄存器GOA1中晶体管M2的一侧。类似地，与栅极线G1连接的第一移位寄存器GOA1和与栅极线G2连接的第二辅助电路A2位于显示区AA的第一侧(左侧)，其中第二辅助电路A2位于显示区AA 与第一移位寄存器GOA1之间。与栅极线G3和G4连接的第一辅助电路A3、第二辅助电路A4、第一移位寄存器GOA3和第二移位寄存器GOA4以类似的方式布局，以此类推。
如图9所示，第一辅助电路A1、A3、A5……和第二辅助电路A2、A4、A6……各自在第二方向上的尺寸基本上等于两行子像素P在第二方向(在图9中为纵向方向，即y方向)上的尺寸之和。这里辅助电路的尺寸可以由辅助电路内的晶体管在衬底基板上的投影尺寸来表征。例如各个晶体管M1和M2在衬底基板上的投影在纵向方向上的尺寸基本等于相邻两行子像素在衬底基板上的投影在纵向方向上的尺寸。
图10示出了根据本公开另一实施例的显示面板的平面示意图。图10的平面布局可以适用于例如上述图5的电路结构，因此下文将结合图5对图10的布局进行说明。
如图10所示，第一辅助电路A1_R位于显示区AA与第三移位寄存器GOA1_R之间，第三辅助电路A1_L位于显示区AA与第一移位寄存器GOA1_L之间。具体地，第一辅助电路A1_R中的晶体管M1位于栅极线G1的第二端(右端)与第三移位寄存器GOA1_R的晶体管M2之间，第三辅助电路A1_L中的晶体管M1位于栅极线G1的第一端(左端)与第一移位寄存器GOA1_L的晶体管M2之间。
由于图5相比于图4具有更多数量的移位寄存器和辅助电路，因此它们的尺寸和位置也相应有所调整。如图10所示，包括第一辅助电路和第三辅助电路在内的各个辅助电路(即其中的晶体管M1)各自在第二方向上的尺寸基本上等于一行子像素P在第二方向(纵向)上的尺寸。
图11示出了根据本公开另一实施例的显示面板的平面示意图。图11的平面布局可以适用于例如上述图6的电路结构，因此下文将结合图6对图11的布局进行说明。
如图11所示，第一移位寄存器GOA1、GOA2、GOA3……均设置在显示区AA的第一侧(左侧)，第一辅助电路A1、A2、A3……均设置在显示区AA的第二侧(右侧)。类似于图10，包括第一辅助电路和第三辅助电路在内的各个辅助电路(即其中的晶体管)各自在第二方向上的尺寸基本上等于一行子像素P在第二方向(纵向)上的尺寸。
图12示出了图9的显示面板的局部布局图。
如图12所示，显示区AA内设置沿第一方向延伸的多条栅极线(在图12中仅标注了栅极线G5、G6)，以及沿第二方向延伸的多条数据线(在图12中仅示出了数据线D1和D2)。显示区AA内还设置有布置成阵列的多个子像素，每子像素可以包括一个或多个晶体管TFT。在图12中，每一行子像素连接同一条栅极线，每一列子像素连接一条 数据线，例如第五行子像素连接栅极线G5，第六行子像素连接栅极线G6；第一列子像素连接数据线D1，第二列子像素连接数据线D2，以此类推。在显示区AA中还设置有多个公共电极Ecom以及沿第一方向延伸沿第二方向排列的多条公共电极线Vcom。公共电极Ecom可以具有镂空图案，并且连接至公共电极线Vcom。公共电极线Vcom连接至位于显示区AA外部的周边区内的公共电极总线Vcom_bus。在图12中，移位寄存器GOA5的晶体管M2和辅助电路A6的晶体管M1位于显示区AA外部的周边区内，且各自具有源极S、漏极D和栅极G。
如图12所示，栅极线G5的第一端通过走线W1连接至移位寄存器GOA5的晶体管M2的漏极D。例如，栅极线G5的第一端通过跨接孔H1与走线W1连接，进而连接至移位寄存器GOA5的晶体管M2的漏极D。移位寄存器GOA5中的晶体管M2的栅极G与电容C的第一电极板E1连接，电容C的第一电极板E1可以通过跨接孔Vc连接至GOA5中的相关结构以接收控制信号。在一些实施例中，如图12所示，电容C的第一电极板E1可以与晶体管M2的栅极G同层设置。电容C的第二电极板E2可以与移位寄存器GOA5中的晶体管M2的源极S和漏极D之一电连接。例如，如图12所示，电容C的第二电极板E2可以与移位寄存器GOA5中的晶体管M2的源极S和漏极D同层设置，并与漏极D连接。
栅极线G6的第二端通过走线W2连接至辅助电路A6的晶体管M1的漏极D。例如栅极线G6的第一端通过跨接孔H2连接至走线W2，进而连接至辅助电路A6的晶体管M1的漏极D。走线W1可以包括沿第一方向延伸的第一部分W1_1和沿着第二方向延伸的第二部分W1_2。走线W2同样可以包括沿第一方向延伸的第一部分W2_1和沿着第二方向延伸的第二部分W2_2。走线W1的第一部分W1_1与走线W2的第一部分W2_1基本上平行。走线W1的第二部分W1_2与走线W2的第二部分W2_2基本平行。走线W1的第二部分W1_2位于走线W2的第二部分W2_2与显示区AA之间。
另外，栅极线G6的第二端还通过走线W3连接至辅助电路A2中的晶体管M1的栅极G，其中辅助电路A2的晶体管M1的漏极D与栅极线G2的第一端连接。例如，栅极线G6的第一端通过跨接孔H2连接至走线W2，走线W2通过跨接孔H3连接至走线W3，走线W3连接至辅助电路A2中的晶体管M1的栅极G。通过这种方式，实现了栅极线G6的第一端与辅助电路A2中的晶体管M1的栅极G之间的电连接。可以看出，在图12的示例中，k＝4，也就是说与栅极线G2连接的辅助电路A2受控于栅极线G6上的扫描信号，与栅极线G4连接的辅助电路A4受控于栅极线G8上的扫描信号，以此 类推。在图12中，走线W3可以沿着第二方向延伸，例如沿第二方向跨越一个晶体管M1延伸，且位于该晶体管M1所连接的走线W2的第二部分W22与晶体管M1之间。
在图12中，晶体管M1和M2各自的源极S和漏极D均设置成梳状图案，且每个晶体管的源极S与漏极D的图案彼此啮合。然而本公开的实施例不限于此，晶体管M和M2的源极S和漏极D可以根据需要设置成任何合适的图案。
本公开的实施例通过设置辅助电路，可以将栅极线的远端的输出信号拉低，降低整条栅极线上的信号下降时间，尤其是对远端信号的下降时间的作用更为明显，降低了栅极线近端和远端的信号下降时间的差异，提升整个显示面板的显示均一性。下面将结合图13至图17来说明辅助电路的作用效果。
图13至图17示出了根据本公开实施例的在采用不同尺寸的晶体管的情况下栅极线两端信号的下降时间的比较结果图。
如图13所示，相比于没有设置辅助电路(晶体管M1)的情况，设置了辅助电路(晶体管M1)的情况下栅极线的近端的信号下降时间Near Tf和远端的信号下降时间Far Tf明显更短。例如对于晶体管M2的沟道宽度为4900μm的情况，通过设置沟道宽度为3200μm的晶体管M1，可以使栅极线近端的信号下降时间从4.056μs缩减至3.361μs，使栅极线远端的信号下降时间从4.547μs缩减至3.227μs。
如图14和15所示，晶体管M1的沟道宽度越大，即辅助电路的尺寸越大，栅极线两端的信号下降时间越短。例如，对于晶体管M2的沟道宽度均为4900μm的情况下，晶体管M1的沟道宽度越大，栅极线的近端的信号下降时间Near Tf和远端的信号下降时间Far Tf越短。
在本公开的实施例中，由于显示面板的边框尺寸是有限的，各个晶体管占用空间受到限制。在本公开的实施例中，移位寄存器中的晶体管M2对于栅极线近端的信号下降起主要作用，辅助电路中的晶体管M1对于栅极线远端的信号下降起主要作用，也就是说，相比于晶体管M1，晶体管M2对于近端信号下降时间的作用更大；相比于M2，晶体管M1对栅极线远端信号下降时间作用更大。故，在有限的空间内，例如在为晶体管M1和M2预留的空间大小总和是固定的情况下，为了使栅极线近端、远端信号下降时间总体较小且相近，可以权衡晶体管M1和M2的尺寸，以实现优化的尺寸分配。如图16和17所示，在晶体管M1和M2的沟道宽度之和固定为8000um的情况下，将晶体管M2递次增大，晶体管M1递次减小。通过图16和17可知，对于上述各个实施例中的显示面板，晶体管M1的沟道宽度可以在1000μm至3000μm的范围 内，晶体管M2的沟道宽度可以在5000μm至7000μm的范围内，晶体管M1和M2的沟道长度可以在3μm至6μm的范围内。在一些实施例中，可以设置晶体管M1和M2的沟道宽度的比例，使得栅极线近端和远端的信号下降时间以及二者的差值都趋于最小，例如使差值小于0.1us。例如，晶体管M1的沟道宽度与晶体管M2的沟道宽度的比值可以设置在0.23至0.45之间，例如可以设置为大约0.33。从图16和17可以看出，在晶体管M2的沟道宽度大约为6000um，晶体管M1的沟道宽度大约为2000um时，栅极线近端、远端的信号下降时间总体较小且相差最小。
本公开的实施例还提供了一种显示设备，包括上述任意实施例的显示面板。显示设备的示例包括但不限于各种具有显示功能的电子设备，例如平板电脑、电视、手机等等。
在一些实施例中，还提供了一种上述任意实施例的显示面板的控制方法，包括多个移位寄存器在多个扫描时段分别向多行子像素提供扫描信号，每个扫描时段包括第一时段和第二时段。
在第一时段，多个移位寄存器中的至少一个移位寄存器通过至少一条栅极线向多个子像素中的至少一行子像素提供扫描信号。
在第二时段，多个辅助电路中的至少一个辅助电路在辅助信号的控制下将参考信号提供至所述栅极线。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲突的情况下可以进行自由组合。
在详细说明本公开的较佳实施例之后，熟悉本领域的技术人员可清楚的了解，在不脱离随附权利要求的保护范围与精神下可进行各种变化与改变，且本公开亦不受限于说明书中所举示例性实施例的实施方式。

Claims (19)

  1. 一种显示面板，包括：
    衬底基板，所述衬底基板包括显示区和围绕显示区的周边区；
    多个子像素，位于所述显示区，且沿第一方向布置成多行；
    多条栅极线，位于所述显示区，所述多条栅极线沿第一方向延伸且沿与第一方向交叉的第二方向排列，每条栅极线与至少一行子像素连接；
    多个移位寄存器，位于所述周边区，并配置为提供扫描信号；
    多个辅助电路，位于所述周边区，其中至少一条栅极线的第一端连接至少一个所述移位寄存器并配置为接收所述至少一个移位寄存器提供的扫描信号，所述至少一条栅极线的第二端连接至少一个所述辅助电路，其中所述辅助电路的控制端配置为接收辅助信号，所述辅助电路的输入端配置为接收参考信号，所述辅助电路的输出端连接至所述栅极线的第二端，所述辅助电路配置为在所述辅助信号的控制下将所述辅助电路的输入端处的参考信号提供至所述辅助电路的输出端。
  2. 根据权利要求1所述的显示面板，其中，与所述多条栅极线中的第i条栅极线连接的辅助电路的控制端连接为接收与第i+k条栅极线连接的移位寄存器提供的扫描信号作为辅助信号，其中i和k为大于或等于1的整数。
  3. 根据权利要求1或2所述的显示面板，其中，
    所述多个移位寄存器包括沿所述第一方向位于所述显示区第一侧且级联连接的多个第一移位寄存器；
    所述多个辅助电路包括沿所述第一方向位于所述显示区与所述第一侧相对的第二侧的多个第一辅助电路；
    所述至少一条栅极线包括多条第一栅极线，所述第一栅极线的第一端位于所述显示区的第一侧且连接所述第一移位寄存器，所述第一栅极线的第二端位于所述显示区的第二侧且连接所述第一辅助电路。
  4. 根据权利要求3所述的显示面板，其中，第i个第一辅助电路的控制端连接第i+k条第一栅极线的第二端，第i个第一辅助电路的输出端连接第i条第一栅极线的第二端。
  5. 根据权利要求3所述的显示面板，其中，
    所述多个移位寄存器还包括位于所述显示区第二侧且级联连接的多个第二移位寄存器；
    所述多个辅助电路还包括位于所述显示区第一侧的多个第二辅助电路；
    所述至少一条栅极线还包括与所述多条第一栅极线交替设置的多条第二栅极线，所述第二栅极线的第一端位于所述显示区的第二侧且连接所述第二移位寄存器，所述第二栅极线的第二端位于所述显示区的第一侧且连接所述第二辅助电路。
  6. 根据权利要求5所述的显示面板，其中，所述第一栅极线连接奇数行子像素、所述第二栅极线连接偶数行子像素。
  7. 根据权利要求6所述的显示面板，其中，k＝4，与每条第一栅极线连接的第一辅助电路的控制端连接至与该第一栅极线间隔三条所述栅极线的第二栅极线所连接的第二移位寄存器的输出信号端；与每条第二栅极线连接的第二辅助电路的控制端连接至与该第二栅极线间隔三条所述栅极线的第一栅极线所连接的第一移位寄存器的输出信号端。
  8. 根据权利要求5-7中任一项所述的显示面板，其中，第一辅助电路位于所述显示区与所述第二移位寄存器之间，所述第二辅助电路位于所述显示区与所述第一移位寄存器之间。
  9. 根据权利要求8所述的显示面板，其中，所述第一辅助电路和所述第二辅助电路各自在第二方向上的尺寸等于两行子像素在第二方向上的尺寸之和。
  10. 根据权利要求3所述的显示基板，其中，所述多个移位寄存器还包括位于所述显示区第二侧的多个第三移位寄存器；
    所述多个辅助电路还包括位于所述显示区第一侧的多个第三辅助电路；
    所述第一栅极线的第一端还连接所述第三辅助电路，所述第一栅极线的第二端还连接所述第三移位寄存器。
  11. 根据权利要求10所述的显示面板，其中，所述第一辅助电路位于所述显示区与所述第三移位寄存器之间，所述第三辅助电路位于所述显示区与所述第一移位寄存器之间。
  12. 根据权利要求10或11所述的显示面板，其中，
    第i个第一辅助电路的控制端连接第i+k级第三移位寄存器的输出信号端，第i个第一辅助电路的输出端连接第i条第一栅极线的第二端；
    第i个第三辅助电路的控制端连接第i+k级第一移位寄存器的输出信号端，第i个第三辅助电路的输出端连接第i条第一栅极线的第一端。
  13. 根据权利要求1-12中任一项所述的显示面板，其中，所述辅助电路包括第一 晶体管，所述第一晶体管的栅极作为所述辅助电路的控制端，所述第一晶体管的第一极作为所述辅助电路的输入端，所述第一晶体管的第二极作为所述辅助电路的输出端。
  14. 根据权利要求1-13中任一项所述的显示基板，其中，所述移位寄存器包括：
    输入电路，连接所述移位寄存器的输入信号端和所述移位寄存器的上拉节点，并配置为将所述输入信号端的信号提供至所述上拉节点；
    输出电路，连接所述上拉节点、所述移位寄存器的时钟信号端以及所述移位寄存器的输出信号端，并配置为在所述上拉节点的控制下将所述时钟信号端的信号提供至所述输出信号端，以输出扫描信号；
    控制电路，连接所述移位寄存器的上拉节点和所述移位寄存器的下拉节点，并配置为根据所述上拉节点的电位来控制所述下拉节点的电位；
    下拉电路，连接所述移位寄存器的输出信号端和所述下拉节点，并配置为在所述下拉节点的控制下，下拉所述移位寄存器的输出信号端的电位。
  15. 根据权利要求14所述的显示基板，其中，所述输出电路包括：
    第二晶体管，所述第二晶体管的栅极连接所述上拉节点，所述第二晶体管的第一极连接所述时钟信号端，所述第二晶体管的第二极连接所述移位寄存器的输出信号端；以及
    电容，所述电容的第一极连接所述上拉节点，所述电容的第二极连接所述移位寄存器的输出信号端。
  16. 根据权利要求15所述的显示面板，其中，所述辅助电路包括第一晶体管，所述第一晶体管的栅极作为所述辅助电路的控制端，所述第一晶体管的第一极作为所述辅助电路的输入端，所述第一晶体管的第二极作为所述辅助电路的输出端；
    所述第一晶体管为薄膜晶体管，所述第一晶体管的沟道宽度在1000μm至3000μm的范围内，所述第二晶体管为薄膜晶体管，所述第二晶体管的沟道宽度在5000μm至7000μm的范围内，所述第一晶体管和所述第二晶体管的沟道长度在3μm至6μm的范围内。
  17. 根据权利要求14-16中任一项所述的显示面板，其中，所述移位寄存器还包括：复位电路，所述复位电路连接至所述上拉节点和所述移位寄存器的复位信号端，并配置为在所述复位信号端的控制下将所述上拉节点复位。
  18. 一种显示设备，包括如权利要求1-17中任一项所述的显示面板。
  19. 一种如权利要求1-17中任一项所述的显示面板的控制方法，包括多个移位寄 存器在多个扫描时段分别向多行子像素提供扫描信号，每个扫描时段包括第一时段和第二时段，其中：
    在第一时段，多个移位寄存器中的至少一个移位寄存器通过至少一条栅极线向多个子像素中的至少一行子像素提供扫描信号；
    在第二时段，多个辅助电路中的至少一个辅助电路在辅助信号的控制下将参考信号提供至所述栅极线。
PCT/CN2022/114229 2022-08-23 2022-08-23 显示面板、显示设备和显示面板的控制方法 WO2024040432A1 (zh)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
CN111883077A (zh) * 2020-07-28 2020-11-03 北海惠科光电技术有限公司 栅极驱动电路、显示模组及显示装置
CN111883074A (zh) * 2020-07-28 2020-11-03 北海惠科光电技术有限公司 栅极驱动电路、显示模组及显示装置
CN112164365A (zh) * 2020-10-28 2021-01-01 合肥鑫晟光电科技有限公司 移位寄存器、栅极驱动电路及显示面板
WO2022133729A1 (zh) * 2020-12-22 2022-06-30 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及其驱动方法

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CN111883077A (zh) * 2020-07-28 2020-11-03 北海惠科光电技术有限公司 栅极驱动电路、显示模组及显示装置
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