WO2017128795A1 - 移位寄存器电路、阵列基板和显示装置 - Google Patents

移位寄存器电路、阵列基板和显示装置 Download PDF

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Publication number
WO2017128795A1
WO2017128795A1 PCT/CN2016/104226 CN2016104226W WO2017128795A1 WO 2017128795 A1 WO2017128795 A1 WO 2017128795A1 CN 2016104226 W CN2016104226 W CN 2016104226W WO 2017128795 A1 WO2017128795 A1 WO 2017128795A1
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Prior art keywords
drive
shift register
segment
module
driving
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PCT/CN2016/104226
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English (en)
French (fr)
Inventor
商广良
韩承佑
郑皓亮
姚星
韩明夫
崔贤植
林允植
黄应龙
田正牧
董学
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP16887667.0A priority Critical patent/EP3410425A4/en
Priority to US15/539,220 priority patent/US10096374B2/en
Publication of WO2017128795A1 publication Critical patent/WO2017128795A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display driving technologies, and relates to a partition driving of a GOA (Gate Driver On Array), and more particularly to a shift register circuit, an array substrate, and a display device.
  • GOA Gate Driver On Array
  • a gate driving circuit is required in the display panel to drive the TFT array formed on the array substrate to control display of each pixel or sub-pixel unit.
  • the GOA technology is a technology for fabricating a gate driving circuit on an array substrate, which avoids disposing a circuit board and a chip for forming a gate driving circuit on the outside of the array substrate, thereby greatly reducing the frame size and the improvement of the display. Display panel integration and reduce costs. Therefore, GOA technology is widely used.
  • a shift register circuit comprising two or more driving modules arranged on an array substrate for partition driving in a direction substantially substantially perpendicular to a gate line, each The driving module includes one or more shift registers, and any two of the driving modules adjacent in a direction substantially perpendicular to the gate lines are respectively defined as a first driving module and a second driving module.
  • the first driving input wiring of the first driving module is disposed to sequentially access the first register from the shift register of the first end position of the first driving module to the shift register of the second end position of the first driving module a clock driving signal
  • the second driving input wiring of the second driving module is disposed to be shifted from a shift register at a second end position of the second driving module to a first end position of the second driving module Registers are sequentially connected to the second clock drive letter number.
  • the second end position is opposite the first end position in the direction substantially perpendicular to the gate line.
  • the shift register circuit further includes a first input compensation resistor disposed corresponding to the first drive input wiring, and a second input compensation resistor disposed corresponding to the second drive wiring, wherein The sum of the resistance of the first drive input wiring and the first input compensation resistor is equal to the sum of the resistance of the second drive input wiring and the second input compensation resistor.
  • the first input compensation resistor and/or the second input compensation resistor are disposed on the array substrate and/or outside the array substrate.
  • the first end position corresponds to a minimum arrangement number of the corresponding gate lines of the first driving module or the second driving module on the array substrate
  • the second end position corresponds to the first The maximum arrangement number of the corresponding gate lines of the driving module or the second driving module on the array substrate.
  • the first drive input wiring extends in a direction substantially perpendicular to the gate line and is disposed adjacent to the first driving module;
  • the second driving input wiring includes a first portion disposed in a direction substantially perpendicular to the gate line And a second segment connected to the first segment with respect to the first segment, the second segment being disposed closer to the second drive module than the first segment.
  • the first drive input wiring includes a first segment disposed substantially perpendicular to a direction of the gate line and a second segment vertically bent with respect to the first segment;
  • the second drive input wiring includes A first segment disposed substantially perpendicular to the direction of the gate line and a second segment connected in reverse with respect to the first segment, the second segment being disposed closer to the second drive module than the first segment.
  • the second segment of the first drive input wiring is disposed closer to the first drive module than the first segment.
  • the first end position corresponds to a maximum arrangement number of the corresponding gate lines of the first driving module or the second driving module on the array substrate
  • the second end position corresponds to the first The minimum number of alignments of the corresponding gate lines of the driving module or the second driving module on the array substrate.
  • the first drive input wiring includes a first segment disposed in a direction substantially perpendicular to the gate line and a second segment connected in reverse with respect to the first segment, the first drive input wiring The second segment is disposed closer to the first driving module than the first segment; the second driving input wiring includes a first segment disposed in a direction substantially perpendicular to the gate line And a second segment that is connected perpendicularly to the first segment.
  • the second segment of the second drive input wiring is disposed closer to the second drive module than the first segment.
  • the first driving input wiring and the second driving input wiring are respectively connected to the first clock driving from the same position of the array substrate A signal and the second clock drive signal.
  • the first drive input wiring and the second drive input wiring have substantially the same line width and/or line thickness.
  • the number of shift registers included in each of the drive modules is equal.
  • an array substrate comprising the shift register circuit of any of the above is provided.
  • a display device including the above array substrate is provided.
  • any adjacent ones may be made by arranging the first driving input wiring and the second driving input wiring in opposite directions to the adjacent first driving module and the second driving module, respectively.
  • the RC delay of the two driver modules at their junction does not occur or the hops are greatly reduced.
  • the display device using the shift register does not cause a partition problem on the display, which is advantageous for reducing flicker and reducing horizontal grain spots, and thus, the display effect is significantly improved.
  • 1 is a schematic diagram showing the basic structure of a conventional shift register circuit.
  • FIG. 2 is a schematic diagram showing changes in the resistance load and the capacitive load of the drive signal inputs of the respective shift registers in the shift register circuit of the embodiment shown in FIG.
  • FIG. 3 is a schematic diagram showing the basic structure of a shift register circuit in accordance with one embodiment of the present disclosure.
  • FIG. 4 is a simplified schematic diagram of a shift register circuit of the embodiment shown in FIG.
  • Figure 5 is a diagram showing the driving of each shift register in the shift register circuit of the embodiment shown in Figure 3. Schematic diagram of the trend of the resistive load and capacitive load of the dynamic signal input.
  • FIG. 6 is a simplified schematic diagram of a shift register circuit in accordance with another embodiment of the present disclosure.
  • Fig. 7 is a view showing a trend of changes in resistance load and capacitance load of drive signal inputs of respective shift registers in the shift register circuit of the embodiment shown in Fig. 6.
  • FIG. 8 is a simplified schematic diagram of a shift register circuit in accordance with yet another embodiment of the present disclosure.
  • Fig. 9 is a view showing a trend of changes in resistance load and capacitance load of drive signal inputs of respective shift registers in the shift register circuit of the embodiment shown in Fig. 8.
  • a plurality of parallel gate lines and a plurality of data lines substantially perpendicular to the gate lines are disposed on the array substrate.
  • the direction of the gate line ie, the direction in which the gate line is located
  • the direction perpendicular to the gate line is defined as the direction of the "column", that is, the data line Direction (ie, the direction in which the data lines are arranged on the array substrate), in the Y direction as shown in the figure.
  • the direction of the gate line may be defined as the direction of the "column” and the direction of the data line is defined as the direction of the "row”.
  • a shift register disposed on an array substrate is used to provide a gate drive signal for a corresponding gate line.
  • the shift register can also generally be referred to as a GOA unit.
  • Figure 1 shows the basic structure of a conventional shift register circuit.
  • the shift register circuit 10 includes shift registers SR 1 and SR respectively disposed on the array substrate corresponding to the gate lines GL 1 , GL 2 , . . . , GL n , GL (n+1) , respectively. 2 ,..., SR n , SR (n+1) .
  • the output signal OUT of each shift register ie, OUT 1 , OUT 2 , ...
  • the output signal OUT of the shift register is also input to the shift register of the previous row as the reset signal RESET.
  • the clock drive signals CLK and CLKB input to the shift registers SR 1 , SR 2 , ..., SR n , SR (n+1) are from the same signal source, CLK and CLKB, and pass through the same driver arranged on the array substrate.
  • the input wirings 110a and 110b are respectively connected to the drive signal input terminals of each shift register, that is, CLK and CLKB in the shift register.
  • the change trend of the resistive load and the capacitive load of the drive signal input of each shift register in the shift register circuit can be as shown in the figure. 2 is shown.
  • the abscissa represents the gate lines GL 1, GL 2, ..., GL n shift registers respectively corresponding to the ordinate represents the resistance of the load and capacitive load of the shift register corresponding to the drive signal. It can be seen that the resistive load and the capacitive load of the drive signal between adjacently arranged shift registers are substantially continuously varied, so that no Mura problem occurs during display.
  • more and more shift register circuits adopt a partition driving manner, that is, a plurality of shift registers corresponding to a plurality of rows are divided into one block or region.
  • Block which is defined as a driver module or a GOA block. Between two adjacent GOA blocks, different clock driving signals are used between different GOA blocks to operate at different times, thereby reducing the capacitive load of charging and discharging the clock driving signal and reducing power consumption.
  • FIG. 3 is a schematic diagram showing the basic structure of a shift register circuit in accordance with an embodiment of the present disclosure
  • FIG. 4 is a simplified block diagram showing the shift register circuit of the embodiment shown in FIG. 3 and 4, there is shown a partial circuit configuration of the shift register circuit 30 disposed on an array substrate (not shown).
  • the shift register circuit 30 is mainly used to provide a drive signal output for a plurality of gate lines so that a gate drive signal can be applied to the gate lines.
  • the examples list the input terminals of the plurality of gate lines disposed on the array substrate, specifically the gate lines GL 11 , GL 12 , . . .
  • GL 1 n and the gate lines GL 21 , GL 22 , respectively.
  • , ..., GL 2n wherein the gate line GL 11, GL 12, ..., GL 1n and the gate line GL 21, GL 22, ..., GL 2n are sequentially arranged in parallel in the Y direction.
  • Shift registers SR 11 , SR 12 , ..., SR 1n are provided corresponding to the gate lines GL 11 , GL 12 , ..., GL 1n , respectively; and gate lines GL 21 , GL 22 , ..., Correspondingly, GL 2n is provided with shift registers SR 21 , SR 22 , ..., SR 2n , respectively .
  • each shift register SR is directly connected to the gate line and provides a gate drive signal for the gate line, that is, the output of the drive signal of the output shift register circuit 30, and each shift register SR can also be referred to as "GOA unit".
  • shift register circuit 30 requires at least a clock drive signal to be driven to drive each of shift registers SR therein.
  • the shift register of the shift register circuit 30 on the array substrate can be divided into different drive modules.
  • the shift registers SR 11 , SR 12 , . . . , SR 1n are connected to the clock drive signals CLK and CLKB, and constitute the drive module 310; the shift registers SR 21 , SR 22 , ..
  • the SR 2n accesses the clock drive signals CLK' and CLKB' and constitutes the drive module 320.
  • the driving module 310 and the driving module 320 are divided in the Y direction, and they are respectively input with different clock driving signals, thereby realizing partition driving.
  • each of the drive modules is also integrally disposed on the array substrate, and thus may also be referred to as a "GOA module".
  • These driving modules are respectively driven by different clock signals and respectively operate at different times, thereby facilitating the reduction of the capacitive load of charging and discharging the clock driving signals. Therefore, the partition driving can reduce the overall power consumption of the shift register circuit 30.
  • each shift register SR is also input as an input signal INPUT to the shift register SR corresponding to the next row of gate lines.
  • the output signal of the shift register SR of the next row is also input to the shift register SR of the previous row as the reset signal RESET.
  • All driver modules can simultaneously access the voltage signal VSS, that is, all shift registers SR are connected to the drive input wiring 350. Voltage signal VSS.
  • drive input wirings 311 and 312 are provided corresponding to the driving module 310, wherein the driving input wiring 311 is used to access the clock driving signal CLK, and the driving input wiring 312 is used to access the clock driving signal CLKB; corresponding to the driving module 320
  • the drive input wirings 321 and 322 are provided, wherein the drive input wiring 321 is used to access the clock drive signal CLK', and the drive input wiring 322 is used to access the clock drive signal CLKB'.
  • the driving module 310 and the driving module 320 are adjacently disposed in the Y direction, that is, the gate lines of the last row corresponding to the driving direction of the driving module 310 are in the driving module 320.
  • the gate lines of the first row in the Y direction are adjacent, that is, the gate lines GL 1n and the gate lines GL 21 are adjacent rows, which represent the junction of the driving module 310 and the driving module 320.
  • the first digit corresponding to the subscript of the gate line GL or the shift register SR reflects the driving module to which the sub-number corresponding to the subscript reflects the corresponding arrangement in the subordinate driving module. Ordinal number (for example, the number of rows).
  • a first end position and a second end position may be defined, and the second end position is opposite to the first end position in the direction perpendicular to the gate line (Y direction), that is, they are disposed opposite to each other in the Y direction.
  • Y direction gate line
  • the gate driving module 310 lines GL corresponding to the shift register SR 11 drive the clock input of the position signal 11 may be defined as a first end position, the drive module 310 of the gate line GL 1n
  • the input end position of the clock drive signal of the corresponding shift register SR 1n may be defined as a second end position; accordingly, the drive input wirings 311 and 312 extend in the Y direction and are disposed to be from the first end position of the drive module 310
  • the shift register SR 11 sequentially inputs the clock drive signals CLK and CLKB to the shift register SR 1n of the second end position of the drive module 310, which reflects the access direction of the clock drive signal of the drive module 310.
  • the gate driving module 320 lines GL shift register SR 21 corresponding to the clock input terminal of the position of the drive signal 21 may be defined as a first end position, the drive module 310 of the gate line GL 2n corresponding shift register SR drive clock signal 2N
  • the input terminal position may be defined as a second end position; accordingly, the input wirings 321 and 322 are driven and disposed from the shift register SR 2n at the second end position of the drive module 320 to the first end position of the drive module 320
  • the shift register SR 21 sequentially inputs the clock drive signals CLK' and CLKB', which reflects the access direction of the clock drive signal of the drive module 320.
  • the second end position of the driving module 310 and the first end position of the driving module 320 may also be defined as “adjacent ends” according to the relative positions between adjacent driving modules.
  • the position away from the adjacent end in the Y direction is defined as "distal", that is, the first end position of the driving module 310 is its distal end, and the second end position of the driving module 320 is its distal end.
  • the clock driving signals CLK and CLKB are sequentially connected to the shift register SR from the far end to the adjacent end; for the driving module 320, the clock driving signals CLK' and CLKB' are sequentially connected from the far end to the adjacent end.
  • the shift register SR Into the shift register SR.
  • adjacent end and “distal end” are only relative definitions and clarifications, for example, for the distal end of the driving module 320, a driving module disposed adjacent to the lower side thereof (not shown) It can also be called “adjacent end”.
  • the drive input wirings 311 and 312 may be arranged in parallel in the Y direction on the array substrate and disposed adjacent to one side of the drive module 310.
  • Input to the drive wirings 321 and 322 may, but is not limited to be arranged in an array disposed bent onto the substrate to achieve its second end position of the shift register SR of the shift register SR 2N its first end position 21 of the sequence with the clock Drive signals CLK' and CLKB'.
  • the drive input wirings 311 and 312 and the drive input wirings 321 and 322 are respectively connected to respective clock drive signals from the same position of the array substrate.
  • the access terminals of the clock drive signals CLK and CLKB, CLK' and CLKB' on the array substrate are disposed at substantially upper end positions of the start line of the gate lines.
  • the drive input wirings 311 and 312 are arranged on the array substrate from the top to the bottom in the Y direction, and the drive input wirings 321/222 are first arranged in the Y direction from the top to the bottom of the first segment 321a/322a and reversely bent.
  • the second segment 321b/322b is arranged from bottom to top in the Y direction, that is, the first segments 321a/322a of the drive input wirings 321/322 are arranged in the Y direction, and the second segments 321b/322b are also arranged in the Y direction but relatively close.
  • the driving module 320, the second segment 321b/322b is reversely bent and connected to the first segment 321a/322a.
  • the drive input wirings 311 and 312, and the drive input wirings 321 and 322 may be formed of a conductive material, such as a metal wiring.
  • the drive input wirings 311 and 312 and the drive input wirings 321 and 322 may have the same line width and/or line thickness, which is relatively easy to manufacture.
  • an input compensation resistor may be provided corresponding to each of the drive input wirings.
  • input compensation resistors 331 and 332 are provided corresponding to the drive input wirings 311 and 312, respectively, and input compensation resistors 341 and 342 are provided corresponding to the drive input wirings 321 and 322, respectively.
  • the size of the resistor It should be understood that the resistance of the input compensation resistor can be adjusted by setting the material of the input compensation resistor on the array substrate, the line width and/or the line thickness, etc., and the resistance of each input compensation resistor can be determined according to the corresponding driving input wiring. The size of the resistor is determined.
  • one or more of the input compensation resistors may be disposed outside of the array substrate, that is, the input compensation resistors are not limited to being disposed over the array substrate.
  • clock driving signals CLK and CLKB are different clock signals with respect to the clock driving signals CLK' and CLKB', and their specific forms are not limited, and specifically, various clock driving signals driven by the partitions may be employed.
  • FIG. 5 is a schematic diagram showing changes in the resistance load and the capacitive load of the drive signal inputs of the respective shift registers in the shift register circuit of the embodiment shown in FIG. 3 to 5, the abscissa indicates that the gate lines GL 11 , GL 12 , ..., GL 1n of the shift register circuit 30 and the gate lines GL 21 , GL 22 , ..., GL 2n respectively correspond.
  • a shift register, the ordinate represents a resistive load and a capacitive load corresponding to the drive signal at the shift register described above.
  • the capacitive load C and the resistive load R are cumulatively accumulated to the drive input wiring row by row in accordance with the access direction of the clock drive signal.
  • the clock drive signal is sequentially applied.
  • the number of rows in which it is added increases, and the capacitive load C and the resistive load R increase substantially linearly from row to line, that is, the capacitive load C of the drive signal input of the shift registers SR 11 , SR 12 , ..., SR 1n
  • the resistive load R is gradually increased in accordance with GL 11 to GL 1n .
  • the clock drive signal is sequentially inserted
  • the capacitive load C and the resistive load R are substantially linearly reduced from row to line, that is, the capacitive load C and the resistance of the drive signals input to the shift registers SR 21 , SR 22 , ..., SR 2n
  • the load R is gradually decreased in accordance with GL 21 to GL 2n (the ratio of the resistive load/capacitive load of the drive input wirings 321 and 322 itself to the capacitive load C/resistive load R of the drive signal input is small).
  • the capacitive load C and the resistive load R of the driving signal input do not jump or the hopping is greatly reduced.
  • the RC delay of adjacent drive blocks at the boundary of the partition will not be hopped or the hopping will be greatly reduced, and the delay difference of different blocks in the plane will be reduced, which avoids the problem of partitioning on the display, thereby effectively reducing flicker and reducing. Horizontal stripes problem.
  • FIG. 6 is a simplified block diagram showing a shift register circuit in accordance with another embodiment of the present disclosure.
  • the shift register circuit 40 also employs a partition drive that includes a drive module 410 and a drive module 420.
  • the drive module 410 and the drive module 420 are respectively disposed in substantially the same manner as the drive module 310 and the drive module 320, for example, the first end position and the second end thereof.
  • the definition of the location is also the same, therefore, the drive module 410 and the drive module 420 are not detailed and detailed illustrated herein.
  • drive input wirings 411 and 412 are provided corresponding to the drive module 410 for respectively accessing the clock drive signals CLK and CLKB to the n shift registers SR of the drive module 410.
  • Drive input wirings 421 and 422 are provided corresponding to the drive module 420 for respectively accessing the clock drive signals CLK' and CLKB' to the n shift registers SR of the drive module 420.
  • the drive input wirings 411 and 412 are disposed in order from the shift register (SR 1n ) at the second end position of the drive module 410 to the shift register (SR 11 ) at the first end position of the drive module 410.
  • the clock drive signals CLK and CLKB are connected.
  • the drive input wirings 421 and 422 are disposed to sequentially access the clock drive signal CLK from the shift register (SR 21 ) at the first end position of the drive module 420 to the shift register (SR 2n ) at the second end position of the drive module 420.
  • 'and CLKB' that is, for the driving module 410, the clock driving signals CLK and CLKB are sequentially connected to the shift register SR from the adjacent end to the far end; for the driving module 420, the clock driving signals CLK' and CLKB' are from the adjacent end to The remote end sequentially accesses the shift register SR.
  • the drive input wirings 411/412 first arrange the first segments 411a/412a from top to bottom in the Y direction and reversely bend and then lay the second from bottom to top in the Y direction.
  • the segment 411b/412b that is, the drive input wiring 411/412 includes a first segment 411a/412a and a second segment 411b/412b arranged in the Y direction, the second segment 411b/412b being opposite to the first segment 411a/412a
  • the turns are connected and arranged close to the driving module 410; the driving input wirings 421/422 firstly arrange the first segments 421a/422a from top to bottom in the Y direction and are vertically bent and then arrange the second segments 421b from top to bottom in the Y direction.
  • the wire 421/422 includes a first segment 421a/422a and a second segment 421b/422b arranged in the Y direction, the second segment 421b/422b being vertically bent and disposed adjacent to the first segment 421a/422a and disposed adjacent to the drive module 420.
  • the specific wiring shape of the drive input wirings 411 and 412, 421, and 422 is not limited to this embodiment.
  • an input compensation resistor can be provided for each drive input wiring.
  • R 421 + R 441 ) (R 422 + R 442 ), where R 411 represents the magnitude of the resistance of the drive input wiring 411, R 431 represents the magnitude of the resistance of the input compensation resistor 431, and R 412 represents the magnitude of the resistance of the drive input wiring 412, R 432 denotes the magnitude of the resistance of the input compensation resistor 432, R 421 denotes the magnitude of the resistance of the drive input wiring 421, R 441 denotes the magnitude of the resistance of the input compensation resistor 441, R 422 denotes the magnitude of the resistance of the drive input wiring 422, and R 442 denotes the magnitude of the resistance of the input compensation resistor 442.
  • the size of the resistor is the size of the resistor.
  • one or more of the input compensation resistors 431 and 432 and the input compensation resistors 441 and 442 may be disposed outside of the array substrate, that is, the input compensation resistors are not limited to being disposed in the array. Above the substrate.
  • each of the shift registers SR in the drive modules 410 and 420 is coupled to the voltage signal VSS through the drive input wiring 450.
  • Fig. 7 is a view showing the trend of changes in the resistive load and the capacitive load of the drive signal inputs of the respective shift registers in the shift register circuit of the embodiment shown in Fig. 6.
  • the abscissa indicates a shift register corresponding to the gate line of the shift register circuit 40
  • the ordinate indicates a resistive load and a capacitive load corresponding to the drive signal at the shift register.
  • the capacitive load C and the resistive load R are cumulatively accumulated to the drive input wiring row by row in accordance with the access direction of the clock drive signal.
  • the access direction of the clock drive signal of the shift register circuit 40 is different from the access direction of the clock drive signal of the shift register circuit 30 of the embodiment shown in FIG.
  • the capacitive load C and the resistive load R increase substantially linearly from row to line, that is, the capacitive load of the drive signal input of the shift registers SR 21 , SR 22 , ..., SR 2n C and the resistive load R are gradually increased in synchronization with GL 21 to GL 2n .
  • the capacitive load C and the resistive load R are not tripped or the jump is greatly reduced, and the adjacent driving is performed.
  • the RC delay of the block at the partition junction will not jump or the hop will be greatly reduced.
  • FIG. 8 is a simplified schematic diagram of a shift register circuit in accordance with yet another embodiment of the present disclosure.
  • the shift register circuit 50 is extended relative to the shift register circuit 40, wherein the shift register circuit 50 is extended with respect to the shift register circuit 40 by adding a drive module, i.e., the drive module 530.
  • the same reference numerals denote the same components, and will not be described again.
  • the drive module 530 is disposed adjacent to the drive module 420 in the Y direction, for example, it can include n top to bottom shift registers (eg, SR 31 , SR 32 , . . . SR 3n ), wherein the arrangement of the n shift registers is the same as the arrangement of the shift registers in the drive module 420.
  • the first position end and the second position end are also defined for the driving module 530, that is, the input end position of the clock driving signal of the shift register SR 31 corresponding to the gate line GL 31 of the driving module 530 can be defined as the first position.
  • end position of the drive module input clock signal driving the gate lines GL 3n 530 corresponding to the shift register SR 3n may be defined as a second end position.
  • the first end position of the driving module 530 and the second end position of the driving module 420 may also be defined as “adjacent ends”, and away from the adjacent ends in the Y direction. The location is defined as “remote.”
  • the driving module 420 is defined as "adjacent end” with respect to the driving module 530, and its first end position is defined as “distal end”.
  • Drive input wirings 531 and 532 are provided corresponding to the drive module 530 for respectively accessing the clock drive signals CLK” and CLKB" to the n shift registers SR of the drive module 530.
  • the drive input wirings 531 and 532 are disposed in order from the shift register (SR 3n ) at the second end position of the drive module 530 to the shift register (SR 31 ) at the first end position of the drive module 530.
  • the clock drive signals CLK' and CLKB" are accessed, which reflects the access direction of the clock drive signals CLK” and CLKB" of the drive module 530.
  • the drive input wirings 531/532 first arrange the first segments 531a/532a from top to bottom in the Y direction and reversely bend and then lay the second from bottom to top in the Y direction.
  • the segment 531b/532b that is, the drive input wiring 531/532 includes a first segment 531a/532a and a second segment 531b/532b arranged in the Y direction, the second segment 531b/532b being opposite to the first segment 531a/532a
  • the turns are connected and arranged adjacent to the drive module 530.
  • an input compensation resistor may be provided corresponding to each of the drive input wirings.
  • R 411 represents the magnitude of the resistance of the drive input wiring 411
  • R 431 represents the magnitude of the resistance of the input compensation resistor 431
  • R 412 represents the magnitude of the resistance of the drive input wiring 412
  • R 432 represents the magnitude of the resistance of the input compensation resistor 432
  • R 421 represents the magnitude of the resistance of the drive input wiring 421
  • R 441 represents the input compensation resistor.
  • the magnitude of the resistance of 441, R 422 represents the magnitude of the resistance of the drive input wiring 422
  • R 442 represents the magnitude of the resistance of the input compensation resistor 442
  • R 531 represents the magnitude of the resistance of the drive input wiring 531
  • R 551 represents the magnitude of the resistance of the input compensation resistor 551
  • R 532 denotes the magnitude of the resistance of the drive input wiring 532
  • R 552 denotes the magnitude of the resistance of the input compensation resistor 552.
  • Fig. 9 is a view showing the trend of changes in the resistive load and the capacitive load of the drive signal inputs of the respective shift registers in the shift register circuit of the embodiment shown in Fig. 8.
  • the abscissa indicates the shift register corresponding to the gate line of the shift register circuit 50, and the ordinate indicates the resistive load and the capacitive load corresponding to the drive signal at the shift register.
  • the capacitive load C and the resistive load R are cumulatively accumulated to the drive input wiring row by row in accordance with the access direction of the clock drive signal.
  • the change trend of the capacitive load C and the resistive load R of the driving module 410 and the driving module 420 can also be referred to FIG. 7, at the boundary of the driving modules 410 and 420, that is, the corresponding gate lines GL 1n and GL 21 At the corresponding position, the capacitive load C and the resistive load R also do not jump or the jump is greatly reduced, and the RC delay of the adjacent drive block at the boundary of the partition does not jump or the jump is greatly reduced.
  • the shift register (SR 3n ) from its second end position is sequentially connected to the shift register (SR 31 ) at its first end position, the clock drive signal is sequentially input.
  • the capacitive load C and the resistive load R are linearly reduced substantially linearly from row to line, that is, the capacitance of the drive signal input of the shift registers SR 31 , SR 12 , ..., SR 3n
  • the load C and the resistive load R are gradually decreased in accordance with GL 31 to GL 3n .
  • the capacitive load C and the resistive load R also do not jump or the hopping is greatly reduced, and the adjacent driving blocks are The RC delay at the partition junction also does not jump or the transition is greatly reduced.
  • the shift register circuit 30, 40 or 50 of the above embodiment may be formed on the array substrate to form the array substrate of the embodiment of the present disclosure; based on the array substrate, a corresponding display device may be prepared. The display effect of the display device will be greatly improved.
  • the first end position and the second end position of the driving module are relatively defined to clarify the access direction of the clock driving signals of the adjacent driving modules, and are not limited to the above embodiments.
  • the first end position may also correspond to a maximum order number of the corresponding gate lines of the driving module on the array substrate
  • the second end position may also correspond to a minimum order number of the corresponding gate lines of the driving module on the array substrate.
  • the position of the drive input module 320 of the gate line GL 21 corresponding to 21 clocks shift register SR of the drive signal may be defined as a second end position
  • the input position of the drive signal can be defined as the first end position.

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Abstract

公开了一种移位寄存器电路、阵列基板和显示装置。该移位寄存器电路包括布置在阵列基板上的用于按基本上垂直于栅线的方向进行分区驱动的两个或两个以上驱动模块。对于在基本上垂直于栅线的方向上相邻的第一驱动模块（310）和第二驱动模块（320），第一驱动模块（310）的第一驱动输入布线（311、312）被设置为从第一驱动模块（310）的第一端位置的移位寄存器向第一驱动模块（310）的第二端位置的移位寄存器依次接入第一时钟驱动信号（CLK，CLKB），第二驱动模块（320）的第二驱动输入布线（321、322）被设置为从第二驱动模块（320）的第二端位置的移位寄存器向第二驱动模块（320）的第一端位置的移位寄存器依次接入第二时钟驱动信号（CLK'，CLKB'）。

Description

移位寄存器电路、阵列基板和显示装置
相关申请
本申请要求享有2016年1月25日提交的中国专利申请No.201610046275.8的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开属于显示驱动技术领域，涉及GOA(Gate Driver On Array，位于阵列基板上的驱动)的分区(Block)驱动，尤其涉及一种移位寄存器电路、阵列基板和显示装置。
背景技术
显示面板中需要使用栅极驱动电路来对形成在阵列基板上的TFT阵列进行驱动来控制各个像素或亚像素单元的显示。GOA技术是将栅极驱动电路制作在阵列基板上的技术，其避免了在阵列基板的外部布置用于形成栅极驱动电路的电路板及芯片，因而非常有利于减小显示器的边框尺寸、提高显示面板的集成度并降低成本。因此，GOA技术被广泛应用。
发明内容
本公开的目的在于，提供一种改进的移位寄存器电路、阵列基板和显示装置。
按照本公开的一方面，提供一种移位寄存器电路，包括布置在阵列基板上的用于按基本上基本上垂直于栅线的方向进行分区驱动的两个或两个以上驱动模块，每个驱动模块包括一个或多个移位寄存器，将在基本上垂直于栅线的方向上相邻的任意两个所述驱动模块分别定义为第一驱动模块和第二驱动模块。
第一驱动模块的第一驱动输入布线被设置为从所述第一驱动模块的第一端位置的移位寄存器向所述第一驱动模块的第二端位置的移位寄存器依次接入第一时钟驱动信号，所述第二驱动模块的第二驱动输入布线被设置为从所述第二驱动模块的第二端位置的移位寄存器向所述第二驱动模块的第一端位置的移位寄存器依次接入第二时钟驱动信 号。在每个所述驱动模块中，所述第二端位置在所述基本上垂直于栅线的方向上与所述第一端位置相对。
根据一些实施例，所述移位寄存器电路还包括与所述第一驱动输入布线对应地设置的第一输入补偿电阻，以及与所述第二驱动布线对应地设置的第二输入补偿电阻，其中，第一驱动输入布线的电阻与所述第一输入补偿电阻之和等于第二驱动输入布线的电阻与所述第二输入补偿电阻之和。
根据一些实施例，所述第一输入补偿电阻和/或所述第二输入补偿电阻被设置在所述阵列基板上和/或阵列基板外。
根据一些实施例，所述第一端位置对应所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最小排列序数，所述第二端位置对应为所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最大排列序数。
根据一些实施例，所述第一驱动输入布线在基本上垂直于栅线的方向延伸并且靠近第一驱动模块布置；所述第二驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对所述第一段反转弯折连接的第二段，所述第二段比所述第一段更靠近第二驱动模块布置。
根据一些实施例，所述第一驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对该第一段垂直弯折连接的第二段；所述第二驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对所述第一段反转弯折连接的第二段，所述第二段比所述第一段更靠近第二驱动模块布置。
根据一些实施例，所述第一驱动输入布线的所述第二段比所述第一段更靠近第一驱动模块布置。
根据一些实施例，所述第一端位置对应所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最大排列序数，所述第二端位置对应为所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最小排列序数。
根据一些实施例，所述第一驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对所述第一段反转弯折连接的第二段，所述第一驱动输入布线的第二段比所述第一段更靠近第一驱动模块布置；所述第二驱动输入布线包括在基本上垂直于栅线的方向布置的第一段 和相对该第一段垂直弯折连接的第二段。
根据一些实施例，所述第二驱动输入布线的所述第二段比所述第一段更靠近第二驱动模块布置。
在之前所述任一实施例的移位寄存器电路中，进一步，所述第一驱动输入布线和所述第二驱动输入布线从所述阵列基板的同一位置处分别接入所述第一时钟驱动信号和所述第二时钟驱动信号。
在之前所述任一实施例的移位寄存器电路中，进一步，所述第一驱动输入布线和所述第二驱动输入布线具有基本上相同的线宽和/或线厚。
在之前所述任一实施例的移位寄存器电路中，进一步，每个驱动模块所包括的移位寄存器的个数相等。
按照本公开的另一方面，提供一种阵列基板，其包括以上任一项所述及的移位寄存器电路。
按照本公开的又一方面，提供一种显示装置，其包括以上所述阵列基板。
在本公开的上述实施例中，通过对相邻的第一驱动模块和第二驱动模块分别布置时钟驱动信号接入方向相反的第一驱动输入布线和第二驱动输入布线，可以使任何相邻的两驱动模块在其交界处的RC延迟不会发生跳变或者跳变大大减小。使用该移位寄存器的显示装置在显示上不会产生分区问题，有利于降低闪烁、减小横纹斑点，因此，使得显示效果得到明显提升。
附图说明
从结合附图的以下详细说明中，将会使本公开的上述和其他目的及优点更加完整清楚，其中，相同或相似的要素采用相同的标号表示。
图1是常规移位寄存器电路的基本结构示意图。
图2是图1所示实施例的移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势示意图。
图3是按照本公开的一个实施例的移位寄存器电路的基本结构示意图。
图4是图3所示实施例的移位寄存器电路的简化结构示意图。
图5是图3所示实施例的移位寄存器电路中各个移位寄存器的驱 动信号输入的电阻负载和电容负载的变化趋势示意图。
图6是按照本公开的另一实施例的移位寄存器电路的简化结构示意图。
图7是图6所示实施例的移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势示意图。
图8是按照本公开的又一实施例的移位寄存器电路的简化结构示意图。
图9是图8所示实施例的移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势示意图。
具体实施方式
下面介绍的是本公开的多个可能实施例中的一些，旨在提供对本公开的基本了解，并不旨在确认本公开的关键或决定性的要素或限定所要保护的范围。容易理解，根据本公开的技术方案，在不变更本公开的实质精神下，本领域的一般技术人员可以提出可相互替换的其他实现方式。因此，以下具体实施方式以及附图仅是对本公开的技术方案的示例性说明，而不应当视为本公开的全部或者视为对本公开技术方案的限定或限制。
下面的描述中，为描述的清楚和简明，并没有对图中所示的所有多个部件进行详细描述，附图中示出了本领域普通技术人员为完全能够实现本公开的多个部件，对于本领域技术人员来说，许多部件的操作都是熟悉而且明显的。
在本公开的以下实施例中，在阵列基板上设置有多条平行的栅线以及与栅线基本垂直的多条数据线。将栅线的方向(即栅线所在的方向)定义为“行”的方向，即图中所示的X方向，将垂直于栅线的方向定义为“列”的方向，也即数据线的方向(即数据线在阵列基板上的布置方向)，如图中所示的Y方向。需要理解，在其他可替换的实施例中，例如也可以将栅线的方向定义为“列”的方向，数据线的方向定义为“行”的方向。
在目前的GOA技术中，使用布置在阵列基板上的移位寄存器来为相应的栅线提供栅极驱动信号。移位寄存器通常也可以被称为GOA单元。图1所示为常规移位寄存器电路的基本结构示意图。如图1所示， 移位寄存器电路10包括布置在阵列基板上的与栅线GL1、GL2、...、GLn、GL(n+1)分别对应的移位寄存器SR1、SR2、...、SRn、SR(n+1)。每个移位寄存器的输出信号OUT(即OUT1、OUT2、...或OUT(n+1))还作为输入信号INPUT输入到下一行栅线对应的移位寄存器；同时，下一行的移位寄存器的输出信号OUT还输入到上一行的移位寄存器作为复位信号RESET。移位寄存器SR1、SR2、...、SRn、SR(n+1)输入的时钟驱动信号CLK和CLKB是来自同一信号源，即CLK和CLKB，并且通过阵列基板上布置的相同驱动输入布线110a和110b分别接入每个移位寄存器的驱动信号输入端，即移位寄存器中的CLK和CLKB。
在如图1所示的移位寄存器电路中，由于所有移位寄存器接入同一时钟驱动信号，并且对于每个移位寄存器来说，其驱动信号的输入电阻负载、输入电容负载相对相邻的上一行的移位寄存器的驱动信号的输入电阻负载、输入电容负载是大致连续变化的，因此，移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势可以如图2所示。在图2中，横坐标表示栅线GL1、GL2、...、GLn分别对应的移位寄存器，纵坐标表示对应于上述移位寄存器处的驱动信号的电阻负载和电容负载。可以看到，相邻布置的移位寄存器之间的驱动信号的电阻负载和电容负载是基本连续变化的，因此，在显示时不会出现斑点(Mura)问题。
为了降低如图1所示的移位寄存器电路10的功耗，越来越多的移位寄存器电路采用分区驱动的方式，也即若干行对应的多个移位寄存器被划分为一个块或区(Block)，将其定义为驱动模块或GOA块。在相邻的两个GOA块之间，不同的GOA块之间采用不同的时钟驱动信号以使它们分别在不同的时间工作，从而减少时钟驱动信号充放电的电容负载，降低功耗。
但是，本申请的发明人发现，在相邻的GOA块的交界处，相邻设置的移位寄存器的驱动信号输入的电阻负载和电容负载会发生比较大的跳变，从而相应产生驱动信号输入的延迟跳变。该延迟跳变反映在显示上会产生分区问题，例如在相邻的GOA块对应的显示区域之间产生闪烁、横纹斑点问题。
为此，本公开提供了一种改进的移位寄存器电路。图3所示为按照本公开的一个实施例的移位寄存器电路的基本结构示意图；图4所 示为图3所示实施例的移位寄存器电路的简化结构示意图。结合图3和图4，其中示出了布置在阵列基板(图中未示出)上的移位寄存器电路30的局部电路结构。该移位寄存器电路30主要是用来为多条栅线提供驱动信号输出，从而可以向栅线施加栅极驱动信号。在该实施例中，示例列出了布置在阵列基板上的其中若干条栅线的输入端，具体分别为栅线GL11、GL12、...、GL1n和栅线GL21、GL22、...、GL2n，其中栅线GL11、GL12、...、GL1n和栅线GL21、GL22、...、GL2n在Y方向上依次平行设置。与栅线GL11、GL12、...、GL1n对应地，分别设置了移位寄存器SR11、SR12、...、SR1n；与栅线GL21、GL22、...、GL2n对应地，分别设置了移位寄存器SR21、SR22、...、SR2n。将理解，每个移位寄存器SR的输出端直接连接栅线并为栅线提供栅极驱动信号，也即输出移位寄存器电路30的驱动信号输出，每个移位寄存器SR也可以被称为“GOA单元”。
在本公开的实施例中，移位寄存器电路30需要至少接入时钟驱动信号来驱动其中的每个移位寄存器SR。按照接入的时钟驱动信号来划分，可以将移位寄存器电路30在阵列基板上的移位寄存器划分成不同的驱动模块。在图3所示实施例中，移位寄存器SR11、SR12、...、SR1n接入时钟驱动信号CLK和CLKB，并且构成驱动模块310；移位寄存器SR21、SR22、...、SR2n接入时钟驱动信号CLK’和CLKB’，并且构成驱动模块320。驱动模块310和驱动模块320是在Y方向上进行划分的，它们分别被输入不同的时钟驱动信号，从而实现分区驱动。
需要理解的是，驱动模块的划分是按照接入的时钟驱动信号不同来实现的；图3中示意的虚线框仅是用来清楚示意驱动模块的区域范围。每个驱动模块整体也设置在阵列基板上，因而也可以将其称之为“GOA模块(Block)”。这些驱动模块分别采用不同的时钟信号驱动，分别在不同的时间工作，从而有利于减少时钟驱动信号充放电的电容负载，因此，采用分区驱动可以降低移位寄存器电路30的整体功耗。
继续如图3所示，在多个相邻的驱动模块中，每个移位寄存器SR的输出信号还作为输入信号INPUT输入到下一行栅线对应的移位寄存器SR。同时，下一行的移位寄存器SR的输出信号还输入到上一行的移位寄存器SR作为复位信号RESET。所有驱动模块可以同时接入电压信号VSS，也即所有移位寄存器SR均通过驱动输入布线350接入电 压信号VSS。
继续如图3和图4所示，与不同的驱动模块对应地分别设置不同的驱动输入布线。具体地，与驱动模块310对应地设置驱动输入布线311和312，其中驱动输入布线311用来接入时钟驱动信号CLK，驱动输入布线312用来接入时钟驱动信号CLKB；与驱动模块320对应地设置驱动输入布线321和322，其中驱动输入布线321用来接入时钟驱动信号CLK’，驱动输入布线322用来接入时钟驱动信号CLKB’。
继续如图3和图4所示，驱动模块310和驱动模块320在Y方向上是相邻设置的，也就是说，驱动模块310对应的在Y方向的末行的栅线与驱动模块320在Y方向的首行的栅线是相邻的，也即栅线GL1n和栅线GL21是相邻行，它们表示驱动模块310和驱动模块320的交界处。在本公开实施例中，栅线GL或移位寄存器SR的下标对应的第一位数字反映其所属的驱动模块，其下标对应的第二位数字反映其在所属驱动模块中对应的排列序数(例如行数)。
对应每个驱动模块，可以定义第一端位置和第二端位置，第二端位置在垂直于栅线的方向上(Y方向)与第一端位置相对，也即它们在Y方向相向设置。在如图3所示的实施例中，驱动模块310的栅线GL11对应的移位寄存器SR11的时钟驱动信号的输入端位置可以定义为第一端位置，驱动模块310的栅线GL1n对应的移位寄存器SR1n的时钟驱动信号的输入端位置可以定义为第二端位置；相应地，驱动输入布线311和312在Y方向延伸，并被设置为从驱动模块310的第一端位置的移位寄存器SR11向驱动模块310的第二端位置的移位寄存器SR1n依次接入时钟驱动信号CLK和CLKB，这反映了驱动模块310的时钟驱动信号的接入方向。驱动模块320的栅线GL21对应的移位寄存器SR21的时钟驱动信号的输入端位置可以定义为第一端位置，驱动模块310的栅线GL2n对应的移位寄存器SR2n的时钟驱动信号的输入端位置可以定义为第二端位置；相应地，驱动输入布线321和322并被设置为从驱动模块320的第二端位置的移位寄存器SR2n向驱动模块320的第一端位置的移位寄存器SR21依次接入时钟驱动信号CLK’和CLKB’，这反映了驱动模块320的时钟驱动信号的接入方向。
按照相邻的驱动模块之间的相对位置来定义，也可以将驱动模块310的第二端位置和驱动模块320的第一端位置定义为“相邻端”，在 Y方向上远离相邻端的位置定义为“远端”，也即驱动模块310的第一端位置为其远端、驱动模块320的第二端位置为其远端。对于驱动模块310，其时钟驱动信号CLK和CLKB从远端至相邻端依次接入移位寄存器SR；对于驱动模块320，其时钟驱动信号CLK’和CLKB’从远端至相邻端依次接入移位寄存器SR。但是，需要理解的是，“相邻端”和“远端”只是相对的定义和澄清，例如，对于驱动模块320的远端，相对其下面相邻设置的驱动模块(图中未示出)，也可以被称之为“相邻端”。
继续如图3和图4所示，驱动输入布线311和312可以在Y方向平行地布置在阵列基板上，并靠近驱动模块310的一侧设置。对于驱动输入布线321和322，可以但不限于弯折设置地布置在阵列基板上来实现从其第二端位置的移位寄存器SR2n向其第一端位置的移位寄存器SR21依次接入时钟驱动信号CLK’和CLKB’。
在该实施例中，驱动输入布线311和312以及驱动输入布线321和322从阵列基板的同一位置处分别接入相应的时钟驱动信号。具体地，时钟驱动信号CLK和CLKB、CLK’和CLKB’在阵列基板上的接入端设置在栅线起始行的大致上端位置。这样，驱动输入布线311和312在Y方向上从上至下布置在阵列基板上，驱动输入布线321/322先在Y方向上从上至下布置第一段321a/322a并反转弯折后在Y方向上从下至上布置第二段321b/322b，也就是说，驱动输入布线321/322的第一段321a/322a在Y方向布置，第二段321b/322b也在Y方向布置但相对靠近驱动模块320，第二段321b/322b相对第一段321a/322a反转弯折并与其连接。
在该实施例中，驱动输入布线311和312、驱动输入布线321和322可以由导电材料形成，例如可以为金属布线。驱动输入布线311和312以及驱动输入布线321和322可以具有相同的线宽和/或线厚，制造相对更加容易。
继续如图3和图4所示，可选地，与每条驱动输入布线对应地，可以设置输入补偿电阻。在该实施中，分别与驱动输入布线311和312对应地设置输入补偿电阻331和332，并且分别与驱动输入布线321和322对应地设置输入补偿电阻341和342。鉴于驱动输入布线321和322很可能相对驱动输入布线311和312具有不同的电阻，可以通过设置 它们的补偿电阻的大小，使(R311+R331)＝(R312+R332)＝(R321+R341)＝(R322+R342)，其中，R311表示驱动输入布线311的电阻大小，R331表示输入补偿电阻331的电阻大小，R312表示驱动输入布线312的电阻大小，R332表示输入补偿电阻332的电阻大小，R321表示驱动输入布线321的电阻大小，R341表示输入补偿电阻341的电阻大小，R322表示驱动输入布线322的电阻大小，R342表示输入补偿电阻342的电阻大小。需要理解的是，通过在阵列基板上设置输入补偿电阻的材料、线宽和/线厚等可以调节设置其电阻大小，每个输入补偿电阻的电阻大小可以根据测得的相应的驱动输入布线的电阻大小来确定。
在又一替换实施例中，一个或多个输入补偿电阻可以设置在阵列基板之外，也就是说，输入补偿电阻并不限于设置在阵列基板之上。
需要说明的是，时钟驱动信号CLK和CLKB相对时钟驱动信号CLK’和CLKB’是不同的时钟信号，它们的具体形式不是限制性的，其具体可以采用分区驱动的各种时钟驱动信号。
图5所示为图3所示实施例的移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势示意图。结合图3至图5所示，横坐标表示移位寄存器电路30的栅线GL11、GL12、...、GL1n和栅线GL21、GL22、...、GL2n分别对应的移位寄存器，纵坐标表示对应于上述移位寄存器处驱动信号的电阻负载和电容负载。对于每个驱动模块，其电容负载C和电阻负载R是按照时钟驱动信号的接入方向逐行增加地累积到驱动输入布线的。因此，对于驱动模块310的每个移位寄存器来说，在从其第一端位置的移位寄存器SR11向其第二端位置的移位寄存器SR1n依次接入时钟驱动信号时，随着其所在的行数的增加，电容负载C和电阻负载R是逐行大致线性增加的，也即，移位寄存器SR11、SR12、...、SR1n的驱动信号输入的电容负载C和电阻负载R是按照GL11至GL1n逐渐增加的。对于驱动模块320的每个移位寄存器来说，在从其第二端位置的移位寄存器SR2n向其第一端位置的移位寄存器SR21依次接入时钟驱动信号时，随着其所在的行数的增加，电容负载C和电阻负载R是逐行大致线性减小的，也即，移位寄存器SR21、SR22、...、SR2n的驱动信号输入的电容负载C和电阻负载R是按照GL21至GL2n逐渐降低的(驱动输入布线321和322自身的电阻负载/电容负载相对驱动信号输入的电容负载C/电阻负载R产生 贡献的占比是较小的)。
这样，在驱动模块310和320的交界处，也即对应栅线GL1n和GL21的位置处，驱动信号输入的电容负载C和电阻负载R并不会发生跳变或者跳变大大减小，相邻驱动块在分区交界处的RC延迟也不会发生跳变或者跳变大大减小，面内不同块的延迟差异减小，避免了在显示上产生分区问题，从而有效降低闪烁、减小横纹斑点问题。
图6所示为按照本公开的另一实施例的移位寄存器电路的简化结构示意图。移位寄存器电路40也是采用分区驱动，其包括驱动模块410和驱动模块420。相比于图3所示实施例的移位寄存器电路30，驱动模块410和驱动模块420分别以与驱动模块310和驱动模块320基本相同的方式设置，例如，其第一端位置和第二端位置的定义也是相同的，因此，在此未对驱动模块410和驱动模块420作详述和详细图示。
参见图6，与驱动模块410对应地设置驱动输入布线411和412，分别用来向驱动模块410的n个移位寄存器SR接入时钟驱动信号CLK和CLKB。与驱动模块420对应地设置驱动输入布线421和422，分别用来向驱动模块420的n个移位寄存器SR接入时钟驱动信号CLK’和CLKB’。在该实施例中，驱动输入布线411和412被设置为从驱动模块410的第二端位置的移位寄存器(SR1n)向驱动模块410的第一端位置的移位寄存器(SR11)依次接入时钟驱动信号CLK和CLKB。驱动输入布线421和422被设置为从驱动模块420的第一端位置的移位寄存器(SR21)向驱动模块420的第二端位置的移位寄存器(SR2n)依次接入时钟驱动信号CLK’和CLKB’。也就是说，对于驱动模块410，其时钟驱动信号CLK和CLKB从相邻端至远端依次接入移位寄存器SR；对于驱动模块420，其时钟驱动信号CLK’和CLKB’从相邻端至远端依次接入移位寄存器SR。
继续如图6所示，在示例实施例中，驱动输入布线411/412先在Y方向上从上至下布置第一段411a/412a并反转弯折后在Y方向上从下至上布置第二段411b/412b，也就是说，驱动输入布线411/412包括在Y方向布置的第一段411a/412a和第二段411b/412b，该第二段411b/412b相对第一段411a/412a反转弯折连接并靠近驱动模块410布置；驱动输入布线421/422先在Y方向上从上至下布置第一段421a/422a并垂直弯折后在Y方向上从上至下布置第二段421b/422b，也就是说驱动输入布 线421/422包括在Y方向布置的第一段421a/422a和第二段421b/422b，该第二段421b/422b相对第一段421a/422a垂直弯折连接并靠近驱动模块420布置。驱动输入布线411和412、421和422的具体布线形状不限于该实施例。
继续如图6所示，可选地，对应每条驱动输入布线，可以设置输入补偿电阻。在该实施中，分别与驱动输入布线411和412对应地设置输入补偿电阻431和432，并且分别与驱动输入布线421和422对应地设置输入补偿电阻441和442。鉴于驱动输入布线411和412很可能相对驱动输入布线421和422具有不同的电阻，可以通过设置它们的补偿电阻的大小，使(R411+R431)＝(R412+R432)＝(R421+R441)＝(R422+R442)，其中，R411表示驱动输入布线411的电阻大小，R431表示输入补偿电阻431的电阻大小，R412表示驱动输入布线412的电阻大小，R432表示输入补偿电阻432的电阻大小，R421表示驱动输入布线421的电阻大小，R441表示输入补偿电阻441的电阻大小，R422表示驱动输入布线422的电阻大小，R442表示输入补偿电阻442的电阻大小。
同样地，在又一替换实施例中，输入补偿电阻431和432以及输入补偿电阻441和442的一个或多个可以设置在阵列基板之外，也就是说，输入补偿电阻并不限于设置在阵列基板之上。
继续如图6所示，具体地，在驱动模块410和420中的每个移位寄存器SR均通过驱动输入布线450接入电压信号VSS。
图7所示为图6所示实施例的移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势示意图。横坐标表示移位寄存器电路40的栅线分别对应的移位寄存器，纵坐标表示对应于上述移位寄存器处驱动信号的电阻负载和电容负载。同样，对于每个驱动模块，其电容负载C和电阻负载R是按照时钟驱动信号的接入方向逐行增加地累积到驱动输入布线的。移位寄存器电路40的时钟驱动信号的接入方向不同于图3所示实施例的移位寄存器电路30的时钟驱动信号的接入方向，因此，对于驱动模块410的每个移位寄存器来说，在从其第二端位置的移位寄存器(SR1n)向其第一端位置的移位寄存器(SR11)依次接入时钟驱动信号时，随着其所在的行数的增加，电容负载C和电阻负载R是逐行大致同步线性降低的，也即，移位寄存器SR11、SR12、...、SR1n的驱动信号输入的电容负载C和电阻负载R 是按照GL11至GL1n逐渐降低的(驱动输入布线411和412自身的电阻负载/电容负载相对驱动信号输入的电容负载C/电阻负载R产生贡献的占比是较小的)。对于驱动模块420的每个移位寄存器来说，在从其第一端位置的移位寄存器(SR21)向其第二端位置的移位寄存器(SR2n)依次接入时钟驱动信号时，随着其所在的行数的增加，电容负载C和电阻负载R是逐行大致线性增加的，也即，移位寄存器SR21、SR22、...、SR2n的驱动信号输入的电容负载C和电阻负载R是按照GL21至GL2n同步逐渐增加的。
这样，在驱动模块410和420的交界处，也即对应栅线GL1n和GL21的相应位置处，电容负载C和电阻负载R也不会发生跳变或者跳变大大减小，相邻驱动块在分区交界处的RC延迟也不会发生跳变或者跳变大大减小。
图8所示为按照本公开的又一实施例的移位寄存器电路的简化结构示意图。参照图8和图6，移位寄存器电路50是相对移位寄存器电路40扩展得到的，其中，移位寄存器电路50相对移位寄存器电路40扩展增加了一个驱动模块，即驱动模块530。在移位寄存器电路50和移位寄存器电路40中，其中相同标号表示相同的部件，在此不再一一赘述。
继续参见图8，驱动模块530相对驱动模块420是在Y方向上相邻设置的，例如，其可以包括n个从上至下布置的移位寄存器(例如SR31、SR32、...、SR3n)，其中n个移位寄存器的布置方式与驱动模块420中的移位寄存器的布置方式是相同的。同样地，对于驱动模块530也定义有第一位置端和第二位置端，也即，驱动模块530的栅线GL31对应的移位寄存器SR31的时钟驱动信号的输入端位置可以定义为第一端位置，驱动模块530的栅线GL3n对应的移位寄存器SR3n的时钟驱动信号的输入端位置可以定义为第二端位置。按照相邻的驱动模块之间的相对位置来定义，也可以将驱动模块530的第一端位置和驱动模块420的第二端位置定义为“相邻端”，在Y方向上远离相邻端的位置定义为“远端”。此时，驱动模块420相对驱动模块530来说，其第二端位置定义为“相邻端”，其第一端位置定义为“远端”。
与驱动模块530对应地设置驱动输入布线531和532，分别用来向驱动模块530的n个移位寄存器SR接入时钟驱动信号CLK”和CLKB”。 在该实施例中，驱动输入布线531和532被设置为从驱动模块530的第二端位置的移位寄存器(SR3n)向驱动模块530的第一端位置的移位寄存器(SR31)依次接入时钟驱动信号CLK’和CLKB”，这反映了驱动模块530的时钟驱动信号CLK”和CLKB”的接入方向。
继续如图8所示，在示例实施例中，驱动输入布线531/532先在Y方向上从上至下布置第一段531a/532a并反转弯折后在Y方向上从下至上布置第二段531b/532b，也就是说，驱动输入布线531/532包括在Y方向布置的第一段531a/532a和第二段531b/532b，该第二段531b/532b相对第一段531a/532a反转弯折连接并靠近驱动模块530布置。
继续如图8所示，可选地，对应每条驱动输入布线，可以设置输入补偿电阻。在该实施中，分别与驱动输入布线531和532对应地设置输入补偿电阻551和552。鉴于驱动输入布线411和412、驱动输入布线421和422、驱动输入布线531和532可能具有相互不同的电阻，可以通过设置它们的补偿电阻的大小，使(R411+R431)＝(R412+R432)＝(R421+R441)＝(R422+R442)＝(R531+R551)＝(R532+R552)，其中，R411表示驱动输入布线411的电阻大小，R431表示输入补偿电阻431的电阻大小，R412表示驱动输入布线412的电阻大小，R432表示输入补偿电阻432的电阻大小，R421表示驱动输入布线421的电阻大小，R441表示输入补偿电阻441的电阻大小，R422表示驱动输入布线422的电阻大小，R442表示输入补偿电阻442的电阻大小，R531表示驱动输入布线531的电阻大小，R551表示输入补偿电阻551的电阻大小，R532表示驱动输入布线532的电阻大小，R552表示输入补偿电阻552的电阻大小。
图9所示为图8所示实施例的移位寄存器电路中各个移位寄存器的驱动信号输入的电阻负载和电容负载的变化趋势示意图。横坐标表示移位寄存器电路50的栅线分别对应的移位寄存器，纵坐标表示对应于上述移位寄存器处驱动信号的电阻负载和电容负载。同样，对于每个驱动模块，其电容负载C和电阻负载R是按照时钟驱动信号的接入方向逐行增加地累积到驱动输入布线的。
如图9所示，驱动模块410和驱动模块420的电容负载C和电阻负载R的变化趋势同样可以参照图7，在驱动模块410和420的交界处，也即对应栅线GL1n和GL21的相应位置处，电容负载C和电阻负载R也不会发生跳变或者跳变大大减小，相邻驱动块在分区交界处的RC延 迟也不会发生跳变或者跳变大大减小。对于驱动模块530的每个移位寄存器来说，在从其第二端位置的移位寄存器(SR3n)向其第一端位置的移位寄存器(SR31)依次接入时钟驱动信号时，随着其所在的行数的增加，电容负载C和电阻负载R是逐行大致同步线性降低的，也即，移位寄存器SR31、SR12、...、SR3n的驱动信号输入的电容负载C和电阻负载R是按照GL31至GL3n逐渐降低的。在驱动模块420和530的交界处，也即对应栅线GL2n和GL31的相应位置处，电容负载C和电阻负载R也不会发生跳变或者跳变大大减小，相邻驱动块在分区交界处的RC延迟也不会发生跳变或者跳变大大减小。
本领域技术人员基于以上实施例的教导，在针对具有3个以上的驱动模块进行分区驱动时，可以扩展地设置每个驱动模块的驱动输入布线，使任何相邻的两驱动模块的时钟驱动信号的接入方向(按Y反向)相反地设置，从而使任何相邻的两驱动模块在其交界处的RC延迟不会发生跳变或者跳变大大减小，避免了在显示上产生分区问题，有利于降低闪烁、减小横纹斑点。
进一步，以上实施例的移位寄存器电路30、40或50可以形成在阵列基板上以形成本公开实施例的阵列基板；基于该阵列基板可以制备形成相应的显示装置。该显示装置的显示效果将得到大大提高。
将理解到，驱动模块的第一端位置和第二端位置是为了澄清相邻的驱动模块的时钟驱动信号的接入方向的而相对定义的，其并不限定于以上实施例。在其他实施例中，第一端位置也可以对应驱动模块在阵列基板上所对应栅线的最大排列序数，第二端位置也可以对应为驱动模块在阵列基板上所对应栅线的最小排列序数。例如，驱动模块320的栅线GL21对应的移位寄存器SR21的时钟驱动信号的输入端位置可以定义为第二端位置，驱动模块310的栅线GL1n对应的移位寄存器SR1n的时钟驱动信号的输入端位置可以定义为第一端位置。
还应当理解到，尽管以上各图中示意性地示出各驱动模块具有相同数目的移位寄存器，但是本领域技术人员可以根据实际需要来划分驱动模块并且设计各驱动模块所包括的移位寄存器数目。
以上示例主要说明了本公开的移位寄存器电路。尽管只对其中一些本公开的实施方式进行了描述，但是本领域普通技术人员应当了解，本公开可以在不偏离其主旨与范围内以许多其他的形式实施。因此， 所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本公开精神及范围的情况下，本公开可能涵盖各种的修改与替换。

Claims (15)

  1. 一种移位寄存器电路，包括布置在阵列基板上的用于按基本上垂直于栅线的方向进行分区驱动的两个或两个以上驱动模块，每个驱动模块包括一个或多个移位寄存器，其中，将在基本上垂直于栅线的方向上相邻的任意两个所述驱动模块分别定义为第一驱动模块和第二驱动模块；
    其中，所述第一驱动模块的第一驱动输入布线被设置为从所述第一驱动模块的第一端位置的移位寄存器向所述第一驱动模块的第二端位置的移位寄存器依次接入第一时钟驱动信号，所述第二驱动模块的第二驱动输入布线被设置为从所述第二驱动模块的第二端位置的移位寄存器向所述第二驱动模块的第一端位置的移位寄存器依次接入第二时钟驱动信号；并且
    其中，在每个所述驱动模块中，所述第二端位置在所述基本上垂直于栅线的方向上与所述第一端位置相对。
  2. 如权利要求1所述的移位寄存器电路，其中，还包括与所述第一驱动输入布线对应地设置的第一输入补偿电阻，以及与所述第二驱动布线对应地设置的第二输入补偿电阻，其中，第一驱动输入布线的电阻与所述第一输入补偿电阻之和等于第二驱动输入布线的电阻与所述第二输入补偿电阻之和。
  3. 如权利要求2所述的移位寄存器电路，其中，所述第一输入补偿电阻和/或所述第二输入补偿电阻被设置在所述阵列基板上和/或阵列基板外。
  4. 如权利要求1所述的移位寄存器电路，其中，所述第一端位置对应所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最小排列序数，所述第二端位置对应为所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最大排列序数。
  5. 如权利要求4所述的移位寄存器电路，其中，所述第一驱动输入布线在基本上垂直于栅线的方向靠近第一驱动模块布置；所述第二驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对所述第一段反转弯折连接的第二段，所述第二段比所述第一段更靠近第二驱动模块布置。
  6. 如权利要求4所述的移位寄存器电路，其中，所述第一驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对该第一段垂直弯折连接的第二段；所述第二驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对所述第一段反转弯折连接的第二段，所述第二段比所述第一段更靠近第二驱动模块布置。
  7. 如权利要求6所述的移位寄存器电路，其中，所述第一驱动输入布线的所述第二段比所述第一段更靠近第一驱动模块布置。
  8. 如权利要求1所述的移位寄存器电路，其中，所述第一端位置对应所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最大排列序数，所述第二端位置对应为所述第一驱动模块或第二驱动模块在所述阵列基板上所对应栅线的最小排列序数。
  9. 如权利要求8所述的移位寄存器电路，其中，所述第一驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对所述第一段反转弯折连接的第二段，所述第一驱动输入布线的第二段比所述第一段更靠近第一驱动模块布置；所述第二驱动输入布线包括在基本上垂直于栅线的方向布置的第一段和相对该第一段垂直弯折连接的第二段。
  10. 如权利要求9所述的移位寄存器电路，其中，所述第二驱动输入布线的所述第二段比所述第一段更靠近第二驱动模块布置。
  11. 如权利要求1所述的移位寄存器电路，其中，所述第一驱动输入布线和所述第二驱动输入布线从所述阵列基板的同一位置处分别接入所述第一时钟驱动信号和所述第二时钟驱动信号。
  12. 如权利要求1或5或6或9所述的移位寄存器电路，其中，所述第一驱动输入布线和所述第二驱动输入布线具有基本上相同的线宽和/或线厚。
  13. 如权利要求1所述的移位寄存器电路，其中，每个驱动模块所包括的移位寄存器的个数相等。
  14. 一种阵列基板，包括如权利要求1至13中任一项所述的移位寄存器电路。
  15. 一种显示装置，包括如权利要求14所述的阵列基板。
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