WO2016107043A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2016107043A1
WO2016107043A1 PCT/CN2015/078676 CN2015078676W WO2016107043A1 WO 2016107043 A1 WO2016107043 A1 WO 2016107043A1 CN 2015078676 W CN2015078676 W CN 2015078676W WO 2016107043 A1 WO2016107043 A1 WO 2016107043A1
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Prior art keywords
pull
row
module
pixel unit
sub
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PCT/CN2015/078676
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English (en)
French (fr)
Inventor
永山和由
宋松
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京东方科技集团股份有限公司
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Priority to US14/894,002 priority Critical patent/US10056039B2/en
Publication of WO2016107043A1 publication Critical patent/WO2016107043A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • a gate driver In the existing array substrate Gate On Array (GOA), a gate driver is often designed on a circuit board of a non-display area on one side or both sides of an array substrate.
  • the prior art In packaging, the prior art often shields the circuit board with the frame of the display device to keep the appearance clean and beautiful. Therefore, under the traditional GOA design, the gate driver will occupy a certain frame width, which is not conducive to the narrowing of the frame of the display device.
  • the present invention provides an array substrate and a display device, which can alleviate or avoid the problem that the gate driver restricts the narrowing of the frame.
  • the present invention provides an array substrate comprising a plurality of pixel units arranged in an array and a plurality of shift register units corresponding to each row of pixel units, and the shift register unit corresponding to any row of pixel units comprises:
  • a row sharing module located outside the display area of the array substrate, the input end of the row sharing module is connected to the clock signal line and the gate signal line of the pixel unit of the previous row, and the pull-up control signal of the output end and the pixel unit of the row The line and the pull-down control signal line of the pixel unit of the line are connected;
  • An output pull-up module located in a display area of the array substrate, the output pull-up module being connected to the pull-up control signal line of the pixel unit of the row and a gate signal line of the pixel unit of the row;
  • An output pull-down module located within the display area of the array substrate, the output pull-down module being connected to the pull-down control signal line of the pixel unit of the row and the gate signal line of the pixel unit of the row.
  • the output pull-up module includes a plurality of pull-up sub-modules disposed in the pixel unit of the row, and each of the pull-up sub-modules and the pull-up control signal of the row of pixel units a line and a gate signal line of the pixel unit of the row are connected;
  • the output pull-down module includes a plurality of pull-down sub-modules disposed in the pixel unit of the row, each of the pull-down sub-blocks The modules are all connected to the pull-down control signal line of the pixel unit of the row and the gate signal line of the pixel unit of the row.
  • the corresponding column in which the pixel unit of the pull-up sub-module is disposed in any row of pixel units is also disposed in the pixel unit of the other row, and the pull-up sub-module is also disposed in any row of pixel units;
  • the corresponding column in which the pixel unit of the pull-down sub-module is located is also provided with the pull-down sub-module in the pixel unit of the other row.
  • the plurality of columns in which the pixel unit of the pull-up sub-module is disposed and the plurality of columns in which the pixel unit in which the pull-down sub-module is disposed are alternately and evenly distributed on the array substrate. Display area.
  • the plurality of columns in which the pixel unit of the pull-up sub-module is disposed and the plurality of columns in which the pixel unit in which the pull-down sub-module is disposed are distributed on a side of the array substrate or In multiple columns on both sides of the edge.
  • the pull-up sub-module and the pull-down sub-module are alternately disposed in a plurality of pixel units that are consecutive in position;
  • the upper row is provided with a plurality of columns in which the pixel units of the pull-up sub-module and the pull-down sub-module are located, and the pixel unit in which the pull-up sub-module and the pull-down sub-module are disposed in the next row
  • the plurality of columns are staggered to the left or to the right by a predetermined plurality of columns;
  • the first row of pixel units is provided with the column of the pixel unit of the pull-up sub-module or the pull-down sub-module starting from the first column; the last row of pixel units is provided with the pixel unit of the pull-up sub-module or the pull-down sub-module The column ends in the last column.
  • At least one of the pixel units of any row is a pixel unit provided with the pull-up sub-module, and at least one of the pixel units of any row is The pixel unit of the pull-down sub-module is provided.
  • the pull-up sub-module includes a pull-up transistor and a capacitor, and a gate of the pull-up transistor is connected to a pull-up control signal line of the row of pixel units, and one of a source and a drain
  • the gate signal lines of the pixel unit of the row are connected, and the other is connected to the first clock signal line of the clock signal line; one end of the capacitor is connected to the pull-up control signal line of the pixel unit of the row, and the other end is connected Connected to the gate signal line of the pixel unit of the row.
  • the pull-down sub-module includes a pull-down transistor, a gate of the pull-down transistor is connected to a pull-down control signal line of the pixel unit of the row, and one of the source and the drain is connected to a low-level line, and One is connected to the gate signal line of the pixel unit of the row.
  • the row sharing module includes a first transistor and a second transistor, wherein:
  • a gate of the first transistor is connected to a gate signal line of the pixel unit of the previous row, and one of the source and the drain is connected to a pull-up control signal line of the pixel unit of the row, and the other is connected to the upper a gate signal line of a row of pixel units is connected;
  • a gate of the second transistor is connected to a gate signal line of the pixel unit of the row, one of the source and the drain is connected to the low-level line, and the other is a pull-up control signal of the pixel unit of the row Line connected
  • a second clock signal line of the clock signal line is connected to a pull-down control signal line of the row of pixel units.
  • the present invention also provides a display device comprising any of the above array substrates.
  • the display device is a top emission type organic light emitting diode display device.
  • the present invention divides the shift register unit corresponding to each row of pixel units into three parts: a row sharing module, an output pull-up module, and an output pull-down module, and sets the row sharing module in the display area of the array substrate.
  • the output pull-up module and the output pull-down module are disposed within the display area of the array substrate, thereby facilitating the reduction of the area occupied by the gate driver on one or both sides of the array substrate on the circuit board, thereby enabling use
  • the frame that shields the circuit board is narrowed, that is, the present invention can solve the problem that the gate driver restricts the narrowing of the frame.
  • FIG. 1 is a schematic diagram showing the position and structure of a pixel unit and a shift register unit of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module in a special-shaped display area according to an embodiment of the present invention
  • FIG. 6 is a circuit structural diagram of a shift register unit in an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of the above shift register unit on an array substrate according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram showing the position and structure of a pixel unit and a shift register unit of an array substrate in an embodiment of the present invention.
  • the array substrate includes a plurality of pixel units (not all shown in FIG. 1) arranged in an array, for example, the area indicated by hatching in FIG. 1 is a pixel unit of the fourth row and the third column.
  • the area indicated by hatching in FIG. 1 is a pixel unit of the fourth row and the third column.
  • FIG. 1 only a conventional rectangular pixel unit array is taken as an example, and the outer edges of the plurality of pixel units arranged in an array in the array substrate may be other geometric shapes.
  • the array substrate further includes a plurality of shift register units corresponding to each row of pixel units, wherein the shift register unit corresponding to any row of pixel units includes a row sharing module outside the display area of the array substrate, and a display of the array substrate An output pull-down module within the display area of the output pull-up module and the array substrate within the area.
  • the actual circuit of the shift register unit may specifically adopt the structural design of the shift register circuit of any one of the gate drivers in the prior art, which is not limited by the present invention.
  • the electronic component for pulling up the potential of the gate signal line in the shift register circuit constitutes the output pull-up module
  • the electronic component for pulling down the potential of the gate signal line of the line constitutes the above The pull-down module is output, and the other components belong to the above-mentioned row sharing module.
  • the row sharing module needs to connect the gate signal line of the previous row to realize the function of the gate driver (of course, the cascading manner of other shift register units can also be adopted in a special design, such as cross Row cascading, which does not change the essence of the embodiment of the present invention, and the row sharing module may need to connect a signal (such as a clock signal) from the timing controller, and thus may need to be connected to a control signal line such as a clock signal line of an external circuit.
  • a signal such as a clock signal
  • the gate driver design in the prior art can be referred to, which is not limited by the present invention.
  • the above-mentioned output pull-up module generally includes a pull-up transistor (hereinafter referred to as TU).
  • the TFT, and the above output pull-down module generally includes a TFT which can be called a pull-down transistor (hereinafter referred to as TD).
  • the device size of the TU and TD in the shift register circuit of the gate driver is significantly larger than other TFTs (of course, The projection length of the area where the TFT is located in the row direction of the pixel unit is also significantly larger than other TFTs. Therefore, designing the output pull-up module including the TU and the output pull-down module including the TD in the display area of the array substrate can greatly reduce the length of the shift register unit in the row direction outside the display area, thereby facilitating the border. Narrowing.
  • the row sharing module X3 of the third row is located outside the display area of the array substrate (X1 to X5 in FIG. 1 respectively represent the row sharing modules of the first row to the fifth row), and the input terminal of the row sharing module X3 is The clock signal line CLK and the gate signal line G2 of the previous row are connected (the connection relationship is not shown in FIG. 1 for the sake of simplicity, and G1 to G5 in FIG. 1 respectively represent the gate signal lines of the first to fifth rows), and the output terminal is The pull-up control signal line C3A of the line and the pull-down control signal line C3B of the line are connected (C1A to C5A in Fig. 1 respectively indicate pull-up control signal lines of the first to fifth lines, and C1B to C5B in Fig. 1 respectively indicate Pull-down control signal lines from one line to the fifth line).
  • the output pull-up module is represented as a plurality of pull-up sub-modules connected in parallel with each other (for example, U1-1 to U5-1 respectively represent the first pull-up sub-modules of the first to fifth rows, U1-2 to U5-2 represents the second pull-up sub-module of the first row to the fifth row, respectively, and the output pull-down module is represented as a plurality of parallel pull-down sub-modules (for example, D1-1 to D5-1 respectively represent the first row to the first The first drop-down sub-module of the five rows, D1-2 to D5-2 respectively represent the second pull-down sub-module of the first row to the fifth row).
  • the output pull-up module and the output pull-down module of any row may have any structural composition and position distribution in the display area of the array substrate, but In order to achieve the loss
  • the pull-up module and the output pull-down module pull up and pull down the potential of the gate signal line, and the output pull-up module of any row can be connected with the above-mentioned pull-up control signal line of the line and the gate signal line of the line;
  • the output pull-down module can be connected to the above-mentioned pull-down control signal line of the line and the gate signal line of the line.
  • the pull-up sub-modules U3-1 and U3-2 of the third row in FIG. 1 are both connected to the pull-up control signal line C3A of the row, and the pull-down sub-modules D3-1 and D3-2 of the third row are both The pull-down control signal line C3B of the row is connected.
  • the shift register unit corresponding to one row of pixel units is divided into three parts: a row sharing module, an output pull-up module, and an output pull-down module, and the row sharing module is disposed outside the display area of the array substrate.
  • the output pull-up module and the output pull-down module are disposed within the display area of the array substrate, thereby facilitating the reduction of the area occupied by the gate driver on one side or both sides of the array substrate on the circuit board, thereby enabling shielding
  • the frame of the circuit board is narrowed, that is, the embodiment of the present invention can solve the problem that the gate driver restricts the narrowing of the frame.
  • the embodiment of the present invention can make the length of the shift register unit in the row direction outside the display area greatly reduced, thereby further Conducive to the narrowing of the border.
  • the large-sized output pull-up/pull-down module can also be divided as shown in FIG. Multiple small-sized pull-up/pull-down submodules, namely:
  • the output pull-up module includes a plurality of pull-up sub-modules disposed in the pixel unit of the row, and each of the pull-up sub-modules is connected to the pull-up control signal line of the row and the gate signal line of the row;
  • the output pull-down module includes a plurality of pull-down sub-modules disposed in the pixel unit of the row, and each of the pull-down sub-modules is connected to the pull-down control signal line of the row and the gate signal line of the row.
  • the output pull-up module includes a plurality of pull-up sub-modules disposed in the pixel unit of the row, such as U4- 1, U4-2, of course, the number of pull-up sub-modules can also be other positive integers greater than 2; the output pull-down module includes a plurality of pull-down sub-modules set in the pixel unit of the row, such as D4-1, D4 -2, of course, the number of drop-down submodules can also be other than A positive integer of 2.
  • the pull-up sub-module U4-1 is connected to the pull-up control signal line C4A of the line and the gate signal line G4 of the current line, and the other pull-up sub-modules of the line are also connected to the pull-up control signal line C4A and the gate signal line G4.
  • the following pull submodule D4-1 is connected to the pull-down control signal line C4B of the line and the gate signal line G4 of the current line, and the other pull-down sub-modules of the line are also connected to the pull-down control signal line C4B and the gate signal line G4. .
  • the design makes the entire output pull-up module equivalent to a plurality of pull-up sub-modules connected in parallel with each other, thus pulling up the gate signal line
  • the function of the upper potential can be implemented by a plurality of pull-up sub-modules.
  • the large-sized pull-up transistor TU can be divided into a plurality of small-sized sub-up pull-up transistors TUx connected in parallel, so that a plurality of TUx are pulled up control signals.
  • the pull-up of the potential on the gate signal line is jointly performed under the control, so that the requirement of the pull-up speed of the gate signal line potential is ensured by adjusting the size and number of the TUx. Moreover, since the circuit structure of a larger size is disposed in a single pixel unit and the circuit structure of a smaller size is set in the plurality of pixel units, the output pull-up module and the output pull-down module are reduced to the pixel unit.
  • the effect of the aperture ratio is beneficial to improve the brightness uniformity of a plurality of pixel units throughout the display area.
  • the specific number and design size can be designed according to the amplitude and timing of the actual desired gate signal.
  • different positions and sizes of the pull-up sub-module and the pull-down sub-module and different application scenarios can also be arranged in different ways. More specifically, an alternative arrangement of several pull-up sub-modules and pull-down sub-modules will be described below with reference to the accompanying drawings.
  • FIG. 2 illustrates an alternative arrangement of a pull-up sub-module and a pull-down sub-module in one embodiment of the present invention.
  • a row of pixel units corresponding to a row sharing module such as X1 to X5 disposed outside the display area
  • pixel units Ux provided with a pull-up sub-module (for example, set in FIG. 1) U1-1, the pixel unit of U3-2) and the pixel unit Dx provided with the pull-down sub-module (for example, the pixel unit in which D2-2 and D5-1 are provided in FIG. 1).
  • the plurality of columns in which the pixel unit Ux having the pull-up sub-module is located and the plurality of columns in which the pixel unit Dx provided with the pull-down sub-module are located are distributed in a plurality of columns near one side or both side edges of the array substrate.
  • the pull-up sub-module and the pull-down sub-module are both disposed on one side or both sides of the row sharing module near the array substrate, so the above-mentioned pull-up control signal line and the pull-down control signal line do not need to run through the entire line, and only Set at the edge of the array substrate (can be reduced Set the length). Therefore, the solution saves material and layout space in the middle of the display area. More importantly, since the above Ux and Dx are disposed only at the edge position of the display area, the above-described adverse effect may not be caused to the aperture ratio of the pixel unit in the middle portion of the display area.
  • the setting scheme is suitable.
  • FIG. 3 illustrates an alternative arrangement of another pull-up sub-module and pull-down sub-module in one embodiment of the present invention. Consistent with the reference numerals of FIG. 2, in the arrangement shown in FIG. 3, a plurality of columns in which the pixel unit Ux of the pull-up sub-module is disposed and a plurality of columns in which the pixel unit Dx in which the pull-down sub-module is disposed are alternately arranged The ground is evenly distributed in the display area of the array substrate. Of course, in FIG. 3, only two columns are alternately arranged, and other uniform arrangement schemes can be obtained by referring to the setting manner.
  • the advantage of using the above uniform arrangement is that although the aperture ratio of a part of the columns in the display area may be lower than other columns, as long as the columns with lower aperture ratios are evenly distributed in the display area, the overall display effect is not obtained. It has a great influence (sufficiently sparse, and the difference in aperture ratio is small enough for the human eye to observe), that is, the human eye does not feel the difference between these columns and the surrounding columns as much as possible, and the problem of reducing the above-mentioned aperture ratio is reduced in the display area.
  • the effect of brightness uniformity For the usage scenario where the brightness and brightness uniformity in the display area are required to be high, the setting scheme is suitable.
  • the corresponding column in which the pixel unit Ux of the pull-up sub-module is disposed in any row is also provided with the pull-up sub-module in the pixel unit of the other row;
  • the corresponding column in which the pixel unit Dx of the above-mentioned pull-down sub-module is located in any row is also provided with the above-mentioned pull-down sub-module in the pixel unit of the other row, that is, the above Ux and Dx are all set in columns.
  • Ux and Dx may also be arranged not in columns.
  • it may also be promoted as a point-like uniform setting scheme in the entire rectangular display area to obtain better brightness and brightness. Uniformity.
  • Figure 4 shows an alternative arrangement of another pull-up sub-module and drop-down sub-module that is not arranged in columns. Consistent with the reference numerals of Figures 2 and 3, in Figure 4, the pull-up in any row The module and the pull-down sub-module are alternately disposed in a plurality of pixel units that are consecutive in position. Moreover, in the two adjacent rows, the upper row is provided with a plurality of columns in which the pixel units Ux and Dx of the pull-up sub-module and the pull-down sub-module are located, and the pixel unit Ux having the pull-up sub-module and the pull-down sub-module is disposed on the next row.
  • the plurality of columns in which Dx is located are shifted to the left or to the right by a predetermined plurality of columns (in FIG. 4, a staggered column is taken as an example).
  • the first row is provided with the column of the pixel unit Ux or Dx of the pull-up sub-module or the pull-down sub-module starting from the first column;
  • the last row is provided with the pixel unit Ux of the pull-up sub-module or the pull-down sub-module Or the column where Dx is located ends in the last column, that is, the entire Ux and Dx setting area covers a diagonal line of the display area.
  • This setting makes the two rows alternately arranged, which helps to improve the uniformity of the brightness of the display area.
  • the pull-up sub-module and the pull-down sub-module are set in a large number, it is suitable to apply the setting scheme.
  • any one of the above setting manners may be applied.
  • the number of pixel units per row and column may be inconsistent, and thus, for this case, It is also necessary to meet certain conditions when setting: at least one pixel unit of any row of pixel units is a pixel unit provided with the above-mentioned pull-up sub-module, and at least one pixel unit of any row of pixel units is provided with the above-mentioned pull-down sub-module Pixel unit. That is, in order to guarantee the integrity of any one row of shift register units, at least one pull-up sub-module and one pull-down sub-module are provided in any row.
  • the shape of the display area 51 is substantially "concave", and the circuit board 52 on which the data driver is located is disposed on one side (the lower side in the drawing) of the display area 51.
  • the above-mentioned row sharing module Xt (which may include X1 to X5 as shown in FIG. 1) should be disposed on the other side or both sides of the display area 51 (the left and right sides are taken as an example in FIG. 5).
  • At least one column Ux and one column Dx can cover all the rows in the display area.
  • the above Ux and the above Dx are set in FIG. 5 in two shaded areas in FIG. 5 which can cover all the lines of the display area 51.
  • the plurality of pull-up modules or the plurality of pull-down modules may be modules having the same structure and size specifications, or modules having different structures or sizes.
  • the plurality of pull-up modules or the plurality of pull-down modules may be modules having the same structure and size specifications.
  • a specific shift register unit circuit that can be applied to the present invention
  • the structure can adopt various circuit structures well known to those skilled in the art, and the present invention does not limit the circuit structure of the specific shift register unit.
  • the specific relationship between the line sharing module, the pull-up module, and the pull-down module may be different from the previous embodiment.
  • FIG. 6 is a circuit configuration diagram of a shift register unit in another embodiment of the present invention.
  • the clock signal line CLK includes a first clock signal line CLK_A and a second clock signal line CLK_B whose phases of the signals differ by a half cycle, specifically, for the nth line shift Register unit (n is a positive integer):
  • the pull-up sub-module includes a pull-up transistor TU and a capacitor C1, and the gate of the pull-up transistor TU is connected to the pull-up control signal line of the current row (indicated by a node CA in FIG. 6), in the source and the drain.
  • One is connected to the gate signal line Gn of the above-mentioned row, and the other is connected to the first clock signal line CLK_A of the clock signal line; one end of the capacitor is connected to the pull-up control signal line (node CA) of the above-mentioned row, The other end is connected to the gate signal line Gn of the above-mentioned row.
  • the above structure can cause the pull-up transistor TU to pull up the potential on the gate signal line Gn under the control of the voltage signal on the pull-up control signal line (at the node CA).
  • other circuit configurations can be used to achieve this.
  • the pull-down sub-module includes a pull-down transistor TD, a gate of the pull-down transistor TD and a pull-down control signal line of the current row (in this embodiment, a signal provided by the second clock signal line CLK_B of the clock signal line may be used as
  • the pull-down control signal is thus connected to the pull-down control signal line by CLK_B, one of the source and the drain is connected to the low-level line Vss, and the other is connected to the gate signal line Gn of the above-mentioned row.
  • the above structure can cause the pull-down transistor TD to pull down the potential on the gate signal line Gn under the control of the voltage signal on the pull-down control signal line (here specifically, the second clock signal line CLK_B).
  • the second clock signal line CLK_B the second clock signal line
  • the row sharing module includes a first transistor T1 and a second transistor T2, wherein: a gate of the first transistor T1 is connected to a gate signal line Gn-1 of the upper row, and one of a source and a drain is connected to the above
  • the pull-up control signal line (node CA) is connected, the other is connected to the gate signal line Gn-1 of the previous row (diode connection mode);
  • the gate of the second transistor T2 is connected to the gate signal line Gn of the above-mentioned row (Thus, in this embodiment, the second transistor T2) can be controlled by the gate signal supplied from the gate signal line Gn of the row, one of the source and the drain is connected to the low-level line Vss, and the other Connected to the pull-up control signal line (node CA) of the above line; the second clock signal in the above clock signal line
  • the line CLK_B serves as the pull-down control signal line of the line.
  • the row sharing module under the circuit structure can provide a pull-up control signal by pulling up the sub-module through the pull-up control signal line according to the voltage signal on the gate signal line Gn-1 of the previous row and the signal on the clock signal line, and is controlled by pull-down.
  • the signal line provides a pull-down control signal to the pull-down sub-module.
  • other circuit configurations can be used to achieve this.
  • any one of the above transistors may be an N-type thin film transistor or a P-type thin film transistor TFT.
  • the method of connecting the drain and the source of any one of the TFTs is determined according to whether the TFT is N-type or P-type: if it is an N-type TFT, the upper end of the TFT in the figure is the drain and the lower end is the source; if it is the P For a TFT, the upper end of the TFT is the source and the lower end is the drain.
  • circuit structure shown in FIG. 6 is only an example of the circuit structure of a shift register unit, and the specific circuit timing and operation principle are well understood by those skilled in the art, and are not described herein again.
  • the shift register unit of the nth row includes a row sharing unit Xn located outside the display area 51 of the array substrate and a plurality of the above-described pull-up sub-modules (including the above-described pull-up transistor TU and The capacitor C1) and a plurality of pull-down sub-modules (including the pull-down transistor TD) located within the display area 51.
  • the gate of the pull-up transistor TU in each pull-up sub-module is connected to the pull-up control signal line CnA of the current line, and one of the source and the drain is connected to the gate signal line Gn of the current row.
  • the other is connected to the first clock signal line CLK_A in the clock signal line (it can be taken out by Xn described above, or can be taken out from other circuit modules, not shown in FIG. 7).
  • one end of the capacitor C1 is connected to the pull-up control signal line CnA of the current line, and the other end is connected to the gate signal line Gn of the current line.
  • FIG. 7 is only a schematic diagram of the structure of the above shift register unit disposed on the array substrate. The manner of setting the pull-up sub-module and the pull-down sub-module can be specifically referred to the above embodiments.
  • the length of the pull-up transistor TU in the row direction is on the order of 1000 micrometers
  • the length of the pull-down transistor TD in the row direction is 1000 micrometers.
  • the magnitude of the other TFTs in the row direction is on the order of 10 or 100 microns. It can be seen that the embodiment of the present invention
  • the larger pull-up transistor TU and the pull-down transistor TD are disposed in the display area of the array substrate, so that the length of the circuit structure located outside the display area in the row direction is greatly reduced (from the original 1000 micron level to 10).
  • the example can effectively solve the problem that the gate driver restricts the narrowing of the frame.
  • an embodiment of the present invention provides a display device including any of the above array substrates.
  • the display device can be: various GOA-designed display panels, electronic paper, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, and the like, or any display product or component.
  • any of the above array substrates is particularly suitable for a top emission type organic light emitting diode display device, because in the display device, the TFTs disposed on the array substrate are located below the light emitting region, thereby outputting the pull-up module and the output pull-down module. It does not affect the aperture ratio of the pixel unit, and thus does not require a special design for the arrangement of the pull-up or pull-down sub-modules.
  • any of the above display devices includes any of the above array substrates, the technical features, the technical problems solved, and the technical effects that can be achieved are corresponding, and thus the present embodiment is not described in detail herein. .
  • an array substrate and a display device divide a shift register unit corresponding to a row of pixel units into three parts: a row sharing module, an output pull-up module, and an output pull-down module, and
  • the row sharing module is disposed outside the display area of the array substrate, and the output pull-up module and the output pull-down module are disposed within the display area of the array substrate, thereby facilitating the gate driver on one side or both sides of the array substrate in the circuit
  • the area occupied by the board is reduced, so that the frame for shielding the circuit board can be narrowed, that is, the present invention can solve the problem that the gate driver restricts the narrowing of the frame.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • a fixed connection a detachable connection, or an integral connection
  • it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.

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Abstract

一种阵列基板和显示装置，该阵列基板包括阵列设置的多个像素单元以及每个对应一行像素单元的多个移位寄存器单元，与任一行像素单元对应的移位寄存器单元包括：位于所述阵列基板的显示区之外的行共用模块（X1—X5），所述行共用模块（X1—X5）的输入端与时钟信号线（CLK）以及上一行的栅信号线（G1—G5）相连，输出端与本行的上拉控制信号线（C1A—C5A）以及本行的下拉控制信号线相连（C1B—C5B）；位于所述阵列基板的显示区之内的输出上拉模块（U1-1—U5-1），所述输出上拉模块（U1-1—U5-1）与本行的所述上拉控制信号线（C1A—C5A）以及本行的栅信号线（G1—G5）相连；位于所述阵列基板的显示区之内的输出下拉模块（D1-2—D5-2），所述输出下拉模块（D1-2—D5-2）与本行的所述下拉控制信号线（C1B—C5B）以及本行的栅信号线相连（G1—G5）。其可以解决栅极驱动器制约边框窄化的问题。

Description

阵列基板和显示装置 技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板和显示装置。
背景技术
现有的阵列基板行驱动技术(Gate On Array，GOA)中，栅极驱动器(Gate Driver)常被设计在阵列基板一侧或两侧的非显示区的电路板上。在封装时，现有技术常利用显示装置的边框对该电路板进行遮蔽，以保持外观上的整洁和美观。因此，在传统的GOA设计下，栅极驱动器会占据一定的边框宽度，不利于显示装置边框的窄化。
发明内容
针对现有技术中的缺陷，本发明提供一种阵列基板和显示装置，可以减轻或避免栅极驱动器制约边框窄化的问题。
第一方面，本发明提供了一种阵列基板，包括阵列设置的多个像素单元以及每个对应一行像素单元的多个移位寄存器单元，与任一行像素单元对应的移位寄存器单元包括：
位于所述阵列基板的显示区之外的行共用模块，所述行共用模块的输入端与时钟信号线以及上一行像素单元的栅信号线相连，输出端与本行像素单元的上拉控制信号线以及本行像素单元的下拉控制信号线相连；
位于所述阵列基板的显示区之内的输出上拉模块，所述输出上拉模块与本行像素单元的所述上拉控制信号线以及本行像素单元的栅信号线相连；
位于所述阵列基板的显示区之内的输出下拉模块，所述输出下拉模块与本行像素单元的所述下拉控制信号线以及本行像素单元的栅信号线相连。
可选地，所述输出上拉模块包括多个设置在本行的所述像素单元中的上拉子模块，每一所述上拉子模块均与本行像素单元的所述上拉控制信号线以及本行像素单元的栅信号线相连；所述输出下拉模块包括多个设置在本行的所述像素单元中的下拉子模块，每一所述下拉子 模块均与本行像素单元的所述下拉控制信号线以及本行像素单元的栅信号线相连。
可选地，任一行像素单元中设置有所述上拉子模块的像素单元所在的对应列在其他行的像素单元中也设置有所述上拉子模块；任一行像素单元中设置有所述下拉子模块的像素单元所在的对应列在其他行的像素单元中也设置有所述下拉子模块。
可选地，所述设置有所述上拉子模块的像素单元所在的多个列以及所述设置有所述下拉子模块的像素单元所在的多个列交替地均匀分布在所述阵列基板的显示区内。
可选地，所述设置有所述上拉子模块的像素单元所在的多个列以及所述设置有所述下拉子模块的像素单元所在的多个列分布于靠近所述阵列基板一侧或者两侧边缘的多个列中。
可选地，任一行像素单元中，所述上拉子模块与所述下拉子模块交替地设置在位置连续的多个像素单元中；
相邻的两行像素单元中，上一行设置有所述上拉子模块和下拉子模块的像素单元所在的多个列相对于下一行设置有所述上拉子模块和下拉子模块的像素单元所在的多个列向左或向右错开预定多列的位置；
第一行像素单元设置有所述上拉子模块或下拉子模块的像素单元所在的列从第一列开始；最后一行像素单元设置有所述上拉子模块或下拉子模块的像素单元所在的列结束于最后一列。
可选地，在所述阵列基板的显示区形状不规则时，任一行的像素单元中至少有一个是设置有所述上拉子模块的像素单元，且任一行的像素单元中至少有一个是设置有所述下拉子模块的像素单元。
可选地，所述上拉子模块包括上拉晶体管和电容，所述上拉晶体管的栅极与所述本行像素单元的上拉控制信号线相连，源极与漏极中的一个与所述本行像素单元的栅信号线相连，另一个与所述时钟信号线中的第一时钟信号线相连；所述电容的一端与所述本行像素单元的上拉控制信号线相连，另一端与所述本行像素单元的栅信号线相连。
可选地，所述下拉子模块包括下拉晶体管，所述下拉晶体管的栅极与所述本行像素单元的下拉控制信号线相连，源极与漏极中的一个与低电平线相连，另一个与所述本行像素单元的栅信号线相连。
可选地，所述行共用模块包括第一晶体管与第二晶体管，其中：
所述第一晶体管的栅极与所述上一行像素单元的栅信号线相连，源极与漏极中的一个与所述本行像素单元的上拉控制信号线相连，另一个与所述上一行像素单元的栅信号线相连；
所述第二晶体管的栅极与所述本行像素单元的栅信号线相连，源极与漏极中的一个与低电平线相连，另一个与所述本行像素单元的上拉控制信号线相连；
所述时钟信号线中的第二时钟信号线与所述本行像素单元的下拉控制信号线相连。
第二方面，本发明还提供了一种显示装置，该显示装置包括上述任意一种阵列基板。
可选地，所述显示装置为顶发射式有机发光二极管显示装置。
由上述技术方案可知，本发明将与每一行像素单元对应的移位寄存器单元分成了行共用模块、输出上拉模块和输出下拉模块三部分，并将行共用模块设置在阵列基板的显示区之外，将输出上拉模块和输出下拉模块设置在阵列基板的显示区之内，因而有利于位于阵列基板一侧或两侧的栅极驱动器在电路板上占用的面积的缩小，从而可以使得用于遮蔽该电路板的边框窄化，即本发明可以解决栅极驱动器制约边框窄化的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单的介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一个实施例中一种阵列基板的像素单元以及移位寄存器单元的位置和结构示意图；
图2是本发明一个实施例中一种上拉子模块与下拉子模块的可选设置方式示意图；
图3是本发明一个实施例中一种上拉子模块与下拉子模块的可选设置方式示意图；
图4是本发明一个实施例中一种上拉子模块与下拉子模块的可选设置方式示意图；
图5是本发明一个实施例中一种异形显示区中上拉子模块与下拉子模块的可选设置方式示意图；
图6是本发明一个实施例中一种移位寄存器单元的电路结构图；
图7是本发明一个实施例中一种阵列基板上的上述移位寄存器单元结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是本发明一个实施例中一种阵列基板的像素单元以及移位寄存器单元的位置和结构示意图。
参见图1，该阵列基板中包括多个按阵列设置的多个像素单元(图1中未全部示出)，例如图1中以阴影表示的区域为第四行第三列的像素单元。图1中仅以传统的矩形像素单元阵列为示例，上述阵列基板中按阵列设置的多个像素单元的外边缘还可以是其他的几何形状。
上述阵列基板还包括每个对应一行像素单元的多个移位寄存器单元，其中，与任一行像素单元对应的移位寄存器单元包括位于阵列基板的显示区之外的行共用模块、阵列基板的显示区之内的输出上拉模块和阵列基板的显示区之内的输出下拉模块。其中，移位寄存器单元的实际电路具体可以采用现有技术中的任意一种栅极驱动器的移位寄存器电路的结构设计，本发明对此不做限定。在本发明的一个实施例中，上述移位寄存器电路中用于拉高本行栅信号线电位的电子元器件组成上述输出上拉模块，用于拉低本行栅信号线电位的电子元器件组成上述输出下拉模块，而其他组成部分则均属于上述行共用模块。当然，行共用模块需要连接上一行的栅信号线以实现栅极驱动器的功能(当然特殊设计下也可以采用其他移位寄存器单元的级联方式，如跨 行级联，其不改变本发明实施例的实质)，且行共用模块可能需要连接来自时序控制器的信号(如时钟信号)，因此可能需要与外部电路的时钟信号线一类的控制信号线相连，具体的外部连接结构均可以参照现有技术中的栅极驱动器设计，本发明对此不做限定。
这里，由于可采用两种薄膜晶体管TFT(Thin Film Transistor)分别进行栅信号线的电位的上拉和下拉，因此上述输出上拉模块一般都会包括一可称为上拉晶体管(下文以TU表示)的TFT，而上述输出下拉模块一般都会包括一可称为下拉晶体管(下文以TD表示)的TFT。具体地，由于栅极驱动器常对栅信号线上电位的上拉速度和下拉速度要求很高，因此栅极驱动器的移位寄存器电路中TU与TD的器件尺寸会显著地大于其他TFT(当然其TFT所在区域在像素单元的行方向上的投影长度也会显著大于其他TFT)。因此，将包括TU的输出上拉模块与包括TD的输出下拉模块设计在阵列基板的显示区中，可以使得移位寄存器单元在显示区外部的行方向上所占长度大大减少，因而更加有利于边框的窄化。
下面以第3行为例说明移位寄存器单元的具体结构：
参见图1，第三行的行共用模块X3位于上述阵列基板的显示区之外(图1中X1至X5分别表示第一行至第五行的行共用模块)，且行共用模块X3的输入端与时钟信号线CLK以及上一行的栅信号线G2相连(简洁起见部分连接关系未在图1中示出，图1中G1至G5分别表示第一行至第五行的栅信号线)，输出端与本行的上拉控制信号线C3A以及本行的下拉控制信号线C3B相连(图1中C1A至C5A分别表示第一行至第五行的上拉控制信号线、图1中C1B至C5B分别表示第一行至第五行的下拉控制信号线)。
图1中，输出上拉模块被表示为多个相互并联的上拉子模块(比如U1-1至U5-1分别表示第一行至第五行的第一个上拉子模块，U1-2至U5-2分别表示第一行至第五行的第二个上拉子模块)，输出下拉模块被表示为多个并联的下拉子模块(比如D1-1至D5-1分别表示第一行至第五行的第一个下拉子模块，D1-2至D5-2分别表示第一行至第五行的第二个下拉子模块)。当然，图1所示的输出上拉模块和输出下拉模块只是一种示例，任一行的输出上拉模块和输出下拉模块在阵列基板的显示区内均可以有任意的结构组成和位置分布，但是为了实现输 出上拉模块与输出下拉模块上拉与下拉栅信号线的电位的功能，任一行的输出上拉模块可与本行的上述上拉控制信号线以及本行的栅信号线相连；任一行的输出下拉模块可与本行的上述下拉控制信号线以及本行的栅信号线相连。例如，图1中第三行的上拉子模块U3-1与U3-2均与本行的上拉控制信号线C3A相连，第三行的下拉子模块D3-1与D3-2均与本行的下拉控制信号线C3B相连。
由此可见，本发明实施例将与一行像素单元对应的移位寄存器单元分成了行共用模块、输出上拉模块和输出下拉模块三部分并将行共用模块设置在阵列基板的显示区之外，将输出上拉模块和输出下拉模块设置在阵列基板的显示区之内，因而有利于位于阵列基板一侧或两侧的栅极驱动器在电路板上占用的面积的缩小，从而可以使得用于遮蔽该电路板的边框窄化，即本发明实施例可以解决栅极驱动器制约边框窄化的问题。
进一步地，在输出上拉模块包括上述上拉晶体管TU、输出下拉模块包括下拉晶体管TD时，本发明实施例可以使得移位寄存器单元在显示区外部的行方向上所占长度大大减少，因而更加有利于边框的窄化。
然而，在上述实施例中，若将较大尺寸的输出上拉模块和/或输出下拉模块设置在单个像素单元中，则会不可避免地降低该像素单元的开口率，甚至有可能影响正常的显示功能。因此，为了尽量减小对开口率的影响，除了可以使输出上拉模块与输出下拉模块设置在不同的像素单元中，还可以如图1所示将大尺寸的输出上拉/下拉模块分为多个小尺寸的上拉/下拉子模块，即：
上述输出上拉模块包括多个设置在本行的上述像素单元中的上拉子模块，每一上述上拉子模块均与本行的上述上拉控制信号线以及本行的栅信号线相连；上述输出下拉模块包括多个设置在本行的上述像素单元中的下拉子模块，每一上述下拉子模块均与本行的上述下拉控制信号线以及本行的栅信号线相连。
例如，如图1中的第四行所示，与该行像素单元对应的移位寄存器单元中，输出上拉模块包括多个设置在本行的像素单元中的上拉子模块，如U4-1、U4-2所示，当然上拉子模块的数量还可以是其他大于2的正整数；输出下拉模块包括多个设置在本行的像素单元中的下拉子模块，如D4-1、D4-2所示，当然下拉子模块的数量也可以是其他大于 2的正整数。如上拉子模块U4-1与本行的上拉控制信号线C4A和本行的栅信号线G4相连一样，本行的其他上拉子模块也均与上拉控制信号线C4A和栅信号线G4相连；如下拉子模块D4-1与本行的下拉控制信号线C4B和本行的栅信号线G4相连一样，本行的其他下拉子模块也均与下拉控制信号线C4B和栅信号线G4相连。
由此，以输出上拉模块为例(对于输出下拉模块而言是类似的)，该设计使得整个输出上拉模块相当于由多个相互并联的上拉子模块组成，因而上拉栅信号线上电位的功能可以由多个上拉子模块共同实现。例如，在输出上拉子模块包括上述上拉晶体管TU时，可以将大尺寸的上拉晶体管TU分为多个相互并联的小尺寸的子上拉晶体管TUx，使得多个TUx在上拉控制信号的控制下共同进行栅信号线上电位的上拉，因而通过调整TUx的尺寸和数量保障对栅信号线电位的上拉速度的要求。而且，由于避免了在单一像素单元中设置较大尺寸的电路结构而改为在多个像素单元中设置较小尺寸的电路结构，因而减小了上述输出上拉模块和输出下拉模块对像素单元的开口率的影响，并有利于提升整个显示区内多个像素单元的亮度均匀性。
当然，对于上述多个上拉子模块与多个下拉子模块，其具体数量与设计尺寸可以根据实际所需栅信号的幅值和时序来进行设计。而且，对于不同数量和尺寸的上拉子模块和下拉子模块以及不同的应用场景，也可以采用不同的方式来进行其位置的排布。更具体地，下面将结合附图介绍几种上拉子模块与下拉子模块的可选设置方式。
图2示出了本发明一个实施例中一种上拉子模块与下拉子模块的可选设置方式。参见图2，在与设置在显示区之外的行共用模块(如X1至X5)相对应的一行像素单元中，有多个设置有上拉子模块的像素单元Ux(例如图1中设置有U1-1、U3-2的像素单元)和设置有下拉子模块的像素单元Dx(例如图1中设置有D2-2、D5-1的像素单元)。而且，设置有上拉子模块的像素单元Ux所在的多个列以及设置有下拉子模块的像素单元Dx所在的多个列分布于靠近阵列基板一侧或者两侧边缘的多个列中。
该设置方案下，上拉子模块与下拉子模块均靠近阵列基板设置有行共用模块的一侧或两侧，因而上述上拉控制信号线与下拉控制信号线不需要贯穿整行，而只需在阵列基板的边缘处设置即可(可以减小 设置长度)。因此，本方案节省了材料和显示区中部的布局空间。更重要的是，由于上述Ux与Dx只设置在显示区的边缘位置，因而可以不对显示区中间部分的像素单元的开口率造成上述不利影响。对于上拉子模块和下拉子模块设置数量较少(远小于一行中像素单元的数量)、对显示区边缘的显示效果要求不高的使用场景下，适于应用该设置方案。
图3示出了本发明一个实施例中另一种上拉子模块与下拉子模块的可选设置方式。与图2的附图标记一致，图3所示的设置方案中，设置有上拉子模块的像素单元Ux所在的多个列以及设置有上述下拉子模块的像素单元Dx所在的多个列交替地均匀分布在阵列基板的显示区内。当然，图3中仅以交替地间隔两列为例，参照该设置方式还可以得到其他的均匀设置方案。
采用上述均匀设置方案的好处在于，虽然显示区中一部分列的开口率较其他列可能会偏低，然而只要这些开口率较低的列均匀分布在显示区中，就不会对总体的显示效果造成很大影响(足够稀疏、开口率差别足够小时人眼很难观察到)，即尽可能地使人眼感受不到这些列与周围列的不同，降低上述开口率下降的问题对显示区内亮度均匀性的影响。对于显示区内亮度和亮度均匀性均要求较高的使用场景，适于应用该设置方案。
另一方面，图2与图3所示的设置方案中，任一行中设置有上述上拉子模块的像素单元Ux所在的对应列在其他行的像素单元中也设置有上述上拉子模块；任一行中设置有上述下拉子模块的像素单元Dx所在的对应列在其他行的像素单元中也设置有上述下拉子模块，即上述Ux、Dx均是按列设置的。这样设置的好处在于，由于Ux、Dx按列集中设置(Ux、Dx所在的列是已知的)，因而可以很容易地通过外部手段来对这些列较低的开口率进行校正，例如通过调整Γ(gamma)校正参考电压来进行上述校正。
当然，上述Ux与Dx也可以不按列设置，例如根据图2所示的线状均匀设置方案还可以推广为在整个矩形显示区内的点状均匀设置方案，以得到更佳的亮度和亮度均匀性。
图4示出了不按列设置的另一种上拉子模块与下拉子模块的可选设置方式。与图2与图3的附图标记一致，图4中，任一行中上拉子 模块与下拉子模块均交替地设置在位置连续的多个像素单元中。而且，相邻的两行中，上一行设置有上拉子模块和下拉子模块的像素单元Ux和Dx所在的多个列相对于下一行设置有上拉子模块和下拉子模块的像素单元Ux和Dx所在的多个列向左或向右错开预定多列的位置(图4中以错开一列为例)。在一个实施例中，第一行设置有上拉子模块或下拉子模块的像素单元Ux或Dx所在的列从第一列开始；最后一行设置有上拉子模块或下拉子模块的像素单元Ux或Dx所在的列结束于最后一列，即整个Ux与Dx的设置区域覆盖显示区的一条对角线。该设置方式使两行交替排列，有助于提升显示区亮度的均匀性。对于上拉子模块和下拉子模块设置数量较多的使用场景，适于应用该设置方案。
可见，对于常规的矩形显示区，可以应用上述任意一种设置方式，但对于阵列基板的显示区形状不规则的情形，每行每列的像素单元个数可能会不一致，因而针对这种情形，还需要在设置时满足一定条件：任一行的像素单元中至少有一个像素单元是设置有上述上拉子模块的像素单元，任一行的像素单元中至少有一个像素单元是设置有上述下拉子模块的像素单元。即，为了保障任意一行移位寄存器单元的完整性，任意一行都要至少设置有一个上拉子模块和一个下拉子模块。
举例来说，参见图5所示出的异形显示区中上拉子模块与下拉子模块的可选设置方式。图5中，显示区51的形状呈大致的“凹”形，而数据驱动器所在的电路板52设置在显示区51的一侧(图中的下侧)。那么按照上述技术方案，上述行共用模块Xt(可以包括如图1中所示的X1至X5)应设置在显示区51的另外一侧或两侧(图5中以左右两侧为例)。而为了保障移位寄存器单元的完整性，按照上述Ux、Dx按列设置的方式设置Ux和Dx时，至少要使一列Ux和一列Dx可以覆盖显示区所有行。例如图5中将上述Ux和上述Dx设置在图5中的两个可以覆盖显示区51所有行的阴影区域中。
在上述各实施例中，所述多个上拉模块或所述多个下拉模块可以是具有相同结构和尺寸规格的模块，也可以是具有不同结构或尺寸规格的模块。但是一般来说为了尽可能地提高亮度均一性、简化工艺，可以使所述多个上拉模块或所述多个下拉模块均是具有相同结构和尺寸规格的模块。
应当理解的是，可以应用于本发明的具体的移位寄存器单元电路 结构可以采用本领域技术人员熟知的各种电路结构，本发明对具体的移位寄存器单元电路结构并不作限定。但是，对于某些具体的移位寄存器单元电路结构，为了简化电路结构，其体现出的行共用模块、上拉模块以及下拉模块之间的具体关系可能与之前的实施例有所不同。
例如，图6是本发明的另一实施例中一种移位寄存器单元的电路结构图。图6所示的移位寄存器单元电路中，上述时钟信号线CLK包括其信号的相位相差半个周期的第一时钟信号线CLK_A和第二时钟信号线CLK_B，具体地，对于第n行移位寄存器单元(n为正整数)：
上述上拉子模块包括上拉晶体管TU和电容C1，上述上拉晶体管TU的栅极与上述本行的上拉控制信号线(在图6中以节点CA表示)相连，源极与漏极中的一个与上述本行的栅信号线Gn相连，另一个与上述时钟信号线中的第一时钟信号线CLK_A相连；上述电容的一端与上述本行的上拉控制信号线(节点CA)相连，另一端与上述本行的栅信号线Gn相连。上述结构可以使上拉晶体管TU在上拉控制信号线上(节点CA处)的电压信号的控制下上拉栅信号线Gn上的电位。当然，为实现这一功能还可以采用其他的电路结构。
上述下拉子模块包括下拉晶体管TD，上述下拉晶体管TD的栅极与上述本行的下拉控制信号线(在该实施例中，可以采用上述时钟信号线中的第二时钟信号线CLK_B提供的信号作为下拉控制信号，因此以CLK_B来表示下拉控制信号线)相连，源极与漏极中的一个与低电平线Vss相连，另一个与上述本行的栅信号线Gn相连。上述结构可以使下拉晶体管TD在下拉控制信号线(这里具体为第二时钟信号线CLK_B)上的电压信号的控制下下拉栅信号线Gn上的电位。当然，为实现这一功能还可以采用其他的电路结构。
上述行共用模块包括第一晶体管T1与第二晶体管T2，其中：上述第一晶体管T1的栅极与上述上一行的栅信号线Gn-1相连，源极与漏极中的一个与上述本行的上拉控制信号线(节点CA)相连，另一个与上述上一行的栅信号线Gn-1相连(二极管连接方式)；上述第二晶体管T2的栅极与上述本行的栅信号线Gn相连(因此，在该实施例中，可以借助本行的栅极信号线Gn提供的栅极信号来控制第二晶体管T2)，源极与漏极中的一个与低电平线Vss相连，另一个与上述本行的上拉控制信号线(节点CA)相连；上述时钟信号线中的第二时钟信号 线CLK_B作为本行的下拉控制信号线。该电路结构下的行共用模块可以根据上一行的栅信号线Gn-1上的电压信号以及时钟信号线上的信号通过上拉控制信号线向上拉子模块提供上拉控制信号，并通过下拉控制信号线向下拉子模块提供下拉控制信号。当然，为实现这一功能还可以采用其他的电路结构。
需要说明的是，上述任意一个晶体管均可以是N型的薄膜晶体管或P型的薄膜晶体管TFT。上述任意一个TFT的漏极与源极的连接方式均根据该TFT是N型还是P型来决定：若为N型TFT，则图中TFT的上端为漏极、下端为源极；若为P型TFT，则图中TFT的上端为源极、下端为漏极。
当然，图6所示的电路结构仅是一种移位寄存器单元的电路结构示例，其具体的电路时序和工作原理均是本领域技术人员容易理解的，在此不再赘述。
基于上述移位寄存器单元的电路结构，设置在阵列基板上的上述移位寄存器单元结构示意参见图7。图7中，第n行的移位寄存器单元包括位于阵列基板的显示区51之外的行共用单元Xn和位于显示区51之内的多个上述上拉子模块(包括上述上拉晶体管TU和上述电容C1)以及位于显示区51之内的多个下拉子模块(包括上述下拉晶体管TD)。其中，每一上拉子模块中的上拉晶体管TU的栅极均与本行的上拉控制信号线CnA相连，源极与漏极中的一个与所述本行的栅信号线Gn相连，另一个与时钟信号线中的第一时钟信号线CLK_A相连(可由上述Xn引出，也可以由其他电路模块处引出，图7中未示出)。而电容C1的一端与本行的上拉控制信号线CnA相连，另一端与所述本行的栅信号线Gn相连。每一下拉子模块中的下拉晶体管TD的栅极与本行的下拉控制信号线CnB相连，源极与漏极中的一个与低电平线Vss相连，另一个与所述本行的栅信号线Gn相连。当然，图7仅是一种设置在阵列基板上的上述移位寄存器单元结构示意，上拉子模块和下拉子模块的设置方式可以具体参见上述各个实施例。
以上述移位寄存器单元的电路结构为例，在该阵列基板中，上述上拉晶体管TU在行方向上所占的长度为1000微米量级，上述下拉晶体管TD在行方向上所占的长度为1000微米量级，而其他TFT在行方向上所占的长度为10或100微米量级。可见，本发明实施例由于将尺 寸较大的上拉晶体管TU和下拉晶体管TD设置在阵列基板的显示区中，可以使得位于显示区外的电路结构在行方向上所占的长度大大缩小(由原本的1000微米量级降至10或100微米量级)，因而有利于位于阵列基板一侧或两侧的栅极驱动器在电路板上占用的面积的缩小，从而可以使得用于遮蔽该电路板的边框窄化，即本发明实施例可以有效地解决栅极驱动器制约边框窄化的问题。
基于同样的发明构思，本发明实施例提供了一种显示装置，该显示装置包括上述任意一种阵列基板。该显示装置可以为：各类基于GOA设计的显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，上述任意一种阵列基板尤其适用于顶发射式的有机发光二极管显示装置，因为在该显示装置中，设置在阵列基板上的TFT位于发光区域之下，因而输出上拉模块与输出下拉模块不会影响像素单元的开口率，因而也不需要对上拉或下拉子模块的排布做相应的特殊设计。此外，由于上述任意一种显示装置均包括上述任意一种阵列基板，其所具有的技术特征、所解决的技术问题以及可以达到的技术效果均是相应的，因而本实施例不在此进行详述。
综上所述，本发明的实施例所提供的一种阵列基板和显示装置，将与一行像素单元对应的移位寄存器单元分成了行共用模块、输出上拉模块和输出下拉模块三部分，并将行共用模块设置在阵列基板的显示区之外，将输出上拉模块和输出下拉模块设置在阵列基板的显示区之内，因而有利于位于阵列基板一侧或两侧的栅极驱动器在电路板上占用的面积的缩小，从而可以使得用于遮蔽该电路板的边框窄化，即本发明可以解决栅极驱动器制约边框窄化的问题。
在本发明的描述中需要说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域 的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (12)

  1. 一种阵列基板，包括阵列设置的多个像素单元以及每个对应一行像素单元的多个移位寄存器单元，其中与任一行像素单元对应的移位寄存器单元包括：
    位于所述阵列基板的显示区之外的行共用模块，所述行共用模块的输入端与时钟信号线以及上一行像素单元的栅信号线相连，输出端与本行像素单元的上拉控制信号线以及本行像素单元的下拉控制信号线相连；
    位于所述阵列基板的显示区之内的输出上拉模块，所述输出上拉模块与本行像素单元的所述上拉控制信号线以及本行像素单元的栅信号线相连；
    位于所述阵列基板的显示区之内的输出下拉模块，所述输出下拉模块与本行像素单元的所述下拉控制信号线以及本行像素单元的栅信号线相连。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述输出上拉模块包括多个设置在本行的所述像素单元中的上拉子模块，每一所述上拉子模块均与本行像素单元的所述上拉控制信号线以及本行像素单元的栅信号线相连；所述输出下拉模块包括多个设置在本行的所述像素单元中的下拉子模块，每一所述下拉子模块均与本行像素单元的所述下拉控制信号线以及本行像素单元的栅信号线相连。
  3. 根据权利要求2所述的阵列基板，其特征在于，任一行像素单元中设置有所述上拉子模块的像素单元所在的对应列在其他行的像素单元中也设置有所述上拉子模块；任一行像素单元中设置有所述下拉子模块的像素单元所在的对应列在其他行的像素单元中也设置有所述下拉子模块。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述设置有所述上拉子模块的像素单元所在的多个列以及所述设置有所述下拉子模块的像素单元所在的多个列交替地均匀分布在所述阵列基板的显示区内。
  5. 根据权利要求3所述的阵列基板，其特征在于，所述设置有所述上拉子模块的像素单元所在的多个列以及所述设置有所述下拉子模 块的像素单元所在的多个列分布于靠近所述阵列基板一侧或者两侧边缘的多个列中。
  6. 根据权利要求2所述的阵列基板，其特征在于，任一行像素单元中，所述上拉子模块与所述下拉子模块交替地设置在位置连续的多个像素单元中；
    相邻的两行像素单元中，上一行设置有所述上拉子模块和下拉子模块的像素单元所在的多个列相对于下一行设置有所述上拉子模块和下拉子模块的像素单元所在的多个列向左或向右错开预定多列的位置；
    第一行像素单元中设置有所述上拉子模块或下拉子模块的像素单元所在的列从第一列开始；最后一行像素单元中设置有所述上拉子模块或下拉子模块的像素单元所在的列结束于最后一列。
  7. 根据权利要求2至5任意一项所述的阵列基板，其特征在于，在所述阵列基板的显示区形状不规则时，任一行的像素单元中至少有一个是设置有所述上拉子模块的像素单元，且任一行的像素单元中至少有一个是设置有所述下拉子模块的像素单元。
  8. 根据权利要求2至6任意一项所述的阵列基板，其特征在于，所述上拉子模块包括上拉晶体管和电容，所述上拉晶体管的栅极与所述本行像素单元的上拉控制信号线相连，源极与漏极中的一个与所述本行像素单元的栅信号线相连，另一个与所述时钟信号线中的第一时钟信号线相连；所述电容的一端与所述本行像素单元的上拉控制信号线相连，另一端与所述本行像素单元的栅信号线相连。
  9. 根据权利要求8所述的阵列基板，其特征在于，所述下拉子模块包括下拉晶体管，所述下拉晶体管的栅极与所述本行像素单元的下拉控制信号线相连，源极与漏极中的一个与低电平线相连，另一个与所述本行像素单元的栅信号线相连。
  10. 根据权利要求9所述的阵列基板，其特征在于，所述行共用模块包括第一晶体管与第二晶体管，其中：
    所述第一晶体管的栅极与所述上一行像素单元的栅信号线相连，源极与漏极中的一个与所述本行像素单元的上拉控制信号线相连，另一个与所述上一行像素单元的栅信号线相连；
    所述第二晶体管的栅极与所述本行像素单元的栅信号线相连，源 极与漏极中的一个与所述低电平线相连，另一个与所述本行像素单元的上拉控制信号线相连；
    所述时钟信号线中的第二时钟信号线与所述本行像素单元的下拉控制信号线相连。
  11. 一种显示装置，其特征在于，该显示装置包括如权利要求1至10中任意一项所述的阵列基板。
  12. 根据权利要求11所述的显示装置，其特征在于，所述显示装置为顶发射式有机发光二极管显示装置。
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