WO2016107043A1 - 阵列基板和显示装置 - Google Patents
阵列基板和显示装置 Download PDFInfo
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- WO2016107043A1 WO2016107043A1 PCT/CN2015/078676 CN2015078676W WO2016107043A1 WO 2016107043 A1 WO2016107043 A1 WO 2016107043A1 CN 2015078676 W CN2015078676 W CN 2015078676W WO 2016107043 A1 WO2016107043 A1 WO 2016107043A1
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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Definitions
- the present invention relates to the field of display technologies, and in particular, to an array substrate and a display device.
- a gate driver In the existing array substrate Gate On Array (GOA), a gate driver is often designed on a circuit board of a non-display area on one side or both sides of an array substrate.
- the prior art In packaging, the prior art often shields the circuit board with the frame of the display device to keep the appearance clean and beautiful. Therefore, under the traditional GOA design, the gate driver will occupy a certain frame width, which is not conducive to the narrowing of the frame of the display device.
- the present invention provides an array substrate and a display device, which can alleviate or avoid the problem that the gate driver restricts the narrowing of the frame.
- the present invention provides an array substrate comprising a plurality of pixel units arranged in an array and a plurality of shift register units corresponding to each row of pixel units, and the shift register unit corresponding to any row of pixel units comprises:
- a row sharing module located outside the display area of the array substrate, the input end of the row sharing module is connected to the clock signal line and the gate signal line of the pixel unit of the previous row, and the pull-up control signal of the output end and the pixel unit of the row The line and the pull-down control signal line of the pixel unit of the line are connected;
- An output pull-up module located in a display area of the array substrate, the output pull-up module being connected to the pull-up control signal line of the pixel unit of the row and a gate signal line of the pixel unit of the row;
- An output pull-down module located within the display area of the array substrate, the output pull-down module being connected to the pull-down control signal line of the pixel unit of the row and the gate signal line of the pixel unit of the row.
- the output pull-up module includes a plurality of pull-up sub-modules disposed in the pixel unit of the row, and each of the pull-up sub-modules and the pull-up control signal of the row of pixel units a line and a gate signal line of the pixel unit of the row are connected;
- the output pull-down module includes a plurality of pull-down sub-modules disposed in the pixel unit of the row, each of the pull-down sub-blocks The modules are all connected to the pull-down control signal line of the pixel unit of the row and the gate signal line of the pixel unit of the row.
- the corresponding column in which the pixel unit of the pull-up sub-module is disposed in any row of pixel units is also disposed in the pixel unit of the other row, and the pull-up sub-module is also disposed in any row of pixel units;
- the corresponding column in which the pixel unit of the pull-down sub-module is located is also provided with the pull-down sub-module in the pixel unit of the other row.
- the plurality of columns in which the pixel unit of the pull-up sub-module is disposed and the plurality of columns in which the pixel unit in which the pull-down sub-module is disposed are alternately and evenly distributed on the array substrate. Display area.
- the plurality of columns in which the pixel unit of the pull-up sub-module is disposed and the plurality of columns in which the pixel unit in which the pull-down sub-module is disposed are distributed on a side of the array substrate or In multiple columns on both sides of the edge.
- the pull-up sub-module and the pull-down sub-module are alternately disposed in a plurality of pixel units that are consecutive in position;
- the upper row is provided with a plurality of columns in which the pixel units of the pull-up sub-module and the pull-down sub-module are located, and the pixel unit in which the pull-up sub-module and the pull-down sub-module are disposed in the next row
- the plurality of columns are staggered to the left or to the right by a predetermined plurality of columns;
- the first row of pixel units is provided with the column of the pixel unit of the pull-up sub-module or the pull-down sub-module starting from the first column; the last row of pixel units is provided with the pixel unit of the pull-up sub-module or the pull-down sub-module The column ends in the last column.
- At least one of the pixel units of any row is a pixel unit provided with the pull-up sub-module, and at least one of the pixel units of any row is The pixel unit of the pull-down sub-module is provided.
- the pull-up sub-module includes a pull-up transistor and a capacitor, and a gate of the pull-up transistor is connected to a pull-up control signal line of the row of pixel units, and one of a source and a drain
- the gate signal lines of the pixel unit of the row are connected, and the other is connected to the first clock signal line of the clock signal line; one end of the capacitor is connected to the pull-up control signal line of the pixel unit of the row, and the other end is connected Connected to the gate signal line of the pixel unit of the row.
- the pull-down sub-module includes a pull-down transistor, a gate of the pull-down transistor is connected to a pull-down control signal line of the pixel unit of the row, and one of the source and the drain is connected to a low-level line, and One is connected to the gate signal line of the pixel unit of the row.
- the row sharing module includes a first transistor and a second transistor, wherein:
- a gate of the first transistor is connected to a gate signal line of the pixel unit of the previous row, and one of the source and the drain is connected to a pull-up control signal line of the pixel unit of the row, and the other is connected to the upper a gate signal line of a row of pixel units is connected;
- a gate of the second transistor is connected to a gate signal line of the pixel unit of the row, one of the source and the drain is connected to the low-level line, and the other is a pull-up control signal of the pixel unit of the row Line connected
- a second clock signal line of the clock signal line is connected to a pull-down control signal line of the row of pixel units.
- the present invention also provides a display device comprising any of the above array substrates.
- the display device is a top emission type organic light emitting diode display device.
- the present invention divides the shift register unit corresponding to each row of pixel units into three parts: a row sharing module, an output pull-up module, and an output pull-down module, and sets the row sharing module in the display area of the array substrate.
- the output pull-up module and the output pull-down module are disposed within the display area of the array substrate, thereby facilitating the reduction of the area occupied by the gate driver on one or both sides of the array substrate on the circuit board, thereby enabling use
- the frame that shields the circuit board is narrowed, that is, the present invention can solve the problem that the gate driver restricts the narrowing of the frame.
- FIG. 1 is a schematic diagram showing the position and structure of a pixel unit and a shift register unit of an array substrate according to an embodiment of the present invention
- FIG. 2 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module according to an embodiment of the present invention
- FIG. 3 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module according to an embodiment of the present invention
- FIG. 4 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module according to an embodiment of the present invention
- FIG. 5 is a schematic diagram of an optional setting manner of a pull-up sub-module and a pull-down sub-module in a special-shaped display area according to an embodiment of the present invention
- FIG. 6 is a circuit structural diagram of a shift register unit in an embodiment of the present invention.
- FIG. 7 is a schematic structural diagram of the above shift register unit on an array substrate according to an embodiment of the present invention.
- FIG. 1 is a schematic diagram showing the position and structure of a pixel unit and a shift register unit of an array substrate in an embodiment of the present invention.
- the array substrate includes a plurality of pixel units (not all shown in FIG. 1) arranged in an array, for example, the area indicated by hatching in FIG. 1 is a pixel unit of the fourth row and the third column.
- the area indicated by hatching in FIG. 1 is a pixel unit of the fourth row and the third column.
- FIG. 1 only a conventional rectangular pixel unit array is taken as an example, and the outer edges of the plurality of pixel units arranged in an array in the array substrate may be other geometric shapes.
- the array substrate further includes a plurality of shift register units corresponding to each row of pixel units, wherein the shift register unit corresponding to any row of pixel units includes a row sharing module outside the display area of the array substrate, and a display of the array substrate An output pull-down module within the display area of the output pull-up module and the array substrate within the area.
- the actual circuit of the shift register unit may specifically adopt the structural design of the shift register circuit of any one of the gate drivers in the prior art, which is not limited by the present invention.
- the electronic component for pulling up the potential of the gate signal line in the shift register circuit constitutes the output pull-up module
- the electronic component for pulling down the potential of the gate signal line of the line constitutes the above The pull-down module is output, and the other components belong to the above-mentioned row sharing module.
- the row sharing module needs to connect the gate signal line of the previous row to realize the function of the gate driver (of course, the cascading manner of other shift register units can also be adopted in a special design, such as cross Row cascading, which does not change the essence of the embodiment of the present invention, and the row sharing module may need to connect a signal (such as a clock signal) from the timing controller, and thus may need to be connected to a control signal line such as a clock signal line of an external circuit.
- a signal such as a clock signal
- the gate driver design in the prior art can be referred to, which is not limited by the present invention.
- the above-mentioned output pull-up module generally includes a pull-up transistor (hereinafter referred to as TU).
- the TFT, and the above output pull-down module generally includes a TFT which can be called a pull-down transistor (hereinafter referred to as TD).
- the device size of the TU and TD in the shift register circuit of the gate driver is significantly larger than other TFTs (of course, The projection length of the area where the TFT is located in the row direction of the pixel unit is also significantly larger than other TFTs. Therefore, designing the output pull-up module including the TU and the output pull-down module including the TD in the display area of the array substrate can greatly reduce the length of the shift register unit in the row direction outside the display area, thereby facilitating the border. Narrowing.
- the row sharing module X3 of the third row is located outside the display area of the array substrate (X1 to X5 in FIG. 1 respectively represent the row sharing modules of the first row to the fifth row), and the input terminal of the row sharing module X3 is The clock signal line CLK and the gate signal line G2 of the previous row are connected (the connection relationship is not shown in FIG. 1 for the sake of simplicity, and G1 to G5 in FIG. 1 respectively represent the gate signal lines of the first to fifth rows), and the output terminal is The pull-up control signal line C3A of the line and the pull-down control signal line C3B of the line are connected (C1A to C5A in Fig. 1 respectively indicate pull-up control signal lines of the first to fifth lines, and C1B to C5B in Fig. 1 respectively indicate Pull-down control signal lines from one line to the fifth line).
- the output pull-up module is represented as a plurality of pull-up sub-modules connected in parallel with each other (for example, U1-1 to U5-1 respectively represent the first pull-up sub-modules of the first to fifth rows, U1-2 to U5-2 represents the second pull-up sub-module of the first row to the fifth row, respectively, and the output pull-down module is represented as a plurality of parallel pull-down sub-modules (for example, D1-1 to D5-1 respectively represent the first row to the first The first drop-down sub-module of the five rows, D1-2 to D5-2 respectively represent the second pull-down sub-module of the first row to the fifth row).
- the output pull-up module and the output pull-down module of any row may have any structural composition and position distribution in the display area of the array substrate, but In order to achieve the loss
- the pull-up module and the output pull-down module pull up and pull down the potential of the gate signal line, and the output pull-up module of any row can be connected with the above-mentioned pull-up control signal line of the line and the gate signal line of the line;
- the output pull-down module can be connected to the above-mentioned pull-down control signal line of the line and the gate signal line of the line.
- the pull-up sub-modules U3-1 and U3-2 of the third row in FIG. 1 are both connected to the pull-up control signal line C3A of the row, and the pull-down sub-modules D3-1 and D3-2 of the third row are both The pull-down control signal line C3B of the row is connected.
- the shift register unit corresponding to one row of pixel units is divided into three parts: a row sharing module, an output pull-up module, and an output pull-down module, and the row sharing module is disposed outside the display area of the array substrate.
- the output pull-up module and the output pull-down module are disposed within the display area of the array substrate, thereby facilitating the reduction of the area occupied by the gate driver on one side or both sides of the array substrate on the circuit board, thereby enabling shielding
- the frame of the circuit board is narrowed, that is, the embodiment of the present invention can solve the problem that the gate driver restricts the narrowing of the frame.
- the embodiment of the present invention can make the length of the shift register unit in the row direction outside the display area greatly reduced, thereby further Conducive to the narrowing of the border.
- the large-sized output pull-up/pull-down module can also be divided as shown in FIG. Multiple small-sized pull-up/pull-down submodules, namely:
- the output pull-up module includes a plurality of pull-up sub-modules disposed in the pixel unit of the row, and each of the pull-up sub-modules is connected to the pull-up control signal line of the row and the gate signal line of the row;
- the output pull-down module includes a plurality of pull-down sub-modules disposed in the pixel unit of the row, and each of the pull-down sub-modules is connected to the pull-down control signal line of the row and the gate signal line of the row.
- the output pull-up module includes a plurality of pull-up sub-modules disposed in the pixel unit of the row, such as U4- 1, U4-2, of course, the number of pull-up sub-modules can also be other positive integers greater than 2; the output pull-down module includes a plurality of pull-down sub-modules set in the pixel unit of the row, such as D4-1, D4 -2, of course, the number of drop-down submodules can also be other than A positive integer of 2.
- the pull-up sub-module U4-1 is connected to the pull-up control signal line C4A of the line and the gate signal line G4 of the current line, and the other pull-up sub-modules of the line are also connected to the pull-up control signal line C4A and the gate signal line G4.
- the following pull submodule D4-1 is connected to the pull-down control signal line C4B of the line and the gate signal line G4 of the current line, and the other pull-down sub-modules of the line are also connected to the pull-down control signal line C4B and the gate signal line G4. .
- the design makes the entire output pull-up module equivalent to a plurality of pull-up sub-modules connected in parallel with each other, thus pulling up the gate signal line
- the function of the upper potential can be implemented by a plurality of pull-up sub-modules.
- the large-sized pull-up transistor TU can be divided into a plurality of small-sized sub-up pull-up transistors TUx connected in parallel, so that a plurality of TUx are pulled up control signals.
- the pull-up of the potential on the gate signal line is jointly performed under the control, so that the requirement of the pull-up speed of the gate signal line potential is ensured by adjusting the size and number of the TUx. Moreover, since the circuit structure of a larger size is disposed in a single pixel unit and the circuit structure of a smaller size is set in the plurality of pixel units, the output pull-up module and the output pull-down module are reduced to the pixel unit.
- the effect of the aperture ratio is beneficial to improve the brightness uniformity of a plurality of pixel units throughout the display area.
- the specific number and design size can be designed according to the amplitude and timing of the actual desired gate signal.
- different positions and sizes of the pull-up sub-module and the pull-down sub-module and different application scenarios can also be arranged in different ways. More specifically, an alternative arrangement of several pull-up sub-modules and pull-down sub-modules will be described below with reference to the accompanying drawings.
- FIG. 2 illustrates an alternative arrangement of a pull-up sub-module and a pull-down sub-module in one embodiment of the present invention.
- a row of pixel units corresponding to a row sharing module such as X1 to X5 disposed outside the display area
- pixel units Ux provided with a pull-up sub-module (for example, set in FIG. 1) U1-1, the pixel unit of U3-2) and the pixel unit Dx provided with the pull-down sub-module (for example, the pixel unit in which D2-2 and D5-1 are provided in FIG. 1).
- the plurality of columns in which the pixel unit Ux having the pull-up sub-module is located and the plurality of columns in which the pixel unit Dx provided with the pull-down sub-module are located are distributed in a plurality of columns near one side or both side edges of the array substrate.
- the pull-up sub-module and the pull-down sub-module are both disposed on one side or both sides of the row sharing module near the array substrate, so the above-mentioned pull-up control signal line and the pull-down control signal line do not need to run through the entire line, and only Set at the edge of the array substrate (can be reduced Set the length). Therefore, the solution saves material and layout space in the middle of the display area. More importantly, since the above Ux and Dx are disposed only at the edge position of the display area, the above-described adverse effect may not be caused to the aperture ratio of the pixel unit in the middle portion of the display area.
- the setting scheme is suitable.
- FIG. 3 illustrates an alternative arrangement of another pull-up sub-module and pull-down sub-module in one embodiment of the present invention. Consistent with the reference numerals of FIG. 2, in the arrangement shown in FIG. 3, a plurality of columns in which the pixel unit Ux of the pull-up sub-module is disposed and a plurality of columns in which the pixel unit Dx in which the pull-down sub-module is disposed are alternately arranged The ground is evenly distributed in the display area of the array substrate. Of course, in FIG. 3, only two columns are alternately arranged, and other uniform arrangement schemes can be obtained by referring to the setting manner.
- the advantage of using the above uniform arrangement is that although the aperture ratio of a part of the columns in the display area may be lower than other columns, as long as the columns with lower aperture ratios are evenly distributed in the display area, the overall display effect is not obtained. It has a great influence (sufficiently sparse, and the difference in aperture ratio is small enough for the human eye to observe), that is, the human eye does not feel the difference between these columns and the surrounding columns as much as possible, and the problem of reducing the above-mentioned aperture ratio is reduced in the display area.
- the effect of brightness uniformity For the usage scenario where the brightness and brightness uniformity in the display area are required to be high, the setting scheme is suitable.
- the corresponding column in which the pixel unit Ux of the pull-up sub-module is disposed in any row is also provided with the pull-up sub-module in the pixel unit of the other row;
- the corresponding column in which the pixel unit Dx of the above-mentioned pull-down sub-module is located in any row is also provided with the above-mentioned pull-down sub-module in the pixel unit of the other row, that is, the above Ux and Dx are all set in columns.
- Ux and Dx may also be arranged not in columns.
- it may also be promoted as a point-like uniform setting scheme in the entire rectangular display area to obtain better brightness and brightness. Uniformity.
- Figure 4 shows an alternative arrangement of another pull-up sub-module and drop-down sub-module that is not arranged in columns. Consistent with the reference numerals of Figures 2 and 3, in Figure 4, the pull-up in any row The module and the pull-down sub-module are alternately disposed in a plurality of pixel units that are consecutive in position. Moreover, in the two adjacent rows, the upper row is provided with a plurality of columns in which the pixel units Ux and Dx of the pull-up sub-module and the pull-down sub-module are located, and the pixel unit Ux having the pull-up sub-module and the pull-down sub-module is disposed on the next row.
- the plurality of columns in which Dx is located are shifted to the left or to the right by a predetermined plurality of columns (in FIG. 4, a staggered column is taken as an example).
- the first row is provided with the column of the pixel unit Ux or Dx of the pull-up sub-module or the pull-down sub-module starting from the first column;
- the last row is provided with the pixel unit Ux of the pull-up sub-module or the pull-down sub-module Or the column where Dx is located ends in the last column, that is, the entire Ux and Dx setting area covers a diagonal line of the display area.
- This setting makes the two rows alternately arranged, which helps to improve the uniformity of the brightness of the display area.
- the pull-up sub-module and the pull-down sub-module are set in a large number, it is suitable to apply the setting scheme.
- any one of the above setting manners may be applied.
- the number of pixel units per row and column may be inconsistent, and thus, for this case, It is also necessary to meet certain conditions when setting: at least one pixel unit of any row of pixel units is a pixel unit provided with the above-mentioned pull-up sub-module, and at least one pixel unit of any row of pixel units is provided with the above-mentioned pull-down sub-module Pixel unit. That is, in order to guarantee the integrity of any one row of shift register units, at least one pull-up sub-module and one pull-down sub-module are provided in any row.
- the shape of the display area 51 is substantially "concave", and the circuit board 52 on which the data driver is located is disposed on one side (the lower side in the drawing) of the display area 51.
- the above-mentioned row sharing module Xt (which may include X1 to X5 as shown in FIG. 1) should be disposed on the other side or both sides of the display area 51 (the left and right sides are taken as an example in FIG. 5).
- At least one column Ux and one column Dx can cover all the rows in the display area.
- the above Ux and the above Dx are set in FIG. 5 in two shaded areas in FIG. 5 which can cover all the lines of the display area 51.
- the plurality of pull-up modules or the plurality of pull-down modules may be modules having the same structure and size specifications, or modules having different structures or sizes.
- the plurality of pull-up modules or the plurality of pull-down modules may be modules having the same structure and size specifications.
- a specific shift register unit circuit that can be applied to the present invention
- the structure can adopt various circuit structures well known to those skilled in the art, and the present invention does not limit the circuit structure of the specific shift register unit.
- the specific relationship between the line sharing module, the pull-up module, and the pull-down module may be different from the previous embodiment.
- FIG. 6 is a circuit configuration diagram of a shift register unit in another embodiment of the present invention.
- the clock signal line CLK includes a first clock signal line CLK_A and a second clock signal line CLK_B whose phases of the signals differ by a half cycle, specifically, for the nth line shift Register unit (n is a positive integer):
- the pull-up sub-module includes a pull-up transistor TU and a capacitor C1, and the gate of the pull-up transistor TU is connected to the pull-up control signal line of the current row (indicated by a node CA in FIG. 6), in the source and the drain.
- One is connected to the gate signal line Gn of the above-mentioned row, and the other is connected to the first clock signal line CLK_A of the clock signal line; one end of the capacitor is connected to the pull-up control signal line (node CA) of the above-mentioned row, The other end is connected to the gate signal line Gn of the above-mentioned row.
- the above structure can cause the pull-up transistor TU to pull up the potential on the gate signal line Gn under the control of the voltage signal on the pull-up control signal line (at the node CA).
- other circuit configurations can be used to achieve this.
- the pull-down sub-module includes a pull-down transistor TD, a gate of the pull-down transistor TD and a pull-down control signal line of the current row (in this embodiment, a signal provided by the second clock signal line CLK_B of the clock signal line may be used as
- the pull-down control signal is thus connected to the pull-down control signal line by CLK_B, one of the source and the drain is connected to the low-level line Vss, and the other is connected to the gate signal line Gn of the above-mentioned row.
- the above structure can cause the pull-down transistor TD to pull down the potential on the gate signal line Gn under the control of the voltage signal on the pull-down control signal line (here specifically, the second clock signal line CLK_B).
- the second clock signal line CLK_B the second clock signal line
- the row sharing module includes a first transistor T1 and a second transistor T2, wherein: a gate of the first transistor T1 is connected to a gate signal line Gn-1 of the upper row, and one of a source and a drain is connected to the above
- the pull-up control signal line (node CA) is connected, the other is connected to the gate signal line Gn-1 of the previous row (diode connection mode);
- the gate of the second transistor T2 is connected to the gate signal line Gn of the above-mentioned row (Thus, in this embodiment, the second transistor T2) can be controlled by the gate signal supplied from the gate signal line Gn of the row, one of the source and the drain is connected to the low-level line Vss, and the other Connected to the pull-up control signal line (node CA) of the above line; the second clock signal in the above clock signal line
- the line CLK_B serves as the pull-down control signal line of the line.
- the row sharing module under the circuit structure can provide a pull-up control signal by pulling up the sub-module through the pull-up control signal line according to the voltage signal on the gate signal line Gn-1 of the previous row and the signal on the clock signal line, and is controlled by pull-down.
- the signal line provides a pull-down control signal to the pull-down sub-module.
- other circuit configurations can be used to achieve this.
- any one of the above transistors may be an N-type thin film transistor or a P-type thin film transistor TFT.
- the method of connecting the drain and the source of any one of the TFTs is determined according to whether the TFT is N-type or P-type: if it is an N-type TFT, the upper end of the TFT in the figure is the drain and the lower end is the source; if it is the P For a TFT, the upper end of the TFT is the source and the lower end is the drain.
- circuit structure shown in FIG. 6 is only an example of the circuit structure of a shift register unit, and the specific circuit timing and operation principle are well understood by those skilled in the art, and are not described herein again.
- the shift register unit of the nth row includes a row sharing unit Xn located outside the display area 51 of the array substrate and a plurality of the above-described pull-up sub-modules (including the above-described pull-up transistor TU and The capacitor C1) and a plurality of pull-down sub-modules (including the pull-down transistor TD) located within the display area 51.
- the gate of the pull-up transistor TU in each pull-up sub-module is connected to the pull-up control signal line CnA of the current line, and one of the source and the drain is connected to the gate signal line Gn of the current row.
- the other is connected to the first clock signal line CLK_A in the clock signal line (it can be taken out by Xn described above, or can be taken out from other circuit modules, not shown in FIG. 7).
- one end of the capacitor C1 is connected to the pull-up control signal line CnA of the current line, and the other end is connected to the gate signal line Gn of the current line.
- FIG. 7 is only a schematic diagram of the structure of the above shift register unit disposed on the array substrate. The manner of setting the pull-up sub-module and the pull-down sub-module can be specifically referred to the above embodiments.
- the length of the pull-up transistor TU in the row direction is on the order of 1000 micrometers
- the length of the pull-down transistor TD in the row direction is 1000 micrometers.
- the magnitude of the other TFTs in the row direction is on the order of 10 or 100 microns. It can be seen that the embodiment of the present invention
- the larger pull-up transistor TU and the pull-down transistor TD are disposed in the display area of the array substrate, so that the length of the circuit structure located outside the display area in the row direction is greatly reduced (from the original 1000 micron level to 10).
- the example can effectively solve the problem that the gate driver restricts the narrowing of the frame.
- an embodiment of the present invention provides a display device including any of the above array substrates.
- the display device can be: various GOA-designed display panels, electronic paper, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, and the like, or any display product or component.
- any of the above array substrates is particularly suitable for a top emission type organic light emitting diode display device, because in the display device, the TFTs disposed on the array substrate are located below the light emitting region, thereby outputting the pull-up module and the output pull-down module. It does not affect the aperture ratio of the pixel unit, and thus does not require a special design for the arrangement of the pull-up or pull-down sub-modules.
- any of the above display devices includes any of the above array substrates, the technical features, the technical problems solved, and the technical effects that can be achieved are corresponding, and thus the present embodiment is not described in detail herein. .
- an array substrate and a display device divide a shift register unit corresponding to a row of pixel units into three parts: a row sharing module, an output pull-up module, and an output pull-down module, and
- the row sharing module is disposed outside the display area of the array substrate, and the output pull-up module and the output pull-down module are disposed within the display area of the array substrate, thereby facilitating the gate driver on one side or both sides of the array substrate in the circuit
- the area occupied by the board is reduced, so that the frame for shielding the circuit board can be narrowed, that is, the present invention can solve the problem that the gate driver restricts the narrowing of the frame.
- the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
- a fixed connection a detachable connection, or an integral connection
- it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
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Abstract
Description
Claims (12)
- 一种阵列基板,包括阵列设置的多个像素单元以及每个对应一行像素单元的多个移位寄存器单元,其中与任一行像素单元对应的移位寄存器单元包括:位于所述阵列基板的显示区之外的行共用模块,所述行共用模块的输入端与时钟信号线以及上一行像素单元的栅信号线相连,输出端与本行像素单元的上拉控制信号线以及本行像素单元的下拉控制信号线相连;位于所述阵列基板的显示区之内的输出上拉模块,所述输出上拉模块与本行像素单元的所述上拉控制信号线以及本行像素单元的栅信号线相连;位于所述阵列基板的显示区之内的输出下拉模块,所述输出下拉模块与本行像素单元的所述下拉控制信号线以及本行像素单元的栅信号线相连。
- 根据权利要求1所述的阵列基板,其特征在于,所述输出上拉模块包括多个设置在本行的所述像素单元中的上拉子模块,每一所述上拉子模块均与本行像素单元的所述上拉控制信号线以及本行像素单元的栅信号线相连;所述输出下拉模块包括多个设置在本行的所述像素单元中的下拉子模块,每一所述下拉子模块均与本行像素单元的所述下拉控制信号线以及本行像素单元的栅信号线相连。
- 根据权利要求2所述的阵列基板,其特征在于,任一行像素单元中设置有所述上拉子模块的像素单元所在的对应列在其他行的像素单元中也设置有所述上拉子模块;任一行像素单元中设置有所述下拉子模块的像素单元所在的对应列在其他行的像素单元中也设置有所述下拉子模块。
- 根据权利要求3所述的阵列基板,其特征在于,所述设置有所述上拉子模块的像素单元所在的多个列以及所述设置有所述下拉子模块的像素单元所在的多个列交替地均匀分布在所述阵列基板的显示区内。
- 根据权利要求3所述的阵列基板,其特征在于,所述设置有所述上拉子模块的像素单元所在的多个列以及所述设置有所述下拉子模 块的像素单元所在的多个列分布于靠近所述阵列基板一侧或者两侧边缘的多个列中。
- 根据权利要求2所述的阵列基板,其特征在于,任一行像素单元中,所述上拉子模块与所述下拉子模块交替地设置在位置连续的多个像素单元中;相邻的两行像素单元中,上一行设置有所述上拉子模块和下拉子模块的像素单元所在的多个列相对于下一行设置有所述上拉子模块和下拉子模块的像素单元所在的多个列向左或向右错开预定多列的位置;第一行像素单元中设置有所述上拉子模块或下拉子模块的像素单元所在的列从第一列开始;最后一行像素单元中设置有所述上拉子模块或下拉子模块的像素单元所在的列结束于最后一列。
- 根据权利要求2至5任意一项所述的阵列基板,其特征在于,在所述阵列基板的显示区形状不规则时,任一行的像素单元中至少有一个是设置有所述上拉子模块的像素单元,且任一行的像素单元中至少有一个是设置有所述下拉子模块的像素单元。
- 根据权利要求2至6任意一项所述的阵列基板,其特征在于,所述上拉子模块包括上拉晶体管和电容,所述上拉晶体管的栅极与所述本行像素单元的上拉控制信号线相连,源极与漏极中的一个与所述本行像素单元的栅信号线相连,另一个与所述时钟信号线中的第一时钟信号线相连;所述电容的一端与所述本行像素单元的上拉控制信号线相连,另一端与所述本行像素单元的栅信号线相连。
- 根据权利要求8所述的阵列基板,其特征在于,所述下拉子模块包括下拉晶体管,所述下拉晶体管的栅极与所述本行像素单元的下拉控制信号线相连,源极与漏极中的一个与低电平线相连,另一个与所述本行像素单元的栅信号线相连。
- 根据权利要求9所述的阵列基板,其特征在于,所述行共用模块包括第一晶体管与第二晶体管,其中:所述第一晶体管的栅极与所述上一行像素单元的栅信号线相连,源极与漏极中的一个与所述本行像素单元的上拉控制信号线相连,另一个与所述上一行像素单元的栅信号线相连;所述第二晶体管的栅极与所述本行像素单元的栅信号线相连,源 极与漏极中的一个与所述低电平线相连,另一个与所述本行像素单元的上拉控制信号线相连;所述时钟信号线中的第二时钟信号线与所述本行像素单元的下拉控制信号线相连。
- 一种显示装置,其特征在于,该显示装置包括如权利要求1至10中任意一项所述的阵列基板。
- 根据权利要求11所述的显示装置,其特征在于,所述显示装置为顶发射式有机发光二极管显示装置。
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CN104517564A (zh) | 2015-04-15 |
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