WO2022100728A1 - 一种正负电压电荷泵电路、芯片及通信终端 - Google Patents

一种正负电压电荷泵电路、芯片及通信终端 Download PDF

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Publication number
WO2022100728A1
WO2022100728A1 PCT/CN2021/130586 CN2021130586W WO2022100728A1 WO 2022100728 A1 WO2022100728 A1 WO 2022100728A1 CN 2021130586 W CN2021130586 W CN 2021130586W WO 2022100728 A1 WO2022100728 A1 WO 2022100728A1
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Prior art keywords
nmos transistor
pmos transistor
charge pump
inverter
gate
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PCT/CN2021/130586
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English (en)
French (fr)
Inventor
王永寿
陈成
李春领
林升
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上海唯捷创芯电子技术有限公司
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Application filed by 上海唯捷创芯电子技术有限公司 filed Critical 上海唯捷创芯电子技术有限公司
Priority to EP21891248.3A priority Critical patent/EP4246791A4/en
Priority to KR1020237020469A priority patent/KR20230116826A/ko
Priority to JP2023529972A priority patent/JP2023549414A/ja
Publication of WO2022100728A1 publication Critical patent/WO2022100728A1/zh
Priority to US18/318,026 priority patent/US20230291309A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/008—Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators

Definitions

  • the invention relates to a positive and negative voltage charge pump circuit, and also relates to an integrated circuit chip including the positive and negative voltage charge pump circuit and a corresponding communication terminal, belonging to the technical field of analog integrated circuits.
  • the charge pump circuit As a basic module circuit, is widely used in various integrated circuit products.
  • the main function of the charge pump circuit is to provide the system with a positive voltage source higher than the positive rail of the input power supply voltage, and a negative voltage source lower than the negative rail of the input power supply voltage, so as to better meet the system design specifications.
  • positive power supply high voltage charge pump circuits have appeared in many application scenarios, with the continuous improvement of system index requirements, more and more electronic systems need to be able to generate positive and negative high voltages at the same time to work stably and reliably. . Therefore, there is an increasingly urgent need for a charge pump circuit design that can provide stable and reliable voltages that are higher than the positive rail of the input power supply and lower than the negative rail of the input power supply at the same time.
  • a positive and negative high voltage charge pump circuit is disclosed. Its working principle is based on the asymmetric cross-coupling unilateral cascade charge pump structure. Negative high voltage output. However, this circuit cannot output both positive and negative supply voltages at the same time.
  • a charge pump circuit for generating positive and negative voltage sources is disclosed in patent number ZL 201610004368.4, which uses a three-phase frequency divider to realize three clock signals of a fixed pulse sequence to control the charge and discharge of capacitors to realize positive and negative voltages source output. Although this circuit can realize positive and negative voltage source output, the absolute value of its output voltage source is lower than that of the input voltage source, which makes it very limited in practical application.
  • the primary technical problem to be solved by the present invention is to provide a positive and negative voltage charge pump circuit.
  • Another technical problem to be solved by the present invention is to provide a chip including a positive and negative voltage charge pump circuit and a corresponding communication terminal.
  • a positive and negative voltage charge pump circuit including a clock generation module, a positive voltage charge pump module, a transient enhancement module and a negative voltage charge pump module, wherein the output end of the clock generation module connecting the input terminals of the positive voltage charge pump module and the negative voltage charge pump module, the output terminal of the positive voltage charge pump module is connected to the input terminal of the transient enhancement module, and the output terminal of the transient enhancement module connected to the input power supply terminal of the negative voltage charge pump module, and the power supply terminals of the clock generation module, the positive voltage charge pump module and the transient enhancement module are all connected to a supply voltage;
  • the positive voltage charge pump module generates a positive voltage according to the clock signal output by the clock generation module, and the positive voltage and the power supply voltage are sampled by the transient enhancement module as an input voltage source and converted into a current for comparison, A switchable input voltage is provided to the negative voltage charge pump module according to the comparison result, so that the negative voltage charge pump module generates a negative voltage according to the clock signal output by the clock generation module.
  • the positive voltage charge pump module includes a first clock conversion unit and at least one positive voltage charge pump unit, the input end of the first clock conversion unit is connected to the output end of the clock generation module, and the first clock conversion unit is connected to the output end of the clock generation module.
  • the output terminal of a clock conversion unit is connected to the input terminal of each of the positive voltage charge pump units.
  • the first clock conversion unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate and a first Two NAND gates; the input end of the first inverter is connected to the output end of the clock generating module and an input end of the second NAND gate, and the output end of the first inverter is connected to the An input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the first output end and the The input end of the third inverter, the output end of the third inverter is connected to the other input end and the second output end of the second NAND gate, and the output end of the second NAND gate is connected to the The input end of the fourth inverter, the output end of the fourth inverter is connected to the fourth output end and the input end of the fifth inverter, and the output end of the fifth invert
  • the input voltage of each positive voltage charge pump unit is connected to the positive voltage of the previous positive voltage charge pump unit. pressure output.
  • the positive voltage charge pump unit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth A PMOS transistor, a first capacitor, a second capacitor and a third capacitor;
  • the gate of the first NMOS transistor is connected to the fourth output end of the first clock conversion unit, the first NMOS transistor and the second NMOS transistor have The source is grounded respectively, the drain of the first NMOS transistor is respectively connected to one end of the second capacitor and the drain of the first PMOS transistor, and the gate of the first PMOS transistor is connected to the first clock conversion unit the second output terminal of the second NMOS transistor, the gate of the second NMOS transistor is connected to the first output terminal of the first clock conversion unit, and the drain of the second NMOS transistor is respectively connected to one end of the first capacitor and the The drain of the second PMOS transistor, the gate of the second PMOS transistor is connected to the third
  • the transient enhancement module includes a voltage sampling and comparison unit and a voltage switching unit, the input terminal of the voltage sampling and comparison unit is connected to the positive voltage output terminal of the positive voltage charge pump unit and the power supply voltage, and the voltage The output end of the sampling and comparison unit is connected to the input end of the voltage switching unit.
  • the voltage sampling and comparison unit includes a first resistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a second resistor, A third resistor and a fourth capacitor; one end of the first resistor, the source of the fifth PMOS transistor and the sixth PMOS transistor are respectively connected to the supply voltage, and the other end of the first resistor is respectively connected to the first The drain and gate of the five NMOS transistors, the gate of the sixth NMOS transistor, and the drain of the sixth NMOS transistor are respectively connected to the drain and gate of the fifth PMOS transistor and the sixth PMOS transistor , the drain of the sixth PMOS transistor is respectively connected to one end of the fourth capacitor and one end of the third resistor, the drain of the seventh NMOS transistor and the voltage switching unit, the first The gates of the seven NMOS transistors are respectively connected to the gate and drain of the eighth NMOS transistor and one end of the second resistor
  • the voltage switching unit includes a hysteresis inverter, a logic level conversion subunit and a switch subunit; the input end of the hysteresis inverter is connected to the output end of the voltage sampling and comparison unit, and the hysteresis inverter is connected to the output end of the voltage sampling and comparison unit.
  • the output end of the inverter is connected to the input end of the logic level conversion subunit, and the output end of the logic level conversion subunit is connected to the input end of the switch subunit.
  • the logic level conversion subunit includes a sixth inverter, a seventh inverter, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor,
  • the input end of the sixth inverter is connected to the hysteresis inverter
  • the output end of the sixth inverter is connected to the input end of the seventh inverter and the gate of the thirteenth NMOS transistor, and the output end of the seventh inverter is connected to the an input end of the switch subunit, the gate of the fourteenth NMOS transistor;
  • the drain of the fifteenth PMOS transistor is respectively connected to one end of the sixth capacitor and the drain of the eighteenth NMOS transistor, and the source of the eighteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor , the other end of the sixth capacitor is respectively connected to the source of the fifteenth NMOS transistor, an input end of the third NAND gate, and the drain of the tenth PMOS transistor, and the fifteenth NMOS transistor
  • the drain of the transistor is respectively connected to the drain of the sixteenth NMOS transistor, and the source of the sixteenth NMOS transistor is respectively connected to the drain of the eleventh PMOS transistor, one end of the fifth capacitor and the One input end of the fourth NAND gate, and the other end of the fifth capacitor is respectively connected to the drain of the fourteenth PMOS transistor, the drain of the seventeenth NMOS transistor, and the drain of the seventeenth NMOS transistor.
  • the source is connected to the drain of the thirteenth NMOS transistor, the gate of the twelfth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the drain of the twelfth NMOS transistor is respectively connected to the The drain and gate of the thirteenth PMOS transistor, the gate of the sixteenth NMOS transistor and the fifteenth NMOS transistor, and the source of the thirteenth PMOS transistor are respectively connected to the twelfth PMOS transistor.
  • the eleventh PMOS transistor and the gate of the tenth PMOS transistor are both connected to the positive voltage output terminal of the positive voltage charge pump unit, and the fourteenth NMOS transistor and the thirteenth NMOS transistor are connected to the positive voltage output terminal of the positive voltage charge pump unit.
  • the sources of the twelfth NMOS transistor are grounded respectively, the sources of the fourteenth PMOS transistor and the fifteenth PMOS transistor are respectively connected to the negative rail voltage of the voltage domain where they are located, and the other of the third NAND gate
  • the input terminal is respectively connected to the output terminal of the fourth NAND gate and the other input terminal of the switch subunit, and the output terminal of the third NAND gate is connected to the other input terminal of the fourth NAND gate.
  • the switch subunit includes a sixteenth PMOS transistor and a seventeenth PMOS transistor, the gate of the sixteenth PMOS transistor is connected to the output end of the fourth NAND gate, and the sixteenth PMOS transistor is connected to the output end of the fourth NAND gate.
  • the source of the PMOS transistor is connected to the positive voltage output terminal of the positive voltage charge pump unit, the gate of the seventeenth PMOS transistor is connected to the output terminal of the seventh inverter, and the source of the seventeenth PMOS transistor
  • the electrodes are connected to the power supply voltage, and the drains of the seventeenth PMOS transistor and the sixteenth PMOS transistor serve as the output ends of the switch subunit.
  • the negative voltage charge pump module includes a second clock conversion unit and a negative voltage charge pump unit, the input end of the second clock conversion unit is connected to the output end of the clock generation module, and the second clock The output end of the conversion unit is connected to the input end of the negative voltage charge pump unit, and the input end of the negative voltage charge pump unit is connected to the output end of the voltage switching unit.
  • the second clock conversion unit includes an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, and a fifth NAND gate and the sixth NAND gate; the input end of the eighth inverter is connected to the output end of the clock generating module and an input end of the sixth NAND gate, and the output end of the eighth inverter is connected An input end of the fifth NAND gate, the output end of the fifth NAND gate is connected to the input end of the ninth inverter, and the output end of the ninth inverter is connected to the fifth output end and the The input end of the tenth inverter, the output end of the tenth inverter is connected to the other input end of the sixth NAND gate and the sixth output end, and the output end of the sixth NAND gate connected to the input end of the eleventh inverter, the output end of the eleventh inverter is connected to the eighth output end and the input end of the twelfth inverter
  • the negative voltage charge pump unit includes an eighteenth PMOS transistor, a nineteenth PMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, The twenty-first NMOS transistor, the twenty-second NMOS transistor, the seventh capacitor, the eighth capacitor and the ninth capacitor; the gate of the eighteenth PMOS transistor is connected to the eighth output end of the second clock conversion unit, The drains of the eighteenth PMOS transistor and the nineteenth PMOS transistor are respectively connected to the output voltage of the voltage switching unit, and the source electrodes of the eighteenth PMOS transistor are respectively connected to one end of the eighth capacitor and the The source of the nineteenth NMOS transistor, the gate of the nineteenth NMOS transistor is connected to the sixth output end of the second clock conversion unit, and the gate of the nineteenth PMOS transistor is connected to the second clock
  • the fifth output terminal of the conversion unit, the source of the nineteenth PMOS transistor is respectively connected to one end of the seventh capacitor and the source of the twentieth NMOS
  • an integrated circuit chip including the above-mentioned positive and negative voltage charge pump circuit.
  • a communication terminal including the above-mentioned positive and negative voltage charge pump circuit.
  • a positive voltage charge pump module generates a positive voltage according to a clock signal output by a clock generation module, and at the same time, a transient enhancement module is used to sample the positive voltage and the power supply voltage, and convert it into a current.
  • a switchable input voltage can be provided for the negative voltage charge pump module.
  • the negative voltage charge pump module can not only quickly and reliably establish a negative voltage, but also improve the negative voltage generated by the negative voltage charge pump module. The speed and efficiency of the voltage, but also the flexibility to achieve different negative pressure requirements.
  • FIG. 1 is a schematic block diagram of a positive and negative voltage charge pump circuit provided by an embodiment of the present invention
  • FIG. 2 is a circuit schematic diagram of a positive voltage charge pump module in a positive and negative voltage charge pump circuit provided by an embodiment of the present invention
  • FIG. 3 is a circuit schematic diagram of a transient enhancement module in a positive and negative voltage charge pump circuit provided by an embodiment of the present invention
  • FIG. 4 is a circuit schematic diagram of a negative voltage charge pump module in a positive and negative voltage charge pump circuit provided by an embodiment of the present invention.
  • the present invention provides a positive and negative voltage charge pump circuit, including a clock generation module 100 , a positive voltage charge pump module 101 , a transient enhancement module 102 and a negative voltage charge pump module 103 .
  • the output end of the clock generation module 100 is connected to the input end of the positive voltage charge pump module 101 and the negative voltage charge pump module 103 , the output end of the positive voltage charge pump module 101 is connected to the input end of the transient enhancement module 102 , and the The output terminal is connected to the input power terminal of the negative voltage charge pump module 103 , and the power terminals of the clock generation module 100 , the positive voltage charge pump module 101 and the transient enhancement module 102 are all connected to the power supply voltage VDD.
  • the positive voltage charge pump module 101 generates a positive voltage according to the clock signal output by the clock generation module 100.
  • the positive voltage and the power supply voltage are sampled by the transient enhancement module 102 as an input voltage source and converted into a current for comparison. According to the comparison result, it is a negative voltage.
  • the charge pump module 103 provides a switchable input voltage, so that the negative voltage charge pump module 103 generates a negative voltage output according to the clock signal output by the clock generation module 100 .
  • the clock generating module 100 is used for generating a clock signal.
  • the clock generation module 100 can be implemented by an oscillator with any structure, and its main purpose is to provide a clock signal of a certain frequency for the positive voltage charge pump module 101 and the negative voltage charge pump module 103 .
  • the positive voltage charge pump module 101 includes a first clock conversion unit 201 and at least one positive voltage charge pump unit 202.
  • the input end of the first clock conversion unit 201 is connected to the output end of the clock generation module 100, and the first clock
  • the output terminal of the conversion unit 201 is connected to the input terminal of each positive voltage charge pump unit 202 .
  • the first clock converting unit 201 is configured to convert the clock signal output by the clock generating module 100 to generate two complementary non-overlapping clock signals. As shown in FIG. 2, the first clock conversion unit 201 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a first The NAND gate NAND1 and the second NAND gate NAND2; the input end of the first inverter INV1 is connected to the output end of the clock generating module 100 and an input end of the second NAND gate NAND2, and the output end of the first inverter INV1 An input terminal of the first NAND gate NAND1 is connected, the output terminal of the first NAND gate NAND1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the first output terminal and the third inverter.
  • the input terminal of the inverter INV3, the output terminal of the third inverter INV3 is connected to the other input terminal of the second NAND gate NAND2 and the second output terminal, and the output terminal of the second NAND gate NAND2 is connected to the fourth inverter INV4
  • the input end of the fourth inverter INV4 is connected to the fourth output end and the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is connected to the other input end of the first NAND gate NAND1 with the third output.
  • the first clock conversion unit 201 receives the clock signal CLK output by the clock generation module 100, and inputs the clock signal CLK through the inverters INV1-INV5 and 2 into the NAND gates NAND1 and NAND2, and converts it into two non-overlapping clock signals,
  • the first non-overlapping clock signals CLK_i and CLK_b; the second non-overlapping clock signals are CLK_if and CLK_bf.
  • the first clock conversion unit 201 converts the clock signal CLK into two non-overlapping clock signals, which is a mature technology in the prior art, and will not be described in detail here.
  • the first clock conversion unit 201 needs to complete the level conversion function.
  • the voltage domain of the clock signal CLK is the power supply voltage VDD and the ground voltage VSS, where the power supply voltage VDD is the positive rail of the input signal voltage, and VSS is the negative rail of the input signal voltage; the first clock conversion unit 201 needs to convert the swing of the clock signal CLK to The positive rail value VDDi of the required conversion target voltage and the ground voltage VSS are in the voltage domain.
  • the positive voltage charge pump unit 202 includes a first NMOS transistor MN0 , a second NMOS transistor MN1 , a first PMOS transistor MP0 , a second PMOS transistor MP1 , a third NMOS transistor MN2 , a fourth NMOS transistor MN3 , and a third NMOS transistor MN3 .
  • the gate of the first NMOS transistor MN0 is connected to the fourth output end of the first clock conversion unit 201, the first NMOS transistor
  • the sources of the transistor MN0 and the second NMOS transistor MN1 are both grounded, the drain of the first NMOS transistor MN0 is respectively connected to one end of the second capacitor CF2 and the drain of the first PMOS transistor MP0, and the gate of the first PMOS transistor MP0 is connected to the first The second output terminal of the clock conversion unit 201, the gate of the second NMOS transistor MN1 is connected to the first output terminal of the first clock conversion unit 201, the drain of the second NMOS transistor MN1 is respectively connected to one end of the first capacitor CF1 and the second The drain of the PMOS transistor MP1, the gate of the second PMOS transistor MP1 are connected to the third output terminal of the first clock conversion unit 201, the second PMOS transistor MP
  • the first NMOS transistor MN0, the second NMOS transistor MN1, the first PMOS transistor MP0, and the second PMOS transistor MP1 are switch transistors, respectively, the third NMOS transistor MN2, the fourth NMOS transistor MN3, the third PMOS transistor MP2, the fourth The PMOS transistors MP3 are transmission transistors respectively; the first NMOS transistor MN0, the second NMOS transistor MN1, the first PMOS transistor MP0, and the second PMOS transistor MP1 are controlled by two complementary non-overlapping clock signals output by the first clock conversion unit 201
  • the turn-on and turn-off of the first capacitor CF1 and the second capacitor CF2 are realized successively, and the conduction through the third NMOS transistor MN2, the fourth NMOS transistor MN3, the third PMOS transistor MP2 and the fourth PMOS transistor MP3
  • the charges of the first capacitor CF1 and the second capacitor CF2 are transferred to the third capacitor Chold, thereby realizing a positive voltage output.
  • the non-overlapping clock signal CLK_i when the non-overlapping clock signal CLK_i is at a high level, that is, when the power supply voltage VDD is provided for the first clock conversion unit 201 , the non-overlapping clock signal CLK_b is at a low level level, that is, the ground voltage VSS is provided for the first clock conversion unit 201 , and at the same time, the levels of the non-overlapping clock signals CLK_if and CLK_bf are the power supply voltage VDD and the ground voltage VSS, respectively.
  • the first NMOS transistor MN0 and the second PMOS transistor MP1 are in an on state, and the first PMOS transistor MP0 and the second NMOS transistor MN1 are in an off state, so that the two ends of the first capacitor CF1 are respectively connected to the power supply voltage VDD
  • the fourth NMOS transistor MN3 is provided with a power supply voltage VDD whose gate voltage is twice as large, and the source voltage of the fourth NMOS transistor MN3 is VDD, so that the fourth NMOS transistor MN3 is in a conducting state, and the gate of the third PMOS transistor MP2
  • the voltage is the power supply voltage VDD, so that the third PMOS transistor MP2 is in an on state, so that the charges in the first capacitor CF1 are all transferred to the third capacitor Chold through the third PMOS transistor MP2, that is, the third capacitor Chold is charged, thereby Realize positive voltage output.
  • the gate voltage and source voltage of the third NMOS transistor MN2 are both the power supply voltage VDD, so that the third NMOS transistor MN2 is in the off state, the fourth PMOS transistor MP3 is also in the off state, and one end of the second capacitor CF2 is connected to the power supply
  • the voltage VDD is connected to the ground voltage VSS at the other end, so as to charge the second capacitor CF2.
  • the non-overlapping clock signal CLK_i is at a low level, that is, when the ground voltage VSS is provided for the first clock conversion unit 201
  • the non-overlapping clock signal CLK_b is at a high level, that is, the first clock conversion unit 201 is provided with power supply voltage VDD
  • the levels of the non-overlapping clock signals CLK_if and CLK_bf are the ground voltage VSS and the supply voltage VDD, respectively.
  • the second NMOS transistor MN1 and the first PMOS transistor MP0 are in an on state, and the first NMOS transistor MN0 and the second PMOS transistor MP1 are in an off state, so that the two ends of the second capacitor CF2 are respectively connected to the power supply voltage VDD
  • the gate voltage of the third NMOS transistor MN2 is provided with a power supply voltage VDD that is twice as large, and the source voltage of the third NMOS transistor MN2 is VDD, so that the third NMOS transistor MN2 is in a conducting state, and the gate of the fourth PMOS transistor MP3
  • the voltage is the power supply voltage VDD, so that the fourth PMOS transistor MP3 is in an on state, so that the charges in the second capacitor CF2 are all transferred to the third capacitor Chold through the fourth PMOS transistor MP3, that is, the third capacitor Chold is charged, thereby Realize positive voltage output.
  • the gate voltage and source voltage of the fourth NMOS transistor MN3 are both the power supply voltage VDD, so that the fourth NMOS transistor MN3 is in the off state, the third PMOS transistor MP2 is also in the off state, and one end of the first capacitor CF1 is connected to the power supply The voltage VDD, and the other end is connected to the ground voltage VSS, so as to charge the first capacitor CF1. After several cycles, the charges in the first capacitor CF1 and the second capacitor CF2 are transferred, so that the positive voltage output terminal VDDH finally reaches the output voltage VDD that is twice the power supply voltage.
  • the non-overlapping clock signals CLK_if and CLK_bf respectively correspond to the non-overlapping clock signals whose phases are advanced by the non-overlapping clock signals CLK_i and CLK_b, and the non-overlapping clock signal CLK_if and the non-overlapping clock signal CLK_i are in the same phase
  • the non-overlapping clock signals, the non-overlapping clock signals CLK_bf and the non-overlapping clock signals CLK_b are in-phase non-overlapping clock signals; the non-overlapping clock signals CLK_if and CLK_bf can avoid the PMOS transistor and NMOS in the positive voltage charge pump unit 202 The problem of simultaneous conduction of the tubes occurs.
  • a plurality of positive voltage charge pump units 202 can be cascaded, that is, the second positive voltage charge pump unit 202 Initially, the input voltage Vin of each positive voltage charge pump unit 202 is connected to the positive voltage output terminal VDDH of the previous positive voltage charge pump unit 202 .
  • the transient enhancement module 102 includes a voltage sampling and comparison unit 301 and a voltage switching unit 302.
  • the input terminal of the voltage sampling and comparison unit 301 is connected to the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 and the power supply voltage VDD.
  • the voltage The output terminal of the sampling and comparison unit 301 is connected to the input terminal of the voltage switching unit 302 .
  • the positive voltage output by the positive voltage charge pump unit 202 and the power supply voltage VDD are sampled by the voltage sampling and comparison unit 301, and the positive voltage and the power supply voltage VDD are converted into corresponding currents for comparison, so that the node VDET outputs the state of the detection signal, and the voltage switching unit 302 performs necessary level conversion processing on the state of the detection signal and then controls the switch to switch the voltage, thereby providing a switchable input voltage for the negative voltage charge pump module 103, thereby improving the speed and speed of the negative voltage charge pump module 103 generating a negative voltage. efficiency.
  • the voltage sampling and comparison unit 301 includes a first resistor R1, a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a fifth PMOS transistor MP4, and a sixth PMOS transistor
  • the tube MP5, the second resistor R2, the third resistor R3, and the fourth capacitor C1; one end of the first resistor R1, the source of the fifth PMOS tube MP4 and the sixth PMOS tube MP5 are respectively connected to the power supply voltage VDD, and the first resistor R1 is connected to the power supply voltage VDD.
  • the other end is respectively connected to the drain and gate of the fifth NMOS transistor MN4, the gate of the sixth NMOS transistor MN5, and the drain of the sixth NMOS transistor MN5 is respectively connected to the drain and gate of the fifth PMOS transistor MP4, and the sixth PMOS transistor
  • the gate of the transistor MP5, the drain of the sixth PMOS transistor MP5 are respectively connected to one end of the fourth capacitor C1 and one end of the third resistor R3, the drain of the seventh NMOS transistor MN6 and the voltage switching unit 302, and the seventh NMOS transistor MN6
  • the gate is respectively connected to the gate and drain of the eighth NMOS transistor MN7 and one end of the second resistor R2, the other end of the second resistor R2 is connected to the positive voltage output terminal VDDH of the positive voltage charge pump unit 202, the eighth NMOS transistor MN7 and the The source of the seventh NMOS transistor MN6, the other end of the third resistor R3 and the fourth capacitor C1, and the sources of the sixth NMOS transistor MN5 and
  • the working principle of the voltage sampling and comparison unit 301 is: sampling the output voltage of the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 through the second resistor R2 and the eighth NMOS transistor MN7, and converting the positive voltage into a corresponding current.
  • the seventh NMOS transistor MN6 is replicated according to the preset ratio; the supply voltage VDD is sampled through the first resistor R1 and the fifth NMOS transistor MN4, and the supply voltage VDD is converted into a corresponding current, which passes through the sixth NMOS transistor MN5 in sequence , the fifth PMOS transistor MP4 and the sixth PMOS transistor MP5 are replicated according to a preset ratio; wherein, the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 and the power supply voltage VDD are sampled and converted into corresponding currents, The current is correspondingly copied to the drain of the eighth NMOS transistor MN7 and the drain of the sixth PMOS transistor MP5 according to the preset ratio, which are respectively expressed as:
  • R 1 is the first resistor
  • R 2 is the second resistor
  • ⁇ 0 ⁇ nCoxW0/L0
  • ⁇ 3 ⁇ nCoxW3/L3
  • un is the electron mobility
  • Cox is the gate oxide capacitance
  • W0/L0 is the fifth NMOS
  • the width-length ratio of the tube MN4, W3/L3 is the width-length ratio of the eighth NMOS tube MN7
  • VDDH is the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit
  • VDD is the power supply voltage
  • VT is the circuit design threshold Voltage.
  • the current in the sixth PMOS transistor MP5 is greater than the current in the seventh NMOS transistor MN6, so that the state of the detection signal output by the node VDET is Close to the high level of the power supply voltage VDD, as the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 gradually increases, the I D7 current will also increase accordingly;
  • the positive voltage output by the voltage output terminal VDDH exceeds the circuit design threshold voltage or reaches the target steady state (such as reaching twice the supply voltage VDD)
  • the current in the seventh NMOS transistor MN6 is much larger than the current in the sixth PMOS transistor MP5, and the node VDET outputs
  • the state of the detection signal is to jump from a high-level power supply voltage VDD to a low-level ground voltage VSS output; thereby realizing the dynamic detection of the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump
  • the voltage switching unit 302 includes a hysteresis inverter 3020, a logic level conversion subunit 3021 and a switch subunit 3022; the input end of the hysteresis inverter 3020 is connected to the output end of the voltage sampling and comparison unit 301, and the hysteresis inverter The output end of the phase converter 3020 is connected to the input end of the logic level conversion subunit 3021 , and the output end of the logic level conversion subunit 3021 is connected to the input end of the switch subunit 3022 .
  • the hysteresis inverter 3020 includes a ninth NMOS transistor MN8, a tenth NMOS transistor MN9, an eleventh NMOS transistor MN10, a seventh PMOS transistor MP6, an eighth PMOS transistor MP7, a ninth PMOS transistor MP8, and a seventh PMOS transistor MP6.
  • the gates of the nine NMOS transistors MN8, the tenth NMOS transistor MN9, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 are connected together as the input terminals of the hysteresis inverter 3020, and are used to connect the node VDET of the sampling and comparison unit 301 to Receiving the state of the detection signal output by the voltage sampling and comparison unit 301, the drain of the ninth NMOS transistor MN8 and the source of the tenth NMOS transistor MN9 are respectively connected to the drain of the ninth PMOS transistor MP8, and the drain of the tenth NMOS transistor MN9 is connected to the drain of the ninth PMOS transistor MP8.
  • the drain of the eighth PMOS transistor MP7, the gate of the ninth PMOS transistor MP8 and the eleventh NMOS transistor MN10 are connected to each other as the output terminal of the hysteresis inverter 3020, and the source of the eighth PMOS transistor MP7 and the seventh PMOS transistor MP6
  • the drain of the ninth NMOS transistor MN10 is connected to the drain of the eleventh NMOS transistor MN10 respectively, the sources of the seventh PMOS transistor MP6 and the ninth PMOS transistor MP8 are respectively connected to the supply voltage VDD, and the sources of the ninth NMOS transistor MN8 and the eleventh NMOS transistor MN10 ground.
  • the operating voltage domain of the hysteresis inverter 3020 is the supply voltage VDD and the ground voltage VSS.
  • the main function of the hysteresis inverter 3020 is to shape the state of the detection signal output by the voltage sampling and comparison unit 301 to obtain a logic level opposite to the state of the detection signal, and to achieve a certain hysteresis function to prevent the power supply voltage VDD and detection.
  • the state of the signal has a glitch level, which makes the circuit work more safely and reliably.
  • the logic level conversion sub-unit 3021 includes a sixth inverter INV6, a seventh inverter INV7, a twelfth NMOS transistor MN11, a thirteenth NMOS transistor MN12, a fourteenth NMOS transistor MN13, and a thirteenth NMOS transistor MN13.
  • the drain of the PMOS transistor MP10, one end of the fifth capacitor C2, and one input end of the fourth NAND gate NAND4, and the other end of the fifth capacitor C2 is respectively connected to the drain of the fourteenth PMOS transistor MP13 and the seventeenth NMOS transistor MN16
  • the drain of the seventeenth NMOS transistor MN16 is connected to the drain of the thirteenth NMOS transistor MN12
  • the gate of the twelfth NMOS transistor MN11 is connected to the drain of the fifth NMOS transistor
  • the drain of the twelfth NMOS transistor MN11 poles are respectively connected to the thirteenth PMOS transistor MP12
  • the drain and gate, the gates of the sixteenth NMOS transistor MN15 and the fifteenth NMOS transistor MN14, and the source of the thirteenth PMOS transistor MP12 are respectively connected to the drain and gate of the twelfth PMOS transistor MP11, and the eleventh
  • the source of the fifteenth PMOS transistor MP14 is respectively connected to the negative rail voltage VDDL of the voltage domain where it is located, and the other input terminal of the third NAND gate NAND3 is respectively connected to the output terminal of the fourth NAND gate NAND4 and the other side of the switch subunit 3022
  • the input terminal, the output terminal of the third NAND gate NAND3 is connected to the other input terminal of the fourth NAND gate NAND4.
  • the switch subunit 3022 includes a sixteenth PMOS transistor MP15 and a seventeenth PMOS transistor MP16, and the gate of the sixteenth PMOS transistor MP15 is used as another input end of the switch subunit 3022 for connecting the fourth The output terminal of the NAND gate NAND4, the source of the sixteenth PMOS transistor MP15 is connected to the positive voltage output terminal VDDH of the positive voltage charge pump unit 202, and the gate of the seventeenth PMOS transistor MP16 is used as an input terminal of the switch subunit 3022, It is used to connect the output terminal of the seventh inverter INV7, the source of the seventeenth PMOS transistor MP16 is connected to the power supply voltage VDD, and the drains of the seventeenth PMOS transistor MP16 and the sixteenth PMOS transistor MP15 are used as the output of the switch sub-unit 3022 The terminal is used for the output voltage VDD_neg, and is implemented to provide a switchable input voltage for the negative voltage charge pump module 103 .
  • the voltage domain in which the third NAND gate NAND3 and the fourth NAND gate NAND4 work is the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 (the value of the positive rail voltage in the voltage domain) and the Negative rail voltage VDDL of the voltage domain.
  • the negative rail voltage VDDL in the voltage domain is set to the power supply voltage VDD.
  • the output voltage VDD_neg of the transient enhancement module 102 is selected by controlling the gate voltages of the sixteenth PMOS transistor MP15 and the seventeenth PMOS transistor MP16.
  • the current of the fifth NMOS transistor MN4 in the voltage sampling and comparison unit 301 is copied according to a preset ratio through the twelfth NMOS transistor MN11, the twelfth PMOS transistor MP11 is connected to the thirteenth PMOS transistor MP12, and the thirteenth PMOS transistor MP12 is Diode connection, the tenth PMOS transistor MP9, the eleventh PMOS transistor MP10 and the twelfth PMOS transistor MP11 are proportional mirror current sources, and the thirteenth PMOS transistor MP12 provides the sixteenth NMOS transistor MN15 and the fifteenth NMOS transistor MN14.
  • the static gate voltage is controlled by the narrow pulse signal RST for the gate voltage of the fourteenth PMOS transistor MP13, the fifteenth PMOS transistor MP14, the seventeenth NMOS transistor MN16, and the eighteenth NMOS transistor MN17 to realize the fifth capacitor.
  • C2 and the sixth capacitor C3 are pre-charged, the capacitance values of the fifth capacitor C2 and the sixth capacitor C3 are equal, and the two capacitor charges are initialized. , generate a narrow pulse signal RST, and use this signal RST to realize the level conversion of the detection signal output by the node VDET.
  • the working process of the transient enhancement module 102 is as follows: when the circuit is powered on, the positive voltage charge pump module 101 starts to work, and the positive voltage output from the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 gradually starts from the supply voltage VDD.
  • the state of the detection signal output by the node VDET is close to the high level of the supply voltage VDD
  • the sixth inverter INV6 and the seventh inverter INV7 the first The gate voltages of the thirteenth NMOS transistor MN12 and the fourteenth NMOS transistor MN13 are the power supply voltage VDD and the ground voltage VSS, respectively, so that the thirteenth NMOS transistor MN12 is in an on state, and the fourteenth NMOS transistor MN13 is in an off state.
  • the gate voltage XL provided by the seventeenth PMOS transistor MP16 serving as a switch transistor provides the ground voltage VSS, so that the seventeenth PMOS transistor MP16 is in a conducting state.
  • the state of the detection signal output by the node VDET changes, it is shaped by the hysteresis inverter 3020, so that the output signal of the X node also changes state.
  • the output signal passes through the digital delay units D1-D4 and XOR After the combinational logic of the gate XOR1, a narrow pulse signal RST whose high level is the power supply voltage VDD is generated, and the signal RST is used to realize the level conversion of the detection signal output by the node VDET.
  • the detection signal output by the node VDET jumps from the ground voltage VSS to the power supply voltage VDD
  • the X node voltage jumps from the power supply voltage VDD to the ground voltage VSS, and passes through the digital delay units D1 ⁇ D4 and XOR
  • a narrow pulse signal RST whose high level is the power supply voltage VDD is generated; when the level of the narrow pulse signal RST is the ground voltage VSS, the fourteenth PMOS transistor MP13 and the fifteenth PMOS transistor MP14 is turned on, the seventeenth NMOS transistor MN16 and the eighteenth NMOS transistor MN17 are turned off, then the plates A and B of the fifth capacitor C2 and the sixth capacitor C3 are precharged to the supply voltage VDD, while the fifth capacitor C2 and the sixth capacitor C3 are precharged to the supply voltage VDD.
  • the plates C and D of the six capacitors C3 are charged by the tenth PMOS transistor MP9 and the
  • the fourteenth PMOS transistor MP13 and the fifteenth PMOS transistor MP14 are turned off, the seventeenth NMOS transistor MN16 and the eighteenth NMOS transistor MN17 are turned on, because the thirteenth NMOS transistor MN12 is turned on.
  • the fourteenth NMOS transistor MN13 is turned off, so the voltage of the A plate of the fifth capacitor C2 is quickly pulled to the ground voltage VSS, and the voltage of the plate C of the fifth capacitor C2 also drops rapidly;
  • the sixteenth NMOS transistor MN15 is turned on, pulling up the voltage of the plate C of the fifth capacitor C2; until the sixteenth NMOS transistor MN15 is turned off, the fourteenth NMOS transistor MN13 will The voltage of the plate C of the fifth capacitor C2 is charged to be equal to the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 and equal to the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202.
  • the fourteenth NMOS transistor MN13 is in an off state, the voltage across the sixth capacitor does not change;
  • the fourteenth PMOS transistor MP13 and the fifteenth PMOS transistor MP14 are turned on again, the seventeenth NMOS transistor MN16 and the eighteenth NMOS transistor MN17 are turned off, and the fifth capacitor C2 and The sixth capacitor C3 is in a precharged state again, waiting for the next narrow pulse of the narrow pulse signal RST to be triggered.
  • the voltage on the plate D of the sixth capacitor C3 does not change in the whole process, and still remains equal to the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202;
  • the C voltage first decreases and then increases to be equal to the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202.
  • the fourth NAND gate NAND4 The output voltage XH is pulled up to be equal to the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 , so the sixteenth PMOS transistor MP15 serving as a switch transistor is in an off state. Since the seventeenth PMOS transistor MP16 is turned on and the sixteenth PMOS transistor MP15 is turned off, the output voltage VDD_neg of the voltage switching unit 302 in this state is equal to the power supply voltage VDD.
  • the detection signal output by the node VDET jumps from the high-level power supply voltage VDD to the low-level ground voltage VSS.
  • the gate voltages of the thirteenth NMOS transistor MN12 and the fourteenth NMOS transistor MN13 are the ground voltage VSS and the power supply voltage VDD, respectively, so that the fourteenth NMOS transistor MN13 is in an on state and the thirteenth NMOS transistor MN12 is in an off state. Therefore, the thirteenth NMOS transistor MN12 is in an off state.
  • the seventeen PMOS tube MP16 is in the off state; at the same time, the X node voltage jumps from the ground voltage VSS to the power supply voltage VDD, and after the combinational logic sub-unit composed of the digital delay units D1 ⁇ D4 and the exclusive OR gate XOR1, a high level is generated It is the narrow pulse signal RST of the power supply voltage VDD, which is an effective detection pulse, so that the voltage of the plate D of the sixth capacitor C3 will first drop and then rise, while the voltages of the two plates of the fifth capacitor C2 remain unchanged, so the third and non- The voltage output by the gate NAND3 is equal to the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 that has completed the establishment or reached the target voltage, and the output voltage of the fourth NAND gate NAND4 is the low-level power supply voltage VDD, so that the first The voltage XH output by the four NAND gate NAND4 is the power supply voltage VDD, and at this time, the sixteenth PMOS transistor MP15 is in
  • the output voltage VDD_neg of the voltage switching unit 302 is the same as the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 that is established or reaches the target voltage.
  • the positive voltages of the outputs are equal.
  • the negative voltage charge pump module 103 generates a negative voltage output according to the clock signal generated by the clock generation module 100 and the clock swing voltage VDD_neg provided by the transient enhancement module 102 .
  • the negative voltage charge pump module 103 includes a second clock conversion unit 401 and a negative voltage charge pump unit 402.
  • the input end of the second clock conversion unit 401 is connected to the output end of the clock generation module 100, and the second clock conversion unit
  • the output terminal of 401 is connected to the input terminal of the negative voltage charge pump unit 402
  • the input terminal of the negative voltage charge pump unit 402 is connected to the output terminal of the voltage switching unit 302 .
  • the second clock converting unit 401 is configured to convert the clock signal output by the clock generating module 100 to generate two complementary non-overlapping clock signals.
  • the second clock conversion unit 401 includes an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12,
  • the input end of the eighth inverter INV8 is connected to the output end of the clock generating module 100 and an input end of the sixth NAND gate NAND6, and the The output end is connected to an input end of the fifth NAND gate NAND5, the output end of the fifth NAND gate NAND5 is connected to the input end of the ninth inverter INV9, and the output end of the ninth inverter INV9 is connected to the fifth output end and the first
  • the input end of the inverter INV11, the output end of the eleventh inverter INV11 is connected to the eighth output end and the input end of the twelfth inverter INV12, and the output end of the twelfth inverter INV12 is connected to the fifth NAND gate
  • the second clock conversion unit 401 receives the clock signal CLK output by the clock generation module 100, and inputs the clock signal CLK through the inverters INV8-INV12 and 2 to the NAND gates NAND5 and NAND6, and converts it into two non-overlapping clock signals,
  • the first non-overlapping clock signals CLK_i′ and CLK_b′; the second non-overlapping clock signals are CLK_if′ and CLK_bf′.
  • the operating voltage domains of the 2-input NAND gates NAND5 and NAND6 are the output voltage VDD_neg and the ground voltage VSS of the voltage switching unit 302 .
  • the second clock conversion unit 401 converts the clock signal CLK into two non-overlapping clock signals, which is a mature technology in the prior art, and will not be described in detail here.
  • the negative voltage charge pump unit 402 includes an eighteenth PMOS transistor MP17, a nineteenth PMOS transistor MP18, a nineteenth NMOS transistor MN18, a twentieth NMOS transistor MN19, a twentieth PMOS transistor MP19, a second The eleventh PMOS transistor MP20, the twenty-first NMOS transistor MN20, the twenty-second NMOS transistor MN21, the seventh capacitor CF3, the eighth capacitor CF4 and the ninth capacitor Chold1; the gate of the eighteenth PMOS transistor MP17 is connected to the second clock
  • the eighth output terminal of the conversion unit 401, the drains of the eighteenth PMOS transistor MP17 and the nineteenth PMOS transistor MP18 are respectively connected to the output voltage VDD_neg of the voltage switching unit 302, and the sources of the eighteenth PMOS transistor MP17 are respectively connected to the eighth capacitor
  • One end of CF4 is connected to the source of the nineteenth NMOS transistor MN18, the gate of the nineteenth NMOS transistor MN18 is connected to the
  • the gate is respectively connected to the source of the twentieth PMOS transistor MP19, the other end of the seventh capacitor CF3, the gate of the twenty-second NMOS transistor MN21 and the source of the twenty-first NMOS transistor MN20, and the twentieth PMOS transistor MP19
  • the gate is connected to the source of the twenty-first PMOS transistor MP20, the other end of the eighth capacitor CF4, the gate of the twenty-first NMOS transistor MN20 and the source of the twenty-second NMOS transistor MN21, respectively.
  • the drains of the NMOS transistor MN20 and the twenty-second NMOS transistor MN21 are both connected to the ninth capacitor Chold1 and the negative voltage output terminal VSSH, and the other end of the ninth capacitor Chold1 is grounded.
  • the positive voltage charge pump unit 202 and the negative voltage charge pump unit 402 work at the same time, if the positive rail voltage of the positive and negative voltage charge pump circuit voltage domain is the supply voltage VDD, and the negative rail voltage is the ground voltage VSS, the voltage generated by the positive voltage charge pump unit 202 will be quickly established to the target voltage; during this process, the transient enhancement module 102 samples the supply voltage VDD and the positive voltage output by the positive voltage output terminal VDDH of the positive voltage charge pump unit 202 , if the positive voltage of the sampled positive voltage charge pump unit 202 does not reach the target value, the supply voltage VDD is used as the input voltage of the negative voltage charge pump unit 402.
  • the non-overlapping clock signal CLK_i' When the non-overlapping clock signal CLK_i' is at a high level, the non-overlapping clock signal CLK_b' is a low level, and at the same time, the levels of the non-overlapping clock signals CLK_if' and CLK_bf' are the power supply voltage VDD and the ground voltage VSS, respectively.
  • the eighteenth PMOS transistor MP17 and the twentieth NMOS transistor MN19 are in an on state, and the nineteenth NMOS transistor MN18 and the nineteenth NMOS transistor MN18 are in an off state, so that both ends of the seventh capacitor CF3 are respectively connected
  • the power supply voltage VDD realizes that the gate voltage provided to the twenty-first PMOS transistor MP20 is the ground voltage VSS-supply voltage VDD, and the source voltage of the twenty-first PMOS transistor MP20 is VDD, so that the twenty-first PMOS transistor MP20 is in conduction.
  • the gate voltage of the twenty-first NMOS transistor MN20 is the power supply voltage VDD, so that the twenty-first NMOS transistor MN20 is in an on state, so that all the charges in the seventh capacitor CF3 are passed through the twenty-first NMOS transistor MN20. It is transferred to the ninth capacitor Chold1, that is, the ninth capacitor Chold1 is charged, so as to realize a negative voltage output.
  • the voltage VDD_neg provided by the transient enhancement module 102 to the negative voltage charge pump unit 402 is the supply voltage VDD
  • the negative voltage VSSH generated by the negative voltage charge pump unit 402 is the ground voltage VSS-supply voltage VDD.
  • the twentieth PMOS transistor MP19 and the twenty-second NMOS transistor MN21 are in the off state, and one end of the eighth capacitor CF4 is connected to the power supply voltage VDD, and the other end is connected to the ground voltage VSS to charge the eighth capacitor CF4.
  • the positive voltage of the positive voltage charge pump unit 202 When the positive voltage of the positive voltage charge pump unit 202 reaches the target value, the positive voltage of the positive voltage charge pump unit 202 is used as the input voltage of the negative voltage charge pump unit 402, and the nineteenth PMOS transistor is controlled by the non-overlapping clock signal at this time.
  • MP18 and the nineteenth NMOS transistor MN18 are in the conducting state
  • the eighteenth PMOS transistor MP17 and the twentieth NMOS transistor MN19 are in the off state
  • the twentieth PMOS transistor MP19 and the twenty-second NMOS transistor MN21 are in the conducting state
  • the twentieth PMOS transistor MP19 and the twenty-second NMOS transistor MN21 are in the conducting state.
  • the voltage VDD_neg provided by the pump unit 402 is the positive voltage of the positive voltage charge pump unit 202 .
  • the negative voltage VSSH generated by the negative voltage charge pump unit 402 is the ground voltage VSS - the positive voltage of the positive voltage charge pump unit 202 .
  • the negative voltage charge pump unit 402 will draw current from the positive voltage charge pump unit 202 to complete its own negative voltage establishment. It can be seen from this that the establishment time of the output voltage of the positive voltage charge pump unit 202 will not be affected by the operation of the negative voltage charge pump unit 402. At the same time, during the establishment of the positive voltage, the negative voltage charge pump unit 402 has been established to ground in advance The voltage VSS - the voltage of the supply voltage VDD, when the output voltage of the positive voltage charge pump unit 202 reaches a stable state, the voltage is used to complete the generation of the negative voltage, thereby speeding up the negative voltage establishment time of the negative voltage charge pump unit 402 .
  • non-overlapping clock signals CLK_if′ and CLK_bf′ correspond to the non-overlapping clock signals CLK_i′ and CLK_b′ leading-phase clock signals respectively, and the clock signals CLK_if′ and CLK_i′ are in-phase, and the clock signals CLK_bf′ and CLK_b′ are in-phase clock signals;
  • the non-overlapping clock signals CLK_if′ and CLK_bf′ can avoid the problem that the PMOS transistor and the NMOS transistor in the negative voltage charge pump unit 402 are turned on at the same time.
  • the positive and negative voltage charge pump circuits provided in the embodiments of the present invention can be used in integrated circuit chips.
  • the specific structures of the positive and negative voltage charge pump circuits in the integrated circuit chip will not be described in detail here.
  • the above positive and negative voltage charge pump circuits can also be used in communication terminals as an important part of analog integrated circuits.
  • the communication terminal mentioned here refers to the computer equipment that can be used in the mobile environment and supports various communication standards such as GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including mobile phones, notebook computers, tablet computers, car computers, etc.
  • GSM Global System for Mobile communications
  • EDGE TD_SCDMA
  • TDD_LTE Time Division Duplex
  • FDD_LTE Frequency Division Duplex
  • the technical solutions provided by the embodiments of the present invention are also applicable to other analog integrated circuit applications, such as communication base stations.
  • the positive and negative voltage charge pump circuit provided by the embodiment of the present invention generates a positive voltage through a positive voltage charge pump module, and at the same time adopts a transient enhancement module to sample the positive voltage and the power supply voltage, convert it into a current for comparison, and realize a negative voltage according to the comparison result.
  • the voltage charge pump module provides a switchable input voltage, and the negative voltage charge pump module can not only quickly and reliably establish a negative voltage according to the clock signal output by the clock generation module, thereby improving the speed and efficiency of the negative voltage charge pump module to generate negative voltage, but also Different negative pressure requirements can be flexibly realized.

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Abstract

一种正负电压电荷泵电路，包括时钟发生模块、正电压电荷泵模块、瞬态增强模块和负电压电荷泵模块。正电压电荷泵模块根据时钟发生模块输出的时钟信号产生正电压，同时采用瞬态增强模块将该正电压和供电电压进行采样并转换成电流进行比较，根据比较结果实现为负电压电荷泵模块提供可切换的输入电压，负电压电荷泵模块根据时钟发生模块输出的时钟信号不仅能够快速可靠的建立负电压，进而提高负电压电荷泵模块产生负电压的速度和效率，而且还可以灵活地实现不同负压的要求。还公开了包括上述正负电压电荷泵电路的集成电路芯片和通信终端。

Description

一种正负电压电荷泵电路、芯片及通信终端 技术领域
本发明涉及一种正负电压电荷泵电路，同时也涉及包括该正负电压电荷泵电路的集成电路芯片及相应的通信终端，属于模拟集成电路技术领域。
背景技术
随着集成电路集成度的不断提高，工艺节点不断向深亚微米极限演进，以及芯片应用环境的多元化，电荷泵电路作为一个基本的模块电路，广泛应用于各种集成电路产品中。电荷泵电路的主要作用是为系统提供高于输入电源电压正轨的正电压源，以及低于输入电源电压负轨的负电压源，从而更好地满足系统设计指标。尽管正电源高压电荷泵电路已经在较多的应用场景出现，但是随着系统指标要求的不断提高，越来越多的电子系统内部需要能够同时产生正向高压和负向高压来稳定可靠的工作。因此，对于能够提供稳定可靠，且同时产生高于输入电源正轨以及低于输入电源负轨电压的电荷泵电路设计的需求日益紧迫。
在专利号为ZL 200810142157.2的中国发明专利中，公开了一种正负高压的电荷泵电路，其工作原理是基于非对称交叉耦合单边级联电荷泵结构，并通过选择器来实现正高压或者负高压输出。但是，该电路无法做到同时输出正电源电压和负电源电压。另外，在专利号为ZL 201610004368.4中公开了一种产生正负电压源的电荷泵电路，其采用了三相分频器实现了固定脉冲序列的三个时钟信号来控制电容充放电实现正负电压源的输出。尽管该电路可以实现正、负电压源输出，但是其输出电压源的绝对值都比输入电压源低，使得在实际应用中存在很大的局限性。
发明内容
本发明所要解决的首要技术问题在于提供一种正负电压电荷泵电路。
本发明所要解决的另一技术问题在于提供一种包括正负电压电荷 泵电路的芯片及相应的通信终端。
为了实现上述目的，本发明采用下述技术方案：
根据本发明实施例的第一方面，提供一种正负电压电荷泵电路，包括时钟发生模块、正电压电荷泵模块、瞬态增强模块和负电压电荷泵模块，所述时钟发生模块的输出端连接所述正电压电荷泵模块和所述负电压电荷泵模块的输入端，所述正电压电荷泵模块的输出端连接所述瞬态增强模块的输入端，所述瞬态增强模块的输出端连接所述负电压电荷泵模块的输入电源端，所述时钟发生模块、所述正电压电荷泵模块和所述瞬态增强模块的电源端均连接供电电压；
所述正电压电荷泵模块根据所述时钟发生模块输出的时钟信号产生正电压，所述正电压与所述供电电压作为输入电压源被所述瞬态增强模块采样并转换成电流后进行比较，根据比较结果为所述负电压电荷泵模块提供可切换的输入电压，使得所述负电压电荷泵模块根据所述时钟发生模块输出的时钟信号产生负电压。
其中较优地，所述正电压电荷泵模块包括第一时钟转换单元和至少一个正电压电荷泵单元，所述第一时钟转换单元的输入端连接所述时钟发生模块的输出端，所述第一时钟转换单元的输出端连接每个所述正电压电荷泵单元的输入端。
其中较优地，所述第一时钟转换单元包括第一反相器、第二反相器、第三反相器、第四反相器、第五反相器、第一与非门和第二与非门；所述第一反相器的输入端连接所述时钟发生模块的输出端与所述第二与非门的一个输入端，所述第一反相器的输出端连接所述第一与非门的一个输入端，所述第一与非门的输出端连接所述第二反相器的输入端，所述第二反相器的输出端连接第一输出端与所述第三反相器的输入端，所述第三反相器的输出端连接所述第二与非门的另一个输入端与第二输出端，所述第二与非门的输出端连接所述第四反相器的输入端，所述第四反相器的输出端连接第四输出端与所述第五反相器的输入端，所述第五反相器的输出端连接所述第一与非门的另一个输入端与第三输出端。
其中较优地，当采用多个所述正电压电荷泵单元时，从第二个正电压电荷泵单元开始，每一个正电压电荷泵单元的输入电压连接其上 一个正电压电荷泵单元的正压输出端。
其中较优地，所述正电压电荷泵单元包括第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、第三NMOS管、第四NMOS管、第三PMOS管、第四PMOS管、第一电容、第二电容和第三电容；所述第一NMOS管的栅极连接第一时钟转换单元的第四输出端，所述第一NMOS管与所述第二NMOS管的源极分别接地，所述第一NMOS管漏极分别连接所述第二电容的一端与所述第一PMOS管的漏极，所述第一PMOS管的栅极连接所述第一时钟转换单元的第二输出端，所述第二NMOS管的栅极连接所述第一时钟转换单元的第一输出端，所述第二NMOS管的漏极分别连接所述第一电容的一端与所述第二PMOS管的漏极，所述第二PMOS管的栅极连接所述第一时钟转换单元的第三输出端，所述第二PMOS管、所述第一PMOS管、所述第三NMOS管和所述第四NMOS管的源极均连接输入电压，所述第四NMOS管的栅极分别连接所述第三NMOS管漏极、所述第一电容的另一端、所述第四PMOS管的栅极和所述第三PMOS管的漏极，所述第三NMOS管的栅极分别连接所述第四NMOS管漏极、所述第二电容的另一端、所述第三PMOS管的栅极和所述第四PMOS管的漏极，所述第三PMOS管与所述第四PMOS管的源极均连接所述第三电容的一端和正压输出端，所述第三电容的另一端接地。
其中较优地，所述瞬态增强模块包括电压采样比较单元和电压切换单元，所述电压采样比较单元的输入端连接所述正电压电荷泵单元的正压输出端和供电电压，所述电压采样比较单元的输出端连接所述电压切换单元的输入端。
其中较优地，所述电压采样比较单元包括第一电阻、第五NMOS管、第六NMOS管、第七NMOS管、第八NMOS管、第五PMOS管、第六PMOS管、第二电阻、第三电阻、第四电容；所述第一电阻的一端、所述第五PMOS管与所述第六PMOS管的源极分别连接供电电压，所述第一电阻的另一端分别连接所述第五NMOS管的漏极和栅极、所述第六NMOS管的栅极，所述第六NMOS管的漏极分别连接所述第五PMOS管的漏极与栅极、所述第六PMOS管的栅极，所述第六PMOS管的漏极分别连接所述第四电容的一端与所述第三电阻的一端、所述第七NMOS管的漏极以及所述电压切换单元，所述第七NMOS管的栅极分别连接所述第八 NMOS管的栅极与漏极以及所述第二电阻的一端，所述第二电阻的另一端连接所述正电压电荷泵单元的正压输出端,所述第八NMOS管与所述第七NMOS管的源极、所述第三电阻与所述第四电容的另一端以及所述第六NMOS管与所述第五NMOS管的源极均接地。
其中较优地，所述电压切换单元包括迟滞反相器、逻辑电平转换子单元和开关子单元；所述迟滞反相器的输入端连接所述电压采样比较单元的输出端，所述迟滞反相器的输出端连接所述逻辑电平转换子单元的输入端，所述逻辑电平转换子单元的输出端连接所述开关子单元的输入端。
其中较优地，所述逻辑电平转换子单元包括第六反相器、第七反相器、第十二NMOS管、第十三NMOS管、第十四NMOS管、第十五NMOS管、第十六NMOS管、第十七NMOS管、第十八NMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第十三PMOS管、第十四PMOS管、第十五PMOS管、第五电容、第六电容、第三与非门、第四与非门、异或门和多个数字延迟单元；所述第六反相器的输入端连接所述迟滞反相器的输出端，所述第六反相器的输出端连接所述第七反相器的输入端、所述第十三NMOS管的栅极，所述第七反相器的输出端连接所述开关子单元的一个输入端、所述第十四NMOS管的栅极；X节点分别连接所述迟滞反相器的输出端、第一数字延迟单元的输入端、所述异或门的一个输入端，所述第一数字延迟单元的输出端到最后一个数字延迟单元的输入端之间串联多个数字延迟单元，最后一个数字延迟单元的输出端连接所述异或门的另一个输入端，所述异或门的输出端分别连接所述第十八NMOS管与所述第十七NMOS管的栅极以及所述第十四PMOS管与所述第十五PMOS管的栅极，所述第十五PMOS管的漏极分别连接所述第六电容的一端、所述第十八NMOS管的漏极，所述第十八NMOS管的源极连接所述第十四NMOS管的漏极，所述第六电容的另一端分别连接所述第十五NMOS管的源极、所述第三与非门的一个输入端、所述第十PMOS管的漏极，所述第十五NMOS管的漏极分别连接所述第十六NMOS管的漏极，所述第十六NMOS管的源极分别连接所述第十一PMOS管的漏极、所述第五电容的一端以及所述第四与非门的一个输入端，所述第五电容的另一端分别连接所述第十四PMOS管的漏极、所述 第十七NMOS管的漏极，所述第十七NMOS管的源极连接所述第十三NMOS管的漏极，所述第十二NMOS管的栅极连接所述第五NMOS管的漏极，所述第十二NMOS管的漏极分别连接所述第十三PMOS管的漏极和栅极、所述第十六NMOS管与所述第十五NMOS管的栅极，所述第十三PMOS管的源极分别连接所述第十二PMOS管的漏极和栅极、所述第十一PMOS管与所述第十PMOS管的栅极，所述第十二PMOS管、所述第十一PMOS管、所述第十PMOS管的源极和所述第十五NMOS管的漏极、所述第十六NMOS管的漏极均连接所述正电压电荷泵单元的正压输出端，所述第十四NMOS管、所述第十三NMOS管和所述第十二NMOS管的源极分别接地，所述第十四PMOS管与所述第十五PMOS管的源极分别连接所在电压域的负轨电压，所述第三与非门的另一个输入端分别连接所述第四与非门的输出端、所述开关子单元的另一个输入端，所述第三与非门的输出端连接所述第四与非门的另一个输入端。
其中较优地，所述开关子单元包括第十六PMOS管与第十七PMOS管，所述第十六PMOS管的栅极连接所述第四与非门的输出端，所述第十六PMOS管的源极连接所述正电压电荷泵单元的正压输出端，所述第十七PMOS管的栅极连接所述第七反相器的输出端，所述第十七PMOS管的源极连接供电电压，所述第十七PMOS管与所述第十六PMOS管的漏极作为所述开关子单元的输出端。
其中较优地，所述负电压电荷泵模块包括第二时钟转换单元和负电压电荷泵单元，所述第二时钟转换单元的输入端连接所述时钟发生模块的输出端，所述第二时钟转换单元的输出端连接所述负电压电荷泵单元的输入端，所述负电压电荷泵单元的输入端连接所述电压切换单元的输出端。
其中较优地，所述第二时钟转换单元包括第八反相器、第九反相器、第十反相器、第十一反相器、第十二反相器、第五与非门和第六与非门；所述第八反相器的输入端连接所述时钟发生模块的输出端与所述第六与非门的一个输入端，所述第八反相器的输出端连接所述第五与非门的一个输入端，所述第五与非门的输出端连接所述第九反相器的输入端，所述第九反相器的输出端连接第五输出端与所述第十反相器的输入端，所述第十反相器的输出端连接所述第六与非门的另一 个输入端与第六输出端，所述第六与非门的输出端连接所述第十一反相器的输入端，所述第十一反相器的输出端连接第八输出端与所述第十二反相器的输入端，所述第十二反相器的输出端连接所述第五与非门的另一个输入端与第七输出端。
其中较优地，所述负电压电荷泵单元包括第十八PMOS管、第十九PMOS管、第十九NMOS管、第二十NMOS管、第二十PMOS管、第二十一PMOS管、第二十一NMOS管、第二十二NMOS管、第七电容、第八电容和第九电容；所述第十八PMOS管的栅极连接所述第二时钟转换单元的第八输出端，所述第十八PMOS管与所述第十九PMOS管的漏极分别连接所述电压切换单元的输出电压，所述第十八PMOS管的源极分别连接所述第八电容的一端与所述第十九NMOS管的源极，所述第十九NMOS管的栅极连接所述第二时钟转换单元的第六输出端，所述第十九PMOS管的栅极连接所述第二时钟转换单元的第五输出端，所述第十九PMOS管的源极分别连接所述第七电容的一端与所述第二十NMOS管的源极，所述第二十NMOS管的栅极连接所述第二时钟转换单元的第七输出端，所述第十九NMOS管、所述第二十NMOS管、所述第二十PMOS管和所述第二十一PMOS管的漏极分别接地，所述第二十一PMOS管的栅极分别连接所述第二十PMOS管的源极、所述第七电容的另一端、所述第二十二NMOS管的栅极和所述第二十一NMOS管的源极，所述第二十PMOS管的栅极分别连接所述第二十一PMOS管的源极、所述第八电容的另一端、所述第二十一NMOS管的栅极和所述第二十二NMOS管的源极，所述第二十一NMOS管与所述第二十二NMOS管的漏极分别连接所述第九电容和负压输出端，所述第九电容的另一端接地。
根据本发明实施例的第二方面，提供一种集成电路芯片，包括上述的正负电压电荷泵电路。
根据本发明实施例的第三方面，提供一种通信终端，包括上述的正负电压电荷泵电路。
本发明实施例提供的正负电压电荷泵电路通过正电压电荷泵模块根据时钟发生模块输出的时钟信号产生正电压，同时采用瞬态增强模块将该正电压和供电电压进行采样并转换成电流进行比较，根据比较结果实现为负电压电荷泵模块提供可切换的输入电压，负电压电荷泵 模块根据时钟发生模块输出的时钟信号不仅能够快速可靠的建立负电压，进而提高负电压电荷泵模块产生负电压的速度和效率，而且还可以灵活地实现不同负压的要求。
附图说明
图1为本发明实施例提供的正负电压电荷泵电路原理框图；
图2为本发明实施例提供的正负电压电荷泵电路中，正电压电荷泵模块的电路原理图；
图3为本发明实施例提供的正负电压电荷泵电路中，瞬态增强模块的电路原理图；
图4为本发明实施例提供的正负电压电荷泵电路中，负压电荷泵模块的电路原理图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
为了能够同时稳定可靠地实现高于输入电源电压正轨的正电压以及低于输入电源电压负轨的负电压的输出，并使得输出的负电压灵活、快速地建立，如图1所示，本发明实施例中提供了一种正负电压电荷泵电路，包括时钟发生模块100、正电压电荷泵模块101、瞬态增强模块102和负电压电荷泵模块103。时钟发生模块100的输出端连接正电压电荷泵模块101和负电压电荷泵模块103的输入端，正电压电荷泵模块101的输出端连接瞬态增强模块102的输入端，瞬态增强模块102的输出端连接负电压电荷泵模块103的输入电源端，时钟发生模块100、正电压电荷泵模块101和瞬态增强模块102的电源端均连接供电电压VDD。
正电压电荷泵模块101根据时钟发生模块100输出的时钟信号产生正电压，该正电压与供电电压作为输入电压源被瞬态增强模块102采样并转换成电流后进行比较，根据比较结果为负电压电荷泵模块103提供可切换的输入电压，使得负电压电荷泵模块103根据时钟发生模块100输出的时钟信号产生负电压输出。
时钟发生模块100，用于产生时钟信号。该时钟发生模块100可以采用任意结构的振荡器实现，其主要目的是为正电压电荷泵模块101 和负电压电荷泵模块103提供一定频率的时钟信号。
如图2所示，正电压电荷泵模块101包括第一时钟转换单元201和至少一个正电压电荷泵单元202，第一时钟转换单元201的输入端连接时钟发生模块100的输出端，第一时钟转换单元201的输出端连接每个正电压电荷泵单元202的输入端。
第一时钟转换单元201，用于将时钟发生模块100输出的时钟信号进行转换，产生2路互补的非交叠时钟信号。如图2所示，第一时钟转换单元201包括第一反相器INV1、第二反相器INV2、第三反相器INV3、第四反相器INV4、第五反相器INV5、第一与非门NAND1和第二与非门NAND2；第一反相器INV1的输入端连接时钟发生模块100的输出端与第二与非门NAND2的一个输入端，第一反相器INV1的输出端连接第一与非门NAND1的一个输入端，第一与非门NAND1的输出端连接第二反相器INV2的输入端，第二反相器INV2的输出端连接第一输出端与第三反相器INV3的输入端，第三反相器INV3的输出端连接第二与非门NAND2的另一个输入端与第二输出端，第二与非门NAND2的输出端连接第四反相器INV4的输入端，第四反相器INV4的输出端连接第四输出端与第五反相器INV5的输入端，第五反相器INV5的输出端连接第一与非门NAND1的另一个输入端与第三输出端。
第一时钟转换单元201接收时钟发生模块100输出的时钟信号CLK，并将该时钟信号CLK通过反相器INV1～INV5以及2输入与非门NAND1和NAND2，转化为2路非交叠时钟信号，第一路非交叠时钟信号CLK_i和CLK_b；第二路非交叠时钟信号为CLK_if和CLK_bf。第一时钟转换单元201将时钟信号CLK转化为2路非交叠时钟信号是现有成熟技术，在此不再详述。
另外，若第一时钟转换单元201的电压域和接收的时钟信号CLK的电压域不同，则该第一时钟转换单元201需要完成电平转换功能。例如：时钟信号CLK的电压域为供电电压VDD和接地电压VSS，其中供电电压VDD为输入信号电压正轨，VSS为输入信号电压负轨；第一时钟转换单元201需要将时钟信号CLK摆幅转换到所需要转换目标电压的正轨值VDDi和接地电压VSS电压域中。
如图2所示，正电压电荷泵单元202包括第一NMOS管MN0、第二 NMOS管MN1、第一PMOS管MP0、第二PMOS管MP1、第三NMOS管MN2、第四NMOS管MN3、第三PMOS管MP2、第四PMOS管MP3、第一电容CF1、第二电容CF2和第三电容Chold；第一NMOS管MN0的栅极连接第一时钟转换单元201的第四输出端，第一NMOS管MN0与第二NMOS管MN1的源极均接地，第一NMOS管MN0漏极分别连接第二电容CF2的一端与第一PMOS管MP0的漏极，第一PMOS管MP0的栅极连接第一时钟转换单元201的第二输出端，第二NMOS管MN1的栅极连接第一时钟转换单元201的第一输出端，第二NMOS管MN1的漏极分别连接第一电容CF1的一端与第二PMOS管MP1的漏极，第二PMOS管MP1的栅极连接第一时钟转换单元201的第三输出端，第二PMOS管MP1、第一PMOS管MP0、第三NMOS管MN2和第四NMOS管MN3的源极均连接输入电压Vin，第四NMOS管MN3的栅极分别连接第三NMOS管MN2漏极、第一电容CF1的另一端、第四PMOS管MP3的栅极和第三PMOS管MP2的漏极，第三NMOS管MN2的栅极分别连接第四NMOS管MN3漏极、第二电容CF2的另一端、第三PMOS管MP2的栅极和第四PMOS管MP3的漏极，第三PMOS管MP2与第四PMOS管MP3的源极分别连接第三电容Chold的一端和正压输出端VDDH，第三电容Chold的另一端接地。
其中，第一NMOS管MN0、第二NMOS管MN1、第一PMOS管MP0、第二PMOS管MP1分别为开关管，第三NMOS管MN2、第四NMOS管MN3、第三PMOS管MP2、第四PMOS管MP3分别为传输管；通过第一时钟转换单元201输出的2路互补的非交叠时钟信号控制第一NMOS管MN0、第二NMOS管MN1、第一PMOS管MP0、第二PMOS管MP1的导通和关断，实现对第一电容CF1和第二电容CF2进行逐次充放电，并通过第三NMOS管MN2、第四NMOS管MN3、第三PMOS管MP2、第四PMOS管MP3的导通和关断，实现将第一电容CF1和第二电容CF2的电荷传输至第三电容Chold，从而实现正电压输出。其中，第一电容CF1和第二电容CF2的电容值相等，并且输入电压Vin最高等于供电电压VDD。
具体地说，以输入电压Vin最高等于供电电压VDD为例，当非交叠时钟信号CLK_i为高电平，即为第一时钟转换单元201提供供电电压VDD时，非交叠时钟信号CLK_b为低电平，即为第一时钟转换单元201提供接地电压VSS，同时，非交叠时钟信号CLK_if和CLK_bf的电 平分别为供电电压VDD和接地电压VSS。此时，第一NMOS管MN0和第二PMOS管MP1处于导通状态，第一PMOS管MP0和第二NMOS管MN1处于关断状态，使得第一电容CF1的两端分别接入供电电压VDD，实现向第四NMOS管MN3提供栅极电压为2倍的供电电压VDD，第四NMOS管MN3的源极电压为VDD，使得第四NMOS管MN3处于导通状态，第三PMOS管MP2的栅极电压为供电电压VDD，使得第三PMOS管MP2为导通状态，实现将第一电容CF1中的电荷通过第三PMOS管MP2全部传输至第三电容Chold，即对第三电容Chold进行充电，从而实现正电压输出。而第三NMOS管MN2的栅极电压和源极电压均为供电电压VDD，使得第三NMOS管MN2处于截止状态，第四PMOS管MP3同样处于截止状态，并且第二电容CF2的一端接入供电电压VDD，另一端接入接地电压VSS，实现为第二电容CF2进行充电。
同理，当非交叠时钟信号CLK_i为低电平，即为第一时钟转换单元201提供接地电压VSS时，非交叠时钟信号CLK_b为高电平，即为第一时钟转换单元201提供供电电压VDD，同时，非交叠时钟信号CLK_if和CLK_bf的电平分别为接地电压VSS和供电电压VDD。此时，第二NMOS管MN1和第一PMOS管MP0处于导通状态，第一NMOS管MN0和第二PMOS管MP1处于关断状态，使得第二电容CF2的两端分别接入供电电压VDD，实现向第三NMOS管MN2提供栅极电压为2倍的供电电压VDD，第三NMOS管MN2的源极电压为VDD，使得第三NMOS管MN2处于导通状态，第四PMOS管MP3的栅极电压为供电电压VDD，使得第四PMOS管MP3为导通状态，实现将第二电容CF2中的电荷通过第四PMOS管MP3全部传输至第三电容Chold，即对第三电容Chold进行充电，从而实现正电压输出。而第四NMOS管MN3的栅极电压和源极电压均为供电电压VDD，使得第四NMOS管MN3处于截止状态，第三PMOS管MP2同样处于截止状态，并且第一电容CF1的一端接入供电电压VDD，另一端接入接地电压VSS，实现为第一电容CF1进行充电。经过若干周期对第一电容CF1和第二电容CF2中的电荷搬移，使得正压输出端VDDH最终达到输出2倍的供电电压VDD。
需要强调的是，非交叠时钟信号CLK_if和CLK_bf分别对应为非交叠时钟信号CLK_i和CLK_b超前相位的非交叠时钟信号，并且，非 交叠时钟信号CLK_if与非交叠时钟信号CLK_i为同相非交叠时钟信号，非交叠时钟信号CLK_bf与非交叠时钟信号CLK_b为同相非交叠时钟信号；通过非交叠时钟信号CLK_if和CLK_bf可以避免正电压电荷泵单元202中的PMOS管与NMOS管发生同时导通的问题。
此外，如果需要正电压电荷泵单元202的正压输出端VDDH输出更高的正电压，可以采用将多个正电压电荷泵单元202进行级联，即除从第二个正电压电荷泵单元202开始，每一个正电压电荷泵单元202的输入电压Vin连接其上一个正电压电荷泵单元202的正压输出端VDDH。
如图3所示，瞬态增强模块102包括电压采样比较单元301和电压切换单元302，电压采样比较单元301的输入端连接正电压电荷泵单元202的正压输出端VDDH和供电电压VDD，电压采样比较单元301的输出端连接电压切换单元302的输入端。通过电压采样比较单元301采样正电压电荷泵单元202输出的正电压和供电电压VDD，将该正电压与供电电压VDD转换成相应电流后进行比较，使得节点VDET输出检测信号的状态，电压切换单元302将检测信号的状态进行必要的电平转换处理之后控制开关实现电压的切换，从而为负电压电荷泵模块103提供可切换的输入电压，进而提高负电压电荷泵模块103产生负电压的速度和效率。
如图3所示，电压采样比较单元301包括第一电阻R1、第五NMOS管MN4、第六NMOS管MN5、第七NMOS管MN6、第八NMOS管MN7、第五PMOS管MP4、第六PMOS管MP5、第二电阻R2、第三电阻R3、第四电容C1；第一电阻R1的一端、第五PMOS管MP4与第六PMOS管MP5的源极分别连接供电电压VDD，第一电阻R1的另一端分别连接第五NMOS管MN4的漏极和栅极、第六NMOS管MN5的栅极，第六NMOS管MN5的漏极分别连接第五PMOS管MP4的漏极与栅极、第六PMOS管MP5的栅极，第六PMOS管MP5的漏极分别连接第四电容C1的一端与第三电阻R3的一端、第七NMOS管MN6的漏极以及电压切换单元302，第七NMOS管MN6的栅极分别连接第八NMOS管MN7的栅极与漏极以及第二电阻R2的一端，第二电阻R2的另一端连接正电压电荷泵单元202的正压输出端VDDH,第八NMOS管MN7与第七NMOS管MN6的源极、第三电阻 R3与第四电容C1的另一端以及第六NMOS管MN5与第五NMOS管MN4的源极均接地。
电压采样比较单元301的工作原理为：通过第二电阻R2与第八NMOS管MN7采样正电压电荷泵单元202的正压输出端VDDH输出电压，并将该正电压转换成相应的电流，该电流经过第七NMOS管MN6按照预设比例进行复制；通过第一电阻R1与第五NMOS管MN4采样供电电压VDD，并将该供电电压VDD转换成相应的电流，该电流依次经过第六NMOS管MN5、第五PMOS管MP4和第六PMOS管MP5按照预设比例进行复制；其中，正电压电荷泵单元202的正压输出端VDDH输出的正电压与供电电压VDD被采样并转换成相应的电流，该电流按照预设比例对应复制到第八NMOS管MN7漏极与第六PMOS管MP5漏极上，分别表示为：
Figure PCTCN2021130586-appb-000001
Figure PCTCN2021130586-appb-000002
上式中，R 1为第一电阻，R 2为第二电阻，β0＝μnCoxW0/L0，β3＝μnCoxW3/L3，un为电子迁移率，Cox为栅氧化层电容，W0/L0为第五NMOS管MN4的宽长比,W3/L3为第八NMOS管MN7的宽长比；VDDH为正电压电荷泵单元的正压输出端VDDH输出的正电压，VDD为供电电压，V T为电路设计阈值电压。
当正电压电荷泵单元202的正压输出端VDDH输出的正电压和供电电压VDD相等时，第六PMOS管MP5中电流大于第七NMOS管MN6中电流，使得节点VDET输出的检测信号的状态为接近于供电电压VDD的高电平，随着正电压电荷泵单元202的正压输出端VDDH输出的正电压逐渐增大，I D7电流也会随之增加；当正电压电荷泵单元202的正压输出端VDDH输出的正电压超过电路设计阈值电压或者达到目标稳态(如达到两倍供电电压VDD)时第七NMOS管MN6中的电流远大于第六PMOS管MP5中的电流，节点VDET输出的检测信号的状态为从高电平供电电压VDD跳变为一个低电平接地电压VSS输出；由此实现对正电压电荷泵单元202的正压输出端VDDH输出的正电压的动态检测。只有当正电压电荷泵单元202的正压输出端VDDH输出的正电压升高或者下降达到 预定值，电压采样比较单元301输出的检测信号的状态则发生一次翻转。
如图3所示，电压切换单元302包括迟滞反相器3020、逻辑电平转换子单元3021和开关子单元3022；迟滞反相器3020的输入端连接电压采样比较单元301的输出端，迟滞反相器3020的输出端连接逻辑电平转换子单元3021的输入端，逻辑电平转换子单元3021的输出端连接开关子单元3022的输入端。
如图3所示，迟滞反相器3020包括第九NMOS管MN8、第十NMOS管MN9、第十一NMOS管MN10、第七PMOS管MP6、第八PMOS管MP7、第九PMOS管MP8，第九NMOS管MN8、第十NMOS管MN9、第七PMOS管MP6、第八PMOS管MP7的栅极连接在一起作为迟滞反相器3020的输入端，用于连接采样比较单元301的节点VDET，以接收电压采样比较单元301输出的检测信号的状态，第九NMOS管MN8的漏极与第十NMOS管MN9的源极分别连接第九PMOS管MP8的漏极，第十NMOS管MN9的漏极与第八PMOS管MP7的漏极、第九PMOS管MP8与第十一NMOS管MN10的栅极相互连接作为迟滞反相器3020的输出端，第八PMOS管MP7的源极与第七PMOS管MP6的漏极分别连接第十一NMOS管MN10的漏极，第七PMOS管MP6与第九PMOS管MP8的源极分别连接供电电压VDD，第九NMOS管MN8与第十一NMOS管MN10的源极接地。
迟滞反相器3020工作电压域为供电电压VDD和接地电压VSS。迟滞反相器3020的主要作用是将电压采样比较单元301输出的检测信号的状态进行整形，得到与检测信号的状态反向的逻辑电平，同时实现一定的迟滞功能，防止供电电压VDD和检测信号的状态出现毛刺电平，使电路更加安全可靠的工作。
如图3所示，逻辑电平转换子单元3021包括第六反相器INV6、第七反相器INV7、第十二NMOS管MN11、第十三NMOS管MN12、第十四NMOS管MN13、第十五NMOS管MN14、第十六NMOS管MN15、第十七NMOS管MN16、第十八NMOS管MN17、第十PMOS管MP9、第十一PMOS管MP10、第十二PMOS管MP11、第十三PMOS管MP12、第十四PMOS管MP13、第十五PMOS管MP14、第五电容C2、第六电容C3、第三与非门NAND3、第四与非门NAND4、数字延迟单元D1～D4和异或门XOR1；逻 辑电平转换子单元3021各个部分连接关系如下：第六反相器INV6的输入端连接迟滞反相器3020的输出端，第六反相器INV6的输出端分别连接第七反相器INV7的输入端、第十三NMOS管MN12的栅极，第七反相器INV7的输出端分别连接开关子单元3022的一个输入端、第十四NMOS管MN13的栅极；X节点分别连接迟滞反相器3020的输出端、第一数字延迟单元D1的输入端、异或门XOR1的一个输入端，第一数字延迟单元D1的输出端到第四数字延迟单元D4的输入端之间串联第二数字延迟单元D2和第三数字延迟单元D3，第四数字延迟单元D4的输出端连接异或门XOR1的另一个输入端，异或门XOR1的输出端分别连接第十八NMOS管MN17与第十七NMOS管MN16的栅极以及第十四PMOS管MP13与第十五PMOS管MP14的栅极，第十五PMOS管MP14的漏极分别连接第六电容C3的一端、第十八NMOS管MN17的漏极，第十八NMOS管MN17的源极连接第十四NMOS管MN13的漏极，第六电容C3的另一端分别连接第十五NMOS管MN14的源极、第三与非门NAND3的一个输入端、第十PMOS管MP9的漏极，第十五NMOS管MN14的漏极分别连接第十六NMOS管MN15的漏极，第十六NMOS管MN15的源极分别连接第十一PMOS管MP10的漏极、第五电容C2的一端以及第四与非门NAND4的一个输入端，第五电容C2的另一端分别连接第十四PMOS管MP13的漏极、第十七NMOS管MN16的漏极，第十七NMOS管MN16的源极连接第十三NMOS管MN12的漏极，第十二NMOS管MN11的栅极连接第五NMOS管的漏极，第十二NMOS管MN11的漏极分别连接第十三PMOS管MP12的漏极和栅极、第十六NMOS管MN15与第十五NMOS管MN14的栅极，第十三PMOS管MP12的源极分别连接第十二PMOS管MP11的漏极和栅极、第十一PMOS管MP10与第十PMOS管MP9的栅极，第十二PMOS管MP11、第十一PMOS管MP10、第十PMOS管MP9的源极和第十五NMOS管MN14、第十六NMOS管MN15的漏极均连接正电压电荷泵单元202的正压输出端VDDH，第十四NMOS管MN13、第十三NMOS管MN12和第十二NMOS管MN11的源极分别接地，第十四PMOS管MP13与第十五PMOS管MP14的源极分别连接所在电压域的负轨电压VDDL，第三与非门NAND3的另一个输入端分别连接第四与非门NAND4的输出端、开关子单元3022的另一个输入端，第三与非门NAND3的输出端连接第四与非 门NAND4的另一个输入端。
如图3所示，开关子单元3022包括第十六PMOS管MP15与第十七PMOS管MP16，第十六PMOS管MP15的栅极作为开关子单元3022的另一个输入端，用于连接第四与非门NAND4的输出端，第十六PMOS管MP15的源极连接正电压电荷泵单元202的正压输出端VDDH，第十七PMOS管MP16的栅极作为开关子单元3022的一个输入端，用于连接第七反相器INV7的输出端，第十七PMOS管MP16的源极连接供电电压VDD，第十七PMOS管MP16与第十六PMOS管MP15的漏极作为开关子单元3022的输出端，用于输出电压VDD_neg，实现为负电压电荷泵模块103提供可切换的输入电压。
需要强调的是，第三与非门NAND3与第四与非门NAND4工作的电压域为正电压电荷泵单元202的正压输出端VDDH输出的正电压(所在电压域的正轨电压值)和所在电压域的负轨电压VDDL。在本发明的实施例中，所在电压域的负轨电压VDDL设置为供电电压VDD。当电压采样比较单元301输出的检测信号的状态由高电平供电电压VDD和低电平接地电压VSS的电压域转换至高电平正电压电荷泵单元202的正压输出端VDDH输出的正电压和低电平供电电压VDD的电压域中之后，通过控制开关管第十六PMOS管MP15与第十七PMOS管MP16的栅电压来选择瞬态增强模块102的输出电压VDD_neg。并且，通过第十二NMOS管MN11按照预设比例复制电压采样比较单元301中第五NMOS管MN4的电流，第十二PMOS管MP11与第十三PMOS管MP12连接，第十三PMOS管MP12为二极管方式连接，第十PMOS管MP9、第十一PMOS管MP10和第十二PMOS管MP11为比例镜像电流源，第十三PMOS管MP12为第十六NMOS管MN15与第十五NMOS管MN14提供静态栅极电压，通过窄脉冲信号RST为第十四PMOS管MP13、第十五PMOS管MP14、第十七NMOS管MN16、第十八NMOS管MN17的栅极电压进行控制来实现对第五电容C2、第六电容C3预充电，第五电容C2、第六电容C3电容值相等,将两个电容电荷进行初始化，由数字延迟单元D1～D4和异或门XOR1对X节点输出信号组合逻辑之后,产生一个窄脉冲信号RST,利用该信号RST来实现对节点VDET输出的检测信号的电平转换。
为了便于对电压切换单元302工作原理的理解，下面结合电压采 样比较单元301，对电压切换单元302的工作原理进行详细说明。其中，瞬态增强模块102的工作过程为：当电路上电后，正电压电荷泵模块101开始工作，在正电压电荷泵单元202的正压输出端VDDH输出的正电压从供电电压VDD开始逐渐增大，但还未达到目标电压的过程中，使得节点VDET输出的检测信号的状态为接近于供电电压VDD的高电平，经过第六反相器INV6和第七反相器INV7之后，第十三NMOS管MN12和第十四NMOS管MN13的栅电压分别为供电电压VDD和接地电压VSS，使得第十三NMOS管MN12处于导通状态，第十四NMOS管MN13处于截止状态，此时向作为开关管的第十七PMOS管MP16提供的栅电压XL接地电压VSS，从而使得第十七PMOS管MP16处于导通状态。
当节点VDET输出的检测信号的状态发生跳变时，经过迟滞反相器3020整形，使得X节点输出信号也随之发生状态的跳变，该输出信号经过数字延时单元D1～D4以及异或门XOR1的组合逻辑之后，产生一个高电平为供电电压VDD的窄脉冲信号RST，利用信号RST来实现对节点VDET输出的检测信号的电平转换。
当电源电压正常上电之后，节点VDET输出的检测信号从接地电压VSS跳变为供电电压VDD，X节点电压由电源电压VDD跳变为接地电压VSS，经过数字延时单元D1～D4以及异或门XOR1构成的组合逻辑子单元之后，产生一个高电平为供电电压VDD的窄脉冲信号RST；当窄脉冲信号RST电平为接地电压VSS时，第十四PMOS管MP13和第十五PMOS管MP14导通，第十七NMOS管MN16和第十八NMOS管MN17截止，则第五电容C2和第六电容C3的极板A和B进行预充电至供电电压VDD，同时第五电容C2和第六电容C3的极板C和D被第十PMOS管MP9和第十一PMOS管MP10充电至与正电压电荷泵单元202的正压输出端VDDH输出的正电压相等；
当窄脉冲信号RST为供电电压VDD时，第十四PMOS管MP13和第十五PMOS管MP14截止，第十七NMOS管MN16和第十八NMOS管MN17导通，由于第十三NMOS管MN12导通，第十四NMOS管MN13截止，因此第五电容C2的A极板电压被迅速拉到接地电压VSS，则第五电容C2的极板C的电压也迅速下降；当第五电容C2的极板C电压下降到一定幅值，第十六NMOS管MN15导通，将第五电容C2的极板C的电压上拉； 直到第十六NMOS管MN15截止后，通过第十四NMOS管MN13将第五电容C2的极板C电压充电至与正电压电荷泵单元202的正压输出端VDDH输出的正电压相等与正电压电荷泵单元202的正压输出端VDDH输出的正电压相等，在此过程中由于第十四NMOS管MN13处于截止状态，使得第六电容两端电压未发生变化；
当窄脉冲信号RST再次变为接地电压VSS后，第十四PMOS管MP13和第十五PMOS管MP14再次导通，第十七NMOS管MN16和第十八NMOS管MN17截止，第五电容C2和第六电容C3再次处于预充电状态，等待窄脉冲信号RST的下一个窄脉冲触发。
在上述过程中，第六电容C3极板D电压在整个过程中未发生变化，依然保持与正电压电荷泵单元202的正压输出端VDDH输出的正电压相等；由于第五电容C2的极板C电压先降低后升高至与正电压电荷泵单元202的正压输出端VDDH输出的正电压相等，当第五电容C2的极板C电压接近供电电压VDD电压时，第四与非门NAND4输出的电压XH拉高至与正电压电荷泵单元202的正压输出端VDDH输出的正电压相等，因此作为开关管的第十六PMOS管MP15处于截止状态。由于第十七PMOS管MP16导通，第十六PMOS管MP15截止，因此该状态下电压切换单元302的输出电压VDD_neg等于供电电压VDD。
当正电压电荷泵单元202的正压输出端VDDH输出的正电压从完成建立或者达到目标电压后，节点VDET输出的检测信号由高电平供电电压VDD跳变为低电平接地电压VSS，第十三NMOS管MN12和第十四NMOS管MN13的栅电压分别为接地电压VSS和供电电压VDD，使得第十四NMOS管MN13处于导通状态，第十三NMOS管MN12处于截止状态，因此，第十七PMOS管MP16处于截止状态；同时X节点电压由接地电压VSS跳变为供电电压VDD，经过数字延时单元D1～D4以及异或门XOR1构成的组合逻辑子单元之后，产生一个高电平为供电电压VDD的窄脉冲信号RST，即有效的检测脉冲，使得第六电容C3极板D电压会先降后升，而第五电容C2两个极板电压保持不变，因此第三与非门NAND3输出的电压与完成建立或者达到目标电压的正电压电荷泵单元202的正压输出端VDDH输出的正电压相等，第四与非门NAND4输出的电压为低电平供电电压VDD，使得第四与非门NAND4输出的电压XH为供电电 压VDD，此时，第十六PMOS管MP15处于导通状态。由于第十七PMOS管MP16截止，第十六PMOS管MP15导通，因此该状态下电压切换单元302的输出电压VDD_neg与完成建立或者达到目标电压的正电压电荷泵单元202的正压输出端VDDH输出的正电压相等。
负电压电荷泵模块103根据时钟发生模块100产生的时钟信号以及瞬态增强模块102提供的时钟摆幅电压VDD_neg来产生负电压输出。如图4所示，负电压电荷泵模块103包括第二时钟转换单元401和负电压电荷泵单元402，第二时钟转换单元401的输入端连接时钟发生模块100的输出端，第二时钟转换单元401的输出端连接负电压电荷泵单元402的输入端，负电压电荷泵单元402的输入端连接电压切换单元302的输出端。
第二时钟转换单元401，用于将时钟发生模块100输出的时钟信号进行转换，产生2路互补的非交叠时钟信号。如图4所示，第二时钟转换单元401包括第八反相器INV8、第九反相器INV9、第十反相器INV10、第十一反相器INV11、第十二反相器INV12、第五与非门NAND5和第六与非门NAND6；第八反相器INV8的输入端连接时钟发生模块100的输出端与第六与非门NAND6的一个输入端，第八反相器INV8的输出端连接第五与非门NAND5的一个输入端，第五与非门NAND5的输出端连接第九反相器INV9的输入端，第九反相器INV9的输出端连接第五输出端与第十反相器INV10的输入端，第十反相器INV10的输出端连接第六与非门NAND6的另一个输入端与第六输出端，第六与非门NAND6的输出端连接第十一反相器INV11的输入端，第十一反相器INV11的输出端连接第八输出端与第十二反相器INV12的输入端，第十二反相器INV12的输出端连接第五与非门NAND5的另一个输入端与第七输出端。
第二时钟转换单元401接收时钟发生模块100输出的时钟信号CLK，并将该时钟信号CLK通过反相器INV8～INV12以及2输入与非门NAND5和NAND6，转化为2路非交叠时钟信号，第一路非交叠时钟信号CLK_iˊ和CLK_bˊ；第二路非交叠时钟信号为CLK_ifˊ和CLK_bfˊ。其中，2输入与非门NAND5和NAND6的工作电压域为电压切换单元302的输出电压VDD_neg和接地电压VSS。第二时钟转换单元401将时钟信号 CLK转化为2路非交叠时钟信号是现有成熟技术，在此不再详述。
如图4所示，负电压电荷泵单元402包括第十八PMOS管MP17、第十九PMOS管MP18、第十九NMOS管MN18、第二十NMOS管MN19、第二十PMOS管MP19、第二十一PMOS管MP20、第二十一NMOS管MN20、第二十二NMOS管MN21、第七电容CF3、第八电容CF4和第九电容Chold1；第十八PMOS管MP17的栅极连接第二时钟转换单元401的第八输出端，第十八PMOS管MP17与第十九PMOS管MP18的漏极分别连接电压切换单元302的输出电压VDD_neg，第十八PMOS管MP17的源极分别连接第八电容CF4的一端与第十九NMOS管MN18的源极，第十九NMOS管MN18的栅极连接第二时钟转换单元401的第六输出端，第十九PMOS管MP18的栅极连接第二时钟转换单元401的第五输出端，第十九PMOS管MP18的源极分别连接第七电容CF3的一端与第二十NMOS管MN19的源极，第二十NMOS管MN19的栅极连接第二时钟转换单元401的第七输出端，第十九NMOS管MN18、第二十NMOS管MN19、第二十PMOS管MP19和第二十一PMOS管MP20的漏极分别接地，第二十一PMOS管MP20的栅极分别连接第二十PMOS管MP19的源极、第七电容CF3的另一端、第二十二NMOS管MN21的栅极和第二十一NMOS管MN20的源极，第二十PMOS管MP19的栅极分别连接第二十一PMOS管MP20的源极、第八电容CF4的另一端、第二十一NMOS管MN20的栅极和第二十二NMOS管MN21的源极，第二十一NMOS管MN20与第二十二NMOS管MN21的漏极均连接第九电容Chold1和负压输出端VSSH，第九电容Chold1的另一端接地。
当正负电压电荷泵电路开始工作时，正电压电荷泵单元202和负电压电荷泵单元402同时工作，如果正负电压电荷泵电路电压域的正轨电压为供电电压VDD，负轨电压为接地电压VSS，正电压电荷泵单元202产生的电压将快速建立到目标电压；在此过程中，瞬态增强模块102对供电电压VDD和正电压电荷泵单元202的正压输出端VDDH输出的正电压进行采样，若采样的正电压电荷泵单元202的正电压未达到目标值，将供电电压VDD作为负电压电荷泵单元402的输入电压，当非交叠时钟信号CLK_iˊ为高电平时，非交叠时钟信号CLK_bˊ为低电平，同时，非交叠时钟信号CLK_ifˊ和CLK_bfˊ的电平分别为供电电 压VDD和接地电压VSS。此时，第十八PMOS管MP17和第二十NMOS管MN19处于导通状态，第十九NMOS管MN18和第十九NMOS管MN18处于关断状态，使得第七电容CF3的两端分别接入供电电压VDD，实现向第二十一PMOS管MP20提供栅极电压为接地电压VSS-供电电压VDD，第二十一PMOS管MP20的源极电压为VDD，使得第二十一PMOS管MP20处于导通状态，第二十一NMOS管MN20的栅极电压为供电电压VDD，使得第二十一NMOS管MN20为导通状态，实现将第七电容CF3中的电荷通过第二十一NMOS管MN20全部传输至第九电容Chold1，即对第九电容Chold1进行充电，从而实现负电压输出，该负电压VSSH＝VSS-VDD_neg，即当瞬态增强模块102采样的正电压电荷泵单元202的正电压未达到目标值时，瞬态增强模块102为负电压电荷泵单元402提供的电压VDD_neg为供电电压VDD，此时负电压电荷泵单元402产生的负电压VSSH为接地电压VSS-供电电压VDD。而第二十PMOS管MP19与第二十二NMOS管MN21处于截止状态，并且第八电容CF4的一端接入供电电压VDD，另一端接入接地电压VSS，实现为第八电容CF4进行充电。
当正电压电荷泵单元202的正电压达到目标值后，将正电压电荷泵单元202的正电压作为负电压电荷泵单元402的输入电压，此时通过非交叠时钟信号控制第十九PMOS管MP18与第十九NMOS管MN18处于导通状态，第十八PMOS管MP17和第二十NMOS管MN19处于截止状态，第二十PMOS管MP19与第二十二NMOS管MN21处于导通状态，第二十一PMOS管MP20与第二十一NMOS管MN20处于截止状态，使得实现将第八电容CF4中的电荷通过第二十二NMOS管MN21全部传输至第九电容Chold1，即对第九电容Chold1进行充电，从而实现负电压输出，该负电压VSSH＝VSS-VDD_neg，即当瞬态增强模块102采样的正电压电荷泵单元202的正电压达到目标值时，瞬态增强模块102为负电压电荷泵单元402提供的电压VDD_neg为正电压电荷泵单元202的正电压，此时负电压电荷泵单元402产生的负电压VSSH为接地电压VSS-正电压电荷泵单元202的正电压。
因此，正电压电荷泵单元202的输出电压建立好之后，负电压电荷泵单元402才会从正电压电荷泵单元202中抽取电流，完成自己的 负压建立。由此可知，正电压电荷泵单元202输出电压的建立时间不会受负电压电荷泵单元402工作的影响，与此同时，在正电压建立过程中，负电压电荷泵单元402已经提前建立到接地电压VSS-供电电压VDD的电压，当正电压电荷泵单元202输出电压达到稳定状态之后，再利用该电压完成负电压的生成，从而又加快了负电压电荷泵单元402的负电压建立时间。
需要强调的是，非交叠时钟信号CLK_ifˊ和CLK_bfˊ分别对应为非交叠时钟信号CLK_iˊ和CLK_bˊ超前相位时钟信号，并且，时钟信号CLK_ifˊ与CLK_iˊ为同相，时钟信号CLK_bfˊ与CLK_bˊ为同相时钟信号；通过非交叠时钟信号CLK_ifˊ和CLK_bfˊ可以避免负电压电荷泵单元402中的PMOS管与NMOS管发生同时导通的问题。
另外，本发明实施例中提供的正负电压电荷泵电路可以被用在集成电路芯片中。对于该集成电路芯片中正负电压电荷泵电路的具体结构，在此不再一一详述。
上述正负电压电荷泵电路还可以被用在通信终端中，作为模拟集成电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明实施例提供的技术方案也适用于其他模拟集成电路应用的场合，例如通信基站等。
本发明实施例提供的正负电压电荷泵电路通过正电压电荷泵模块产生正电压，同时采用瞬态增强模块将该正电压和供电电压进行采样并转换成电流进行比较，根据比较结果实现为负电压电荷泵模块提供可切换的输入电压，负电压电荷泵模块根据时钟发生模块输出的时钟信号不仅能够快速可靠的建立负电压，进而提高负电压电荷泵模块产生负电压的速度和效率，而且还可以灵活地实现不同负压的要求。
以上对本发明所提供的正负电压电荷泵电路、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (15)

  1. 一种正负电压电荷泵电路，其特征在于包括时钟发生模块、正电压电荷泵模块、瞬态增强模块和负电压电荷泵模块，所述时钟发生模块的输出端连接所述正电压电荷泵模块和所述负电压电荷泵模块的输入端，所述正电压电荷泵模块的输出端连接所述瞬态增强模块的输入端，所述瞬态增强模块的输出端连接所述负电压电荷泵模块的输入电源端，所述时钟发生模块、所述正电压电荷泵模块和所述瞬态增强模块的电源端均连接供电电压；
    所述正电压电荷泵模块根据所述时钟发生模块输出的时钟信号产生正电压，所述正电压与所述供电电压作为输入电压源被所述瞬态增强模块采样并转换成电流后进行比较，根据比较结果为所述负电压电荷泵模块提供可切换的输入电压，使得所述负电压电荷泵模块根据所述时钟发生模块输出的时钟信号产生负电压。
  2. 如权利要求1所述的正负电压电荷泵电路，其特征在于：
    所述正电压电荷泵模块包括第一时钟转换单元和至少一个正电压电荷泵单元，所述第一时钟转换单元的输入端连接所述时钟发生模块的输出端，所述第一时钟转换单元的输出端连接每个所述正电压电荷泵单元的输入端。
  3. 如权利要求2所述的正负电压电荷泵电路，其特征在于：
    所述第一时钟转换单元包括第一反相器、第二反相器、第三反相器、第四反相器、第五反相器、第一与非门和第二与非门；所述第一反相器的输入端连接所述时钟发生模块的输出端与所述第二与非门的一个输入端，所述第一反相器的输出端连接所述第一与非门的一个输入端，所述第一与非门的输出端连接所述第二反相器的输入端，所述第二反相器的输出端连接第一输出端与所述第三反相器的输入端，所述第三反相器的输出端连接所述第二与非门的另一个输入端与第二输出端，所述第二与非门的输出端连接所述第四反相器的输入端，所述第四反相器的输出端连接第四输出端与所述第五反相器的输入端，所述第五反相器的输出端连接所述第一与非门的另一个输入端与第三输出端。
  4. 如权利要求2所述的正负电压电荷泵电路，其特征在于：
    当采用多个所述正电压电荷泵单元时，从第二个正电压电荷泵单元开始，每一个正电压电荷泵单元的输入电压连接其上一个正电压电荷泵单元的正压输出端。
  5. 如权利要求4所述的正负电压电荷泵电路，其特征在于：
    所述正电压电荷泵单元包括第一NMOS管、第二NMOS管、第一PMOS管、第二PMOS管、第三NMOS管、第四NMOS管、第三PMOS管、第四PMOS管、第一电容、第二电容和第三电容；所述第一NMOS管的栅极连接第一时钟转换单元的第四输出端，所述第一NMOS管与所述第二NMOS管的源极分别接地，所述第一NMOS管漏极分别连接所述第二电容的一端与所述第一PMOS管的漏极，所述第一PMOS管的栅极连接所述第一时钟转换单元的第二输出端，所述第二NMOS管的栅极连接所述第一时钟转换单元的第一输出端，所述第二NMOS管的漏极分别连接所述第一电容的一端与所述第二PMOS管的漏极，所述第二PMOS管的栅极连接所述第一时钟转换单元的第三输出端，所述第二PMOS管、所述第一PMOS管、所述第三NMOS管和所述第四NMOS管的源极均连接输入电压，所述第四NMOS管的栅极分别连接所述第三NMOS管漏极、所述第一电容的另一端、所述第四PMOS管的栅极和所述第三PMOS管的漏极，所述第三NMOS管的栅极分别连接所述第四NMOS管漏极、所述第二电容的另一端、所述第三PMOS管的栅极和所述第四PMOS管的漏极，所述第三PMOS管与所述第四PMOS管的源极均连接所述第三电容的一端和正压输出端，所述第三电容的另一端接地。
  6. 如权利要求5所述的正负电压电荷泵电路，其特征在于：
    所述瞬态增强模块包括电压采样比较单元和电压切换单元，所述电压采样比较单元的输入端连接所述正电压电荷泵单元的正压输出端和供电电压，所述电压采样比较单元的输出端连接所述电压切换单元的输入端。
  7. 如权利要求6所述的正负电压电荷泵电路，其特征在于：
    所述电压采样比较单元包括第一电阻、第五NMOS管、第六NMOS管、第七NMOS管、第八NMOS管、第五PMOS管、第六PMOS管、第二电阻、第三电阻、第四电容；所述第一电阻的一端、所述第五PMOS管 与所述第六PMOS管的源极分别连接供电电压，所述第一电阻的另一端分别连接所述第五NMOS管的漏极和栅极、所述第六NMOS管的栅极，所述第六NMOS管的漏极分别连接所述第五PMOS管的漏极与栅极、所述第六PMOS管的栅极，所述第六PMOS管的漏极分别连接所述第四电容的一端与所述第三电阻的一端、所述第七NMOS管的漏极以及所述电压切换单元，所述第七NMOS管的栅极分别连接所述第八NMOS管的栅极与漏极以及所述第二电阻的一端，所述第二电阻的另一端连接所述正电压电荷泵单元的正压输出端,所述第八NMOS管与所述第七NMOS管的源极、所述第三电阻与所述第四电容的另一端以及所述第六NMOS管与所述第五NMOS管的源极均接地。
  8. 如权利要求6所述的正负电压电荷泵电路，其特征在于：
    所述电压切换单元包括迟滞反相器、逻辑电平转换子单元和开关子单元；所述迟滞反相器的输入端连接所述电压采样比较单元的输出端，所述迟滞反相器的输出端连接所述逻辑电平转换子单元的输入端，所述逻辑电平转换子单元的输出端连接所述开关子单元的输入端。
  9. 如权利要求8所述的正负电压电荷泵电路，其特征在于：
    所述逻辑电平转换子单元包括第六反相器、第七反相器、第十二NMOS管、第十三NMOS管、第十四NMOS管、第十五NMOS管、第十六NMOS管、第十七NMOS管、第十八NMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第十三PMOS管、第十四PMOS管、第十五PMOS管、第五电容、第六电容、第三与非门、第四与非门、异或门和多个数字延迟单元；所述第六反相器的输入端连接所述迟滞反相器的输出端，所述第六反相器的输出端连接所述第七反相器的输入端、所述第十三NMOS管的栅极，所述第七反相器的输出端连接所述开关子单元的一个输入端、所述第十四NMOS管的栅极；X节点分别连接所述迟滞反相器的输出端、第一数字延迟单元的输入端、所述异或门的一个输入端，所述第一数字延迟单元的输出端到最后一个数字延迟单元的输入端之间串联多个数字延迟单元，最后一个数字延迟单元的输出端连接所述异或门的另一个输入端，所述异或门的输出端分别连接所述第十八NMOS管与所述第十七NMOS管的栅极以及所述第十四PMOS管与所述第十五PMOS管的栅极，所述第十五PMOS管的漏极连接所述第六电容 的一端、所述第十八NMOS管的漏极，所述第十八NMOS管的源极连接所述第十四NMOS管的漏极，所述第六电容的另一端连接所述第十五NMOS管的源极、所述第三与非门的一个输入端、所述第十PMOS管的漏极，所述第十五NMOS管的漏极连接所述第十六NMOS管的漏极，所述第十六NMOS管的源极连接所述第十一PMOS管的漏极、所述第五电容的一端以及所述第四与非门的一个输入端，所述第五电容的另一端分别连接所述第十四PMOS管的漏极、所述第十七NMOS管的漏极，所述第十七NMOS管的源极连接所述第十三NMOS管的漏极，所述第十二NMOS管的栅极连接所述第五NMOS管的漏极，所述第十二NMOS管的漏极分别连接所述第十三PMOS管的漏极和栅极、所述第十六NMOS管与所述第十五NMOS管的栅极，所述第十三PMOS管的源极分别连接所述第十二PMOS管的漏极和栅极、所述第十一PMOS管与所述第十PMOS管的栅极，所述第十二PMOS管、所述第十一PMOS管、所述第十PMOS管的源极和所述第十五NMOS管、所述第十六NMOS管的漏极均连接所述正电压电荷泵单元的正压输出端，所述第十四NMOS管、所述第十三NMOS管和所述第十二NMOS管的源极分别接地，所述第十四PMOS管与所述第十五PMOS管的源极分别连接所在电压域的负轨电压，所述第三与非门的另一个输入端连接到所述第四与非门的输出端、所述开关子单元的另一个输入端，所述第三与非门的输出端连接所述第四与非门的另一个输入端。
  10. 如权利要求9所述的正负电压电荷泵电路，其特征在于：
    所述开关子单元包括第十六PMOS管与第十七PMOS管，所述第十六PMOS管的栅极连接所述第四与非门的输出端，所述第十六PMOS管的源极连接所述正电压电荷泵单元的正压输出端，所述第十七PMOS管的栅极连接所述第七反相器的输出端，所述第十七PMOS管的源极连接供电电压，所述第十七PMOS管与所述第十六PMOS管的漏极作为所述开关子单元的输出端。
  11. 如权利要求10所述的正负电压电荷泵电路，其特征在于：
    所述负电压电荷泵模块包括第二时钟转换单元和负电压电荷泵单元，所述第二时钟转换单元的输入端连接所述时钟发生模块的输出端，所述第二时钟转换单元的输出端连接所述负电压电荷泵单元的输入端， 所述负电压电荷泵单元的输入端连接所述电压切换单元的输出端。
  12. 如权利要求11所述的正负电压电荷泵电路，其特征在于：
    所述第二时钟转换单元包括第八反相器、第九反相器、第十反相器、第十一反相器、第十二反相器、第五与非门和第六与非门；所述第八反相器的输入端连接所述时钟发生模块的输出端与所述第六与非门的一个输入端，所述第八反相器的输出端连接所述第五与非门的一个输入端，所述第五与非门的输出端连接所述第九反相器的输入端，所述第九反相器的输出端连接第五输出端与所述第十反相器的输入端，所述第十反相器的输出端连接所述第六与非门的另一个输入端与第六输出端，所述第六与非门的输出端连接所述第十一反相器的输入端，所述第十一反相器的输出端连接第八输出端与所述第十二反相器的输入端，所述第十二反相器的输出端连接所述第五与非门的另一个输入端与第七输出端。
  13. 如权利要求12所述的正负电压电荷泵电路，其特征在于：
    所述负电压电荷泵单元包括第十八PMOS管、第十九PMOS管、第十九NMOS管、第二十NMOS管、第二十PMOS管、第二十一PMOS管、第二十一NMOS管、第二十二NMOS管、第七电容、第八电容和第九电容；所述第十八PMOS管的栅极连接所述第二时钟转换单元的第八输出端，所述第十八PMOS管与所述第十九PMOS管的漏极分别连接所述电压切换单元的输出电压，所述第十八PMOS管的源极分别连接所述第八电容的一端与所述第十九NMOS管的源极，所述第十九NMOS管的栅极连接所述第二时钟转换单元的第六输出端，所述第十九PMOS管的栅极连接所述第二时钟转换单元的第五输出端，所述第十九PMOS管的源极分别连接所述第七电容的一端与所述第二十NMOS管的源极，所述第二十NMOS管的栅极连接所述第二时钟转换单元的第七输出端，所述第十九NMOS管、所述第二十NMOS管、所述第二十PMOS管和所述第二十一PMOS管的漏极分别接地，所述第二十一PMOS管的栅极分别连接所述第二十PMOS管的源极、所述第七电容的另一端、所述第二十二NMOS管的栅极和所述第二十一NMOS管的源极，所述第二十PMOS管的栅极分别连接所述第二十一PMOS管的源极、所述第八电容的另一端、所述第二十一NMOS管的栅极和所述第二十二NMOS管的源极，所述第二十 一NMOS管与所述第二十二NMOS管的漏极分别连接所述第九电容的一端和负压输出端，所述第九电容的另一端接地。
  14. 一种集成电路芯片，其特征在于包括权利要求1～13中任意一项所述的正负电压电荷泵电路。
  15. 一种通信终端，其特征在于包括权利要求1～13中任意一项所述的正负电压电荷泵电路。
PCT/CN2021/130586 2020-11-16 2021-11-15 一种正负电压电荷泵电路、芯片及通信终端 WO2022100728A1 (zh)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115001477A (zh) * 2022-07-19 2022-09-02 深圳芯能半导体技术有限公司 一种用于正负电压输入的信号接口电路
CN115037149A (zh) * 2022-08-11 2022-09-09 深圳市微源半导体股份有限公司 负压电荷泵电路
CN115425958A (zh) * 2022-11-04 2022-12-02 西安水木芯邦半导体设计有限公司 一种用于控制高压模拟开关的栅源电压保持电路
CN115469242A (zh) * 2022-09-13 2022-12-13 江苏万邦微电子有限公司 负电源监控系统及方法
CN115498856A (zh) * 2022-09-19 2022-12-20 上海南麟电子股份有限公司 一种驱动电路及芯片

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112448576B (zh) * 2020-11-16 2022-10-25 上海唯捷创芯电子技术有限公司 一种正负电压电荷泵电路、芯片及通信终端
CN113050507B (zh) * 2021-03-26 2022-02-01 广州穗源微电子科技有限公司 一种应用于低电源电压射频开关的控制电路
CN113315371B (zh) * 2021-04-13 2024-05-10 拓尔微电子股份有限公司 四开关管升降压变换器自适应电荷泵控制电路及控制方法
CN115800728B (zh) * 2021-09-10 2024-08-20 圣邦微电子（北京）股份有限公司 一种配置输出电压的时钟电荷泵电路
CN216437058U (zh) * 2021-12-28 2022-05-03 深圳飞骧科技股份有限公司 一种输出电压可控型电荷泵电路及射频芯片
CN114779870B (zh) * 2022-05-11 2023-10-20 中科芯磁科技(珠海)有限责任公司 电压自适应调整电路和芯片
CN116780890B (zh) * 2023-06-06 2024-06-11 深圳飞渡微电子有限公司 一种级联电荷泵正负输出电压可调电路及其控制方法
CN117294139A (zh) * 2023-10-08 2023-12-26 西安航天民芯科技有限公司 一种应用于电池管理芯片的负电压电荷泵电路
CN118117874B (zh) * 2024-04-29 2024-07-09 深圳市爱普特微电子有限公司 用于负压电荷泵的可级联的降压电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103973100A (zh) * 2013-01-25 2014-08-06 北京兆易创新科技股份有限公司 一种正负电压产生装置
US20150187316A1 (en) * 2013-12-31 2015-07-02 Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. Positive and negative voltage generating circuit, liquid crystal display module driving system, and voice over internet protocol phone
CN105954670A (zh) * 2016-05-26 2016-09-21 工业和信息化部电子第五研究所 集成电路esd失效预警电路
CN109039059A (zh) * 2018-08-23 2018-12-18 合肥工业大学 一种高效的多模式电荷泵
CN111146941A (zh) * 2019-12-31 2020-05-12 江苏芯力特电子科技有限公司 一种高性能的正负倍压电荷泵电路
CN112448576A (zh) * 2020-11-16 2021-03-05 上海唯捷创芯电子技术有限公司 一种正负电压电荷泵电路、芯片及通信终端

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05268763A (ja) * 1992-03-17 1993-10-15 Nec Corp Ｄｃ／ｄｃコンバータ回路およびそれを用いたｒｓ−２３２インタフェース回路
FR2717918B1 (fr) * 1994-03-25 1996-05-24 Suisse Electronique Microtech Circuit pour contrôler les tensions entre caisson et sources des transistors mos et système d'asservissement du rapport entre les courants dynamique et statique d'un circuit logique mos.
CN1306690C (zh) * 2003-07-30 2007-03-21 百利通电子(上海)有限公司 一种可对正负极分别充电的双电压电荷泵及其控制电路
JP4405216B2 (ja) * 2003-09-16 2010-01-27 株式会社ルネサステクノロジ 半導体装置
JP2006178018A (ja) * 2004-12-21 2006-07-06 Renesas Technology Corp 液晶表示駆動用半導体集積回路
CN101647182B (zh) * 2006-12-30 2013-01-30 先进模拟科技公司 包括升压电感式开关前置调节器和电容式开关后置转换器的高效dc/dc电压转换器
JP4925866B2 (ja) * 2007-02-28 2012-05-09 オンセミコンダクター・トレーディング・リミテッド チャージポンプ回路
US7911261B1 (en) * 2009-04-13 2011-03-22 Netlogic Microsystems, Inc. Substrate bias circuit and method for integrated circuit device
KR101003154B1 (ko) * 2009-05-15 2010-12-21 주식회사 하이닉스반도체 반도체 메모리 장치
TWI385903B (zh) * 2009-07-01 2013-02-11 Novatek Microelectronics Corp 可防止閉鎖現象之電壓產生裝置及其方法
JP5504782B2 (ja) * 2009-09-18 2014-05-28 ヤマハ株式会社 チャージポンプ
KR101097444B1 (ko) * 2009-12-29 2011-12-23 주식회사 하이닉스반도체 내부전압 생성회로 및 내부전압 생성방법
US9338036B2 (en) * 2012-01-30 2016-05-10 Nvidia Corporation Data-driven charge-pump transmitter for differential signaling
US10333397B2 (en) * 2017-07-18 2019-06-25 Stmicroelectronics International N.V. Multi-stage charge pump circuit operating to simultaneously generate both a positive voltage and a negative voltage
CN108418420B (zh) * 2018-04-27 2019-12-10 电子科技大学 一种基于多路非交叠时钟的电荷泵电路
CN115004561A (zh) * 2020-01-16 2022-09-02 Qorvo美国公司 多模天线调谐器电路和相关装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103973100A (zh) * 2013-01-25 2014-08-06 北京兆易创新科技股份有限公司 一种正负电压产生装置
US20150187316A1 (en) * 2013-12-31 2015-07-02 Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. Positive and negative voltage generating circuit, liquid crystal display module driving system, and voice over internet protocol phone
CN105954670A (zh) * 2016-05-26 2016-09-21 工业和信息化部电子第五研究所 集成电路esd失效预警电路
CN109039059A (zh) * 2018-08-23 2018-12-18 合肥工业大学 一种高效的多模式电荷泵
CN111146941A (zh) * 2019-12-31 2020-05-12 江苏芯力特电子科技有限公司 一种高性能的正负倍压电荷泵电路
CN112448576A (zh) * 2020-11-16 2021-03-05 上海唯捷创芯电子技术有限公司 一种正负电压电荷泵电路、芯片及通信终端

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4246791A4

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115001477A (zh) * 2022-07-19 2022-09-02 深圳芯能半导体技术有限公司 一种用于正负电压输入的信号接口电路
CN115037149A (zh) * 2022-08-11 2022-09-09 深圳市微源半导体股份有限公司 负压电荷泵电路
CN115469242A (zh) * 2022-09-13 2022-12-13 江苏万邦微电子有限公司 负电源监控系统及方法
CN115469242B (zh) * 2022-09-13 2024-01-12 江苏万邦微电子有限公司 负电源监控系统及方法
CN115498856A (zh) * 2022-09-19 2022-12-20 上海南麟电子股份有限公司 一种驱动电路及芯片
CN115425958A (zh) * 2022-11-04 2022-12-02 西安水木芯邦半导体设计有限公司 一种用于控制高压模拟开关的栅源电压保持电路

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