WO2022078059A1 - 一种电荷泵电路、芯片及通信终端 - Google Patents

一种电荷泵电路、芯片及通信终端 Download PDF

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Publication number
WO2022078059A1
WO2022078059A1 PCT/CN2021/113336 CN2021113336W WO2022078059A1 WO 2022078059 A1 WO2022078059 A1 WO 2022078059A1 CN 2021113336 W CN2021113336 W CN 2021113336W WO 2022078059 A1 WO2022078059 A1 WO 2022078059A1
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Prior art keywords
charge pump
capacitor
output
pmos transistor
sub
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PCT/CN2021/113336
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English (en)
French (fr)
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高晨阳
林升
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唯捷创芯(天津)电子技术股份有限公司
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Priority to JP2023522442A priority Critical patent/JP2023546065A/ja
Priority to EP21879106.9A priority patent/EP4228136A1/en
Priority to KR1020237015987A priority patent/KR20230084304A/ko
Publication of WO2022078059A1 publication Critical patent/WO2022078059A1/zh
Priority to US18/299,056 priority patent/US20230291310A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0043—Converters switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/081—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H02M1/15—Arrangements for reducing ripples from dc input or output using active elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Definitions

  • the invention relates to a charge pump circuit, an integrated circuit chip including the charge pump circuit and a corresponding communication terminal, and belongs to the field of analog integrated circuits.
  • the charge pump circuit is more and more integrated inside the chip, but because the charge pump circuit has high requirements on the power supply, in order to reduce the ripple interference of the charge pump circuit on the power supply, it is generally necessary to Add large off-chip capacitors to its power port. This means not only increasing the cost of the power supply system, but also reducing the reliability of the entire system.
  • a charge pump circuit is disclosed in the Chinese invention patent with the patent number of ZL 201810049855.1.
  • the working principle of the circuit is to divide the charge pump into N-stage sub-charge pump circuits, and then use the delay to delay the clock signal one by one to provide the corresponding clock signal for the N-stage sub-charge pump, and then detect the charge through the control unit.
  • the output voltage ripple of the pump is adjusted, and the delay is adjusted to reduce the output voltage ripple of the charge pump.
  • the number of sub-charge pump circuits will be increased, which will not only increase the circuit complexity, but also increase the peak current of the input power supply.
  • the primary technical problem to be solved by the present invention is to provide a charge pump circuit.
  • Another technical problem to be solved by the present invention is to provide an integrated circuit chip and a communication terminal including the above-mentioned charge pump circuit.
  • the present invention adopts the following technical scheme:
  • a charge pump circuit including a phase clock generation module, an acceleration response control module, and a plurality of sub-charge pump modules, wherein an output end of the phase clock generation module is connected to an output terminal of each sub-charge pump module.
  • the clock control terminal, the plurality of sub-charge pump modules are connected in parallel to the input power supply terminal and the output voltage terminal, the output voltage terminal is connected to the input terminal of the acceleration response control module, and the output terminal of the acceleration response control module is connected to the an input end of the phase clock generation module and each of the sub-charge pump modules;
  • the phase clock generation module generates a plurality of clock signals with a fixed phase difference, correspondingly controls the plurality of sub-charge pump modules to generate output voltages, and at the same time detects the output voltages by the acceleration response control module, and sends them to the The phase clock generation module and each sub-charge pump module output logic signals, so that when the output voltage does not reach the target value, the phase clock generation module generates an accelerated clock signal to rapidly generate the output voltage, and when the output voltage does not reach the target value When the target value is reached, the phase clock generating module controls each sub-charge pump module to maintain a normal output voltage.
  • the phase clock generation module includes a first inverter and a plurality of phase clock sub-circuits composed of a first NMOS transistor, a first capacitor, a second capacitor, an output node and a second inverter; wherein , the input end of the first inverter is connected to the output end of the acceleration response control module, the output end of the first inverter is connected to the gate of each first NMOS transistor, the The first capacitor is connected in series between the drain and the corresponding output node, the source of each first NMOS transistor is grounded, each output node is connected to the corresponding sub-charge pump module, and each output node is connected to the ground
  • the second capacitors are connected in series, and each of the second inverters is cascaded and connected to the power supply and the ground, and then connected end to end to form a ring oscillator.
  • the second inverter includes a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor are correspondingly connected, and the first PMOS transistor The source of the transistor is connected to the power supply, and the source of the second NMOS transistor is grounded.
  • the size of the load capacitance of the output node of the phase clock generation module is changed to adjust the output voltage generated by the ring oscillator.
  • the width to length ratio of the switch tube in each of the second inverters is changed, so as to change the first
  • the equivalent resistance of the two inverters can adjust the oscillation frequency of a plurality of clock signals with a fixed phase difference generated by the ring oscillator.
  • each sub-charge pump module when each of the sub-charge pump modules provides a higher voltage output than the input power supply, each sub-charge pump module includes a third NMOS transistor, a fourth NMOS transistor, a second PMOS transistor, a third PMOS transistor, The fourth PMOS tube, the fifth PMOS tube, the first selection switch, the second selection switch, the third selection switch, the fourth selection switch and the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor and the eighth capacitor, The substrate end and source of the third NMOS transistor and the substrate end and source of the fourth NMOS transistor are respectively connected to the input power supply, and the gate of the third NMOS transistor is respectively connected to the gate of the fourth NMOS transistor.
  • the drain, a plate of the fourth capacitor and the drain of the second PMOS transistor, the drain of the third NMOS transistor is respectively connected to the gate of the fourth NMOS transistor, the drain of the third capacitor A plate and the drain of the third PMOS transistor, the substrate end and source of the second PMOS transistor, the substrate end and source of the third PMOS transistor, and the liner of the fourth PMOS transistor
  • the bottom end and the source electrode and the substrate end and the source electrode of the fifth PMOS transistor are respectively connected to the output voltage end and one end of the eighth capacitor, the other end of the eighth capacitor is grounded, and the second PMOS transistor is connected to the ground.
  • the gate is respectively connected to a plate of the sixth capacitor, the drain of the fourth PMOS transistor and the gate of the fifth PMOS transistor, and the gate of the third PMOS transistor is respectively connected to the fifth capacitor one plate of the fifth PMOS transistor, the drain of the fifth PMOS transistor and the gate of the fourth PMOS transistor, the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are the other One pole plate is connected to the moving terminal of the corresponding selection switch, the moving terminals of the selection switch are respectively connected to the respective clock control terminals, and the clock control terminal of the selection switch is correspondingly connected to the same output node of the phase clock generation module, One static end of the selector switch is connected to the power supply, the other static end is connected to the ground end, the response control end of the selector switch is respectively connected to the output end of the acceleration response control module, and the input end of the acceleration response control module is connected to the the output voltage terminal.
  • the third NMOS transistor and the fourth NMOS transistor in each sub-charge pump module are correspondingly replaced with the fifth NMOS transistor.
  • NMOS tube and sixth NMOS tube replace the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube with the sixth PMOS tube, the seventh PMOS tube, the third PMOS tube Eight PMOS tubes and a ninth PMOS tube.
  • each selection switch includes a tenth PMOS transistor, a seventh NMOS transistor, an OR gate, an AND gate, a third inverter, and at least one eleventh PMOS transistor and at least one eighth NMOS transistor.
  • the gates of the tenth PMOS transistor and the seventh NMOS transistor are connected to serve as the clock control terminal of the selection switch for connecting an output node of the phase clock generation module, the tenth PMOS transistor and the seventh NMOS transistor.
  • the gate of the gate is correspondingly connected to an input end of the OR gate and the AND gate, the drains of the tenth PMOS transistor and the seventh NMOS transistor, each eleventh PMOS transistor and the corresponding eighth NMOS transistor After the drains are connected to each other, they are used as the moving end of the selection switch, which is used to connect the other plate of the corresponding capacitor.
  • the tenth PMOS tube and the source of each eleventh PMOS tube are respectively connected to the power supply.
  • the seventh The NMOS transistor and the source of each eighth NMOS transistor are respectively grounded, the gate of each eleventh PMOS transistor is connected to the output end of the OR gate, and the gate of each eighth NMOS transistor is connected to the output of the AND gate terminal, the other input terminal of the OR gate is connected to the output terminal of the third inverter, and the other input terminal of the AND gate is connected to the input terminal of the third inverter and the acceleration response control module 's output.
  • the acceleration response control module includes a first resistor, a second resistor and a hysteresis comparator, one end of the first resistor is respectively connected to the output voltage terminals of each sub-charge pump module, and the other end of the first resistor is connected to the output voltage terminals of each sub-charge pump module respectively.
  • One end is respectively connected to one end of the second resistor, the inverting input end of the hysteresis comparator, the other end of the second resistor is grounded, the non-inverting input end of the hysteresis comparator is connected to the reference voltage, and the hysteresis comparator
  • the output end of the inverter is respectively connected to the input end of the first inverter and the input end of the third inverter in each sub-charge pump module.
  • an integrated circuit chip including the above-mentioned charge pump circuit.
  • a communication terminal including the above-mentioned charge pump circuit.
  • the charge pump circuit provided by the present invention generates a plurality of clock signals with a fixed phase difference through a phase clock generation module, so as to correspondingly control a plurality of sub-charge pump modules to generate an output voltage, and respond to the output voltage of each sub-charge pump module by an accelerated response control module.
  • the invention can effectively reduce the peak current drawn by the charge pump circuit from the input power supply, and reduce the ripple interference generated by the charge pump circuit on the input power supply and the output voltage signal, thereby reducing the dependence of the input power supply on off-chip capacitors.
  • Fig. 1 is the typical application block diagram of the existing charge pump circuit
  • FIG. 2 is a structural block diagram of a charge pump circuit provided by an embodiment of the present invention.
  • FIG. 3 is a circuit schematic diagram of a phase clock generation module in the charge pump circuit provided by an embodiment of the present invention.
  • FIG. 5 is a schematic time sequence diagram of a charge pump circuit provided by an embodiment of the present invention.
  • FIG. 6 is another schematic circuit diagram of each sub-charge pump module in the charge pump circuit provided by the embodiment of the present invention.
  • FIG. 7 is a schematic circuit diagram of a selection switch of each sub-charge pump module in a charge pump circuit provided by an embodiment of the present invention.
  • FIG. 8 is a circuit schematic diagram of an accelerated response control module in a charge pump circuit provided by an embodiment of the present invention.
  • an embodiment of the present invention first provides a charge pump circuit, including a phase clock generation module 101, an acceleration response control module 105, and a plurality of sub-charge pump modules (for example, the plurality of sub-charge pump modules 102, 103, 104); the output end of the phase clock generation module 101 is connected to the clock control end of each sub-charge pump module, and the multiple sub-charge pump modules are connected in parallel to the input power supply end VIN and the output voltage end VOUT correspondingly, and the output voltage end VOUT is connected to the acceleration response
  • the input end of the control module 105 and the output end of the acceleration response control module 105 are connected to the phase clock generation module 101 and the input end of each sub-charge pump module.
  • the phase clock generation module 101 is used to generate a plurality of clock signals with a fixed phase difference, so as to correspondingly control a plurality of sub-charge pump modules to generate output voltages.
  • the clock generation module 101 and each sub-charge pump module output logic signals, so that when the output voltages of the plurality of sub-charge pump modules do not reach the target value, the phase clock generation module 101 generates an accelerated clock signal to control each sub-charge pump module to quickly generate an output voltage , and when the output voltages of the plurality of sub-charge pump modules reach the target value, the phase clock generating module 101 controls each sub-charge pump module to maintain a normal output voltage.
  • the above-mentioned phase difference may be 45 degrees, 60 degrees, 90 degrees, 120 degrees, or 180 degrees, etc.
  • the corresponding number of sub-charge pump modules is 8, 6 1, 4, 3 or 2 etc.
  • the number of sub-charge pump modules can be flexibly adjusted on the premise that the rising edge and the falling edge of the clock signal with a fixed phase difference received by each sub-charge-pump module at the same time do not overlap.
  • the phase clock generation module 101 includes a first inverter INV1, a plurality of first NMOS transistors (eg, first NMOS transistors MN4-MN6), a first capacitor (eg, capacitors C11-C31), a second A phase clock sub-circuit composed of capacitors (such as capacitors C1-C3), an output node and the second inverter 1010.
  • a first inverter INV1 a plurality of first NMOS transistors (eg, first NMOS transistors MN4-MN6), a first capacitor (eg, capacitors C11-C31), a second A phase clock sub-circuit composed of capacitors (such as capacitors C1-C3), an output node and the second inverter 1010.
  • the input end of the first inverter INV1 is connected to the output end of the acceleration response control module 105 , the output end of the first inverter INV1 is respectively connected to the gate of each first NMOS transistor, and the drain of each first NMOS transistor
  • the first capacitors are connected in series between the corresponding output nodes (output nodes PH1, PH2 and PH3), the source of each first NMOS transistor is grounded, each output node is connected to the corresponding sub-charge pump module, and each A second capacitor is correspondingly connected in series between the output node and the ground, and each second inverter 1010 is cascaded and connected to the power supply VDD and ground correspondingly, and then connected end to end to form a ring oscillator.
  • the number of the second inverters 1010 can be flexibly adjusted (the same as adjusting the sub-charge pump module). are similar in number and will not be repeated here).
  • the phase clock generating module 101 generates three clock signals with a phase difference of 120 degrees.
  • the phase clock generation module 101 includes a first inverter INV1, three first NMOS transistors MN4-MN6, three first capacitors C11-C31, three second capacitors C1-C3, three output nodes PH1, PH2 and PH3 and three second inverters 1010.
  • the input end of the first inverter INV1 is connected to the output end of the acceleration response control module 105, the output end of the first inverter INV1 is respectively connected to the gates of the three first NMOS transistors MN4-MN6, and the first NMOS transistor MN4
  • a first capacitor C11 is connected in series with the output node PH1
  • a first capacitor C21 is connected in series between the first NMOS transistor MN5 and the output node PH2
  • a first capacitor C31, 3 is connected in series between the first NMOS transistor MN6 and the output node PH3
  • the sources of the first NMOS transistors MN4-MN6 are grounded, the three output nodes PH1, PH2 and PH3 are connected to the corresponding sub-charge pump modules, the second capacitor C1 is connected in series between the output node PH1 and the ground, and the output node PH2 is connected to the ground.
  • the second capacitor C2 is connected in series between the output node PH
  • Each second inverter includes a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor are connected correspondingly, the source of the first PMOS transistor is connected to the power supply, and the second NMOS transistor The source is grounded. As shown in FIG.
  • the phase clock generation module 101 including three second inverters taking the phase clock generation module 101 including three second inverters as an example, the first PMOS transistor MP1 and the second NMOS transistor MN1, the first PMOS transistor MP2 and the second NMOS transistor MN2, the first PMOS transistor MP1 and the second NMOS transistor MN2, the first PMOS transistor MP1 and the second NMOS transistor MN1
  • the tube MP3 and the second NMOS tube MN3 respectively form a one-stage second inverter, thereby obtaining a three-stage second inverter; wherein, the second inverters after the cascade are connected end to end, that is, the third stage second inverter
  • the drains of the first PMOS transistor MP3 and the second NMOS transistor MN3 of the inverter are connected together and then connected to the gates of the first PMOS transistor MP1 and the second NMOS transistor MN1 of the first stage second inverter.
  • the output nodes PH1 ⁇ PH3 of the phase clock generating module 101 are the output nodes of the corresponding second inverters 1010 , and the first capacitors C11 ⁇ C31 and the second capacitors C1 ⁇ C3 are the output nodes of each second inverter 1010 , respectively.
  • the load capacitance of the output node, the gate voltage of the first NMOS transistors MN4 ⁇ MN6 is the output of the first inverter INV1 , and the first inverter INV receives the logic signal output by the acceleration response control module 105 . Because the oscillation frequency f of the ring oscillator composed of the second inverter 1010 has the following relationship:
  • R on represents the equivalent resistance of the second inverter 1010
  • CL represents the load capacitance of the output node of the second inverter 1010 .
  • the load capacitances of the output node of the phase converter 1010 are the second capacitors C1-C3, that is, the load capacitance of the output node PH1 is the second capacitor C1, the load capacitance of the output node PH2 is the second capacitor C2, and the load capacitance of the output node PH3 is the second capacitor C2.
  • Capacitor C3 when the logic signal fast_en output by the acceleration response control module 105 is at a low level, the gate voltages of the first NMOS transistors MN4 to MN6 are at a high level, so that the first NMOS transistors MN4 to MN6 are in a conducting state.
  • the load capacitances of the output nodes of the second inverters 1010 are the second capacitors C1-C3 and the first capacitors C11-C31, that is, the load equivalent capacitance of the output node PH1 is the second capacitor C1 and the first capacitor C11 in parallel, and the output node
  • the load equivalent capacitance of PH2 is the parallel connection of the second capacitor C2 and the first capacitor C21
  • the load equivalent capacitance of the output node PH3 is the parallel connection of the second capacitor C3 and the first capacitor C31.
  • the phase clock generation module 101 controls each sub-charge pump module to quickly generate an output
  • the logic signal output by the acceleration response control module 105 is at a low level
  • the load capacitance of the output node of each second inverter 1010 increases relative to the logic signal output by the acceleration response control module 105 at a high level.
  • the oscillation frequency of the clock signal output by the ring oscillator is reduced, so that when the output voltages of the sub-charge pump modules reach the target value, the phase clock generation module 101 controls each sub-charge pump module to maintain a normal output voltage.
  • the oscillation of the plurality of clock signals with fixed phase differences generated by the ring oscillator can be adjusted.
  • the size of the frequency based on the clock signal output by the phase clock generation module 101 with a phase difference of 120 degrees, not only realizes the control of each sub-charge pump module to generate an output voltage, but also reduces the input power supply at the same time.
  • each sub-charge pump module draws current from the input power supply in a time-sharing manner at the same time, reducing the peak current drawn by each sub-charge pump module from the input power supply, thereby reducing the input power supply due to excessive peak current. resulting input power supply ripple.
  • the width and length of the conduction channel of the switch transistors (ie, the first PMOS transistor and the second NMOS transistor) in each second inverter 1010 can also be changed by changing ratio (referred to as the width-length ratio for short) to change the equivalent resistance of the second inverter 1010 to adjust the oscillation frequency of multiple clock signals with a fixed phase difference generated by the ring oscillator, which will not be described in detail here. .
  • each sub-charge pump module When each sub-charge pump module provides a voltage output higher than the input power supply Vin, as shown in FIG. 4 , each sub-charge pump module includes a third NMOS transistor MN7, a fourth NMOS transistor MN8, a second PMOS transistor MP4, and a third PMOS transistor tube MP5, fourth PMOS tube MP6, fifth PMOS tube MP7, first selection switch SW1, second selection switch SW2, third selection switch SW3, fourth selection switch SW4 and third capacitor C4, fourth capacitor C5, The fifth capacitor C6, the sixth capacitor C7 and the eighth capacitor C8.
  • each part in each sub-charge pump module is as follows: the substrate end and source of the third NMOS transistor MN7, the substrate end and source of the fourth NMOS transistor MN8 are respectively connected to the input power supply Vin, and the third NMOS transistor MN7 is connected to the input power supply Vin.
  • the gate is respectively connected to the drain of the fourth NMOS transistor MN8, one plate A of the fourth capacitor C5 and the drain of the second PMOS transistor MP4, and the drain of the third NMOS transistor MN7 is respectively connected to the gate of the fourth NMOS transistor MN8 , a plate B of the third capacitor C4 and the drain of the third PMOS tube MP5, the substrate end and source of the second PMOS tube MP4, the substrate end and source of the third PMOS tube MP5, and the fourth PMOS tube
  • the substrate terminal and source of MP6 and the substrate terminal and source of the fifth PMOS transistor MP7 are respectively connected to the output voltage terminal VOUT and one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is grounded, and the second PMOS transistor MP4
  • the gate is respectively connected to a plate D of the sixth capacitor C7, the drain of the fourth PMOS transistor MP6 and the gate of the fifth PMOS transistor MP7, and the gate of the third PMOS transistor MP5 is respectively connected to a plate of the fifth capacitor C6 C.
  • the drain of the fifth PMOS transistor MP7 and the gate of the fourth PMOS transistor MP6, the other plate of the third capacitor C4 is connected to the moving end of the first selection switch SW1, and the other plate of the fourth capacitor C5 is connected to the first selection switch SW1.
  • the moving terminal of the second selection switch SW2, the other pole plate of the fifth capacitor C6 is connected to the moving terminal of the third selection switch SW3, the other pole plate of the sixth capacitor C7 is connected to the moving terminal of the fourth selection switch SW4, and the first selection switch
  • the moving terminals of SW1, the second selection switch SW2, the third selection switch SW3 and the fourth selection switch SW4 are respectively connected to their respective clock control terminals.
  • the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the third selection switch The clock control terminals of the four selection switches SW4 are correspondingly connected to the same output node of the phase clock generating module 101, and one static terminal of the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the fourth selection switch SW4 is connected to the power supply VDD, and the other static terminal is connected to the ground terminal GND.
  • the response control terminals of the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the fourth selection switch SW4 are connected to the output terminal of the acceleration response control module 105, and the input terminal of the acceleration response control module 105 is connected to the output voltage terminal VOUT.
  • the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the The four selection switches SW4 receive clock signals from the same output node in the phase clock generation module 101 in time division, that is, the first selection switch SW1 receives the first clock signal ⁇ 1 through the clock control terminal, and the second selection switch SW2 receives the first clock signal ⁇ 1 through the clock control terminal.
  • the first selection switch SW1 receives the first clock signal ⁇ 1 through the clock control terminal
  • the second selection switch SW2 receives the first clock signal ⁇ 1 through the clock control terminal.
  • the third selection switch SW3 receives the third clock signal ⁇ 3 through the clock control terminal
  • the fourth selection switch SW4 receives the fourth clock signal ⁇ 4 through the clock control terminal.
  • the selection switches SW1-SW4 are controlled by the clock signals ⁇ 1- ⁇ 4 output from the same output node in the phase clock generating module 101, and the capacitors C4-C7 are charged and discharged in time-sharing, and the third NMOS transistors MN7, The four NMOS transistors MN8, the second PMOS transistor MP4, the third PMOS transistor MP5, the fourth PMOS transistor MP6 and the fifth PMOS transistor MP7 are turned on and off to transfer the charges on the capacitors C4 to C7 to the eighth capacitor C8 superior.
  • the selection switches SW1-SW4 are controlled by the clock signals ⁇ 1- ⁇ 4 respectively, and the capacitors C4-C7 are charged and discharged in time-sharing to reduce the number of charging capacitors in each sub-charge pump module by the input power supply at the same time, thereby reducing the input power supply due to The input power supply ripple caused by excessive peak current reduces the input power supply's dependence on off-chip capacitors.
  • the capacitors C4 to C7 are charged in time-sharing, thus reducing the charging capacitor of the input power Vin at the same time, thereby reducing the charging current of the input power to the capacitors C4 to C7 and the resulting input power supply ripple.
  • the clock control terminal controls the moving terminals of the selection switches SW1 to SW4 to be connected to the ground terminal GND, so that the fourth capacitor C5 and the third capacitor C4
  • the plates A and B are charged to the Vin potential by the body diodes of the third NMOS transistor MN7 and the fourth NMOS transistor MN8.
  • the plates of the fourth capacitor C5 and the fifth capacitor C6 respectively connected with the second selection switch SW2 and the third selection switch SW3 are connected to the power supply VDD for charging, and the fourth capacitor C5 and the third selection switch SW3 are respectively charged.
  • the fifth capacitor C6 is in a charged state, and the voltages of the plates A and C of the fourth capacitor C5 and the fifth capacitor C6 are the input power source Vin+the power source VDD.
  • the first selection switch SW1 and the fourth selection switch SW4 short-circuit the plates connected to the third capacitor C4 and the sixth capacitor C7 to the ground terminal GND, and the third capacitor C4 and the sixth capacitor C7 are in a hold state, and the voltages of the plates B and D of the third capacitor C4 and the sixth capacitor C7 are the input power Vin.
  • the third NMOS transistor MN7 is turned on, the fourth NMOS transistor MN8 is turned off, the second PMOS transistor MP4 and the fifth PMOS transistor MP7 are turned on, the third PMOS transistor MP5 and the fourth PMOS transistor MP6 are turned off, so the fifth capacitor C6
  • the charges in the fourth capacitor C5 and the fourth capacitor C5 are transferred to the eighth capacitor C8 to charge the eighth capacitor C8, and the third capacitor C4 and the sixth capacitor C7 are in a holding state.
  • the clock signals ⁇ 1 and ⁇ 4 jump from high level to low level, and the plates of the third capacitor C4 and the sixth capacitor C7 respectively connected with the first selection switch SW1 and the fourth selection switch SW4 are connected to the power supply VDD,
  • the voltages of the plates B and D of the third capacitor C4 and the sixth capacitor C7 are respectively the input power supply Vin+power supply VDD; therefore, the third NMOS transistor MN7 is turned off, the fourth NMOS transistor MN8 is turned on, and the second PMOS transistor MP4 and the fifth
  • the PMOS transistor MP7 is turned off, the fourth PMOS transistor MP6 and the third PMOS transistor MP5 are turned on, and the charges in the third capacitor C4 and the sixth capacitor C7 are respectively transferred to the eighth capacitor C8, and the eighth capacitor C8 is charged.
  • the capacitor C5 and the fifth capacitor C6 are in a hold state.
  • the third capacitor C4 and the sixth capacitor C7, and the fourth capacitor C5 and the fifth capacitor C6 do not draw current from the power supply VDD at the same time, so that the power supply VDD
  • the peak current will be significantly smaller, but in the process of charge transfer, the third capacitor C4 and the sixth capacitor C7 or the fourth capacitor C5 and the fifth capacitor C6 jointly provide the transfer charge to the eighth capacitor C8.
  • the fourth capacitor C5 and the fifth capacitor C6 are in a state of providing transfer charges to the eighth capacitor C8, and when the third capacitor C4 and the sixth capacitor C7 are in a charging state, at the moment when the clock is flipped, the fourth capacitor C5 can be First switch from the transfer state to the charge state, then the fifth capacitor C6 switches from the transfer state to the charge state, then the third capacitor C4 switches from the charge state to the transfer state, and finally switches from the charge state to the transfer state.
  • each sub-charge pump module can also provide a voltage output lower than the ground voltage VSS. As shown in FIG. 6 , when a voltage output lower than the ground voltage VSS needs to be provided, it is only necessary to replace the third NMOS transistor MN7 and the fourth NMOS transistor MN8 in each sub-charge pump module with the sixth PMOS transistor MP8 and the fourth NMOS transistor correspondingly.
  • each selection switch includes a tenth PMOS transistor MP12, a seventh NMOS transistor MN11, an OR gate OR1, an AND gate AND1, a third inverter INV2, and at least one eleventh PMOS transistor MP13 and an eighth NMOS transistor Tube MN12.
  • each part of the selection switch is as follows: the gates of the tenth PMOS transistor MP12 and the seventh NMOS transistor MN11 are connected together as the clock control terminal of the selection switch, which is used to connect to a certain output node of the phase clock generation module 101 to receive The clock signal ⁇ i output by the phase clock generation module 101 (any one of the clock signals ⁇ 1 to ⁇ 4); the gates of the tenth PMOS transistor MP12 and the seventh NMOS transistor MN11 are also connected to an input of the OR gate OR1 and the AND gate AND1 correspondingly terminal, the drains of the tenth PMOS transistor MP12 and the seventh NMOS transistor MN11, and the drains of each eleventh PMOS transistor MP13 and the corresponding eighth NMOS transistor MN12 are connected to each other as the moving terminal of the selection switch, used for Connect the other plate of the corresponding capacitor (one of the capacitors C4 to C7), the tenth PMOS transistor MP12 and the source of each eleventh PMOS transistor MP13 are respectively connected to
  • the acceleration response control module 105 detects that the output voltage of each sub-charge pump module does not reach the target value, the logic signal fast_en output by the acceleration response control module 105 to the third inverter INV2 is high level, when the clock signal ⁇ i is high.
  • the output of the AND gate AND1 is a high level, so that the seventh NMOS transistor MN11 and at least one eighth NMOS transistor MN12 are connected in parallel, and the pull-down resistance corresponding to each sub-charge pump module is reduced, that is, the resistance of each sub-charge pump module is increased.
  • the discharge current of the eighth capacitor R8 connected to the output voltage terminal reduces the on-resistance on the discharge path.
  • the output of the OR gate OR11 is at a low level, so that the pull-up resistance of the output voltage VOUT is the parallel impedance of the tenth PMOS transistor MP12 and at least one eleventh PMOS transistor MP13, which reduces the The pull-up resistance corresponding to each sub-charge pump module increases the charging current of the eighth capacitor R8 connected to the output voltage terminal of each sub-charge pump module, and reduces the on-resistance on the charging path.
  • the charging speed of each sub-charge pump module to C4-C7 under the control of the high-frequency clock signal is increased by reducing the on-resistance of the third inverter INV2, thereby reducing the charging speed of each sub-charge pump module.
  • the logic signal is 0, and the clock signal ⁇ i is low level and high level
  • the on-resistance of the third inverter INV2 is determined by the tenth PMOS transistor MP12 respectively. .
  • the on-resistance of the seventh NMOS transistor MN11 is determined.
  • the frequency of the clock signal ⁇ i decreases, and the pull-up and pull-down resistance of the selection switch increases, as long as the charging performance of each sub-charge pump module is not affected. Therefore, after the output voltage of each sub-charge pump module reaches a steady state, due to the increase of the pull-up and pull-down resistance of the selection switch, the speed at which the capacitors C4-C7 draw current from the power supply becomes slower, which can further reduce the input power supply when the charge pump circuit is working. the peak current.
  • the acceleration response control module 105 includes a first resistor R1, a second resistor R0 and a hysteresis comparator Comp; one end of the first resistor R1 is connected to the output voltage terminal VOUT of each sub-charge pump module, and the first resistor R1 The other end is respectively connected to one end of the second resistor R0 and the inverting input end of the hysteresis comparator Comp, the other end of the second resistor R0 is grounded, the non-inverting input end of the hysteresis comparator Comp is connected to the reference voltage VREF, and the output of the hysteresis comparator Comp is connected to the ground.
  • the terminal is connected to the input terminal of the first inverter INV1 of the phase clock generating module 101 and the input terminal of the third inverter INV2 of each sub-charge pump module.
  • each sub-charge pump module is detected by the acceleration response detection module 105.
  • the output logic signal fast_en of the hysteresis comparator Comp is a high level, and is output to Phase clock generation module 101 and each sub-charge pump module.
  • the oscillation frequency of the ring oscillator is changed, and in each sub-charge pump module, the charging and discharging speed of the capacitor is adjusted, so that each sub-charge pump module can quickly generate an output voltage.
  • the output logic signal fast_en of the hysteresis comparator Comp is a low level, so that the charge pump circuit operates in a low peak current and low power consumption state.
  • a threshold inversion voltage can be set in the hysteresis comparator Comp, and the threshold inversion voltage is VREF(1+R1/R0). Adjust the first resistance R1, The ratio of the second resistor R0 can be set to the threshold inversion voltage. If the output voltage of each sub-charge pump module reaches the threshold inversion voltage, it is considered that the output voltage of each sub-charge pump module reaches the target value.
  • charge pump circuit provided by the embodiment of the present invention can be used in an analog integrated circuit chip.
  • the specific structure of the charge pump circuit in the analog integrated circuit chip will not be described in detail here.
  • the above-mentioned charge pump circuit can also be used in various communication terminals as an important part of an analog integrated circuit.
  • the communication terminal mentioned here refers to the computer equipment that can be used in the mobile environment and supports various communication standards such as GSM, EDGE, TDD_LTE, FDD_LTE, 5G NR, etc., including mobile phones, notebook computers, tablet computers, car computers, etc.
  • the technical solutions provided by the present invention are also applicable to other analog integrated circuit applications, such as communication base stations and the like.
  • the charge pump circuit provided by the present invention generates a plurality of clock signals with a fixed phase difference through the phase clock generation module, so as to correspondingly control the plurality of sub-charge pump modules to generate output voltages, and the acceleration response control module is used to control each sub-module.
  • the output voltage of the charge pump module is detected, and logic signals are output to the phase clock generation module and each sub-charge pump module respectively to change the frequency of the clock signal output by the phase clock generation module and reduce the charge and discharge of the capacitors in each sub-charge pump module. time.
  • the invention can effectively reduce the peak current drawn by the charge pump circuit from the input power supply, and reduce the ripple interference generated by the charge pump circuit on the input power supply and the output voltage signal, thereby reducing the dependence of the input power supply on off-chip capacitors.

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Abstract

本发明公开了一种电荷泵电路、芯片及通信终端。该电荷泵电路包括相位时钟产生模块、加速响应控制模块以及多个子电荷泵模块。通过相位时钟产生模块产生多个相位差固定的时钟信号，对应控制多个子电荷泵模块产生输出电压；通过加速响应控制模块对各个子电荷泵模块的输出电压进行检测，并分别向相位时钟产生模块以及各个子电荷泵模块输出逻辑信号，以改变相位时钟产生模块输出的时钟信号的频率，减少各个子电荷泵模块中电容的充放电时间。利用本发明，可以有效减小电荷泵电路从输入电源汲取的峰值电流，并减轻电荷泵电路对输入电源以及输出电压信号产生的纹波干扰。

Description

一种电荷泵电路、芯片及通信终端 技术领域
本发明涉及一种电荷泵电路，同时也涉及包括该电荷泵电路的集成电路芯片及相应的通信终端，属于模拟集成电路领域。
背景技术
传统的电荷泵电路依赖于外部电源供电，该外部电源可以采用低压差线性稳压器或直流-直流电源实现。如图1所示，当采用低压差线性稳压器同时为电荷泵电路与高精度电路进行供电时，由于电荷泵电路自身的特点，当其内部开关进行切换时，往往会伴随着较大的瞬态峰值电流。如果该峰值电流过大，不仅会影响供电系统的电源稳定性，而且还会影响其它高精度电路的精度。例如，高精度数模转换器的有效位数，精密运算放大器的输出失调电压等都会受其影响。
随着集成电路集成度的不断提高，电荷泵电路越来越多地被集成在芯片内部，但是由于电荷泵电路对电源要求较高，为了减小电荷泵电路对电源的纹波干扰，一般需要在其电源端口增加片外大电容。这意味着不仅增加了供电系统成本，而且降低了整个系统的可靠性。
专利号为ZL 201810049855.1的中国发明专利中公开了一种电荷泵电路。该电路的工作原理是通过将电荷泵拆分成N级子电荷泵电路，然后利用延时将时钟信号进行逐一延时，为N级子电荷泵提供相应的时钟信号，再通过调控单元检测电荷泵输出电压纹波大小，进而调整延时以降低电荷泵输出电压纹波的目的。但是，为了降低电荷泵电路输出的电压纹波，子电荷泵电路的数目就会增加，这样不但导致电路复杂度提升，而且会增大输入电源的峰值电流。
发明内容
本发明所要解决的首要技术问题在于提供一种电荷泵电路。
本发明所要解决的另一技术问题在于提供一种包括上述电荷泵电路的集成电路芯片及通信终端。
为了实现上述目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种电荷泵电路，包括相位 时钟产生模块、加速响应控制模块以及多个子电荷泵模块，所述相位时钟产生模块的输出端连接每个子电荷泵模块的时钟控制端，所述多个子电荷泵模块并联后对应连接输入电源端和输出电压端，所述输出电压端连接所述加速响应控制模块的输入端，所述加速响应控制模块的输出端连接所述相位时钟产生模块和每个所述子电荷泵模块的输入端；
所述相位时钟产生模块产生多个相位差固定的时钟信号,对应控制所述多个子电荷泵模块产生输出电压，同时通过所述加速响应控制模块对所述输出电压进行检测后，分别向所述相位时钟产生模块以及各个子电荷泵模块输出逻辑信号，使得在所述输出电压未达到目标值时，所述相位时钟产生模块产生加速时钟信号以快速生成所述输出电压，以及在所述输出电压达到目标值时，所述相位时钟产生模块控制各个子电荷泵模块维持正常的输出电压。
其中较优地，所述相位时钟产生模块包括第一反相器和多个由第一NMOS管、第一电容、第二电容、输出节点以及第二反相器组成的相位时钟子电路；其中，所述第一反相器的输入端连接所述加速响应控制模块的输出端，所述第一反相器的输出端连接每个第一NMOS管的栅极，每个第一NMOS管的漏极与相应的输出节点之间对应串接所述第一电容，每个第一NMOS管的源极接地，每个输出节点连接相应的子电荷泵模块，并且每个输出节点到地之间对应串接所述第二电容，每个所述第二反相器级联并对应连接电源和地后首尾相连形成环形振荡器。
其中较优地，所述第二反相器包括第一PMOS管和第二NMOS管，所述第一PMOS管和所述第二NMOS管的栅极和漏极对应连接，所述第一PMOS管的源极连接电源，所述第二NMOS管的源极接地。
其中较优地，根据所述加速响应控制模块向所述相位时钟产生模块输出的逻辑信号的状态，改变所述相位时钟产生模块输出节点的负载电容的大小，以调节所述环形振荡器产生的多个相位差固定的时钟信号的振荡频率的大小。
其中较优地，根据所述加速响应控制模块向所述相位时钟产生模块输出的逻辑信号的状态，改变每个所述第二反相器中的开关管的宽长比，以改变所述第二反相器的等效电阻，实现调节所述环形振荡器 产生的多个相位差固定的时钟信号的振荡频率的大小。
其中较优地，当每个所述子电荷泵模块提供高于输入电源的电压输出时，每个子电荷泵模块包括第三NMOS管、第四NMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第五PMOS管、第一选择开关、第二选择开关、第三选择开关、第四选择开关和第三电容、第四电容、第五电容、第六电容和第八电容，所述第三NMOS管的衬底端与源极、所述第四NMOS管的衬底端与源极分别连接输入电源，所述第三NMOS管的栅极分别连接所述第四NMOS管的漏极、所述第四电容的一个极板以及所述第二PMOS管的漏极，所述第三NMOS管的漏极分别连接所述第四NMOS管的栅极、所述第三电容的一个极板以及所述第三PMOS管的漏极，所述第二PMOS管的衬底端与源极、所述第三PMOS管的衬底端与源极、所述第四PMOS管的衬底端与源极和所述第五PMOS管的衬底端与源极分别连接输出电压端和所述第八电容的一端，所述第八电容的另一端接地，所述第二PMOS管的栅极分别连接所述第六电容的一个极板、所述第四PMOS管的漏极和所述第五PMOS管的栅极，所述第三PMOS管的栅极分别连接所述第五电容的一个极板、所述第五PMOS管的漏极和所述第四PMOS管的栅极，所述第三电容、所述第四电容、所述第五电容和所述第六电容的另一个极板连接相应的选择开关的动端，所述选择开关的动端分别对应连接各自的时钟控制端，所述选择开关的时钟控制端对应连接所述相位时钟产生模块的同一个输出节点，所述选择开关的一个静端连接电源，另一个静端连接接地端，所述选择开关的响应控制端分别连接所述加速响应控制模块的输出端，所述加速响应控制模块的输入端连接所述输出电压端。
其中较优地，所述相位时钟产生模块中同一个输出节点输出的时钟信号控制相应的选择开关的导通和关断时，第一时钟信号和第三时钟信号、第二时钟信号和第四时钟信号为非交叠时钟信号，其非交叠时间为Tnov1；第一时钟信号和第二时钟信号、第三时钟信号和第四时钟信号为非交叠时钟信号，其非交叠时间分别为Tnov3和Tnov2，各非交叠时间满足关系为Tnov2＝2*Tnov1+Tnov3。
其中较优地，当每个所述子电荷泵模块提供低于接地电压的电压输出时，将每个子电荷泵模块中的所述第三NMOS管和所述第四NMOS 管对应替换为第五NMOS管和第六NMOS管，将所述第二PMOS管、所述第三PMOS管、所述第四PMOS管和所述第五PMOS管对应替换为第六PMOS管、第七PMOS管、第八PMOS管和第九PMOS管。
其中较优地，每个选择开关包括第十PMOS管、第七NMOS管、或门、与门、第三反相器以及至少一个第十一PMOS管和至少一个第八NMOS管，所述第十PMOS管、所述第七NMOS管的栅极连接以作为选择开关的时钟控制端，用于连接所述相位时钟产生模块的一个输出节点，所述第十PMOS管、所述第七NMOS管的栅极对应连接所述或门和所述与门的一个输入端，所述第十PMOS管与所述第七NMOS管的漏极、每个第十一PMOS管与对应的第八NMOS管的漏极相互连接后作为选择开关的动端，用于连接相应的电容的另一个极板，所述第十PMOS管与每个第十一PMOS管的源极分别连接电源，所述第七NMOS管与每个第八NMOS管的源极分别接地，每个第十一PMOS管的栅极连接所述或门的输出端，每个第八NMOS管的栅极连接所述与门的输出端，所述或门的另一个输入端连接所述第三反相器的输出端，所述与门的另一个输入端连接所述第三反相器的输入端和所述加速响应控制模块的输出端。
其中较优地，所述加速响应控制模块包括第一电阻、第二电阻和迟滞比较器，所述第一电阻的一端分别连接各个子电荷泵模块的输出电压端，所述第一电阻的另一端分别连接所述第二电阻的一端、所述迟滞比较器的反相输入端，所述第二电阻的另一端接地，所述迟滞比较器的正相输入端连接参考电压，所述迟滞比较器的输出端分别连接所述第一反相器的输入端、各个子电荷泵模块中的第三反相器的输入端。
根据本发明实施例的第二方面，提供一种集成电路芯片，包括上述的电荷泵电路。
根据本发明实施例的第三方面，提供一种通信终端，包括上述的电荷泵电路。
本发明所提供的电荷泵电路通过相位时钟产生模块产生多个相位差固定的时钟信号，以对应控制多个子电荷泵模块产生输出电压，并通过加速响应控制模块对各个子电荷泵模块的输出电压进行检测，并分别向相位时钟产生模块以及各个子电荷泵模块输出逻辑信号，以改 变相位时钟产生模块输出的时钟信号的频率，和减少各个子电荷泵模块中电容的充放电时间。利用本发明，可以有效减小电荷泵电路从输入电源汲取的峰值电流，并减轻电荷泵电路对输入电源以及输出电压信号产生的纹波干扰，从而减少了输入电源对片外电容的依赖。
附图说明
图1为现有电荷泵电路的典型应用框图；
图2为本发明实施例提供的电荷泵电路结构框图；
图3为本发明实施例提供的电荷泵电路中，相位时钟产生模块的电路原理图；
图4为本发明实施例提供的电荷泵电路中，每个子电荷泵模块的一种电路原理图；
图5为本发明实施例提供的电荷泵电路的一种时序示意图；
图6为本发明实施例提供的电荷泵电路中，每个子电荷泵模块的另一种电路原理图；
图7为本发明实施例提供的电荷泵电路中，每个子电荷泵模块的选择开关的电路原理图；
图8为本发明实施例提供的电荷泵电路中，加速响应控制模块的电路原理图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
为了减轻电荷泵电路对输入电源造成的较大的纹波干扰和噪声，以及减小输入电源对片外电容的依赖，降低供电系统成本并提升该系统的可靠性，以便稳定快速地产生电荷泵输出电压。如图2所示，本发明实施例首先提供一种电荷泵电路，包括相位时钟产生模块101、加速响应控制模块105以及多个子电荷泵模块(例如图1示出的多个子电荷泵模块102、103、104)；相位时钟产生模块101的输出端连接每个子电荷泵模块的时钟控制端，多个子电荷泵模块并联后对应连接输入电源端VIN和输出电压端VOUT，输出电压端VOUT连接加速响应控制模块105的输入端，加速响应控制模块105的输出端连接相位时钟产生模块101和每个子电荷泵模块的输入端。
采用相位时钟产生模块101产生多个相位差固定的时钟信号,以对应控制多个子电荷泵模块产生输出电压，同时通过加速响应控制模块105对各个子电荷泵模块的输出电压进行检测，分别向相位时钟产生模块101以及各个子电荷泵模块输出逻辑信号，使得在多个子电荷泵模块的输出电压未达到目标值时，相位时钟产生模块101产生加速时钟信号，控制各个子电荷泵模块快速生成输出电压，以及在多个子电荷泵模块的输出电压达到目标值时，相位时钟产生模块101控制各个子电荷泵模块维持正常的输出电压。
需要强调的是，在本发明的不同实施例中，上述相位差可以分别为45度、60度、90度、120度或180度等，相应的子电荷泵模块的数量分别为8个、6个、4个、3个或2个等。在保证各个子电荷泵模块同一时刻接收的相位差固定的时钟信号的上升沿和下降沿不会重叠的前提下，可以灵活调整子电荷泵模块的数量。例如，针对图1示出的3路子电荷泵模块102、103、104，相应的相位差为360度/3＝120度，依此类推。
如图3所示，相位时钟产生模块101包括第一反相器INV1、多个由第一NMOS管(如第一NMOS管MN4～MN6)、第一电容(如电容C11～C31)、第二电容(如电容C1～C3)、输出节点以及第二反相器1010组成的相位时钟子电路。其中，第一反相器INV1的输入端连接加速响应控制模块105的输出端，第一反相器INV1的输出端分别连接每个第一NMOS管的栅极，每个第一NMOS管的漏极与相应的输出节点(输出节点PH1、PH2和PH3)之间对应串接第一电容，每个第一NMOS管的源极接地，每个输出节点连接相应的子电荷泵模块，并且每个输出节点到地之间对应串接第二电容，每个第二反相器1010级联并对应连接电源VDD和接地后首尾相连形成环形振荡器。其中，在保证各第二反相器1010产生的相位差固定的时钟信号的上升沿和下降沿不会重叠的前提下，可以灵活调整第二反相器1010的数量(与调整子电荷泵模块的数量类似，在此不予赘述)。
如图3所示，以相位时钟产生模块101产生3个相位差为120度的时钟信号为例。该相位时钟产生模块101包括第一反相器INV1、3个第一NMOS管MN4～MN6、3个第一电容C11～C31、3个第二电容C1～ C3、3个输出节点PH1、PH2和PH3以及3个第二反相器1010。其中，第一反相器INV1的输入端连接加速响应控制模块105的输出端，第一反相器INV1的输出端分别连接3个第一NMOS管MN4～MN6的栅极，第一NMOS管MN4与输出节点PH1之间串接第一电容C11，第一NMOS管MN5与输出节点PH2之间串接第一电容C21，第一NMOS管MN6与输出节点PH3之间串接第一电容C31，3个第一NMOS管MN4～MN6的源极接地，3个输出节点PH1、PH2和PH3连接相应的子电荷泵模块，输出节点PH1到地之间串接第二电容C1，输出节点PH2到地之间串接第二电容C2，输出节点PH3到地之间串接第二电容C3，每个第二反相器1010级联并对应连接电源VDD和接地后首尾相连形成环形振荡器。
每个第二反相器包括第一PMOS管和第二NMOS管，第一PMOS管和第二NMOS管的栅极和漏极对应连接，第一PMOS管的源极连接电源，第二NMOS管的源极接地。如图3所示，以相位时钟产生模块101包括3个第二反相器为例，第一PMOS管MP1和第二NMOS管MN1、第一PMOS管MP2和第二NMOS管MN2、第一PMOS管MP3和第二NMOS管MN3分别组成了一级第二反相器，从而得到三级第二反相器；其中，级联之后的第二反相器首尾相连，即第三级第二反相器的第一PMOS管MP3和第二NMOS管MN3的漏极连接在一起后与第一级第二反相器的第一PMOS管MP1和第二NMOS管MN1的栅极连接。
其中，相位时钟产生模块101的输出节点PH1～PH3为相应的第二反相器1010的输出节点，第一电容C11～C31和第二电容C1～C3分别为每个第二反相器1010的输出节点的负载电容，第一NMOS管MN4～MN6的栅电压为第一反相器INV1的输出，第一反相器INV接收加速响应控制模块105输出的逻辑信号。由于第二反相器1010组成的环形振荡器的振荡频率f有如下关系：
Figure PCTCN2021113336-appb-000001
其中，R on表示第二反相器1010的等效电阻，C L表示第二反相器1010输出节点的负载电容。当加速响应控制模块105输出的逻辑信号fast_en为高电平时，第一NMOS管MN4～MN6的栅电压为低电平，使得第一NMOS管MN4～MN6处于截止状态，此时每个第二反相器1010输出节点的负载电容为第二电容C1～C3，即输出节点PH1的负载电容为 第二电容C1，输出节点PH2的负载电容为第二电容C2，输出节点PH3的负载电容为第二电容C3；当加速响应控制模块105输出的逻辑信号fast_en为低电平时，第一NMOS管MN4～MN6的栅电压为高电平，使得第一NMOS管MN4～MN6处于导通状态，此时每个第二反相器1010输出节点的负载电容为第二电容C1～C3和第一电容C11～C31，即输出节点PH1的负载等效电容为第二电容C1和第一电容C11并联，输出节点PH2的负载等效电容为第二电容C2和第一电容C21并联，输出节点PH3的负载等效电容为第二电容C3和第一电容C31并联。
由上述可知，加速响应控制模块105输出的逻辑信号为高电平时，其相对于加速响应控制模块105输出的逻辑信号为低电平，每个第二反相器1010输出节点的负载电容减小，使得环形振荡器输出的时钟信号的振荡频率增大，实现在多个子电荷泵模块的输出电压未达到目标值时，相位时钟产生模块101产生加速时钟信号，控制各个子电荷泵模块快速生成输出电压；相反，加速响应控制模块105输出的逻辑信号为低电平时，其相对于加速响应控制模块105输出的逻辑信号为高电平，每个第二反相器1010输出节点的负载电容增大，使得环形振荡器输出的时钟信号的振荡频率减小，实现在多个子电荷泵模块的输出电压达到目标值时，相位时钟产生模块101控制各个子电荷泵模块维持正常的输出电压。
因此，根据加速响应控制模块105输出的逻辑信号的状态，通过改变每个第二反相器1010输出节点的负载电容的大小，实现调节环形振荡器产生的多个相位差固定的时钟信号的振荡频率的大小，基于相位时钟产生模块101输出的相位差为120度的时钟信号，不仅实现控制各个子电荷泵模块产生输出电压，还减小了在同一时刻输入电源对各个子电荷泵模块中充电电容的个数，因此在同一时刻各个子电荷泵模块从输入电源上分时抽取电流，减小了各个子电荷泵模块从输入电源汲取的峰值电流，从而降低输入电源上因为峰值电流过大而导致的输入电源纹波。
另外，根据加速响应控制模块105输出的逻辑信号的状态，还可以通过改变每个第二反相器1010中开关管(即第一PMOS管和第二NMOS管)的导电沟道的宽与长的比(简称为宽长比)，以改变第二反相器 1010的等效电阻，实现调节环形振荡器产生的多个相位差固定的时钟信号的振荡频率的大小，在此不再详述。
当每个子电荷泵模块提供高于输入电源Vin的电压输出时，如图4所示，每个子电荷泵模块包括第三NMOS管MN7、第四NMOS管MN8、第二PMOS管MP4、第三PMOS管MP5、第四PMOS管MP6、第五PMOS管MP7、第一选择开关SW1、第二选择开关SW2、第三选择开关SW3、第四选择开关SW4和第三电容C4、第四电容C5、第五电容C6、第六电容C7和第八电容C8。每个子电荷泵模块中的各部分连接关系如下：第三NMOS管MN7的衬底端与源极、第四NMOS管MN8的衬底端与源极分别连接输入电源Vin，第三NMOS管MN7的栅极分别连接第四NMOS管MN8的漏极、第四电容C5的一个极板A以及第二PMOS管MP4的漏极，第三NMOS管MN7的漏极分别连接第四NMOS管MN8的栅极、第三电容C4的一个极板B以及第三PMOS管MP5的漏极，第二PMOS管MP4的衬底端与源极、第三PMOS管MP5的衬底端与源极、第四PMOS管MP6的衬底端与源极和第五PMOS管MP7的衬底端与源极分别连接输出电压端VOUT和第八电容C8的一端，第八电容C8的另一端接地，第二PMOS管MP4的栅极分别连接第六电容C7的一个极板D、第四PMOS管MP6的漏极和第五PMOS管MP7的栅极，第三PMOS管MP5的栅极分别连接第五电容C6的一个极板C、第五PMOS管MP7的漏极和第四PMOS管MP6的栅极，第三电容C4的另一个极板连接第一选择开关SW1的动端，第四电容C5的另一个极板连接第二选择开关SW2的动端，第五电容C6的另一个极板连接第三选择开关SW3的动端，第六电容C7的另一个极板连接第四选择开关SW4的动端，第一选择开关SW1、第二选择开关SW2、第三选择开关SW3和第四选择开关SW4的动端分别对应连接各自的时钟控制端，第一选择开关SW1、第二选择开关SW2、第三选择开关SW3和第四选择开关SW4的时钟控制端对应连接相位时钟产生模块101的同一个输出节点，第一选择开关SW1、第二选择开关SW2、第三选择开关SW3和第四选择开关SW4的一个静端连接电源VDD，另一个静端连接接地端GND。第一选择开关SW1、第二选择开关SW2、第三选择开关SW3和第四选择开关SW4的响应控制端连接加速响应控制模块105的输出端，加速响应控制模块105输入端连接输出电压端VOUT。
当相位时钟产生模块101向每个子电荷泵模块提供相位差为120度的时钟信号时，在每个子电荷泵模块中，第一选择开关SW1、第二选择开关SW2、第三选择开关SW3和第四选择开关SW4从相位时钟产生模块101中的同一个输出节点分时接收时钟信号，即第一选择开关SW1通过时钟控制端接收第一时钟信号Φ1，第二选择开关SW2通过时钟控制端接收第二时钟信号Φ2，第三选择开关SW3通过时钟控制端接收第三时钟信号Φ3，第四选择开关SW4通过时钟控制端接收第四时钟信号Φ4。因此，选择开关SW1～SW4受相位时钟产生模块101中的同一个输出节点输出的时钟信号Φ1～Φ4控制，分时对电容C4～C7进行充放电，通过作为开关的第三NMOS管MN7、第四NMOS管MN8、第二PMOS管MP4、第三PMOS管MP5、第四PMOS管MP6和第五PMOS管MP7的导通和关断，将电容C4～C7上的电荷转移传输至第八电容C8上。通过时钟信号Φ1～Φ4分别控制选择开关SW1～SW4，分时对电容C4～C7进行充放电以减小同一时刻输入电源对各个子电荷泵模块中充电电容的个数，从而降低输入电源上因为峰值电流过大导致的输入电源纹波，减少了输入电源对片外电容的依赖。
如图5所示，通过相位时钟产生模块101中的同一个输出节点输出的时钟信号Φ1～Φ4控制选择开关SW1～SW4的导通和关断时，时钟信号Φ1～Φ4需要满足第一时钟信号Φ1和第三时钟信号Φ3、第二时钟信号Φ2和第四时钟信号Φ4为非交叠时钟信号，其非交叠时间为Tnov1；第一时钟信号Φ1和第二时钟信号Φ2、第三时钟信号Φ3和第四时钟信号Φ4也互为非交叠时钟信号，其非交叠时间分别为Tnov3和Tnov2，时钟信号Φ1～Φ4非交叠时间需要满足关系为Tnov2＝2*Tnov1+Tnov3。
基于以上非交叠时钟信号的控制，电容C4～C7都是分时进行充电的，因此减小了输入电源Vin在同一时刻的充电电容，进而减小了输入电源对电容C4～C7的充电电流和由此引起的输入电源纹波。具体地说，在初始状态时，由于所有时钟信号Φ1～Φ4为低电平，通过时钟控制端控制选择开关SW1～SW4的动端与接地端GND连接，使得第四电容C5和第三电容C4的极板A和B被第三NMOS管MN7、第四NMOS管MN8的体二极管充电至Vin电位，同理输出电压端VOUT和第五电容C6 和第六电容C7的极板C和D初始电位均为输入电源Vin；假设C4＝C5＝C6＝C7＝C；因此，电容C4～C7初始存储电荷均为CVin。
当时钟信号Φ2和Φ3为低电平时，第四电容C5和第五电容C6分别与第二选择开关SW2、第三选择开关SW3相连的极板接到电源VDD进行充电，第四电容C5和第五电容C6处于充电状态，而且第四电容C5和第五电容C6的极板A和C电压为输入电源Vin+电源VDD。与此同时，时钟信号Φ1和Φ4为高电平时，第一选择开关SW1和第四选择开关SW4将第三电容C4和第六电容C7的与其相连的极板短路到接地端GND，第三电容C4和第六电容C7处于保持状态，而且第三电容C4和第六电容C7的极板B和D电压为输入电源Vin。此时，第三NMOS管MN7导通，第四NMOS管MN8截止，第二PMOS管MP4和第五PMOS管MP7导通，第三PMOS管MP5和第四PMOS管MP6截止，因此第五电容C6和第四电容C5中的电荷转移至第八电容C8中，给第八电容C8进行充电，第三电容C4和第六电容C7处于保持状态。
当时钟信号Φ2，Φ3由低电平跳变为高电平后，第四电容C5和第五电容C6与第二选择开关SW2、第三选择开关SW3相连的极板被短路到地，因为电容电压不能突变，第四电容C5和第五电容C6的电压差仍然为输入电源Vin，因此第四电容C5和第五电容C6的极板A和C的电压为输入电源Vin。此时，时钟信号Φ1和Φ4由高电平跳变为低电平，第三电容C4和第六电容C7分别与第一选择开关SW1和第四选择开关SW4相连的极板接至电源VDD，使得第三电容C4和第六电容C7的极板B和D的电压分别为输入电源Vin+电源VDD；因此第三NMOS管MN7截止，第四NMOS管MN8导通，第二PMOS管MP4和第五PMOS管MP7截止，第四PMOS管MP6和第三PMOS管MP5导通，分别将第三电容C4和第六电容C7中的电荷转移至第八电容C8中，给第八电容C8充电，第四电容C5和第五电容C6处于保持状态。
因此，基于非交叠时钟控制的选择开关SW1～SW4，使得第三电容C4和第六电容C7，以及第四电容C5和第五电容C6不会同时从电源VDD上汲取电流，使得该电源VDD的峰值电流会显著变小，但是在电荷传输过程中，是由第三电容C4和第六电容C7或者第四电容C5和第五电容C6共同向第八电容C8提供传输电荷，在时钟翻转的时刻，每 次只有一个电容状态进行切换，使得每个子电荷泵模块的输出电压VOUT的纹波也会显著减小；通过若干个时钟周期，最终达到VOUT＝Vin+VDD，从而使得每个子电荷泵模块达到稳态输出，并实现输出高于输入电源的电压。例如，假设第四电容C5和第五电容C6处于向第八电容C8提供传输电荷的状态，第三电容C4和第六电容C7处于充电状态时，在时钟翻转的时刻，可以是第四电容C5先从传输状态切换到充电状态，然后第五电容C6从传输状态切换到充电状态，再是第三电容C4从充电状态切换到传输状态，最后是从充电状态切换到传输状态。
每个子电荷泵模块除了可以提供高于输入电源Vin的电压输出，还可以提供低于接地电压VSS的电压输出。如图6所示，当需要提供低于接地电压VSS的电压输出时，只需要将每个子电荷泵模块中的第三NMOS管MN7和第四NMOS管MN8对应替换为第六PMOS管MP8和第七PMOS管MP9,将第二PMOS管MP4、第三PMOS管MP5、第四PMOS管MP6和第五PMOS管MP7对应替换为第五NMOS管MN9、第六NMOS管MN10、第九NMOS管MN13和第十NMOS管MN14。该实现过程为上述每个子电荷泵模块提供高于输入电源Vin的电压输出过程的反过程，在此不再详述。
为了能够快速生成输出电压，选择开关SW1～SW4可以进行优化处理，即选择开关SW1～SW4是一个加速选择开关。如图7所示，每个选择开关包括第十PMOS管MP12、第七NMOS管MN11、或门OR1、与门AND1、第三反相器INV2以及至少一个第十一PMOS管MP13和第八NMOS管MN12。该选择开关各部分连接关系如下：第十PMOS管MP12、第七NMOS管MN11的栅极连接在一起作为选择开关的时钟控制端，用于连接相位时钟产生模块101的某一个输出节点，以接收相位时钟产生模块101输出的时钟信号Φi(时钟信号Φ1～Φ4中任意一个时钟信号)；第十PMOS管MP12、第七NMOS管MN11的栅极还对应连接或门OR1和与门AND1的一个输入端，第十PMOS管MP12与第七NMOS管MN11的漏极、每个第十一PMOS管MP13与对应的第八NMOS管MN12的漏极相互连接在一起后作为选择开关的动端，用于连接相应的电容(电容C4～C7中某一个电容)的另一个极板，第十PMOS管MP12与每个第十一PMOS管MP13的源极分别连接电源VDD，第七NMOS管MN11与每个第八NMOS管 MN12的源极分别接地，每个第十一PMOS管MP13的栅极连接或门OR1的输出端，每个第八NMOS管MN12的栅极连接与门的输出端，或门OR1的另一个输入端连接第三反相器INV2的输出端，与门AND1的另一个输入端连接第三反相器INV2的输入端和加速响应控制模块105的输出端。
当加速响应控制模块105检测到各个子电荷泵模块的输出电压未达到目标值时，加速响应控制模块105向第三反相器INV2输出的逻辑信号fast_en为高电平，当时钟信号Φi为高电平时，与门AND1输出为高电平，使得第七NMOS管MN11和至少一个第八NMOS管MN12并联，则各个子电荷泵模块对应的下拉电阻减小，即增大各个子电荷泵模块的输出电压端连接的第八电容R8的放电电流，减小放电路径上的导通电阻。同理，当时钟信号Φi为低电平时，或门OR11输出为低电平，使得输出电压VOUT的上拉电阻为第十PMOS管MP12和至少一个第十一PMOS管MP13并联阻抗，减小了各个子电荷泵模块对应的上拉电阻，即增大各个子电荷泵模块的输出电压端连接的第八电容R8的充电电流，减小充电路径上的导通电阻。
当时钟信号Φi的频率变高时，通过减小第三反相器INV2导通阻抗的方式提高各个子电荷泵模块对C4～C7在高频时钟信号控制下的充电速度，从而减小各个子电荷泵模块的输出电压的建立时间。同时，当各个子电荷泵模块的输出电压达到稳态值后，逻辑信号为0，时钟信号Φi为低电平和高电平时，第三反相器INV2的导通阻抗分别由第十PMOS管MP12、第七NMOS管MN11的导通电阻决定，此时时钟信号Φi的频率降低，选择开关的上下拉电阻增大，只要满足不影响各个子电荷泵模块充电性能即可。因此，在各个子电荷泵模块的输出电压达到稳态之后，由于选择开关上下拉电阻增加，使得电容C4～C7从电源汲取电流的速度变慢，可以进一步减小输入电源在电荷泵电路工作时的峰值电流。
如图8所示，加速响应控制模块105包括第一电阻R1、第二电阻R0和迟滞比较器Comp；第一电阻R1的一端连接各个子电荷泵模块的输出电压端VOUT，第一电阻R1的另一端分别连接第二电阻R0的一端、迟滞比较器Comp的反相输入端，第二电阻R0的另一端接地，迟滞比 较器Comp的正相输入端连接参考电压VREF，迟滞比较器Comp的输出端连接相位时钟产生模块101的第一反相器INV1的输入端、各个子电荷泵模块的第三反相器INV2的输入端。
通过加速响应检测模块105实现对各个子电荷泵模块的输出电压进行检测，当各个子电荷泵模块的输出电压未达到目标值时，迟滞比较器Comp输出逻辑信号fast_en为高电平，并输出至相位时钟产生模块101和各个子电荷泵模块中。在相位时钟产生模块中，改变环形振荡器的振荡频率，在各个子电荷泵模块中，调节电容充放电的速度，从而使各个子电荷泵模块快速生成输出电压。当各个子电荷泵模块的输出电压达到目标值时，迟滞比较器Comp输出逻辑信号fast_en为低电平，使电荷泵电路处于低峰值电流，低功耗状态运行。其中，为了便于判断各个子电荷泵模块的输出电压是否达到目标值，可以在迟滞比较器Comp中设置阈值翻转电压，该阈值翻转电压为VREF(1+R1/R0)，调整第一电阻R1、第二电阻R0的比例，可以设置阈值翻转电压，若各个子电荷泵模块的输出电压达到阈值翻转电压，则认为各个子电荷泵模块的输出电压达到目标值。
需要说明的是，本发明实施例提供的电荷泵电路可以被用在模拟集成电路芯片中。对于该模拟集成电路芯片中电荷泵电路的具体结构，在此不再一一详述。
上述电荷泵电路还可以被用在各类通信终端中，作为模拟集成电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TDD_LTE、FDD_LTE、5G NR等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他模拟集成电路应用的场合，例如通信基站等。
与现有技术相比较，本发明所提供的电荷泵电路通过相位时钟产生模块产生多个相位差固定的时钟信号，以对应控制多个子电荷泵模块产生输出电压，通过加速响应控制模块对各个子电荷泵模块的输出电压进行检测，并分别向相位时钟产生模块以及各个子电荷泵模块输出逻辑信号，以改变相位时钟产生模块输出的时钟信号的频率，减少各个子电荷泵模块中电容的充放电时间。利用本发明，可以有效减小 电荷泵电路从输入电源汲取的峰值电流，并减轻电荷泵电路对输入电源以及输出电压信号产生的纹波干扰，从而减少了输入电源对片外电容的依赖。
以上对本发明所提供的电荷泵电路、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质内容的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (12)

  1. 一种电荷泵电路，其特征在于包括相位时钟产生模块、加速响应控制模块以及多个子电荷泵模块，所述相位时钟产生模块的输出端连接每个子电荷泵模块的时钟控制端，所述多个子电荷泵模块并联后对应连接输入电源端和输出电压端，所述输出电压端连接所述加速响应控制模块的输入端，所述加速响应控制模块的输出端连接所述相位时钟产生模块和每个所述子电荷泵模块的输入端；
    所述相位时钟产生模块产生多个相位差固定的时钟信号,对应控制所述多个子电荷泵模块产生输出电压，同时通过所述加速响应控制模块对所述输出电压进行检测后，分别向所述相位时钟产生模块以及各个子电荷泵模块输出逻辑信号，使得在所述输出电压未达到目标值时，所述相位时钟产生模块产生加速时钟信号以快速生成所述输出电压，以及在所述输出电压达到目标值时，所述相位时钟产生模块控制各个子电荷泵模块维持正常的输出电压。
  2. 如权利要求1所述的电荷泵电路，其特征在于：
    所述相位时钟产生模块包括第一反相器和多个由第一NMOS管、第一电容、第二电容、输出节点以及第二反相器组成的相位时钟子电路；其中，所述第一反相器的输入端连接所述加速响应控制模块的输出端，所述第一反相器的输出端连接每个第一NMOS管的栅极，每个第一NMOS管的漏极与相应的输出节点之间对应串接所述第一电容，每个第一NMOS管的源极接地，每个输出节点连接相应的子电荷泵模块，并且每个输出节点到地之间对应串接所述第二电容，每个所述第二反相器级联并对应连接电源和地后首尾相连形成环形振荡器。
  3. 如权利要求2所述的电荷泵电路，其特征在于：
    所述第二反相器包括第一PMOS管和第二NMOS管，所述第一PMOS管和所述第二NMOS管的栅极和漏极对应连接，所述第一PMOS管的源极连接电源，所述第二NMOS管的源极接地。
  4. 如权利要求1～3中任意一项所述的电荷泵电路，其特征在于：
    根据所述加速响应控制模块向所述相位时钟产生模块输出的逻辑信号的状态，改变所述相位时钟产生模块输出节点的负载电容的大小， 以调节所述环形振荡器产生的多个相位差固定的时钟信号的振荡频率的大小。
  5. 如权利要求1～3中任意一项所述的电荷泵电路，其特征在于：
    根据所述加速响应控制模块向所述相位时钟产生模块输出的逻辑信号的状态，改变每个所述第二反相器中的开关管的宽长比，以改变所述第二反相器的等效电阻，实现调节所述环形振荡器产生的多个相位差固定的时钟信号的振荡频率的大小。
  6. 如权利要求1所述的电荷泵电路，其特征在于：
    当每个所述子电荷泵模块提供高于输入电源的电压输出时，每个子电荷泵模块包括第三NMOS管、第四NMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第五PMOS管、第一选择开关、第二选择开关、第三选择开关、第四选择开关和第三电容、第四电容、第五电容、第六电容和第八电容，所述第三NMOS管的衬底端与源极、所述第四NMOS管的衬底端与源极分别连接输入电源，所述第三NMOS管的栅极分别连接所述第四NMOS管的漏极、所述第四电容的一个极板以及所述第二PMOS管的漏极，所述第三NMOS管的漏极分别连接所述第四NMOS管的栅极、所述第三电容的一个极板以及所述第三PMOS管的漏极，所述第二PMOS管的衬底端与源极、所述第三PMOS管的衬底端与源极、所述第四PMOS管的衬底端与源极和所述第五PMOS管的衬底端与源极分别连接输出电压端和所述第八电容的一端，所述第八电容的另一端接地，所述第二PMOS管的栅极分别连接所述第六电容的一个极板、所述第四PMOS管的漏极和所述第五PMOS管的栅极，所述第三PMOS管的栅极分别连接所述第五电容的一个极板、所述第五PMOS管的漏极和所述第四PMOS管的栅极，所述第三电容、所述第四电容、所述第五电容和所述第六电容的另一个极板连接相应的选择开关的动端，所述选择开关的动端分别对应连接各自的时钟控制端，所述选择开关的时钟控制端对应连接所述相位时钟产生模块的同一个输出节点，所述选择开关的一个静端连接电源，另一个静端连接接地端，所述选择开关的响应控制端分别连接所述加速响应控制模块的输出端，所述加速响应控制模块的输入端连接所述输出电压端。
  7. 如权利要求6所述的电荷泵电路，其特征在于：
    每个选择开关包括第十PMOS管、第七NMOS管、或门、与门、第三反相器以及至少一个第十一PMOS管和至少一个第八NMOS管，所述第十PMOS管、所述第七NMOS管的栅极连接以作为选择开关的时钟控制端，用于连接所述相位时钟产生模块的一个输出节点，所述第十PMOS管、所述第七NMOS管的栅极对应连接所述或门和所述与门的一个输入端，所述第十PMOS管与所述第七NMOS管的漏极、每个第十一PMOS管与对应的第八NMOS管的漏极相互连接后作为选择开关的动端，用于连接相应的电容的另一个极板，所述第十PMOS管与每个第十一PMOS管的源极分别连接电源，所述第七NMOS管与每个第八NMOS管的源极分别接地，每个第十一PMOS管的栅极连接所述或门的输出端，每个第八NMOS管的栅极连接所述与门的输出端，所述或门的另一个输入端连接所述第三反相器的输出端，所述与门的另一个输入端连接所述第三反相器的输入端和所述加速响应控制模块的输出端。
  8. 如权利要求1所述的电荷泵电路，其特征在于：
    所述相位时钟产生模块中同一个输出节点输出的时钟信号控制相应的选择开关的导通和关断时，第一时钟信号和第三时钟信号、第二时钟信号和第四时钟信号为非交叠时钟信号，其非交叠时间为Tnov1；第一时钟信号和第二时钟信号、第三时钟信号和第四时钟信号为非交叠时钟信号，其非交叠时间分别为Tnov3和Tnov2，各非交叠时间满足关系为Tnov2＝2*Tnov1+Tnov3。
  9. 如权利要求1所述的电荷泵电路，其特征在于：
    当每个所述子电荷泵模块提供低于接地电压的电压输出时，将每个子电荷泵模块中的所述第三NMOS管和所述第四NMOS管对应替换为第五NMOS管和第六NMOS管，将所述第二PMOS管、所述第三PMOS管、所述第四PMOS管和所述第五PMOS管对应替换为第六PMOS管、第七PMOS管、第八PMOS管和第九PMOS管。
  10. 如权利要求1所述的电荷泵电路，其特征在于：
    所述加速响应控制模块包括第一电阻、第二电阻和迟滞比较器，所述第一电阻的一端分别连接各个子电荷泵模块的输出电压端，所述第一电阻的另一端分别连接所述第二电阻的一端、所述迟滞比较器的反相输入端，所述第二电阻的另一端接地，所述迟滞比较器的正相输 入端连接参考电压，所述迟滞比较器的输出端分别连接所述第一反相器的输入端、各个子电荷泵模块中的第三反相器的输入端。
  11. 一种集成电路芯片，其特征在于包括权利要求1～10中任意一项所述的电荷泵电路。
  12. 一种通信终端，其特征在于包括权利要求1～10中任意一项所述的电荷泵电路。
PCT/CN2021/113336 2020-10-12 2021-08-18 一种电荷泵电路、芯片及通信终端 WO2022078059A1 (zh)

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