WO2022078059A1

WO2022078059A1 - Charge pump circuit, chip, and communication terminal

Info

Publication number: WO2022078059A1
Application number: PCT/CN2021/113336
Authority: WO
Inventors: 高晨阳; 林升
Original assignee: 唯捷创芯(天津)电子技术股份有限公司
Priority date: 2020-10-12
Filing date: 2021-08-18
Publication date: 2022-04-21
Also published as: KR20230084304A; EP4228136A1; US20230291310A1; JP2023546065A; CN112165250B; CN112165250A

Abstract

Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced. The present invention can effectively reduce the peak current drawn by the charge pump circuit from an input power supply, and reduces the ripple interference of the charge pump circuit on the input power supply and an output voltage signal.

Description

A charge pump circuit, chip and communication terminal

technical field

The invention relates to a charge pump circuit, an integrated circuit chip including the charge pump circuit and a corresponding communication terminal, and belongs to the field of analog integrated circuits.

Background technique

Traditional charge pump circuits rely on an external power supply, which can be implemented using a low dropout linear regulator or a DC-DC power supply. As shown in Figure 1, when a low-dropout linear regulator is used to supply power to the charge pump circuit and the high-precision circuit at the same time, due to the characteristics of the charge pump circuit itself, when the internal switch is switched, it is often accompanied by a large Transient peak current. If the peak current is too large, it will not only affect the power supply stability of the power supply system, but also affect the accuracy of other high-precision circuits. For example, the effective number of bits of a high-precision digital-to-analog converter, the output offset voltage of a precision operational amplifier, etc. are all affected by it.

With the continuous improvement of the integration degree of integrated circuits, the charge pump circuit is more and more integrated inside the chip, but because the charge pump circuit has high requirements on the power supply, in order to reduce the ripple interference of the charge pump circuit on the power supply, it is generally necessary to Add large off-chip capacitors to its power port. This means not only increasing the cost of the power supply system, but also reducing the reliability of the entire system.

A charge pump circuit is disclosed in the Chinese invention patent with the patent number of ZL 201810049855.1. The working principle of the circuit is to divide the charge pump into N-stage sub-charge pump circuits, and then use the delay to delay the clock signal one by one to provide the corresponding clock signal for the N-stage sub-charge pump, and then detect the charge through the control unit. The output voltage ripple of the pump is adjusted, and the delay is adjusted to reduce the output voltage ripple of the charge pump. However, in order to reduce the voltage ripple output by the charge pump circuit, the number of sub-charge pump circuits will be increased, which will not only increase the circuit complexity, but also increase the peak current of the input power supply.

SUMMARY OF THE INVENTION

The primary technical problem to be solved by the present invention is to provide a charge pump circuit.

Another technical problem to be solved by the present invention is to provide an integrated circuit chip and a communication terminal including the above-mentioned charge pump circuit.

In order to achieve the above object, the present invention adopts the following technical scheme:

According to a first aspect of the embodiments of the present invention, a charge pump circuit is provided, including a phase clock generation module, an acceleration response control module, and a plurality of sub-charge pump modules, wherein an output end of the phase clock generation module is connected to an output terminal of each sub-charge pump module. The clock control terminal, the plurality of sub-charge pump modules are connected in parallel to the input power supply terminal and the output voltage terminal, the output voltage terminal is connected to the input terminal of the acceleration response control module, and the output terminal of the acceleration response control module is connected to the an input end of the phase clock generation module and each of the sub-charge pump modules;

The phase clock generation module generates a plurality of clock signals with a fixed phase difference, correspondingly controls the plurality of sub-charge pump modules to generate output voltages, and at the same time detects the output voltages by the acceleration response control module, and sends them to the The phase clock generation module and each sub-charge pump module output logic signals, so that when the output voltage does not reach the target value, the phase clock generation module generates an accelerated clock signal to rapidly generate the output voltage, and when the output voltage does not reach the target value When the target value is reached, the phase clock generating module controls each sub-charge pump module to maintain a normal output voltage.

Preferably, the phase clock generation module includes a first inverter and a plurality of phase clock sub-circuits composed of a first NMOS transistor, a first capacitor, a second capacitor, an output node and a second inverter; wherein , the input end of the first inverter is connected to the output end of the acceleration response control module, the output end of the first inverter is connected to the gate of each first NMOS transistor, the The first capacitor is connected in series between the drain and the corresponding output node, the source of each first NMOS transistor is grounded, each output node is connected to the corresponding sub-charge pump module, and each output node is connected to the ground Correspondingly, the second capacitors are connected in series, and each of the second inverters is cascaded and connected to the power supply and the ground, and then connected end to end to form a ring oscillator.

Preferably, the second inverter includes a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor are correspondingly connected, and the first PMOS transistor The source of the transistor is connected to the power supply, and the source of the second NMOS transistor is grounded.

Preferably, according to the state of the logic signal output by the acceleration response control module to the phase clock generation module, the size of the load capacitance of the output node of the phase clock generation module is changed to adjust the output voltage generated by the ring oscillator. The magnitude of the oscillation frequency of a plurality of clock signals with a fixed phase difference.

Preferably, according to the state of the logic signal output by the acceleration response control module to the phase clock generation module, the width to length ratio of the switch tube in each of the second inverters is changed, so as to change the first The equivalent resistance of the two inverters can adjust the oscillation frequency of a plurality of clock signals with a fixed phase difference generated by the ring oscillator.

Preferably, when each of the sub-charge pump modules provides a higher voltage output than the input power supply, each sub-charge pump module includes a third NMOS transistor, a fourth NMOS transistor, a second PMOS transistor, a third PMOS transistor, The fourth PMOS tube, the fifth PMOS tube, the first selection switch, the second selection switch, the third selection switch, the fourth selection switch and the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor and the eighth capacitor, The substrate end and source of the third NMOS transistor and the substrate end and source of the fourth NMOS transistor are respectively connected to the input power supply, and the gate of the third NMOS transistor is respectively connected to the gate of the fourth NMOS transistor. The drain, a plate of the fourth capacitor and the drain of the second PMOS transistor, the drain of the third NMOS transistor is respectively connected to the gate of the fourth NMOS transistor, the drain of the third capacitor A plate and the drain of the third PMOS transistor, the substrate end and source of the second PMOS transistor, the substrate end and source of the third PMOS transistor, and the liner of the fourth PMOS transistor The bottom end and the source electrode and the substrate end and the source electrode of the fifth PMOS transistor are respectively connected to the output voltage end and one end of the eighth capacitor, the other end of the eighth capacitor is grounded, and the second PMOS transistor is connected to the ground. The gate is respectively connected to a plate of the sixth capacitor, the drain of the fourth PMOS transistor and the gate of the fifth PMOS transistor, and the gate of the third PMOS transistor is respectively connected to the fifth capacitor one plate of the fifth PMOS transistor, the drain of the fifth PMOS transistor and the gate of the fourth PMOS transistor, the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are the other One pole plate is connected to the moving terminal of the corresponding selection switch, the moving terminals of the selection switch are respectively connected to the respective clock control terminals, and the clock control terminal of the selection switch is correspondingly connected to the same output node of the phase clock generation module, One static end of the selector switch is connected to the power supply, the other static end is connected to the ground end, the response control end of the selector switch is respectively connected to the output end of the acceleration response control module, and the input end of the acceleration response control module is connected to the the output voltage terminal.

Preferably, when the clock signal output from the same output node in the phase clock generation module controls the turn-on and turn-off of the corresponding selection switch, the first clock signal and the third clock signal, the second clock signal and the fourth clock signal The clock signal is a non-overlapping clock signal, and its non-overlapping time is Tnov1; the first clock signal and the second clock signal, the third clock signal and the fourth clock signal are non-overlapping clock signals, and their non-overlapping times are respectively For Tnov3 and Tnov2, each non-overlapping time satisfies the relation Tnov2=2*Tnov1+Tnov3.

Preferably, when each of the sub-charge pump modules provides a voltage output lower than the ground voltage, the third NMOS transistor and the fourth NMOS transistor in each sub-charge pump module are correspondingly replaced with the fifth NMOS transistor. NMOS tube and sixth NMOS tube, replace the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube with the sixth PMOS tube, the seventh PMOS tube, the third PMOS tube Eight PMOS tubes and a ninth PMOS tube.

Preferably, each selection switch includes a tenth PMOS transistor, a seventh NMOS transistor, an OR gate, an AND gate, a third inverter, and at least one eleventh PMOS transistor and at least one eighth NMOS transistor. The gates of the tenth PMOS transistor and the seventh NMOS transistor are connected to serve as the clock control terminal of the selection switch for connecting an output node of the phase clock generation module, the tenth PMOS transistor and the seventh NMOS transistor. The gate of the gate is correspondingly connected to an input end of the OR gate and the AND gate, the drains of the tenth PMOS transistor and the seventh NMOS transistor, each eleventh PMOS transistor and the corresponding eighth NMOS transistor After the drains are connected to each other, they are used as the moving end of the selection switch, which is used to connect the other plate of the corresponding capacitor. The tenth PMOS tube and the source of each eleventh PMOS tube are respectively connected to the power supply. The seventh The NMOS transistor and the source of each eighth NMOS transistor are respectively grounded, the gate of each eleventh PMOS transistor is connected to the output end of the OR gate, and the gate of each eighth NMOS transistor is connected to the output of the AND gate terminal, the other input terminal of the OR gate is connected to the output terminal of the third inverter, and the other input terminal of the AND gate is connected to the input terminal of the third inverter and the acceleration response control module 's output.

Preferably, the acceleration response control module includes a first resistor, a second resistor and a hysteresis comparator, one end of the first resistor is respectively connected to the output voltage terminals of each sub-charge pump module, and the other end of the first resistor is connected to the output voltage terminals of each sub-charge pump module respectively. One end is respectively connected to one end of the second resistor, the inverting input end of the hysteresis comparator, the other end of the second resistor is grounded, the non-inverting input end of the hysteresis comparator is connected to the reference voltage, and the hysteresis comparator The output end of the inverter is respectively connected to the input end of the first inverter and the input end of the third inverter in each sub-charge pump module.

According to a second aspect of the embodiments of the present invention, an integrated circuit chip is provided, including the above-mentioned charge pump circuit.

According to a third aspect of the embodiments of the present invention, a communication terminal is provided, including the above-mentioned charge pump circuit.

The charge pump circuit provided by the present invention generates a plurality of clock signals with a fixed phase difference through a phase clock generation module, so as to correspondingly control a plurality of sub-charge pump modules to generate an output voltage, and respond to the output voltage of each sub-charge pump module by an accelerated response control module. Perform detection and output logic signals to the phase clock generation module and each sub-charge pump module respectively to change the frequency of the clock signal output by the phase clock generation module and reduce the charging and discharging time of the capacitors in each sub-charge pump module. The invention can effectively reduce the peak current drawn by the charge pump circuit from the input power supply, and reduce the ripple interference generated by the charge pump circuit on the input power supply and the output voltage signal, thereby reducing the dependence of the input power supply on off-chip capacitors.

Description of drawings

Fig. 1 is the typical application block diagram of the existing charge pump circuit;

2 is a structural block diagram of a charge pump circuit provided by an embodiment of the present invention;

3 is a circuit schematic diagram of a phase clock generation module in the charge pump circuit provided by an embodiment of the present invention;

4 is a circuit schematic diagram of each sub-charge pump module in the charge pump circuit provided by the embodiment of the present invention;

FIG. 5 is a schematic time sequence diagram of a charge pump circuit provided by an embodiment of the present invention;

6 is another schematic circuit diagram of each sub-charge pump module in the charge pump circuit provided by the embodiment of the present invention;

7 is a schematic circuit diagram of a selection switch of each sub-charge pump module in a charge pump circuit provided by an embodiment of the present invention;

FIG. 8 is a circuit schematic diagram of an accelerated response control module in a charge pump circuit provided by an embodiment of the present invention.

Detailed ways

The technical content of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

In order to reduce the large ripple interference and noise caused by the charge pump circuit to the input power supply, and reduce the input power supply's dependence on off-chip capacitors, reduce the cost of the power supply system and improve the reliability of the system, so as to stably and quickly generate a charge pump The output voltage. As shown in FIG. 2, an embodiment of the present invention first provides a charge pump circuit, including a phase clock generation module 101, an acceleration response control module 105, and a plurality of sub-charge pump modules (for example, the plurality of

sub-charge pump modules

102, 103, 104); the output end of the phase clock generation module 101 is connected to the clock control end of each sub-charge pump module, and the multiple sub-charge pump modules are connected in parallel to the input power supply end VIN and the output voltage end VOUT correspondingly, and the output voltage end VOUT is connected to the acceleration response The input end of the control module 105 and the output end of the acceleration response control module 105 are connected to the phase clock generation module 101 and the input end of each sub-charge pump module.

The phase clock generation module 101 is used to generate a plurality of clock signals with a fixed phase difference, so as to correspondingly control a plurality of sub-charge pump modules to generate output voltages. The clock generation module 101 and each sub-charge pump module output logic signals, so that when the output voltages of the plurality of sub-charge pump modules do not reach the target value, the phase clock generation module 101 generates an accelerated clock signal to control each sub-charge pump module to quickly generate an output voltage , and when the output voltages of the plurality of sub-charge pump modules reach the target value, the phase clock generating module 101 controls each sub-charge pump module to maintain a normal output voltage.

It should be emphasized that in different embodiments of the present invention, the above-mentioned phase difference may be 45 degrees, 60 degrees, 90 degrees, 120 degrees, or 180 degrees, etc., and the corresponding number of sub-charge pump modules is 8, 6 1, 4, 3 or 2 etc. The number of sub-charge pump modules can be flexibly adjusted on the premise that the rising edge and the falling edge of the clock signal with a fixed phase difference received by each sub-charge-pump module at the same time do not overlap. For example, for the three-way

sub-charge pump modules

102 , 103 and 104 shown in FIG. 1 , the corresponding phase difference is 360 degrees/3=120 degrees, and so on.

As shown in FIG. 3 , the phase clock generation module 101 includes a first inverter INV1, a plurality of first NMOS transistors (eg, first NMOS transistors MN4-MN6), a first capacitor (eg, capacitors C11-C31), a second A phase clock sub-circuit composed of capacitors (such as capacitors C1-C3), an output node and the second inverter 1010. The input end of the first inverter INV1 is connected to the output end of the acceleration response control module 105 , the output end of the first inverter INV1 is respectively connected to the gate of each first NMOS transistor, and the drain of each first NMOS transistor The first capacitors are connected in series between the corresponding output nodes (output nodes PH1, PH2 and PH3), the source of each first NMOS transistor is grounded, each output node is connected to the corresponding sub-charge pump module, and each A second capacitor is correspondingly connected in series between the output node and the ground, and each second inverter 1010 is cascaded and connected to the power supply VDD and ground correspondingly, and then connected end to end to form a ring oscillator. Wherein, on the premise that the rising edge and falling edge of the clock signal with a fixed phase difference generated by each second inverter 1010 do not overlap, the number of the second inverters 1010 can be flexibly adjusted (the same as adjusting the sub-charge pump module). are similar in number and will not be repeated here).

As shown in FIG. 3 , it is taken as an example that the phase clock generating module 101 generates three clock signals with a phase difference of 120 degrees. The phase clock generation module 101 includes a first inverter INV1, three first NMOS transistors MN4-MN6, three first capacitors C11-C31, three second capacitors C1-C3, three output nodes PH1, PH2 and PH3 and three second inverters 1010. The input end of the first inverter INV1 is connected to the output end of the acceleration response control module 105, the output end of the first inverter INV1 is respectively connected to the gates of the three first NMOS transistors MN4-MN6, and the first NMOS transistor MN4 A first capacitor C11 is connected in series with the output node PH1, a first capacitor C21 is connected in series between the first NMOS transistor MN5 and the output node PH2, and a first capacitor C31, 3 is connected in series between the first NMOS transistor MN6 and the output node PH3 The sources of the first NMOS transistors MN4-MN6 are grounded, the three output nodes PH1, PH2 and PH3 are connected to the corresponding sub-charge pump modules, the second capacitor C1 is connected in series between the output node PH1 and the ground, and the output node PH2 is connected to the ground. The second capacitor C2 is connected in series between the output node PH3 and the ground, and the second capacitor C3 is connected in series between the output node PH3 and the ground.

Each second inverter includes a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor are connected correspondingly, the source of the first PMOS transistor is connected to the power supply, and the second NMOS transistor The source is grounded. As shown in FIG. 3 , taking the phase clock generation module 101 including three second inverters as an example, the first PMOS transistor MP1 and the second NMOS transistor MN1, the first PMOS transistor MP2 and the second NMOS transistor MN2, the first PMOS transistor MP1 and the second NMOS transistor MN2, the first PMOS transistor MP1 and the second NMOS transistor MN1 The tube MP3 and the second NMOS tube MN3 respectively form a one-stage second inverter, thereby obtaining a three-stage second inverter; wherein, the second inverters after the cascade are connected end to end, that is, the third stage second inverter The drains of the first PMOS transistor MP3 and the second NMOS transistor MN3 of the inverter are connected together and then connected to the gates of the first PMOS transistor MP1 and the second NMOS transistor MN1 of the first stage second inverter.

The output nodes PH1 ˜ PH3 of the phase clock generating module 101 are the output nodes of the corresponding second inverters 1010 , and the first capacitors C11 ˜ C31 and the second capacitors C1 ˜ C3 are the output nodes of each second inverter 1010 , respectively. The load capacitance of the output node, the gate voltage of the first NMOS transistors MN4 ˜ MN6 is the output of the first inverter INV1 , and the first inverter INV receives the logic signal output by the acceleration response control module 105 . Because the oscillation frequency f of the ring oscillator composed of the second inverter 1010 has the following relationship:

Wherein, R _on represents the equivalent resistance of the second inverter 1010 , and _CL represents the load capacitance of the output node of the second inverter 1010 . When the logic signal fast_en output from the acceleration response control module 105 is at a high level, the gate voltages of the first NMOS transistors MN4 to MN6 are at a low level, so that the first NMOS transistors MN4 to MN6 are in an off state. The load capacitances of the output node of the phase converter 1010 are the second capacitors C1-C3, that is, the load capacitance of the output node PH1 is the second capacitor C1, the load capacitance of the output node PH2 is the second capacitor C2, and the load capacitance of the output node PH3 is the second capacitor C2. Capacitor C3; when the logic signal fast_en output by the acceleration response control module 105 is at a low level, the gate voltages of the first NMOS transistors MN4 to MN6 are at a high level, so that the first NMOS transistors MN4 to MN6 are in a conducting state. The load capacitances of the output nodes of the second inverters 1010 are the second capacitors C1-C3 and the first capacitors C11-C31, that is, the load equivalent capacitance of the output node PH1 is the second capacitor C1 and the first capacitor C11 in parallel, and the output node The load equivalent capacitance of PH2 is the parallel connection of the second capacitor C2 and the first capacitor C21, and the load equivalent capacitance of the output node PH3 is the parallel connection of the second capacitor C3 and the first capacitor C31.

It can be seen from the above that when the logic signal output by the acceleration response control module 105 is at a high level, the load capacitance of the output node of each second inverter 1010 is reduced relative to the logic signal output by the acceleration response control module 105 is at a low level. , so that the oscillation frequency of the clock signal output by the ring oscillator increases, so that when the output voltages of the multiple sub-charge pump modules do not reach the target value, the phase clock generation module 101 generates an accelerated clock signal, and controls each sub-charge pump module to quickly generate an output On the contrary, when the logic signal output by the acceleration response control module 105 is at a low level, the load capacitance of the output node of each second inverter 1010 increases relative to the logic signal output by the acceleration response control module 105 at a high level. , the oscillation frequency of the clock signal output by the ring oscillator is reduced, so that when the output voltages of the sub-charge pump modules reach the target value, the phase clock generation module 101 controls each sub-charge pump module to maintain a normal output voltage.

Therefore, according to the state of the logic signal output by the acceleration response control module 105, by changing the size of the load capacitance of the output node of each second inverter 1010, the oscillation of the plurality of clock signals with fixed phase differences generated by the ring oscillator can be adjusted. The size of the frequency, based on the clock signal output by the phase clock generation module 101 with a phase difference of 120 degrees, not only realizes the control of each sub-charge pump module to generate an output voltage, but also reduces the input power supply at the same time. The number of capacitors, so each sub-charge pump module draws current from the input power supply in a time-sharing manner at the same time, reducing the peak current drawn by each sub-charge pump module from the input power supply, thereby reducing the input power supply due to excessive peak current. resulting input power supply ripple.

In addition, according to the state of the logic signal output by the acceleration response control module 105, the width and length of the conduction channel of the switch transistors (ie, the first PMOS transistor and the second NMOS transistor) in each second inverter 1010 can also be changed by changing ratio (referred to as the width-length ratio for short) to change the equivalent resistance of the second inverter 1010 to adjust the oscillation frequency of multiple clock signals with a fixed phase difference generated by the ring oscillator, which will not be described in detail here. .

When each sub-charge pump module provides a voltage output higher than the input power supply Vin, as shown in FIG. 4 , each sub-charge pump module includes a third NMOS transistor MN7, a fourth NMOS transistor MN8, a second PMOS transistor MP4, and a third PMOS transistor tube MP5, fourth PMOS tube MP6, fifth PMOS tube MP7, first selection switch SW1, second selection switch SW2, third selection switch SW3, fourth selection switch SW4 and third capacitor C4, fourth capacitor C5, The fifth capacitor C6, the sixth capacitor C7 and the eighth capacitor C8. The connection relationship of each part in each sub-charge pump module is as follows: the substrate end and source of the third NMOS transistor MN7, the substrate end and source of the fourth NMOS transistor MN8 are respectively connected to the input power supply Vin, and the third NMOS transistor MN7 is connected to the input power supply Vin. The gate is respectively connected to the drain of the fourth NMOS transistor MN8, one plate A of the fourth capacitor C5 and the drain of the second PMOS transistor MP4, and the drain of the third NMOS transistor MN7 is respectively connected to the gate of the fourth NMOS transistor MN8 , a plate B of the third capacitor C4 and the drain of the third PMOS tube MP5, the substrate end and source of the second PMOS tube MP4, the substrate end and source of the third PMOS tube MP5, and the fourth PMOS tube The substrate terminal and source of MP6 and the substrate terminal and source of the fifth PMOS transistor MP7 are respectively connected to the output voltage terminal VOUT and one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is grounded, and the second PMOS transistor MP4 The gate is respectively connected to a plate D of the sixth capacitor C7, the drain of the fourth PMOS transistor MP6 and the gate of the fifth PMOS transistor MP7, and the gate of the third PMOS transistor MP5 is respectively connected to a plate of the fifth capacitor C6 C. The drain of the fifth PMOS transistor MP7 and the gate of the fourth PMOS transistor MP6, the other plate of the third capacitor C4 is connected to the moving end of the first selection switch SW1, and the other plate of the fourth capacitor C5 is connected to the first selection switch SW1. The moving terminal of the second selection switch SW2, the other pole plate of the fifth capacitor C6 is connected to the moving terminal of the third selection switch SW3, the other pole plate of the sixth capacitor C7 is connected to the moving terminal of the fourth selection switch SW4, and the first selection switch The moving terminals of SW1, the second selection switch SW2, the third selection switch SW3 and the fourth selection switch SW4 are respectively connected to their respective clock control terminals. The first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the third selection switch The clock control terminals of the four selection switches SW4 are correspondingly connected to the same output node of the phase clock generating module 101, and one static terminal of the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the fourth selection switch SW4 is connected to the power supply VDD, and the other static terminal is connected to the ground terminal GND. The response control terminals of the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the fourth selection switch SW4 are connected to the output terminal of the acceleration response control module 105, and the input terminal of the acceleration response control module 105 is connected to the output voltage terminal VOUT.

When the phase clock generating module 101 provides a clock signal with a phase difference of 120 degrees to each sub-charge pump module, in each sub-charge pump module, the first selection switch SW1, the second selection switch SW2, the third selection switch SW3 and the The four selection switches SW4 receive clock signals from the same output node in the phase clock generation module 101 in time division, that is, the first selection switch SW1 receives the first clock signal Φ1 through the clock control terminal, and the second selection switch SW2 receives the first clock signal Φ1 through the clock control terminal. Two clock signals Φ2, the third selection switch SW3 receives the third clock signal Φ3 through the clock control terminal, and the fourth selection switch SW4 receives the fourth clock signal Φ4 through the clock control terminal. Therefore, the selection switches SW1-SW4 are controlled by the clock signals Φ1-Φ4 output from the same output node in the phase clock generating module 101, and the capacitors C4-C7 are charged and discharged in time-sharing, and the third NMOS transistors MN7, The four NMOS transistors MN8, the second PMOS transistor MP4, the third PMOS transistor MP5, the fourth PMOS transistor MP6 and the fifth PMOS transistor MP7 are turned on and off to transfer the charges on the capacitors C4 to C7 to the eighth capacitor C8 superior. The selection switches SW1-SW4 are controlled by the clock signals Φ1-Φ4 respectively, and the capacitors C4-C7 are charged and discharged in time-sharing to reduce the number of charging capacitors in each sub-charge pump module by the input power supply at the same time, thereby reducing the input power supply due to The input power supply ripple caused by excessive peak current reduces the input power supply's dependence on off-chip capacitors.

As shown in FIG. 5 , when the turn-on and turn-off of the selection switches SW1-SW4 are controlled by the clock signals Φ1-Φ4 output by the same output node in the phase clock generating module 101, the clock signals Φ1-Φ4 need to satisfy the first clock signal Φ1, the third clock signal Φ3, the second clock signal Φ2 and the fourth clock signal Φ4 are non-overlapping clock signals, and their non-overlapping time is Tnov1; the first clock signal Φ1 and the second clock signal Φ2, the third clock signal Φ3 and the fourth clock signal Φ4 are also mutually non-overlapping clock signals, and their non-overlapping times are Tnov3 and Tnov2 respectively, and the non-overlapping times of the clock signals Φ1-Φ4 need to satisfy the relationship Tnov2=2*Tnov1+Tnov3.

Based on the control of the above non-overlapping clock signals, the capacitors C4 to C7 are charged in time-sharing, thus reducing the charging capacitor of the input power Vin at the same time, thereby reducing the charging current of the input power to the capacitors C4 to C7 and the resulting input power supply ripple. Specifically, in the initial state, since all the clock signals Φ1 to Φ4 are at low level, the clock control terminal controls the moving terminals of the selection switches SW1 to SW4 to be connected to the ground terminal GND, so that the fourth capacitor C5 and the third capacitor C4 The plates A and B are charged to the Vin potential by the body diodes of the third NMOS transistor MN7 and the fourth NMOS transistor MN8. Similarly, the initial potential of the output voltage terminal VOUT and the plates C and D of the fifth capacitor C6 and the sixth capacitor C7 They are all input power sources Vin; it is assumed that C4=C5=C6=C7=C; therefore, the initial stored charges of the capacitors C4 to C7 are all CVin.

When the clock signals Φ2 and Φ3 are at low level, the plates of the fourth capacitor C5 and the fifth capacitor C6 respectively connected with the second selection switch SW2 and the third selection switch SW3 are connected to the power supply VDD for charging, and the fourth capacitor C5 and the third selection switch SW3 are respectively charged. The fifth capacitor C6 is in a charged state, and the voltages of the plates A and C of the fourth capacitor C5 and the fifth capacitor C6 are the input power source Vin+the power source VDD. At the same time, when the clock signals Φ1 and Φ4 are at high level, the first selection switch SW1 and the fourth selection switch SW4 short-circuit the plates connected to the third capacitor C4 and the sixth capacitor C7 to the ground terminal GND, and the third capacitor C4 and the sixth capacitor C7 are in a hold state, and the voltages of the plates B and D of the third capacitor C4 and the sixth capacitor C7 are the input power Vin. At this time, the third NMOS transistor MN7 is turned on, the fourth NMOS transistor MN8 is turned off, the second PMOS transistor MP4 and the fifth PMOS transistor MP7 are turned on, the third PMOS transistor MP5 and the fourth PMOS transistor MP6 are turned off, so the fifth capacitor C6 The charges in the fourth capacitor C5 and the fourth capacitor C5 are transferred to the eighth capacitor C8 to charge the eighth capacitor C8, and the third capacitor C4 and the sixth capacitor C7 are in a holding state.

When the clock signals Φ2 and Φ3 jump from low level to high level, the plates connecting the fourth capacitor C5 and the fifth capacitor C6 with the second selection switch SW2 and the third selection switch SW3 are short-circuited to the ground, because the capacitors The voltage cannot be abruptly changed, the voltage difference between the fourth capacitor C5 and the fifth capacitor C6 is still the input power Vin, so the voltages of the plates A and C of the fourth capacitor C5 and the fifth capacitor C6 are the input power Vin. At this time, the clock signals Φ1 and Φ4 jump from high level to low level, and the plates of the third capacitor C4 and the sixth capacitor C7 respectively connected with the first selection switch SW1 and the fourth selection switch SW4 are connected to the power supply VDD, The voltages of the plates B and D of the third capacitor C4 and the sixth capacitor C7 are respectively the input power supply Vin+power supply VDD; therefore, the third NMOS transistor MN7 is turned off, the fourth NMOS transistor MN8 is turned on, and the second PMOS transistor MP4 and the fifth The PMOS transistor MP7 is turned off, the fourth PMOS transistor MP6 and the third PMOS transistor MP5 are turned on, and the charges in the third capacitor C4 and the sixth capacitor C7 are respectively transferred to the eighth capacitor C8, and the eighth capacitor C8 is charged. The capacitor C5 and the fifth capacitor C6 are in a hold state.

Therefore, based on the selection switches SW1-SW4 controlled by non-overlapping clocks, the third capacitor C4 and the sixth capacitor C7, and the fourth capacitor C5 and the fifth capacitor C6 do not draw current from the power supply VDD at the same time, so that the power supply VDD The peak current will be significantly smaller, but in the process of charge transfer, the third capacitor C4 and the sixth capacitor C7 or the fourth capacitor C5 and the fifth capacitor C6 jointly provide the transfer charge to the eighth capacitor C8. At the moment, only one capacitor state is switched at a time, so that the ripple of the output voltage VOUT of each sub-charge pump module will also be significantly reduced; after several clock cycles, VOUT=Vin+VDD is finally reached, thus making each sub-charge pump module The module achieves a steady state output and achieves a voltage higher than the input power supply. For example, assuming that the fourth capacitor C5 and the fifth capacitor C6 are in a state of providing transfer charges to the eighth capacitor C8, and when the third capacitor C4 and the sixth capacitor C7 are in a charging state, at the moment when the clock is flipped, the fourth capacitor C5 can be First switch from the transfer state to the charge state, then the fifth capacitor C6 switches from the transfer state to the charge state, then the third capacitor C4 switches from the charge state to the transfer state, and finally switches from the charge state to the transfer state.

In addition to providing a voltage output higher than the input power Vin, each sub-charge pump module can also provide a voltage output lower than the ground voltage VSS. As shown in FIG. 6 , when a voltage output lower than the ground voltage VSS needs to be provided, it is only necessary to replace the third NMOS transistor MN7 and the fourth NMOS transistor MN8 in each sub-charge pump module with the sixth PMOS transistor MP8 and the fourth NMOS transistor correspondingly. Seven PMOS transistors MP9, the second PMOS transistor MP4, the third PMOS transistor MP5, the fourth PMOS transistor MP6 and the fifth PMOS transistor MP7 are correspondingly replaced by the fifth NMOS transistor MN9, the sixth NMOS transistor MN10, the ninth NMOS transistor MN13 and The tenth NMOS transistor MN14. This realization process is the inverse process of the process of providing a voltage output higher than the input power supply Vin for each of the above-mentioned sub-charge pump modules, and will not be described in detail here.

In order to generate the output voltage quickly, the selection switches SW1 to SW4 can be optimized, that is, the selection switches SW1 to SW4 are acceleration selection switches. As shown in FIG. 7 , each selection switch includes a tenth PMOS transistor MP12, a seventh NMOS transistor MN11, an OR gate OR1, an AND gate AND1, a third inverter INV2, and at least one eleventh PMOS transistor MP13 and an eighth NMOS transistor Tube MN12. The connection relationship of each part of the selection switch is as follows: the gates of the tenth PMOS transistor MP12 and the seventh NMOS transistor MN11 are connected together as the clock control terminal of the selection switch, which is used to connect to a certain output node of the phase clock generation module 101 to receive The clock signal Φi output by the phase clock generation module 101 (any one of the clock signals Φ1 to Φ4); the gates of the tenth PMOS transistor MP12 and the seventh NMOS transistor MN11 are also connected to an input of the OR gate OR1 and the AND gate AND1 correspondingly terminal, the drains of the tenth PMOS transistor MP12 and the seventh NMOS transistor MN11, and the drains of each eleventh PMOS transistor MP13 and the corresponding eighth NMOS transistor MN12 are connected to each other as the moving terminal of the selection switch, used for Connect the other plate of the corresponding capacitor (one of the capacitors C4 to C7), the tenth PMOS transistor MP12 and the source of each eleventh PMOS transistor MP13 are respectively connected to the power supply VDD, and the seventh NMOS transistor MN11 and each The source of the eighth NMOS transistor MN12 is grounded respectively, the gate of each eleventh PMOS transistor MP13 is connected to the output terminal of the OR gate OR1, and the gate of each eighth NMOS transistor MN12 is connected to the output terminal of the AND gate, or the OR gate OR1 The other input terminal of the AND gate AND1 is connected to the output terminal of the third inverter INV2, and the other input terminal of the AND gate AND1 is connected to the input terminal of the third inverter INV2 and the output terminal of the acceleration response control module 105.

When the acceleration response control module 105 detects that the output voltage of each sub-charge pump module does not reach the target value, the logic signal fast_en output by the acceleration response control module 105 to the third inverter INV2 is high level, when the clock signal Φi is high When the level is high, the output of the AND gate AND1 is a high level, so that the seventh NMOS transistor MN11 and at least one eighth NMOS transistor MN12 are connected in parallel, and the pull-down resistance corresponding to each sub-charge pump module is reduced, that is, the resistance of each sub-charge pump module is increased. The discharge current of the eighth capacitor R8 connected to the output voltage terminal reduces the on-resistance on the discharge path. Similarly, when the clock signal Φi is at a low level, the output of the OR gate OR11 is at a low level, so that the pull-up resistance of the output voltage VOUT is the parallel impedance of the tenth PMOS transistor MP12 and at least one eleventh PMOS transistor MP13, which reduces the The pull-up resistance corresponding to each sub-charge pump module increases the charging current of the eighth capacitor R8 connected to the output voltage terminal of each sub-charge pump module, and reduces the on-resistance on the charging path.

When the frequency of the clock signal Φi becomes high, the charging speed of each sub-charge pump module to C4-C7 under the control of the high-frequency clock signal is increased by reducing the on-resistance of the third inverter INV2, thereby reducing the charging speed of each sub-charge pump module. Settling time of the output voltage of the charge pump module. At the same time, when the output voltage of each sub-charge pump module reaches the steady state value, the logic signal is 0, and the clock signal Φi is low level and high level, the on-resistance of the third inverter INV2 is determined by the tenth PMOS transistor MP12 respectively. . The on-resistance of the seventh NMOS transistor MN11 is determined. At this time, the frequency of the clock signal Φi decreases, and the pull-up and pull-down resistance of the selection switch increases, as long as the charging performance of each sub-charge pump module is not affected. Therefore, after the output voltage of each sub-charge pump module reaches a steady state, due to the increase of the pull-up and pull-down resistance of the selection switch, the speed at which the capacitors C4-C7 draw current from the power supply becomes slower, which can further reduce the input power supply when the charge pump circuit is working. the peak current.

As shown in FIG. 8 , the acceleration response control module 105 includes a first resistor R1, a second resistor R0 and a hysteresis comparator Comp; one end of the first resistor R1 is connected to the output voltage terminal VOUT of each sub-charge pump module, and the first resistor R1 The other end is respectively connected to one end of the second resistor R0 and the inverting input end of the hysteresis comparator Comp, the other end of the second resistor R0 is grounded, the non-inverting input end of the hysteresis comparator Comp is connected to the reference voltage VREF, and the output of the hysteresis comparator Comp is connected to the ground. The terminal is connected to the input terminal of the first inverter INV1 of the phase clock generating module 101 and the input terminal of the third inverter INV2 of each sub-charge pump module.

The output voltage of each sub-charge pump module is detected by the acceleration response detection module 105. When the output voltage of each sub-charge pump module does not reach the target value, the output logic signal fast_en of the hysteresis comparator Comp is a high level, and is output to Phase clock generation module 101 and each sub-charge pump module. In the phase clock generation module, the oscillation frequency of the ring oscillator is changed, and in each sub-charge pump module, the charging and discharging speed of the capacitor is adjusted, so that each sub-charge pump module can quickly generate an output voltage. When the output voltage of each sub-charge pump module reaches the target value, the output logic signal fast_en of the hysteresis comparator Comp is a low level, so that the charge pump circuit operates in a low peak current and low power consumption state. Among them, in order to facilitate the judgment of whether the output voltage of each sub-charge pump module reaches the target value, a threshold inversion voltage can be set in the hysteresis comparator Comp, and the threshold inversion voltage is VREF(1+R1/R0). Adjust the first resistance R1, The ratio of the second resistor R0 can be set to the threshold inversion voltage. If the output voltage of each sub-charge pump module reaches the threshold inversion voltage, it is considered that the output voltage of each sub-charge pump module reaches the target value.

It should be noted that, the charge pump circuit provided by the embodiment of the present invention can be used in an analog integrated circuit chip. The specific structure of the charge pump circuit in the analog integrated circuit chip will not be described in detail here.

The above-mentioned charge pump circuit can also be used in various communication terminals as an important part of an analog integrated circuit. The communication terminal mentioned here refers to the computer equipment that can be used in the mobile environment and supports various communication standards such as GSM, EDGE, TDD_LTE, FDD_LTE, 5G NR, etc., including mobile phones, notebook computers, tablet computers, car computers, etc. In addition, the technical solutions provided by the present invention are also applicable to other analog integrated circuit applications, such as communication base stations and the like.

Compared with the prior art, the charge pump circuit provided by the present invention generates a plurality of clock signals with a fixed phase difference through the phase clock generation module, so as to correspondingly control the plurality of sub-charge pump modules to generate output voltages, and the acceleration response control module is used to control each sub-module. The output voltage of the charge pump module is detected, and logic signals are output to the phase clock generation module and each sub-charge pump module respectively to change the frequency of the clock signal output by the phase clock generation module and reduce the charge and discharge of the capacitors in each sub-charge pump module. time. The invention can effectively reduce the peak current drawn by the charge pump circuit from the input power supply, and reduce the ripple interference generated by the charge pump circuit on the input power supply and the output voltage signal, thereby reducing the dependence of the input power supply on off-chip capacitors.

The charge pump circuit, chip and communication terminal provided by the present invention have been described in detail above. For those skilled in the art, any obvious changes made to it without departing from the essential content of the present invention will fall within the protection scope of the patent right of the present invention.

Claims

A charge pump circuit is characterized by comprising a phase clock generation module, an acceleration response control module and a plurality of sub-charge pump modules, the output end of the phase clock generation module is connected to the clock control end of each sub-charge pump module, the plurality of sub-charge pump modules. After the charge pump modules are connected in parallel, the input power supply terminal and the output voltage terminal are correspondingly connected, the output voltage terminal is connected to the input terminal of the acceleration response control module, and the output terminal of the acceleration response control module is connected to the phase clock generation module and each the input end of the sub-charge pump module;

The phase clock generation module generates a plurality of clock signals with a fixed phase difference, correspondingly controls the plurality of sub-charge pump modules to generate output voltages, and at the same time detects the output voltages by the acceleration response control module, and sends them to the The phase clock generation module and each sub-charge pump module output logic signals, so that when the output voltage does not reach the target value, the phase clock generation module generates an accelerated clock signal to rapidly generate the output voltage, and when the output voltage does not reach the target value When the target value is reached, the phase clock generating module controls each sub-charge pump module to maintain a normal output voltage.
The charge pump circuit of claim 1, wherein:

The phase clock generation module includes a first inverter and a plurality of phase clock sub-circuits composed of a first NMOS transistor, a first capacitor, a second capacitor, an output node and a second inverter; wherein the first The input end of the inverter is connected to the output end of the acceleration response control module, the output end of the first inverter is connected to the gate of each first NMOS transistor, and the drain of each first NMOS transistor is connected to the corresponding The first capacitors are correspondingly connected in series between the output nodes, the source of each first NMOS transistor is grounded, each output node is connected to a corresponding sub-charge pump module, and each output node is connected in series with the ground correspondingly. The second capacitor, each of the second inverters is cascaded and connected to the power supply and the ground correspondingly, and then connected end to end to form a ring oscillator.
The charge pump circuit of claim 2, wherein:

The second inverter includes a first PMOS transistor and a second NMOS transistor, the gates and drains of the first PMOS transistor and the second NMOS transistor are connected correspondingly, and the source of the first PMOS transistor is connected For the power supply, the source of the second NMOS transistor is grounded.
The charge pump circuit according to any one of claims 1 to 3, wherein:

According to the state of the logic signal output by the acceleration response control module to the phase clock generation module, the size of the load capacitance of the output node of the phase clock generation module is changed, so as to adjust a plurality of fixed phase differences generated by the ring oscillator The size of the oscillation frequency of the clock signal.
The charge pump circuit according to any one of claims 1 to 3, wherein:

According to the state of the logic signal output by the acceleration response control module to the phase clock generation module, the width to length ratio of the switch tube in each of the second inverters is changed, so as to change the The equivalent resistance is used to adjust the oscillation frequency of a plurality of clock signals with a fixed phase difference generated by the ring oscillator.
The charge pump circuit of claim 1, wherein:

When each of the sub-charge pump modules provides a voltage output higher than the input power supply, each sub-charge pump module includes a third NMOS transistor, a fourth NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, The fifth PMOS tube, the first selection switch, the second selection switch, the third selection switch, the fourth selection switch and the third capacitor, the fourth capacitor, the fifth capacitor, the sixth capacitor and the eighth capacitor, the third NMOS The substrate end and source of the tube, the substrate end and source of the fourth NMOS tube are respectively connected to the input power supply, the gate of the third NMOS tube is respectively connected to the drain of the fourth NMOS tube, the A plate of the fourth capacitor and the drain of the second PMOS transistor, and the drain of the third NMOS transistor are respectively connected to the gate of the fourth NMOS transistor, a plate of the third capacitor and the drain of the third NMOS transistor. The drain of the third PMOS transistor, the substrate end and source of the second PMOS transistor, the substrate end and source of the third PMOS transistor, the substrate end and source of the fourth PMOS transistor and the substrate end and source of the fifth PMOS transistor are respectively connected to the output voltage end and one end of the eighth capacitor, the other end of the eighth capacitor is grounded, and the gate of the second PMOS transistor is connected to the One plate of the sixth capacitor, the drain of the fourth PMOS tube and the gate of the fifth PMOS tube, and the gate of the third PMOS tube is respectively connected to one plate of the fifth capacitor, The drain of the fifth PMOS transistor and the gate of the fourth PMOS transistor, the third capacitor, the fourth capacitor, the fifth capacitor, and the other plate of the sixth capacitor are connected correspondingly. The moving ends of the selection switches are respectively connected to their respective clock control terminals, and the clock control terminals of the selection switches are correspondingly connected to the same output node of the phase clock generation module. One static terminal is connected to the power supply, the other static terminal is connected to the ground terminal, the response control terminals of the selection switch are respectively connected to the output terminals of the acceleration response control module, and the input terminal of the acceleration response control module is connected to the output voltage terminal.
The charge pump circuit of claim 6, wherein:

Each selection switch includes a tenth PMOS transistor, a seventh NMOS transistor, an OR gate, an AND gate, a third inverter, and at least one eleventh PMOS transistor and at least one eighth NMOS transistor. The tenth PMOS transistor, all the The gate of the seventh NMOS transistor is connected as a clock control terminal of the selection switch, which is used to connect an output node of the phase clock generation module, and the gates of the tenth PMOS transistor and the seventh NMOS transistor are connected correspondingly. One input end of the OR gate and the AND gate, the drain of the tenth PMOS transistor and the seventh NMOS transistor, and each eleventh PMOS transistor and the drain of the corresponding eighth NMOS transistor are connected to each other Then it is used as the moving end of the selection switch, which is used to connect the other plate of the corresponding capacitor. The tenth PMOS tube and the source of each eleventh PMOS tube are respectively connected to the power supply, and the seventh NMOS tube and each The source of the eighth NMOS transistor is grounded respectively, the gate of each eleventh PMOS transistor is connected to the output end of the OR gate, the gate of each eighth NMOS transistor is connected to the output end of the AND gate, the OR The other input end of the gate is connected to the output end of the third inverter, and the other input end of the AND gate is connected to the input end of the third inverter and the output end of the acceleration response control module.
The charge pump circuit of claim 1, wherein:

When the clock signal output from the same output node in the phase clock generation module controls the turn-on and turn-off of the corresponding selection switch, the first clock signal and the third clock signal, the second clock signal and the fourth clock signal are non-interchangeable. The non-overlapping time is Tnov1; the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are non-overlapping clock signals, and the non-overlapping time is Tnov3 and Tnov2, respectively. The non-overlapping time satisfies the relation Tnov2=2*Tnov1+Tnov3.
The charge pump circuit of claim 1, wherein:

When each of the sub-charge pump modules provides a voltage output lower than the ground voltage, the third NMOS transistor and the fourth NMOS transistor in each sub-charge pump module are correspondingly replaced with a fifth NMOS transistor and a sixth NMOS transistor. For NMOS transistors, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are correspondingly replaced with the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor and the third PMOS transistor. Nine PMOS tubes.
The charge pump circuit of claim 1, wherein:

The acceleration response control module includes a first resistor, a second resistor and a hysteresis comparator, one end of the first resistor is respectively connected to the output voltage terminals of each sub-charge pump module, and the other end of the first resistor is respectively connected to the One end of the second resistor, the inverting input end of the hysteresis comparator, the other end of the second resistor is grounded, the non-inverting input end of the hysteresis comparator is connected to the reference voltage, and the output ends of the hysteresis comparator are respectively The input terminal of the first inverter is connected to the input terminal of the third inverter in each sub-charge pump module.
An integrated circuit chip is characterized by comprising the charge pump circuit described in any one of claims 1-10.
A communication terminal, characterized by comprising the charge pump circuit described in any one of claims 1-10.