CN114759777B - Circuit for eliminating current burrs of charge pump - Google Patents
Circuit for eliminating current burrs of charge pump Download PDFInfo
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- CN114759777B CN114759777B CN202210679085.5A CN202210679085A CN114759777B CN 114759777 B CN114759777 B CN 114759777B CN 202210679085 A CN202210679085 A CN 202210679085A CN 114759777 B CN114759777 B CN 114759777B
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- 230000008030 elimination Effects 0.000 claims abstract description 9
- 238000003379 elimination reaction Methods 0.000 claims abstract description 9
- 230000005669 field effect Effects 0.000 claims description 138
- 239000003990 capacitor Substances 0.000 claims description 23
- 101150070189 CIN3 gene Proteins 0.000 claims description 7
- 101150110971 CIN7 gene Proteins 0.000 claims description 7
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 7
- 101100508840 Daucus carota INV3 gene Proteins 0.000 claims description 7
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- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 7
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000000740 bleeding effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/373—Design optimisation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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Abstract
The invention belongs to the field of radio frequency integrated circuits, and particularly discloses a circuit for eliminating current burrs of a charge pump, which comprises a current reference circuit, a charge pump circuit and an output end, wherein the current reference circuit, the charge pump circuit and the output end are sequentially connected; the reverse pulse burr eliminating circuit and the forward pulse burr eliminating circuit are respectively connected with the charge pump circuit and the output end. According to the invention, the elimination of the current glitch of the charge pump circuit is realized through the reverse pulse glitch elimination circuit and the forward pulse glitch elimination circuit, and the low stray performance of the phase-locked loop frequency synthesizer is realized.
Description
Technical Field
The invention belongs to the field of radio frequency integrated circuits, and particularly relates to a circuit for eliminating current burrs of a charge pump.
Background
The phase-locked loop frequency synthesizer provides carrier signals for a wireless communication system, and is one of important components of the wireless communication system. The charge pump is used as an important module in the phase-locked loop frequency synthesizer, and the stray performance of the phase-locked loop frequency synthesizer is directly influenced by the non-ideal effects of the charge pump, the charge pump and the charge pump, such as the mismatch of the charge and discharge current, the current glitch and the like.
The traditional charge pump structure realizes the matching between the charge and discharge currents through structures such as operational amplifier clamping, negative feedback and the like, thereby realizing the less periodic jitter of the voltage of an output end and ensuring the stray performance of the phase-locked loop frequency synthesizer. However, the voltage jitter of the output end caused when the charging and discharging current glitch is injected into the output end is often ignored, so that the stray performance of the phase-locked loop frequency synthesizer is influenced. For the current sources and the current sinking uA-level charge-discharge current, the current glitches can be always as high as mA level, and the stray performance of the phase-locked loop frequency synthesizer can be greatly influenced.
With the stricter and stricter indexes of the communication system such as sensitivity, spurious suppression and the like, the design of the low-spurious phase-locked loop frequency synthesizer is very important. Therefore, on the premise of realizing charge-discharge current matching, the charge pump circuit eliminates the current glitch of the charge pump, which becomes a technical problem to be solved urgently.
Disclosure of Invention
In order to solve the technical problems, the invention adopts the technical scheme that:
the invention provides a circuit for eliminating current burrs of a charge pump, which comprises a current reference circuit, a charge pump circuit and an output end, wherein the current reference circuit, the charge pump circuit and the output end are sequentially connected; the reverse pulse burr eliminating circuit and the forward pulse burr eliminating circuit are respectively connected with the charge pump circuit and the output end;
the current reference circuit is connected with a Vref end of the charge pump circuit through a Vo end;
the reverse pulse deburring circuit is connected with an SWP _ D end of the charge pump circuit through an SWP end; the reverse pulse burr eliminating circuit is connected to the output end through an ICP _ UP end and an ICP end of the charge pump circuit;
the forward pulse deburring circuit is connected with an SWN _ D end of the charge pump circuit through an SWN end; the forward pulse burr eliminating circuit is connected to the output end through an ICP _ DN end and an ICP end of the charge pump circuit.
The charge pump circuit is connected with the Vref end of the charge pump circuit through the Vo end, provides a bias voltage signal for the charge pump circuit and ensures accurate copy of reference current. The reverse pulse burr removing circuit provides a node path for current burr discharging for the charge pump circuit, and inhibits the current burr from discharging to the charge pump circuit, thereby ensuring the low stray performance of the frequency synthesizer. Similarly, the forward pulse glitch removal circuit also provides a node path for current glitch discharge for the charge pump circuit, and the current glitch discharge is inhibited in the charge pump circuit, so that the low stray performance of the frequency synthesizer is ensured.
According to the invention, the output ends of the reverse pulse burr eliminating circuit and the forward pulse burr eliminating circuit are connected to the output end of the charge pump circuit, and the positive current burr is released in real time, so that the elimination of the current burr of the charge pump circuit is realized, and the low stray performance of the phase-locked loop frequency synthesizer is realized.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of the overall structure of a charge pump circuit for eliminating current glitches according to the present invention;
FIG. 2 is a schematic diagram of a current reference circuit according to the present invention;
fig. 3 is a schematic structural diagram of a charge pump circuit according to the present invention.
Fig. 4 is a schematic structural diagram of a reverse pulse glitch removal circuit according to the present invention.
Fig. 5 is a schematic structural diagram of a forward pulse glitch removal circuit according to the present invention.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
Wherein Vo is the output voltage; vref is a reference voltage; SWP is a P-type switch; SWP _ D is a P-type switch extension; SWN is an N-type switch; SWN _ D is an N-type switch extension; ICP is the net current; ICP _ UP is the UP current; ICP _ DN is a decreasing current; VDD is a power supply; GND is ground; SW is a positive switch; SWB is a reverse switch; NOR is a NOR gate; the NAND is a NAND gate.
As shown in fig. 1, a circuit for eliminating current glitch of a charge pump comprises a current reference circuit 1, a charge pump circuit 2 and an output end which are connected in sequence; the reverse pulse burr removing circuit 3 and the forward pulse burr removing circuit 4 are respectively connected with the charge pump circuit 2 and the output end;
the current reference circuit 1 is connected with a Vref end of the charge pump circuit 2 through a Vo end;
the reverse pulse deburring circuit 3 is connected with an SWP _ D end of the charge pump circuit 2 through an SWP end; the reverse pulse deburring circuit 3 is connected with the ICP end of the charge pump circuit 2 through the ICP _ UP end and the output end;
the Vo end of the current reference circuit is connected with the Vref end of the charge pump circuit, so that a bias voltage signal can be provided for the core charge pump circuit 2, and accurate copying of reference current is guaranteed.
The forward pulse deburring circuit 4 is connected with the SWN _ D end of the charge pump circuit 2 through the SWN end; the forward pulse glitch elimination circuit 4 is connected to the output terminal through an ICP _ DN terminal and an ICP terminal of the charge pump circuit 2.
According to the invention, the output ends of the reverse pulse deburring circuit 3 and the forward pulse deburring circuit 4 are connected with the input end and the output end of the charge pump circuit 2 to realize the elimination of the current burr of the charge pump circuit 2, so that the low stray performance of the phase-locked loop frequency synthesizer is realized.
Further, as shown in fig. 2, the current reference circuit 1 includes: a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, and a reference current source S1;
one end of the reference current source S1 is connected to VDD, the other end of the reference current source S1 is connected to the drain terminal of the first fet M1, the gate terminal of the first fet M1 is used as the SW terminal of the current reference circuit, the source terminal of the first fet M1 is connected to the drain terminal and the gate terminal of the second fet M2, and the drain terminal of the fourth fet M4, and are used together as the Vo terminal of the current reference circuit;
the source end of the second field effect transistor M2 is connected to the drain end of the third field effect transistor M3, the gate end of the third field effect transistor M3 is connected to VDD, the source end of the third field effect transistor M3 is connected to GND, the gate end of the fourth field effect transistor M4 is used as the SWB end of the current reference circuit, and the source end of the fourth field effect transistor M4 is connected to GND.
In specific implementation, the reference current source S1 provides a reference current, and the second fet M2 and the third fet M3 form a basic current mirror structure to copy the reference current. The first fet M1 and the fourth fet M4 are switching transistors that control the on and off of the reference current. When the SW terminal of the current reference circuit 1 outputs a high level and the SWB terminal outputs a low level, that is, SW =1 and SWB =0, the first fet M1 is turned on, the first fet M1 operates in a linear region, the fourth fet M4 is turned off, and the reference current is copied to the charge pump circuit 2 through the current mirror; when SW =0 and SWB =1, the first fet M1 is turned off, the fourth fet M4 is turned on, and the reference current is turned off.
Further, as shown in fig. 3, the charge pump circuit 2 includes: a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4 and an operational amplifier OPAMP;
the source end of the fifth field-effect tube M5 and the source end of the ninth field-effect tube M9 are connected to VDD, the gate end of the fifth field-effect tube M5 is connected to GND, the drain end of the fifth field-effect tube M5 is connected to the source end of the sixth field-effect tube M6, the gate end of the sixth field-effect tube M6 is connected to one end of the first resistor R1 and the output end of the operational amplifier OPAMP, the drain end of the sixth field-effect tube M6 is connected to the drain end of the seventh field-effect tube M7 and the input positive end of the operational amplifier OPAMP, the gate end of the seventh field-effect tube M7 is connected to one end of the second resistor R2 and used as Vref end of the charge pump circuit, the source end of the seventh field-effect tube M7 is connected to the drain end of the eighth field-effect tube M8, the gate end of the eighth field-effect tube M8 is connected to VDD, and the source end of the eighth field-effect tube M8 is connected to GND;
the other end of the second resistor R2 is connected with one end of a second capacitor C2 and the gate end of an eleventh field-effect tube M11, the other end of the second capacitor C2 is connected with GND, and the drain end of the eleventh field-effect tube M11 is connected with the input negative end of the operational amplifier OPAMP, one end of a third capacitor C3 and the drain end of a tenth field-effect tube M10, and is used as the ICP end of the charge pump circuit;
the other end of the third capacitor C3 is connected with GND, the gate end of the tenth fet M10 is connected with the other end of the first resistor R1 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected with GND, the source end of the tenth fet M10 is connected with the drain end of the ninth fet M9, and the source ends and the drain ends are jointly used as the SWP _ D end of the charge pump circuit;
a gate end of the ninth field-effect transistor M9 is connected with an output end of the second inverter INV2, an input end of the second inverter INV2 is connected with an output end of the first inverter INV1, an input end of the first inverter INV1 is used as an input end of the rising clock signal UP, a source end of the eleventh field-effect transistor M11 is connected with a drain end of the twelfth field-effect transistor M12, and the gate ends and the drain ends are used as the SWN _ D end of the charge pump circuit;
the source end of the twelfth field effect transistor M12 is connected to GND, the gate end of the twelfth field effect transistor M12 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the output end of the third inverter INV3, and the input end of the third inverter INV3 is used as the input end of the falling clock signal DN.
In specific implementation, the fifth fet M5, the sixth fet M6, the seventh fet M7, the eighth fet M8, the ninth fet M9, the tenth fet M10, the eleventh fet M11, and the twelfth fet M12 together form a basic charge pump structure, and charge and discharge current to and from the third capacitor C3. When the gate terminal of the ninth fet M9 is at a low level, the ninth fet M9 is turned on, the tenth fet M10 operates in a saturation region, and the reference current charges the third capacitor C3 through the tenth fet M10; when the gate terminal of the twelfth fet M12 is at a high level, the twelfth fet M12 is turned on, the eleventh fet M11 operates in a saturation region, and the reference current discharges the third capacitor C3 through the eleventh fet M11.
The first resistor R1 and the first capacitor C1, and the second resistor R2 and the second capacitor C2 form low-pass filtering, so that voltage ripples on the gate terminal of the tenth fet M10 and the gate terminal of the eleventh fet M11 are reduced.
The first and second inverters INV1 and INV2 partially delay and drive an input signal. Similarly, the third and fourth inverters INV3 and INV4 partially delay and drive the input signal.
The first operational amplifier OPAMP clamps the potential of the drain terminal of the tenth field-effect transistor M10, the drain terminal of the eleventh field-effect transistor M11, the drain terminal of the sixth field-effect transistor M6 and the drain terminal of the seventh field-effect transistor M7, and ensures the matching of charging and discharging currents.
Further, as shown in fig. 4, the reverse pulse deburring circuit 3 includes: a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, and a NAND gate NAND;
an input end of the fifth inverter INV5 and an input end of the NAND gate NAND are connected to the input end of the rising clock signal UP;
an output end of the fifth inverter INV5 is connected to an input end of the sixth inverter INV6, an output end of the sixth inverter INV6 is connected to an input end of the seventh inverter INV7, and an output end of the seventh inverter INV7 is connected to another input end of the NAND gate NAND;
a drain terminal and a source terminal of the thirteenth field effect transistor M13 are respectively connected to VDD, and a gate terminal of the thirteenth field effect transistor M13 is connected to an output terminal of the sixth inverter INV 6;
the output end of the NAND gate is connected with the gate end of a fourteenth field effect transistor M14 and the gate end of a fifteenth field effect transistor M15 respectively;
the source end of the fourteenth field effect transistor M14 and the source end of the fifteenth field effect transistor M15 are used as the SWP end of the reverse pulse deburring circuit and are connected with the SWP _ D end of the charge pump circuit; the drain terminal of the fourteenth field effect transistor M14 is connected with GND;
the SWP terminal of the reverse pulse glitch removal circuit 3 is connected to the SWP _ D terminal of the charge pump circuit 2, providing a node path for current glitch bleeding.
And the drain terminal of the fifteenth field effect transistor M15 is connected with the ICP terminal of the charge pump circuit as the ICP _ UP terminal of the reverse pulse deburring circuit.
The ICP _ UP end of the reverse pulse burr removing circuit 3 is connected with the ICP end of the charge pump circuit 2, current burrs are inhibited from being discharged to the ICP end of the charge pump circuit 2, signals of an output end are enabled not to be affected by the current burrs, and therefore the low stray performance of the frequency synthesizer is guaranteed.
In specific implementation, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, the thirteenth field effect transistor M13 and the first NAND gate NAND form a combinational logic, so that when the edge of the clock input signal UP changes from low level to high level, an inverted narrow pulse signal is output.
When the clock signal UP goes from low level to high level, the ninth fet M9 in the charge pump circuit 2 is turned on as a switching transistor, and the accumulated current glitch will be injected into the ICP terminal of the charge pump circuit 2. Meanwhile, a narrow pulse signal output by the combinational logic is low, the fourteenth field effect transistor M14 and the fifteenth field effect transistor M15 are conducted together, the fifteenth field effect transistor M15 clamps the source end potential and the drain end potential of the tenth field effect transistor M10 in the charge pump circuit 2 to be consistent, current burrs are inhibited from being injected into an output direct current signal end ICP, the fourteenth field effect transistor M14 serves as a drain tube, and the current burrs are drained to GND, so that the effect of eliminating the current burrs is achieved.
Further, as shown in fig. 5, the forward pulse glitch elimination circuit 4 includes: a sixteenth field effect transistor M16, a seventeenth field effect transistor M17, an eighteenth field effect transistor M18, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, and an NOR;
an input end of the eighth inverter INV8 and one input end of the NOR gate NOR are commonly connected to the input end of the falling clock signal DN;
an output end of the eighth inverter INV8 is connected to an input end of the ninth inverter INV9, an output end of the ninth inverter INV9 is connected to an input end of the tenth inverter INV10, and an output end of the tenth inverter INV10 is connected to another input end of the NOR gate NOR;
a drain terminal and a source terminal of the sixteenth field effect transistor M16 are respectively connected to VDD, and a gate terminal of the sixteenth field effect transistor M16 is connected to an output terminal of the ninth inverter INV 9;
the output end of the NOR gate NOR is respectively connected with the gate end of a seventeenth field-effect tube M17 and the gate end of an eighteenth field-effect tube M18;
the drain end of the seventeenth field-effect tube M17 is used as the ICP _ DN end of the forward pulse deburring circuit and is connected with the ICP of the charge pump circuit;
the ICP _ DN end of the forward pulse burr removing circuit 4 is connected with the ICP end of the charge pump circuit 2, and the directional current burr is inhibited from being discharged to the ICP end of the charge pump circuit 2, so that the signal of the output end is not affected by the current burr, and the low stray performance of the frequency synthesizer is ensured.
The source terminal of the eighteenth fet M18 and the source terminal of the seventeenth fet M17 are connected to the SWN _ D of the charge pump circuit as the SWN terminal of the forward pulse glitch elimination circuit.
The SWN end of the forward pulse deburring circuit 4 is connected with the SWN _ D end of the charge pump circuit 2, and a node path for current burr leakage is provided.
In specific implementation, the eighth inverter INV8, the ninth inverter INV9, the tenth inverter INV10, the sixteenth fet M16 and the first NOR gate NOR form combinational logic, so that when the edge of the clock input signal DN goes from high level to low level, a forward narrow pulse signal is output.
When the clock signal DN goes from high level to low level, the twelfth fet M12 in the charge pump circuit 2 is turned on as a switching tube, and the accumulated current glitch will be injected into the output dc signal ICP. Meanwhile, a narrow pulse signal output by the combinational logic is high, the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18 are conducted together, the source end potential and the drain end potential of the eleventh field-effect transistor M11 in the seventeenth field-effect transistor M17 clamp the charge pump circuit 2 are consistent, current burrs are inhibited from being injected into an ICP end of the charge pump circuit 2, the eighteenth field-effect transistor M18 serves as a drain pipe, and the current burrs are drained to VDD, so that the effect of eliminating the current burrs is achieved.
Further, VDD provides a voltage at a square wave high level; GND pulls the square wave voltage low.
While embodiments of the invention have been disclosed above, it is not limited to the applications listed in the description and the embodiments. It can be applied to all kinds of fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. Therefore, the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention as claimed in the appended claims.
Claims (3)
1. A circuit for eliminating current glitches of a charge pump is characterized by comprising a current reference circuit, a charge pump circuit and an output end which are sequentially connected; the reverse pulse burr eliminating circuit and the forward pulse burr eliminating circuit are respectively connected with the charge pump circuit and the output end;
the current reference circuit is connected with a Vref end of the charge pump circuit through a Vo end;
the reverse pulse deburring circuit is connected with an SWP _ D end of the charge pump circuit through an SWP end; the reverse pulse burr eliminating circuit is connected to the output end through an ICP _ UP end and an ICP end of the charge pump circuit;
the forward pulse deburring circuit is connected with an SWN _ D end of the charge pump circuit through an SWN end; the forward pulse burr eliminating circuit is connected to the output end through an ICP _ DN end and an ICP end of the charge pump circuit;
the charge pump circuit includes: a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4 and an operational amplifier OPAMP;
the source end of the fifth field-effect tube M5 and the source end of the ninth field-effect tube M9 are connected to VDD, the gate end of the fifth field-effect tube M5 is connected to GND, the drain end of the fifth field-effect tube M5 is connected to the source end of the sixth field-effect tube M6, the gate end of the sixth field-effect tube M6 is connected to one end of the first resistor R1 and the output end of the operational amplifier OPAMP, the drain end of the sixth field-effect tube M6 is connected to the drain end of the seventh field-effect tube M7 and the input positive end of the operational amplifier OPAMP, the gate end of the seventh field-effect tube M7 is connected to one end of the second resistor R2 and serves as Vref end of the charge pump circuit, the source end of the seventh field-effect tube M7 is connected to the drain end of the eighth field-effect tube M8, the gate end of the eighth field-effect tube M8 is connected to VDD, and the source end of the eighth field-effect tube M8 is connected to GND;
the other end of the second resistor R2 is connected with one end of a second capacitor C2 and the gate end of an eleventh field-effect tube M11, the other end of the second capacitor C2 is connected with GND, and the drain end of the eleventh field-effect tube M11 is connected with the input negative end of the operational amplifier OPAMP, one end of a third capacitor C3 and the drain end of a tenth field-effect tube M10, and is used as the ICP end of the charge pump circuit;
the other end of the third capacitor C3 is connected with GND, the gate end of the tenth fet M10 is connected with the other end of the first resistor R1 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected with GND, the source end of the tenth fet M10 is connected with the drain end of the ninth fet M9, and the source ends and the drain ends are collectively used as the SWP _ D end of the charge pump circuit;
a gate end of the ninth field-effect transistor M9 is connected with an output end of the second inverter INV2, an input end of the second inverter INV2 is connected with an output end of the first inverter INV1, an input end of the first inverter INV1 is used as an input end of the rising clock signal DN, a source end of the eleventh field-effect transistor M11 is connected with a drain end of the twelfth field-effect transistor M12, and the gate ends and the drain ends are used as an SWN _ D end of the charge pump circuit;
the source end of the twelfth field effect transistor M12 is connected to GND, the gate end of the twelfth field effect transistor M12 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the output end of the third inverter INV3, and the input end of the third inverter INV3 is used as the input end of the falling clock signal DN;
the reverse pulse glitch removal circuit includes: a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, and a NAND gate NAND;
an input end of the fifth inverter INV5 and one input end of the NAND gate NAND are connected to an input end of a rising clock signal DN;
an output end of the fifth inverter INV5 is connected to an input end of the sixth inverter INV6, an output end of the sixth inverter INV6 is connected to an input end of the seventh inverter INV7, and an output end of the seventh inverter INV7 is connected to another input end of the NAND gate NAND;
a drain terminal and a source terminal of the thirteenth field effect transistor M13 are respectively connected to VDD, and a gate terminal of the thirteenth field effect transistor M13 is connected to an output terminal of the sixth inverter INV 6;
the output end of the NAND gate NAND is respectively connected with the gate end of the fourteenth field effect transistor M14 and the gate end of the fifteenth field effect transistor M15;
the source end of the fourteenth field effect transistor M14 and the source end of the fifteenth field effect transistor M15 are used as the SWP end of the reverse pulse glitch elimination circuit and are connected with the SWP _ D end in the charge pump circuit; the drain terminal of the fourteenth field effect transistor M14 is connected with the GND;
the drain terminal of the fifteenth field effect transistor M15 is used as the ICP _ UP terminal of the reverse pulse deburring circuit and is connected with the ICP terminal of the charge pump circuit;
the forward pulse glitch removal circuit includes: a sixteenth field effect transistor M16, a seventeenth field effect transistor M17, an eighteenth field effect transistor M18, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, and an NOR;
wherein an input end of the eighth inverter INV8 is commonly connected to an input end of a falling clock signal DN with one input end of the NOR gate NOR;
an output end of the eighth inverter INV8 is connected to an input end of the ninth inverter INV9, an output end of the ninth inverter INV9 is connected to an input end of the tenth inverter INV10, and an output end of the tenth inverter INV10 is connected to another input end of the NOR gate NOR;
a drain terminal and a source terminal of the sixteenth field effect transistor M16 are respectively connected to VDD, and a gate terminal of the sixteenth field effect transistor M16 is connected to an output terminal of the ninth inverter INV 9;
the output end of the NOR gate NOR is connected with the gate end of the seventeenth field-effect transistor M17 and the gate end of the eighteenth field-effect transistor M18 respectively;
the drain end of the seventeenth field-effect tube M17 is used as the ICP _ DN end of the forward pulse deburring circuit and is connected with the ICP of the charge pump circuit;
the source end of the eighteenth field-effect tube M18 and the source end of the seventeenth field-effect tube M17 are used as the SWN end of the forward pulse deburring circuit and are connected with the SWN _ D of the charge pump circuit.
2. The circuit for charge pump current glitch removal of claim 1, in which the current reference circuit comprises: a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, and a reference current source S1;
one end of a reference current source S1 is connected with VDD, the other end of the reference current source S1 is connected with the drain terminal of a first field effect transistor M1, the gate terminal of the first field effect transistor M1 is used as the SW terminal of the current reference circuit, the source terminal of the first field effect transistor M1 is connected with the drain terminal and the gate terminal of a second field effect transistor M2 and the drain terminal of a fourth field effect transistor M4, and the drain terminals are used as the Vo terminal of the current reference circuit;
the source end of the second field effect transistor M2 is connected to the drain end of the third field effect transistor M3, the gate end of the third field effect transistor M3 is connected to VDD, the source end of the third field effect transistor M3 is connected to GND, the gate end of the fourth field effect transistor M4 is used as the SWB end of the current reference circuit, and the source end of the fourth field effect transistor M4 is connected to GND.
3. The circuit for glitch removal of charge pump current of claim 1, in which the VDD provides a voltage at a square wave high level; the GND pulls the square wave voltage low to a low level.
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| CN202210679085.5A CN114759777B (en) | 2022-06-16 | 2022-06-16 | Circuit for eliminating current burrs of charge pump |
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| CN114759777B true CN114759777B (en) | 2022-09-20 |
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| CN115118277B (en) * | 2022-08-29 | 2022-11-18 | 成都芯矩阵科技有限公司 | Charge pump, phase-locked loop and method for improving reference stray of phase-locked loop |
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|---|---|---|---|---|
| CN103107806A (en) * | 2011-11-14 | 2013-05-15 | 孙茂友 | Low noise spectrum Sigma-Delta decimal-N phase-locked loop |
| CN108471307A (en) * | 2017-10-30 | 2018-08-31 | 四川和芯微电子股份有限公司 | Charge pump circuit |
| CN112600539A (en) * | 2021-03-03 | 2021-04-02 | 上海亿存芯半导体有限公司 | Circuit for filtering burr |
| CN112702043A (en) * | 2021-03-24 | 2021-04-23 | 上海海栎创科技股份有限公司 | Bidirectional deburring circuit |
| CN113557667A (en) * | 2019-05-23 | 2021-10-26 | 华为技术有限公司 | Phase-locked loop |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592857B2 (en) * | 2007-12-21 | 2009-09-22 | G-Time Electronic Co., Ltd. | Charge pump circuit |
| CN106685415B (en) * | 2017-02-07 | 2024-05-07 | 江西华讯方舟智能技术有限公司 | Charge pump circuit and phase-locked loop |
| CN112165250B (en) * | 2020-10-12 | 2022-04-05 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip and communication terminal |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103107806A (en) * | 2011-11-14 | 2013-05-15 | 孙茂友 | Low noise spectrum Sigma-Delta decimal-N phase-locked loop |
| CN108471307A (en) * | 2017-10-30 | 2018-08-31 | 四川和芯微电子股份有限公司 | Charge pump circuit |
| CN113557667A (en) * | 2019-05-23 | 2021-10-26 | 华为技术有限公司 | Phase-locked loop |
| CN112600539A (en) * | 2021-03-03 | 2021-04-02 | 上海亿存芯半导体有限公司 | Circuit for filtering burr |
| CN112702043A (en) * | 2021-03-24 | 2021-04-23 | 上海海栎创科技股份有限公司 | Bidirectional deburring circuit |
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Address after: Building 12, Hard Technology Enterprise Community, No. 3000 Biyuan Second Road, High tech Zone, Xi'an City, Shaanxi Province, 710065 Patentee after: Borui Jixin (Xi'an) Electronic Technology Co.,Ltd. Address before: 710199 building 12, hard technology enterprise community, No. 3000, Biyuan Second Road, high tech Zone, Xi'an, Shaanxi Province Patentee before: XI'AN BORUI JIXIN ELECTRONIC TECHNOLOGY Co.,Ltd. |