CN103346776B

CN103346776B - The switching capacity buffer circuits reinforced is carried out for single particle effect

Info

Publication number: CN103346776B
Application number: CN201310240509.9A
Authority: CN
Inventors: 姚素英; 李渊清; 徐江涛; 史再峰; 高静
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2013-06-17
Filing date: 2013-06-17
Publication date: 2016-01-20
Anticipated expiration: 2033-06-17
Also published as: CN103346776A

Abstract

The present invention relates to the radiation hardened integrated circuit design field in microelectronics, is the switching capacity buffer that can shield the SEE occurred on inner floating node.When on the non-floating node that SEE occurs in circuit, only can produce the exporting change of transient state, expendable signal error can not be caused.During the technical solution used in the present invention, the switching capacity buffer circuits reinforced is carried out for single particle effect, by sampling switch S1, S2, sampling capacitance C1, C2, comparator 1 and comparator 2, the amplifier 3 of driver output, redundancy section 4 and a two input nand gate NAND2 and inverter INV form.The present invention is mainly used in radiation hardened integrated circuit design.

Description

The switching capacity buffer circuits reinforced is carried out for single particle effect

Technical field

The present invention relates to the radiation hardened integrated circuit design field in microelectronics, specifically, carry out the switching capacity buffer circuits reinforced for single particle effect.

Technical background

Design ap-plication is when the integrated circuit of space environment, and the single particle effect (SingleEventEffect, SEE) that high-energy particle bombardment semiconductor produces is the radiation effect that must consider.Carry out anti-SEE for semiconductor chip to reinforce and can consider from technique and design two aspects.Wherein, based on the radiation hardening method (Radiation-HardnessByDesign, RHBD) designed owing to can realize based on commercial process, thus realizing cost and obtaining in higher circuit performance having more advantage.At present, for the achievement in research of integrated circuit RHBD based on digital circuit.This is mainly due to the discreteness of the processing signals of digital circuit own, makes can be realized by the mode of redundancy more easily the protection of information.But the achievement in research at present for the RHBD method of analog circuit is then rare in bibliographical information.In the application of reality, analog circuit is distributed in the periphery of chip usually, is generally used for realizing signal conversion (as analog-to-digital conversion and digital-to-analogue conversion etc.).The analog circuit nodes flow through for there being electric current, when its be subject to SEE affect time, the amplitude of the voltage jump of generation is main relevant with the size of current flowing through this node with width.For the interference of this class, adjustment size of current and Redundancy Design can play the effect alleviating SEE to a certain extent.But, for the another kind of analog circuit based on switching capacity, because inside may exist the capacitive node of temporary transient floating, therefore, after on the interference charge injection brought out by SEE to these nodes, the output of detonator circuit can there is the mistake of non-transient state.Switching capacity buffer is as a kind of conventional circuit unit, and the SEE of its sampling capacitance node can cause the mistake of output.Therefore, carrying out radiation tolerance design for switching capacity buffer is a significant job.

Summary of the invention

For overcoming the deficiencies in the prior art, the present invention aims to provide, the switching capacity buffer that can shield the SEE occurred on inner floating node.When on the non-floating node that SEE occurs in circuit, only can produce the exporting change of transient state, expendable signal error can not be caused.The technical solution used in the present invention is, the switching capacity buffer circuits reinforced is carried out for single particle effect, by sampling switch S1, S2, sampling capacitance C1, C2, comparator 1 and comparator 2, the amplifier 3 of driver output, redundancy section 4 and a two input nand gate NAND2 and inverter INV form, wherein input signal Vin is connected to the top crown of electric capacity C1 and C2 respectively by switch S 1 and S2, the bottom crown ground connection of C1 and C2, the top crown of C1 and C2 is connected to the grid of N-type MOS transistor M5 and M12 simultaneously respectively, the top crown of C1 is connected to the anode of comparator 1 and the negative terminal of comparator 2 respectively, the negative terminal of comparator 1 is connected to reference level V1, the anode of comparator 2 is connected to reference level V2, the output driving N AND2 of comparator 1 and comparator 2, the output of NAND2 drives inverter INV, the source termination power of N-type MOS transistor M1 and M2, drain terminal is connected with the source of P-type crystal pipe M3 with M4 respectively, the drain terminal of M3 with M4 is connected with the drain terminal of M6 respectively at N-type transistor M5, the source of M5 with M6 is connected with the drain terminal of M8 respectively at N-type transistor M7, the source of M7 with M8 is connected, and be jointly connected to the tail current source that size of current is ISS, the source of P-type crystal pipe M9 is connected to power supply, drain terminal is connected to the source of P-type crystal pipe M11, the drain terminal of M11 is connected with the drain terminal of P-type crystal pipe M10, and be jointly connected to the drain terminal of N-type transistor M12, the source of M12 is connected to the drain terminal of N-type transistor M13 and M14, it is I that the source of M13 is connected to size of current _sSthe tail current source of/2, the source of M14 is connected with the source of M8, and the grid end of M1 with M2 is connected and is connected to the drain terminal of M1, is connected to the source of M10 simultaneously, and the output of NAND2 drives the grid end of M3, M14 and M11, the output of INV drives the grid end of M7, M10 and M13, the grid end ground connection of M4, and the grid end of the M6 grid forming output Vout, M8 that are connected with drain terminal connect power supply, and the grid end of M9 is connected with drain terminal.

The phase mutual edge distance of sampling switch S1 and S2 on chip layout is set to long as far as possible.

The present invention possesses following technique effect:

1. can recover in the interference that the floating stage of sampling capacitance C1 produces for SEE, not make the error level of this node propagate to rear class.

2. the SEE occurring in other circuit nodes only can to exporting the interference producing transient state.

Accompanying drawing explanation

Fig. 1 carries out the switching capacity buffer reinforced for single particle effect.

Embodiment

The present invention is further described below in conjunction with accompanying drawing and instantiation.

As shown in Figure 1, this RHBD switching capacity analogue buffer, by sampling switch S1, S2, sampling capacitance C1, C2, comparator 1 and comparator 2, the amplifier 3 of driver output, redundancy section 4 and a two input nand gate NAND2 and inverter INV form.Wherein the negative terminal of comparator 1 and the anode of comparator 2 access reference level V1 and V2 (V1 < V2) respectively.In this buffer operative process, it is interval that the magnitude of voltage that supposing samples obtains should be in (V1, V2) under normal circumstances all the time.Transistor M1, M2 and M9 mate, M3, M4 and M10, M11 coupling, and M5, M6 and M12 mate, M7, M8 and M13, M14 coupling.The tail current size exporting amplifier 3 is I _sS, the tail current of redundant circuit 4 is I _sS/ 2.

In normal work period, as sampling switch S1 and S2 conducting, the magnitude of voltage of sampling is stored in C1 and C2 top crown respectively.Because sampled voltage is in (V1, V2) interval, therefore comparator 1 and comparator 2 all export high level, then NAND2 output low level, and this level, by conducting M3 and M11, turns off M14 simultaneously; Inverter INV exports high level, and this level, by conducting M7 and M13, turns off M10 simultaneously.By adjustment transistor size, M3, M4, M7 and M8 now can be made all to work in linear zone.At this moment, amplifier 3 will as the work of output amplifier, and redundancy section 4 also has electric current I simultaneously _sS/ 2 flow through.

When sampling switch S1 and S2 disconnects, if the electric charge on C1 is subject to SEE interference, and this node voltage exceeds (V1, V2) scope, then comparator 1 and comparator 2 have one at least by output low level.Now, NAND2 will export high level, cause M3 and M11 to turn off, M14 conducting; INV, by output low level, causes M7 and M13 to turn off, M10 conducting.In the case, originally by the electric current of the branch road of M1, M3, M5 and M7 composition, the branch road consisted of was got back to tail current end I M1, M10, M12 and M14 _sS.Now, the actual voltage exporting C2 top crown of this buffer.Due in sample phase, C1 with C2 has sampled identical magnitude of voltage, and therefore, output can not change.

When sampling switch S1 and S2 disconnects, if SEE betides the top crown of C2, then only can produce interference to the state of redundancy section 4, can not affect and export amplifier 3, and this interference will recover when S1 and S2 conducting starts to sample next voltage; When SEE occurs in other circuit nodes, because node flows through electric current all the time, and the interference of consequent level is made to be transient state, recoverable interference.

When specific implementation, should be noted that between related transistor and coupling between electric capacity (C1 and C2).Meanwhile, as far as possible by layout techniques, zoom out the distance of switch S 1 and S2, because if C1 and C2 is subject to SEE impact simultaneously, then may there is mistake in the work of this circuit.

Claims

1. the switching capacity buffer circuits carrying out reinforcing for single particle effect, it is characterized in that, by sampling switch S1, S2, sampling capacitance C1, C2, first comparator and the second comparator, the discharge circuit of driver output, redundant circuit and a two input nand gate NAND2 and inverter INV form, wherein, transistor M1-M8 and size of current are I _sStail current source form discharge circuit, transistor M9-M14 and size of current are I _sSthe tail current source of/2 forms redundant circuit, the input signal Vin of capacitive buffer circuit is connected to the top crown of electric capacity C1 and C2 respectively by switch S 1 and S2, the bottom crown ground connection of electric capacity C1 and C2, the top crown of electric capacity C1 and C2 is connected to the grid end of N-type MOS transistor M5 and M12 simultaneously respectively, the top crown of electric capacity C1 is connected to the in-phase end of the first comparator and the end of oppisite phase of the second comparator respectively, the end of oppisite phase of the first comparator is connected to reference level V1, the in-phase end of the second comparator is connected to reference level V2, the output of the first comparator and the second comparator drives NAND gate NAND2, the output of NAND gate NAND2 drives inverter INV, the source termination power of N-type MOS transistor M1 and M2, drain terminal is connected with the source of P-type crystal pipe M3 with M4 respectively, the drain terminal of transistor M3 with M4 is connected with the drain terminal of M6 with N-type transistor M5 respectively, the source of transistor M5 with M6 is connected with the drain terminal of M8 with N-type transistor M7 respectively, the source of transistor M7 with M8 is connected, and to be jointly connected to size of current be I _sStail current source, the source of P-type crystal pipe M9 is connected to power supply, drain terminal is connected to the source of P-type crystal pipe M11, the drain terminal of transistor M11 is connected with the drain terminal of P-type crystal pipe M10, and be jointly connected to the drain terminal of N-type transistor M12, the source of transistor M12 is connected to the drain terminal of N-type transistor M13 and M14, and it is I that the source of transistor M13 is connected to size of current _sSthe tail current source of/2, the source of transistor M14 is connected with the source of M8, and the grid end of transistor M1 with M2 is connected and is connected to the drain terminal of M1, is connected to the source of transistor M10 simultaneously, the grid end of output driving transistors M3, M14 and M11 of NAND gate NAND2, the grid end of output driving transistors M7, M10 and M13 of inverter INV, the grid end ground connection of transistor M4, the grid end of transistor M6 is connected with drain terminal and forms the lead-out terminal of capacitive buffer circuit, and the grid end of transistor M8 connects power supply, and the grid end of transistor M9 is connected with drain terminal.

2. the switching capacity buffer circuits carrying out reinforcing for single particle effect according to claim 1, is characterized in that, the phase mutual edge distance of sampling switch S1 and S2 on chip layout is set to long as far as possible.