CN103346776A

CN103346776A - Switched capacitor buffer circuit for strengthening single-event effect

Info

Publication number: CN103346776A
Application number: CN2013102405099A
Authority: CN
Inventors: 姚素英; 李渊清; 徐江涛; 史再峰; 高静
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2013-06-17
Filing date: 2013-06-17
Publication date: 2013-10-09
Anticipated expiration: 2033-06-17
Also published as: CN103346776B

Abstract

The invention relates to the field of design of radiation-resistant integrated circuits in microelectronics, in particular to a switched capacitor buffer capable of shielding the SEE occurring to interior floating nodes. When the SEE occurs to a non-floating node of a circuit, only transient output changing can be generated, and unrecoverable signal errors can not be caused. According to the technical scheme, the switched capacitor buffer circuit for strengthening the single-event effect is composed of sampling switches S1 and S2, sampling capacitors C1 and C2, a comparator 1, a comparator 2, operational amplifier 3 for driving output, a redundant part 4, a binary-input NAND gate 2 and a phase inverter INV. The switched capacitor buffer circuit for strengthening the single-event effect is mainly applied to design the radiation-resistant integrated circuits.

Description

The switching capacity buffer circuits of reinforcing at single particle effect

Technical field

The present invention relates to the radiation hardened integrated circuit design field in the microelectronics, specifically, the switching capacity buffer circuits of reinforcing at single particle effect.

Technical background

When design was applied to the integrated circuit of space environment, (Single Event Effect SEE) was the radiation effect that must consider to the single particle effect that the high-energy particle bombardment semiconductor produces.Carrying out anti-SEE at semiconductor chip reinforces and can consider from technology and two aspects of design.Wherein, (Radiation-Hardness By Design RHBD) owing to can realize based on commercial technology, thereby is realizing having more advantage aspect cost and the higher circuit performance of acquisition based on the radiation hardening method of design.At present, at the achievement in research of integrated circuit RHBD based on digital circuit.This mainly is because the discreteness of the processing signals of digital circuit own, make to the protection of information can be more easily mode by redundancy realize.Yet, at present at the achievement in research of the RHBD method of analog circuit rarely in bibliographical information.In the application of reality, analog circuit is distributed in the periphery of chip usually, is generally used for realizing signal conversion (as analog-to-digital conversion and digital-to-analogue conversion etc.).For the analog circuit nodes that has electric current to flow through, when it was subjected to SEE and influences, the amplitude of the voltage jump of generation was main relevant with the size of current that flows through this node with width.For the interference of this class, adjust size of current and Redundancy Design and can play the effect of alleviating SEE to a certain extent.But based on for the analog circuit of switching capacity, owing to innerly may have temporary transient floating empty capacitive node, therefore, after the interference electric charge that is brought out by SEE was injected on these nodes, the mistake of non-transient state took place in output that can detonator circuit for another kind of.The switching capacity buffer is as a kind of circuit unit commonly used, and the SEE of its sampling capacitance node can cause the mistake of output.Therefore, carrying out the radiation hardening design at the switching capacity buffer is a significant job.

Summary of the invention

For overcoming the deficiencies in the prior art, the present invention aims to provide, the switching capacity buffer that can shield the SEE that occurs on the empty node of internal float.When SEE occurred on the non-floating empty node of circuit, the output that only can produce transient state changed, and can not cause expendable signal error.The technical solution used in the present invention is, the switching capacity buffer circuits of reinforcing at single particle effect, by sampling switch S1, S2, sampling capacitance C1, C2, comparator 1 and comparator 2, drive the amplifier 3 of output, redundancy section 4 and two input nand gate NAND2 and an inverter INV form, wherein input signal Vin is connected to the top crown of capacitor C 1 and C2 respectively by switch S 1 and S2, the bottom crown ground connection of C1 and C2, the top crown of C1 and C2 is connected to the grid of N-type MOS transistor M5 and M12 simultaneously respectively, the top crown of C1 is connected to the anode of comparator 1 and the negative terminal of comparator 2 respectively, the negative terminal of comparator 1 is connected to reference level V1, the anode of comparator 2 is connected to reference level V2, the output driving N AND2 of comparator 1 and comparator 2, the output of NAND2 drives inverter INV, the source termination power of P type MOS transistor M1 and M2, drain terminal links to each other with the source end of P transistor npn npn M3 and M4 respectively, the drain terminal of M3 and M4 links to each other respectively at the drain terminal of N-type transistor M5 and M6, the source end of M5 and M6 links to each other respectively at the drain terminal of N-type transistor M7 and M8, the source end of M7 and M8 links to each other, and be connected to the tail current source that size of current is ISS jointly, the source end of P transistor npn npn M9 is connected to power supply, drain terminal is connected to the source end of P transistor npn npn M11, the drain terminal of M11 links to each other with the drain terminal of P transistor npn npn M10, and be connected to the drain terminal of N-type transistor M12 jointly, the source end of M12 is connected to the drain terminal of N-type transistor M13 and M14, and it is I that the source end of M13 is connected to size of current _SS/ 2 tail current source, the source end of M14 links to each other with the source end of M8, and the grid end of M1 and M2 links to each other and is connected to the drain terminal of M1, is connected to the source end of M10 simultaneously, and the output of NAND2 drives the grid end of M3, M14 and M11; The output of INV drives the grid end of M7, M10 and M13, the grid end ground connection of M4, and the grid end of M6 links to each other with drain terminal and constitutes output Vout, and the grid of M8 connect power supply, and the grid end of M9 links to each other with drain terminal.

Sampling switch S1 is set to long as far as possible with the mutual edge distance mutually of S2 on chip layout.

The present invention possesses following technique effect:

1. can recover at the interference that SEE produced in the floating empty stage of sampling capacitance C1, do not make the error level level propagation backward of this node.

2. the SEE that occurs in other circuit nodes only can be to the interference of output generation transient state.

Description of drawings

The switching capacity buffer that Fig. 1 reinforces at single particle effect.

Embodiment

Further describe the present invention below in conjunction with accompanying drawing and instantiation.

As shown in Figure 1, this RHBD switching capacity analogue buffer, by sampling switch S1, S2, sampling capacitance C1, C2, comparator 1 and comparator 2 drive the amplifier of exporting 3, and redundancy section 4 and two input nand gate NAND2 and an inverter INV form.Wherein the anode of the negative terminal of comparator 1 and comparator 2 inserts reference level V1 and V2 (V1＜V2) respectively.In this buffer course of work, suppose that the magnitude of voltage that sampling obtains under normal circumstances should be in (V1, V2) interval all the time.Transistor M1, M2 and M9 coupling, M3, M4 and M10, M11 coupling, M5, M6 and M12 coupling, M7, M8 and M13, M14 coupling.The tail current size of output amplifier 3 is I _SS, the tail current of redundant circuit 4 is I _SS/ 2.

In normal work period, when sampling switch S1 and S2 conducting, the magnitude of voltage of sampling is stored in C1 and C2 top crown respectively.Since sampled voltage be in (V1, V2) interval, so comparator 1 and comparator 2 all export high level, NAND2 output low level then, this level turn-offs M14 simultaneously with conducting M3 and M11; Inverter INV exports high level, and this level turn-offs M10 simultaneously with conducting M7 and M13.By adjusting transistor size, can make M3, M4, M7 and the M8 of this moment all work in linear zone.At this moment, amplifier 3 will be as the work of output amplifier, and redundancy section 4 also has electric current I simultaneously _SS/ 2 flow through.

When sampling switch S1 and S2 disconnection, disturb if the electric charge on the C1 is subjected to SEE, and this node voltage exceeds, and (then comparator 1 and comparator 2 have one at least with output low level for V1, V2) scope.At this moment, NAND2 will export high level, cause M3 and M11 to turn-off the M14 conducting; INV causes M7 and M13 to turn-off the M10 conducting output low level.In the case, originally pass through the electric current of the branch road of M1, M3, M5 and M7 composition, will get back to tail current end I by the branch road that M1, M10, M12 and M14 form _SSAt this moment, this buffer reality is at the voltage of output C2 top crown.Because in sample phase, C1 has sampled identical magnitude of voltage with C2, therefore, output can not change.

When sampling switch S1 and S2 disconnect, if SEE betides the top crown of C2, then only can produce the state of redundancy section 4 and disturb, can not influence output amplifier 3, and this interference will when beginning to sample next voltage, recover in S1 and S2 conducting; When SEE occurs in other circuit nodes, because node flows through electric current all the time, be transient state, recoverable interference and make consequent level disturb.

When specific implementation, should be noted that between the related transistor and electric capacity (C1 and C2) between coupling.Simultaneously, as far as possible by layout techniques, zoom out the distance of switch S 1 and S2, because if C1 and C2 are subjected to the SEE influence simultaneously, then mistake may appear in the work of this circuit.

Claims

1. switching capacity buffer circuits of reinforcing at single particle effect, it is characterized in that, by sampling switch S1, S2, sampling capacitance C1, C2, first comparator and second comparator, drive the amplifier of output, redundancy section and two input nand gate NAND2 and an inverter INV form; Wherein input signal Vin is connected to the top crown of capacitor C 1 and C2, the bottom crown ground connection of C1 and C2 respectively by switch S 1 and S2; The top crown of C1 and C2 is connected to the grid of N-type MOS transistor M5 and M12 simultaneously respectively; The top crown of C1 is connected to the anode of comparator 1 and the negative terminal of comparator 2 respectively; The negative terminal of comparator 1 is connected to reference level V1, and the anode of comparator 2 is connected to reference level V2; The output driving N AND2 of comparator 1 and comparator 2; The output of NAND2 drives inverter INV; The source termination power of P type MOS transistor M1 and M2, drain terminal link to each other with the source end of P transistor npn npn M3 and M4 respectively; The drain terminal of M3 and M4 links to each other respectively at the drain terminal of N-type transistor M5 and M6; The source end of M5 and M6 links to each other respectively at the drain terminal of N-type transistor M7 and M8; The source end of M7 and M8 links to each other, and to be connected to size of current jointly be I _SSTail current source; The source end of P transistor npn npn M9 is connected to power supply, and drain terminal is connected to the source end of P transistor npn npn M11; The drain terminal of M11 links to each other with the drain terminal of P transistor npn npn M10, and is connected to the drain terminal of N-type transistor M12 jointly; The source end of M12 is connected to the drain terminal of N-type transistor M13 and M14, and it is I that the source end of M13 is connected to size of current _SS/ 2 tail current source; The source end of M14 links to each other with the source end of M8; The grid end of M1 and M2 links to each other and is connected to the drain terminal of M1, is connected to the source end of M10 simultaneously; The output of NAND2 drives the grid end of M3, M14 and M11; The output of INV drives the grid end of M7, M10 and M13; The grid end ground connection of M4, the grid end of M6 link to each other with drain terminal and constitute output Vout; The grid of M8 connect power supply; The grid end of M9 links to each other with drain terminal.

2. the switching capacity buffer circuits of reinforcing at single particle effect according to claim 1, the sampling switch S1 of the switching capacity buffer circuits of reinforcing at single particle effect is set to long as far as possible with the mutual edge distance mutually of S2 on chip layout.