CN103456365A - Shift register unit, shift register and display device - Google Patents
Shift register unit, shift register and display device Download PDFInfo
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- CN103456365A CN103456365A CN2013103908150A CN201310390815A CN103456365A CN 103456365 A CN103456365 A CN 103456365A CN 2013103908150 A CN2013103908150 A CN 2013103908150A CN 201310390815 A CN201310390815 A CN 201310390815A CN 103456365 A CN103456365 A CN 103456365A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention relates to the technical field of display, and in particular relates to a shift register unit, a shift register and a display device. The shift register unit comprises a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor. According to the shift register unit, noise reduction is realized with fewer transistors on the basis of the original signal transfer function, so that output errors which are probably caused by drift of threshold voltage of the transistors, interference of adjacent transistors and the like are effectively suppressed, a narrow bezel of a liquid crystal display is realized, the power consumption of a drive circuit is reduced, the output characteristic of the shift register is further improved, and the service life of the transistors is further prolonged.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of shift register cell, shift register and display device.
Background technology
At present, the TFT-LCD driver mainly comprises gate drivers and data driver, and wherein, gate drivers is added on the grid line of display panels after the clock signal of input is changed by shift register.Gate driver circuit has same process with the formation of TFT and is formed on the LCD panel together with TFT simultaneously.Gate driver circuit comprises having multistage shift register, and every grade all is connected to corresponding gate line with the output gate drive signal.The at different levels of gate driver circuit are connected with each other, start signal inputs to first utmost point at different levels and exports gate drive signal to gate line with order, wherein the input end of prime is connected to the output terminal of upper level, and the output terminal of next stage is connected to the control end of prime.
The gate driver circuit of said structure is set on the right side of LCD panel.Yet, because the interference of the drift of transistor in gate driver circuit self threshold voltage and adjacent transistor may cause shift register signal output error and self life-span to descend.
Therefore, for above deficiency, the invention provides a kind of shift register cell, shift register and display device.
Summary of the invention
The technical problem to be solved in the present invention is to solve the problem that the interference of the drift of transistor self threshold voltage in gate driver circuit and adjacent transistor may cause shift register signal output error and self life-span to descend.
In order to solve the problems of the technologies described above, the invention provides a kind of shift register cell, this shift register cell comprises the first transistor, transistor seconds, the 3rd transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and memory capacitance; Wherein,
The grid of described the first transistor is connected the input signal end with first utmost point, and second utmost point connects upper drawknot point;
The grid of described transistor seconds connects the reset signal end, and first utmost point connects described upper drawknot point, and second utmost point connects the datum line;
The described the 3rd transistorized grid connects described upper drawknot point, and first utmost point connects the first clock signal, and second utmost point connects output signal end;
Described the 5th transistorized grid connects drop-down node, and first utmost point connects described output signal end, and second utmost point connects described datum line;
The described the 6th transistorized grid connects described drop-down node, and first utmost point connects described upper drawknot point, and second utmost point connects described datum line;
Described the 7th transistorized grid is connected the second clock signal with first utmost point, and second utmost point connects described drop-down node;
The described the 8th transistorized grid connects the input signal end, and first utmost point connects described drop-down node, and second utmost point connects described datum line;
First utmost point of described memory capacitance connects described upper drawknot point, and second utmost point connects described output signal end.
Further, also comprise the 4th transistor, the described the 4th transistorized grid connects described upper drawknot point, and first utmost point connects drop-down node, and second utmost point connects described datum line.
Further, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor are N-type TFT transistor.
Further, described datum line is low voltage level.
Further, its control method is as follows:
First stage, the first clock signal is low level, and the second clock signal is high level, and the input signal end is opened the first transistor, and memory capacitance is charged;
Subordinate phase, the first clock signal is high level, and the second clock signal is low level, and the input signal end is low level, and the reset signal end is low level, the first clock signal is opened the 3rd transistor, output signal end output high level;
Phase III, the first clock signal is low level, the second clock signal is high level, the reset signal end is opened transistor seconds, and memory capacitance is discharged by transistor seconds, makes first utmost point of transistor seconds reduce to low level, second clock unblanking the 7th transistor, the the 7th transistorized second noble potential very, make the 5th transistor and the 6th transistor respectively to the first utmost point electric discharge of output signal end and transistor seconds, the output signal end output low level;
Fourth stage, the first clock signal is high level, and the second clock signal is low level, and the input signal end is low level, and the reset signal end is low level, the first transistor and the 3rd transistor all end, the output signal end output low level;
Five-stage, the first clock signal is low level, and the second clock signal is high level, and the input signal end is low level, and the reset signal end is low level, and the first transistor and the 3rd transistor all end, and output signal end is output as low level.
The present invention also provides a kind of shift register, comprises the above-mentioned shift register cell of multi-stage cascade;
Except the first order, the input signal end of other arbitrary grade of shift register cell connects the signal output part of upper level;
Except afterbody, the reset signal end of other arbitrary grade of shift register cell connects the signal output part of next stage.
The present invention also provides a kind of display device, and it comprises above-mentioned shift register.
Technique scheme of the present invention has following advantage: shift register cell of the present invention has been realized noise reduction process with less transistor on the basis of original signal transfer function, not only effectively suppressed the output error that may be caused by the drift of transistor self threshold voltage and the interference of adjacent transistor etc., and realized the narrow frame of liquid crystal display, more reduce the power consumption of driving circuit, further promoted output characteristics and the transistorized serviceable life of shift register.
The accompanying drawing explanation
Fig. 1 is the structural representation of embodiment of the present invention shift register cell;
Fig. 2 is the logical sequence schematic diagram of embodiment of the present invention shift register cell;
Fig. 3 is the structural representation of embodiment of the present invention shift register.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for the present invention is described, but are not used for limiting the scope of the invention.
As shown in Figure 1, the embodiment of the present invention provides a kind of shift register cell, and this shift register cell comprises the first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8 and memory capacitance C1; Wherein,
The grid of described the first transistor M1 is connected input signal end G(N-1 with first utmost point), second utmost point connects upper drawknot point PU;
The grid of described transistor seconds M2 connects reset signal end G(N+1), first utmost point connects described upper drawknot point PU, and second utmost point connects datum line VSS;
The grid of described the 3rd transistor M3 connects described upper drawknot point PU, and first utmost point connects the first clock signal clk, and second utmost point connects output signal end G(N);
The grid of described the 4th transistor M4 connects described upper drawknot point PU, and first utmost point connects drop-down node PD, and second utmost point connects described datum line VSS;
The grid of described the 5th transistor M5 connects drop-down node PD, and first utmost point connects described output signal end G(N), second utmost point connects described datum line VSS;
The grid of described the 6th transistor M6 connects described drop-down node PD, and first utmost point connects described upper drawknot point PU, and second utmost point connects described datum line VSS;
The grid of described the 7th transistor M7 is connected second clock signal CLKB with first utmost point, second utmost point connects described drop-down node PD;
The grid of described the 8th transistor M8 connects input signal end G(N+1), first utmost point connects described drop-down node PD, and second utmost point connects described datum line VSS;
First utmost point of described memory capacitance C1 connects described upper drawknot point PU, and second utmost point connects described output signal end G(N).
Wherein, the first clock signal clk all is connected the IC driving circuit, output signal end G(N with second clock signal CLKB) the connection gate line.
Wherein, upper drawknot point PU is identical with the level of the first transistor M1 second utmost point, and drop-down node PD is identical with the level of the 7th transistor M7 second utmost point.
Described the first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8 are N-type TFT transistor.
It should be noted that, described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor also can be P type TFT transistor.
The above-mentioned shift register cell that the embodiment of the present invention provides, on the basis of existing technology, increased noise-reducing design, effectively suppress the output error that the interference due to the drift of transistor self threshold voltage and adjacent transistor causes, and further promoted output characteristics and the transistorized serviceable life of shift register.
The present invention also provides a kind of and has formed shift register by above-mentioned shift register cell cascade, and it comprises the at different levels above-mentioned shift register cell of cascade.
Wherein, the input signal end of first order shift register cell connects the start signal end, and the reset signal end of first order shift register cell connects the output signal end of the second Ghandler motion bit register unit; The input signal end of afterbody shift register cell connects the output signal end of previous stage shift register cell, and the letter bow end that resets of afterbody shift register cell connects the start signal end; Except the first order and afterbody shift register cell, the input signal end of all the other shift register cells at different levels connects the output signal end of upper level shift register cell, and the reset signal end connects the output signal end of next stage shift register cell.
Particularly, this shift register comprises the M level, wherein M is grid line quantity, wherein, M is positive integer, in figure, Shift Register means as shift register cells at different levels described in above-mentioned as shown in Figure 3, start signal end STV is input to first order shift register cell as input signal, and the order export gate drive signal to gate line, the input signal of N level is provided by the output signal of N-l level, N<M wherein, reset signal is provided by the output signal of N+l level, the reset signal of N level is that start signal provides by the input signal of the first order, that is to say the input signal of start signal one side as first utmost point, on the other hand also as the reset signal of N level.
Below in conjunction with the logical sequence schematic diagram shown in Fig. 2, the N(N in the shift register that the embodiment of the present invention is provided<M, the progression that M is shift register) control method of level shift register cell describes, wherein, the all crystals pipe is the high level conducting, the low level cut-off.
First stage T1: clock signal clk is low level, second clock signal CLKB is high level, prime output signal G(N-1 as input signal) be high level, as the output signal G(N+1 of subordinate of reset signal) be low level, VSS is low level signal.The input signal G(N-1 of high level) make the first transistor M1 conducting and memory capacitance C1 is charged, make the PU point be upgraded to high level, now the gate switch of the 3rd transistor M3 is opened, but because clock signal clk now is low level, the 3rd transistor M3 does not have conducting, output signal end G(N) output low level;
In this stage, due to second clock signal CLKB with as the prime output signal G(N-1 of input signal) be high level, the 4th transistor M4, the 7th transistor M7 and the equal conducting of the 8th transistor M8, the 5th transistor M5 and the 6th transistor M6 are all in cut-off state, PD point current potential is low level, has effectively prevented that the 5th transistor M5 and the 6th transistor M6 from having leakage current to cause memory capacitance C1 undercharge due to the drift of self threshold voltage and the interference of adjacent transistor.
Subordinate phase T2: clock signal clk is high level, and second clock signal CLKB is low level, input signal G(N-1) be low level, reset signal G(N+1) be low level.Now the first transistor M1, in cut-off state, stops the charging to memory capacitance C1, the 3rd transistor M3 conducting, output signal end G(N) the output high level;
In this stage, because clock signal clk and PU point are high level, the 7th transistor M7 and the 8th transistor M8 all end, the gate switch of the 4th transistor M4 keeps ON state, the PD point is put to make an uproar and processes and make it keep electronegative potential, prevented that noise that the 5th transistor M5 and the 6th transistor M6 orders due to PD from causing memory capacitance C1 to leak electricity and finally cause output signal end G(N) output error.
Phase III T3: clock signal clk is low level, and second clock signal CLKB is high level, input signal G(N-1) be low level, reset signal G(N+1) be high level.Now transistor seconds M2 conducting, memory capacitance C1 makes rapidly the PU point reduce to low level by transistor seconds M2 electric discharge, the 3rd transistor M3 cut-off.Because second clock signal CLKB is high level, input signal G(N-1) be low level, the 7th transistor M7 conducting, the 8th transistor M8 cut-off, the PD point is noble potential, make the 5th transistor M5 and the 6th transistor M6 respectively to output terminal G(N) and the PU point carry out rapid discharge and guarantee output signal end G(N) be output as low level, realize reset function;
Fourth stage T4: clock signal clk is high level, second clock signal CLKB low level, input signal G(N-1) be low level, reset signal G(N+1) be low level.Now the first transistor M1 cut-off, the PU point is low level, the 3rd transistor M3 cut-off, output signal end G(N) output low level.
In this stage, if the PU point is due to the adjacent transistor generation noise of crosstalking, the 4th transistor M4 grid is opened, constantly the PD point is discharged, make it keep electronegative potential, prevent that noise that the 5th transistor M5 and the 6th transistor M6 orders due to PD from causing memory capacitance C1 to leak electricity and finally cause output signal end G(N) output error.
Five-stage T5: clock signal clk is low level, second clock signal CLKB high level, input signal G(N-1) be low level, reset signal G(N+1) be low level.Now the first transistor M1 cut-off, the PU point is low level, the 3rd transistor M3 cut-off, output signal end G(N) output low level;
In this stage, because second clock signal CLKB is high level, the 7th transistor M7 conducting, the 8th transistor M8 cut-off, the PD point is noble potential, the 5th transistor M5 and the 6th transistor M6 gate switch are opened PU point and output signal end G(N) put the processing of making an uproar, prevent the mistake output that may cause due to the drift of transistor self threshold voltage and the interference of adjacent transistor etc.
Before the next frame signal arrives, cyclical variation along with the first clock signal clk and second clock signal CLKB, the 4th transistor M4, the 5th transistor M5 and the 6th transistor M6 are constantly to PU point, PD point and output signal end G(N) put the processing of making an uproar, prevent the mistake output that may cause due to the drift of transistor self threshold voltage and the interference of adjacent transistor etc., guarantee the Stability and veracity of output.
In shift register cell of the present invention, except the 7th transistor M7, all the other transistors equal working time within a line signal scanning time is few.In addition, in shift register cell of the present invention, with the first transistor, with the 3rd transistor, compare, all the other transistorized channel widths are much smaller, although therefore the 7th transistor longevity of service within a line signal scanning time is a little, but it is many that power consumption does not increase, whole shift register is realized the significantly reduction of power consumption.
In sum, shift register cell of the present invention has been realized noise reduction process with less transistor on the basis of original signal transfer function, not only effectively suppressed the output error that may be caused by the drift of transistor self threshold voltage and the interference of adjacent transistor etc., and realized the narrow frame of liquid crystal display, more reduce the power consumption of driving circuit, further promoted output characteristics and the transistorized serviceable life of shift register.
The above is only several preferred implementation of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and modification, these improve and modification also should be considered as protection scope of the present invention.
Claims (7)
1. a shift register cell, is characterized in that: comprise the first transistor, transistor seconds, the 3rd transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and memory capacitance; Wherein,
The grid of described the first transistor is connected the input signal end with first utmost point, and second utmost point connects upper drawknot point;
The grid of described transistor seconds connects the reset signal end, and first utmost point connects described upper drawknot point, and second utmost point connects the datum line;
The described the 3rd transistorized grid connects described upper drawknot point, and first utmost point connects the first clock signal, and second utmost point connects output signal end;
Described the 5th transistorized grid connects drop-down node, and first utmost point connects described output signal end, and second utmost point connects described datum line;
The described the 6th transistorized grid connects described drop-down node, and first utmost point connects described upper drawknot point, and second utmost point connects described datum line;
Described the 7th transistorized grid is connected the second clock signal with first utmost point, and second utmost point connects described drop-down node;
The described the 8th transistorized grid connects the input signal end, and first utmost point connects described drop-down node, and second utmost point connects described datum line;
First utmost point of described memory capacitance connects described upper drawknot point, and second utmost point connects described output signal end.
2. shift register cell according to claim 1 is characterized in that: also comprise the 4th transistor, the described the 4th transistorized grid connects described upper drawknot point, and first utmost point connects drop-down node, and second utmost point connects described datum line.
3. shift register cell according to claim 2, it is characterized in that: described the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor are N-type TFT transistor.
4. shift register cell according to claim 2, it is characterized in that: described datum line is low voltage level.
5. according to the described shift register cell of claim 2-4 any one, it is characterized in that: its control method is as follows:
First stage, the first clock signal is low level, and the second clock signal is high level, and the input signal end is opened the first transistor, and memory capacitance is charged;
Subordinate phase, the first clock signal is high level, and the second clock signal is low level, and the input signal end is low level, and the reset signal end is low level, the first clock signal is opened the 3rd transistor, output signal end output high level;
Phase III, the first clock signal is low level, the second clock signal is high level, the reset signal end is opened transistor seconds, and memory capacitance is discharged by transistor seconds, makes first utmost point of transistor seconds reduce to low level, second clock unblanking the 7th transistor, the the 7th transistorized second noble potential very, make the 5th transistor and the 6th transistor respectively to the first utmost point electric discharge of output signal end and transistor seconds, the output signal end output low level;
Fourth stage, the first clock signal is high level, and the second clock signal is low level, and the input signal end is low level, and the reset signal end is low level, the first transistor and the 3rd transistor all end, the output signal end output low level;
Five-stage, the first clock signal is low level, and the second clock signal is high level, and the input signal end is low level, and the reset signal end is low level, and the first transistor and the 3rd transistor all end, and output signal end is output as low level.
6. a shift register is characterized in that: comprise multi-stage cascade as the described shift register cell of claim 1-5 any one;
Except the first order, the input signal end of other arbitrary grade of shift register cell connects the signal output part of upper level;
Except afterbody, the reset signal end of other arbitrary grade of shift register cell connects the signal output part of next stage.
7. a display device, is characterized in that: comprise shift register as claimed in claim 6.
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| CN2013103908150A CN103456365A (en) | 2013-08-30 | 2013-08-30 | Shift register unit, shift register and display device |
| PCT/CN2013/089631 WO2015027628A1 (en) | 2013-08-30 | 2013-12-17 | Shift register unit, shift register and display device |
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| CN104575419A (en) * | 2014-12-04 | 2015-04-29 | 上海天马微电子有限公司 | Shifting register and driving method thereof |
| WO2015184659A1 (en) * | 2014-06-07 | 2015-12-10 | 深圳市华星光电技术有限公司 | Driving circuit and liquid crystal display device |
| CN106531112A (en) * | 2017-01-03 | 2017-03-22 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, shifting register and display apparatus |
| CN107146570A (en) * | 2017-07-17 | 2017-09-08 | 京东方科技集团股份有限公司 | Shift register cell, scan drive circuit, array base palte and display device |
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| CN111816127A (en) * | 2020-07-27 | 2020-10-23 | Oppo广东移动通信有限公司 | GOA unit, driving method thereof, GOA circuit and display panel |
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| CN107146570A (en) * | 2017-07-17 | 2017-09-08 | 京东方科技集团股份有限公司 | Shift register cell, scan drive circuit, array base palte and display device |
| WO2019015336A1 (en) * | 2017-07-17 | 2019-01-24 | 京东方科技集团股份有限公司 | Shift register unit, scan drive circuit, array substrate, display device and drive method |
| US11348500B2 (en) | 2017-07-17 | 2022-05-31 | Chongqing Boe Optoelectronics Technology Co., Ltd. | Shift register unit, scan driving circuit, array substrate, display device, and driving method |
| CN111524450A (en) * | 2020-04-29 | 2020-08-11 | 昆山国显光电有限公司 | Display device, binding impedance detection method thereof and screen crack detection method |
| CN111816127A (en) * | 2020-07-27 | 2020-10-23 | Oppo广东移动通信有限公司 | GOA unit, driving method thereof, GOA circuit and display panel |
| CN111816127B (en) * | 2020-07-27 | 2021-11-16 | Oppo广东移动通信有限公司 | GOA unit, driving method thereof, GOA circuit and display panel |
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| Publication number | Publication date |
|---|---|
| WO2015027628A1 (en) | 2015-03-05 |
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