WO2015027628A1

WO2015027628A1 - Shift register unit, shift register and display device

Info

Publication number: WO2015027628A1
Application number: PCT/CN2013/089631
Authority: WO
Inventors: 张晓洁; 邵贤杰; 李小和; 李红敏; 刘永; 姜清华
Original assignee: 合肥京东方光电科技有限公司; 京东方科技集团股份有限公司
Priority date: 2013-08-30
Filing date: 2013-12-17
Publication date: 2015-03-05
Also published as: CN103456365A

Abstract

The present invention relates to the technical field of displays, and particularly relates to a shift register unit, a shift register and a display device. The shift register unit in the present invention comprises a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor. Noise reduction is achieved by the shift register unit in the present invention using fewer transistors on the basis of the original signal transfer function, so that not only the output errors probably caused by the drift of the threshold voltage of the transistors themselves, and by the interference of the adjacent transistors and the like are effectively suppressed, but also a narrow frame of a liquid crystal display is realized, the power consumption of a driving circuit is reduced as well, and the output characteristic of the shift register and the service life of the transistors are further improved.

Description

The present invention relates to the field of display technologies, and in particular, to a shift register unit, a shift register, and a display device.

Currently, a TFT-LCD driver mainly includes a gate driver and a data driver, wherein the gate driver converts the input clock signal through a shift register and applies it to a gate line of the liquid crystal display panel. The gate driving circuit has the same process as the formation of the TFT and is formed on the LCD panel simultaneously with the TFT. The gate drive circuit includes a shift register having a plurality of stages, each stage being connected to a corresponding gate line to output a gate drive signal. The stages of the gate driving circuit are connected to each other, the start signal is input to the first poles of the stages, and the gate driving signals are sequentially output to the gate lines, wherein the input ends of the front stage are connected to the output ends of the upper stage And the output of the next stage is connected to the control end of the previous stage.

A gate drive circuit of the above configuration is disposed on the right side of the LCD panel. However, due to the drift of the transistor's own threshold voltage and the interference of adjacent transistors in the gate drive circuit, the shift register signal output may be erroneous and its lifetime may be degraded.

Therefore, in view of the above deficiencies, the present invention provides a shift register unit, a shift register and a display device.

The technical problem to be solved by the present invention is to solve the problem that the drift of the threshold voltage of the transistor itself in the gate driving circuit and the interference of adjacent transistors may cause the output of the shift register signal to be erroneous and the lifetime thereof to be lowered.

In order to solve the above technical problem, the present invention provides a shift register unit including a first transistor, a second transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. And storage capacitors;

The gate of the first transistor and the first pole are connected to the input signal end, the second pole is connected to the pull-up node; the gate of the second transistor is connected to the reset signal end, and the first pole is connected to the pull-up node, First Two poles connected to the reference level line;

a gate of the third transistor is connected to the pull-up node, a first pole is connected to the first clock signal, and a second pole is connected to the output signal terminal;

a gate of the fifth transistor is connected to the pull-down node, a first pole is connected to the output signal terminal, and a second pole is connected to the reference level line;

a gate of the sixth transistor is connected to the pull-down node, a first pole is connected to the pull-up node, and a second pole is connected to the reference level line;

The gate of the seventh transistor and the first pole are connected to the second clock signal, and the second pole is connected to the pull-down node;

The gate of the eighth transistor is connected to the input signal terminal, the first pole is connected to the pull-down node, and the second pole is connected to the reference level line;

The first pole of the storage capacitor is connected to the pull-up node, and the second pole is connected to the output signal end. Further, further comprising a fourth transistor, a gate of the fourth transistor is connected to the pull-up node, a first pole is connected to the pull-down node, and a second pole is connected to the reference level line.

Further, the first transistor, the second transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type TFT transistors.

Further, the first transistor, the second transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type TFT transistors.

The reference level line is at a low level.

Further, the control method is as follows:

In the first stage, the first clock signal is low level, the second clock signal is high level, the input signal is high level to turn on the first transistor, and the storage capacitor is charged;

In the second stage, the first clock signal is at a high level, the second clock signal is at a low level, the input signal terminal is at a low level, the reset signal terminal is at a low level, and the first clock signal is turned on a second transistor, and the output signal is The terminal outputs a high level;

In the third stage, the first clock signal is low level, the second clock signal is high level, the reset signal is high level to turn on the second transistor, and the storage capacitor is discharged through the second transistor, so that the first transistor of the second transistor is lowered. Is low, the second clock signal turns on the seventh transistor, and the second transistor is at a second high level, so that the fifth transistor and the sixth transistor respectively output the signal terminal and the second transistor The first pole discharge, the output signal terminal outputs a low level;

In the fourth stage, the first clock signal is at a high level, the second clock signal is at a low level, the input signal terminal is at a low level, the reset signal terminal is at a low level, and the first transistor and the third transistor are both turned off, and the output signal is output. The terminal outputs a low level;

In the fifth stage, the first day clock signal is low level, the second clock signal is high level, the input signal end is low level, the reset signal end is low level, and the first transistor and the third transistor are both turned off. The output signal output is low.

The present invention also provides a shift register comprising a plurality of cascaded shift register units; wherein the input signal terminals of any other stage shift register unit are connected to the upper stage except the first stage shift register unit Signal output

Except for the last stage shift register unit, the reset signal terminal of any other stage shift register unit is connected to the signal output of the next stage.

The input signal terminal of the first stage shift register unit and the reset signal terminal of the last first stage shift register unit are both connected to the start signal terminal.

The present invention also provides a display device including the above shift register.

The above technical solution of the present invention has the following advantages: The shift register unit of the present invention implements noise reduction processing with fewer transistors on the basis of the original signal transmission function, and not only effectively reduces the drift of the threshold voltage of the transistor itself. The output of the adjacent transistor may cause an output error, and the narrow frame of the liquid crystal display is realized, the power consumption of the driving circuit is further reduced, and the output characteristics of the shift register and the service life of the transistor are further improved.

1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;

2 is a logic timing diagram of a shift register unit in accordance with an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention. detailed description

The specific embodiments of the present invention are described in further detail below in conjunction with the drawings and embodiments. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention. As shown in FIG. 1 , an embodiment of the present invention provides a shift register unit, where the shift register unit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor CI; wherein

The first transistor M1 has a gate and a first pole connected to the input signal terminal G (N--1), and a second pole is connected to the pull-up node PU;

The gate of the second transistor M2 is connected to the reset signal terminal G (N l ), the first pole is connected to the pull-up node PU, and the second pole is connected to the reference level line VSS;

The gate of the third transistor M3 is connected to the pull-up node PU, the first pole is connected to the first clock signal CLK, and the second pole is connected to the output signal terminal G(N) _;

The gate of the fourth transistor M4 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the reference level line VSS;

The gate of the fifth transistor M5 is connected to the pull-down node PD, the first pole is connected to the output signal terminal G (N), and the second pole is connected to the reference level line VSS;

The gate of the sixth transistor M6 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the reference level line vss;

The gate of the seventh transistor M7 and the first pole are connected to the second clock signal CLKB, and the second pole is connected to the pull-down node PD;

The gate of the eighth transistor M8 is connected to the input signal terminal G (N+1 ), the first pole is connected to the pull-down node PD, and the second pole is connected to the reference level line VSS;

The first pole of the storage capacitor C1 is connected to the pull-up node PU, and the second pole is connected to the output signal terminal G (N).

The first clock signal CLK and the second clock signal CLKB are both connected to the IC driving circuit, and the output signal terminal G (N) is connected to the gate line.

The pull-up node PU has the same level as the second pole of the first transistor M1, and the pull-down node PD has the same level as the second pole of the seventh transistor M7.

The first transistor M1, the second transistor M2, the second transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all N-type TFT transistors. It should be noted that the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may all be P-type TFT transistors.

The above-mentioned shift register unit provided by the embodiment of the present invention adds a noise reduction design based on the prior art, and effectively suppresses an output error caused by the drift of the threshold voltage of the transistor itself and the interference of adjacent transistors, and The output characteristics of the shift register and the lifetime of the transistor are further improved.

The present invention also provides a shift register formed by cascading the shift register units described above, which includes cascaded stages of the above shift register unit.

Wherein, the input signal end of the first stage shift register unit is connected to the start signal end, and the reset signal end of the first stage shift register unit is connected to the output signal end of the second pole shift register unit; the last stage shift register unit The input signal end is connected to the output signal end of the shift register unit of the previous stage, and the reset signal end of the last stage shift register unit is connected to the start signal end; except for the first stage and the last stage shift register unit, The input signal terminal of the stage shift register unit is connected to the output signal terminal of the shift register unit of the first stage, and the reset signal terminal is connected to the output signal terminal of the shift register unit of the next stage.

Specifically, the shift register includes M stages, where M is the number of gate lines, where M is a positive integer, as shown in FIG. 3, the Shift Register represents the shift register units of the above stages, and the start signal end The STV is input as an input signal to the input signal terminal of the first stage shift register unit, and - the gate drive signal is sequentially output to the gate line, and the input signal of the Nth stage shift register unit is determined by the Nth level The output signal of the shift register unit is provided, and the reset signal is provided by an output signal of the N+1th stage shift register unit, wherein N<M, the reset signal of the Mth stage shift register unit is used by the first stage shift register unit The input signal is the start signal, that is to say the start signal is used as the input signal of the first-pole shift register unit on the one hand and the reset signal of the M-stage shift register unit on the other hand.

The control method of the Nth (N<M, M is the number of stages of the shift register) shift register unit in the shift register provided by the embodiment of the present invention is described below with reference to the logic H-order diagram shown in FIG. 2 . , wherein all transistors are high-level on and low-level off.

The first stage T1: the clock signal CLK is at a low level, and the second clock signal CLKB is at a high level. The front stage output signal G (Ni ) as an input signal is at a high level, the lower stage output signal G (N+I ) as a reset signal is at a low level, and VSS is a low level signal. The high-level input signal G (N--1 ) causes the first transistor M1 to be turned on and charges the storage capacitor C1 to raise the PU point to a high level, at which time the gate of the third transistor M3 is turned on, but due to At this time, the clock signal CLK is at a low level, the third transistor M3 is not turned on, and the output signal terminal G (N) outputs a low level;

In this stage, since the second clock signal CLKB and the pre-stage output signal G (N--1) as the input signal are at a high level, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are both turned on. The fifth transistor M5 and the sixth transistor M6 are both in an off state, and the PD point is at a low level, effectively preventing the fifth transistor M5 and the sixth transistor M6 from being leaked due to drift of the threshold voltage and interference of adjacent transistors. The storage capacitor C1 is not fully charged.

The second stage T2: the clock signal CLK is high level, the second clock signal CLKB is low level, the input signal G (N 1 ) is low level, and the reset signal G (N-f l ) is low level. At this time, the first transistor M1 is in an off state, the charging of the storage capacitor C1 is stopped, the third transistor M3 is turned on, and the output signal terminal G (N ) outputs a high level;

In this stage, since the clock signal CLK and the PU point are at a high level, the second clock signal CLKB and the output signal G (N-1) are at a low level, and the seventh transistor M7 and the eighth transistor M8 are both turned off, fourth The gate switch of the transistor M4 is kept in an on state, and the PD point is subjected to noise cancellation processing and kept at a low level, thereby preventing the fifth transistor M5 and the sixth transistor M6 from leaking due to noise of the PD point, thereby eventually causing an output. Signal terminal G (N) output error.

The third stage T3: The clock signal CLK is low, the second clock signal CLKB is high, the input signal G (N-1) is low, and the reset signal G (N+1) is high. At this time, the second transistor M2 is turned on, and the storage capacitor C1 is discharged through the second transistor M2 to quickly lower the PU point to a low level, and the third transistor Μ3 is turned off. Since the second clock signal CLKB is at a high level, the input signal G (N-1) is at a low level, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, and the PD point is at a high level, so that the fifth transistor M5 is turned off. And the sixth transistor M6 performs fast discharge on the output terminals G (N) and PLI points respectively to ensure that the output signal terminal G (N) outputs a low level to realize a reset function;

The fourth stage T4: the clock signal CLK is at a high level, the second clock signal CLKB is at a low level, the input signal G (N 1 ) is at a low level, and the reset signal G (N+1 ) is at a low level. At this time, the first transistor M1 is turned off, the PU point is low, the third transistor M3 is turned off, and the output signal terminal G (N) is output low. Flat.

In this stage, if the PU point generates noise due to crosstalk of adjacent transistors, the gate of the fourth transistor M4 is turned on, and the PD point is continuously discharged to keep it low, preventing the fifth transistor M5 and the sixth transistor M6 from being PD. The noise of the point causes the storage capacitor C1 to leak and eventually causes the output signal terminal (; (N) output error.

The fifth stage T5: The clock signal CLK is low, the second clock signal CLKB is high level, the input signal G (N-I) is low level, and the reset signal G (N+I) is low level. At this time, the first transistor M1 is turned off, the PU point is low, the third transistor M3 is turned off, and the output signal terminal G (N) is output low;

In this stage, since the second clock signal CLKB is at a high level, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the PD point is at a high level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The PU point and the output signal terminal G (N) perform noise-cancellation processing to prevent erroneous output due to drift of the threshold voltage of the transistor itself and interference of adjacent transistors.

Before the arrival of the next frame signal, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 continuously align the PU point, the PD point, and the output with the periodic change of the first clock signal CLK and the second clock signal CLKB. The signal terminal G (N) performs noise-cancellation processing to prevent erroneous output due to drift of the voltage of the transistor itself and interference of adjacent transistors, thereby ensuring output accuracy and stability.

In the shift register unit of the present invention, except for the seventh transistor M7, the remaining transistors operate for a minimum of one line of signal scanning time. In addition, in the shift register unit of the present invention, the channel widths of the remaining transistors are much smaller than those of the first transistor and the second transistor, so that although the seventh transistor operates for a longer period of time in one line of signal scanning time, However, the power consumption has not increased a lot, and the entire shift register achieves a significant reduction in power consumption.

In summary, the shift register unit of the present invention implements noise reduction processing with fewer transistors on the basis of the original signal transmission function, and not only effectively reduces the threshold voltage drift of the transistor itself and the thousand of adjacent transistors. Interference and other possible output errors, and the narrow frame of the liquid crystal display is realized, the power consumption of the driving circuit is further reduced, and the output characteristics of the shift register are further improved and the above is only a few preferred implementations of the present invention. It should be noted that those skilled in the art can make thousands if without departing from the technical principle of the present invention. Modifications and variations, these modifications and variations should also be considered as protection scope of the present invention.

Claims

1. A shift register unit, characterized by: including a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor; wherein,

The gate electrode and the first electrode of the first transistor are connected to the input signal terminal, and the second electrode is connected to the pull-up node; the gate electrode of the second transistor is connected to the reset signal terminal, and the first electrode is connected to the pull-up node, The second pole is connected to the reference level line;

The gate of the third transistor is connected to the pull-up node, the first electrode is connected to the first clock signal, and the second electrode is connected to the output signal terminal;

The gate of the fifth transistor is connected to the pull-down node, the first electrode is connected to the output signal terminal, and the second electrode is connected to the reference level line;

The gate of the sixth transistor is connected to the pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the reference level.

The gate and first electrode of the seventh transistor are connected to the second clock signal, and the second electrode is connected to the pull-down node;

The gate of the eighth transistor is connected to the input signal terminal, the first electrode is connected to the pull-down node, and the second electrode is connected to the reference level line;

The first pole of the storage capacitor is connected to the pull-up node, and the second pole is connected to the output signal terminal.

2. The shift register unit according to claim 1, characterized in that: it further includes a fourth transistor, the gate of the fourth transistor is connected to the pull-up node, the first electrode is connected to the pull-down node, and the second pole is connected to the reference level line.

3. The shift register unit according to claim 2, characterized in that: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor The transistors are all N-type TFT transistors.

4. The shift register unit according to claim 2, characterized in that: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor The transistors are all P-type TFT transistors.

5. The shift register unit according to claim 2, characterized in that: the reference level line is low.

6. The shift register unit according to any one of claims 2 to 5, characterized in that: its control method is as follows:

In the first stage, the first clock signal is low level, the second clock signal is high level, and the input signal terminal is high level to turn on the first transistor to charge the storage capacitor;

In the second stage, the first clock signal is high level, the second clock signal is low level, the input signal terminal is low level, the reset signal terminal is low level, the first clock signal turns on the third transistor and outputs The signal terminal outputs high level;

In the third stage, the first clock signal is at a low level, the second clock signal is at a high level, the reset signal terminal is at a high level to turn on the second transistor, and the storage capacitor is discharged through the second transistor, causing the second transistor to One pole drops to a low level, the second clock signal turns on the seventh transistor, and the second pole of the seventh transistor reaches a high level, causing the fifth transistor and the sixth transistor to discharge the output signal terminal and the first pole of the second transistor respectively. , the output signal terminal outputs low level;

In the fourth stage, the first clock signal is high level, the second clock signal is low level, the input signal terminal is low level, the reset signal terminal is low level, the first transistor and the second transistor are both turned off, and the output signal terminal Output low level;

In the fifth stage, the first clock signal is low level, the second clock signal is high level, the input signal terminal is low level, the reset signal terminal is low level, the first transistor and the third transistor are both turned off, and the output The signal terminal output is low level.

7. A shift register, characterized in that: it includes a multi-stage cascade of shift register units according to any one of claims 1 to 5;

Except for the first-stage shift register unit, the input signal terminal of any other stage shift register unit is connected to the signal output terminal of the previous stage;

Except for the last stage shift register unit, the reset signal terminal of any other stage shift register unit is connected to the signal output terminal of the next stage.

8. The shift register according to claim 7, characterized in that:

The input signal terminal of the first-stage shift register unit and the reset signal terminal of the last first-stage shift register unit are both connected to the start signal terminal.

9. A display device, characterized by: comprising the shift register as claimed in claim 6.