CN104575419B - A kind of shift register and its driving method - Google Patents
A kind of shift register and its driving method Download PDFInfo
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- CN104575419B CN104575419B CN201410738158.9A CN201410738158A CN104575419B CN 104575419 B CN104575419 B CN 104575419B CN 201410738158 A CN201410738158 A CN 201410738158A CN 104575419 B CN104575419 B CN 104575419B
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Abstract
The invention discloses a kind of shift register and its driving method, shift register, including the shift register circuit of multi-stage cascade, per one-level shift register circuit, including：Main outfan, primary input module, the first output module, the second output module, the node between primary input module and the first output module are primary nodal point；Also include：First reseting module, for the first reset signal being input into according to reset signal input, makes primary nodal point and main outfan be reset to low level；Second reseting module, for receiving the second reset signal of next stage shift-register circuit output, makes primary nodal point and main outfan be reset to low level.First reseting module was realized before input initial signal, by primary nodal point and the voltage amplitude of main outfan, gate drive signal is not affected by the drift of the threshold voltage of thin film transistor (TFT), solve the problems, such as that thin film transistor (TFT) is because the drift of threshold voltage causes display unit abnormal show in prior art.
Description
Technical field
The present invention relates to liquid crystal flat-panel display technology field, more particularly to a kind of shift register and its driving method.
Background technology
Liquid crystal display (LCD) is typically made up of the driving means of display panels and its outside, and driving means are used for
Drive signal is provided for display unit.At present, integrated driving means on a display panel can make the structure of display tighter
Gather, for example, be integrated on display pannel the non-crystalline silicon grid that the pixel cell for display floater provides gate drive signal
Driving means, because amorphous silicon film transistor technology is relatively ripe, uniformity is good, and cost is relatively low, therefore non-crystalline silicon grid
Driving means are widely used in liquid crystal display.
Shift register in non-crystalline silicon driving means, including multiple shifting deposit units, each shifting deposit unit
Shift register circuit is generally made up of multiple thin film transistor (TFT)s, when thin film transistor (TFT) easily makes which in the state of long-term conducting
Threshold voltage changes, referred to as the drift of threshold voltage, and the accumulation of the drift of the threshold voltage fills would generally raster data model
Put the driving to display unit and produce exception, cause the abnormal show of display unit.For example there is the drop-down of drop-down current potential effect
Transistor, because when the row pixel cell of display floater is not driven, drop-down in the gate drive apparatus of the row pixel cell
Transistor will be constantly in conducting state, and the threshold voltage shift of the thin film transistor (TFT) being chronically under conducting state easily makes grid
The output signal exception of electrode driving device.
To sum up, the thin film transistor (TFT) in gate drive apparatus is there is in prior art because the drift of threshold voltage can be to aobvious
Show that the driving of unit produces exception, cause the problem of the abnormal show of display unit.
Content of the invention
The embodiment of the present invention provides a kind of shift register and its driving method, in order to solve grid present in prior art
Thin film transistor (TFT) in electrode driving device is abnormal because the drift of threshold voltage can be produced to the driving of display unit, causes display single
The problem of the abnormal show of unit.
The embodiment of the present invention provides a kind of shift register, including the shift register circuit of multi-stage cascade, shifts per one-level
Register circuit, including：
Main outfan, for output drive signal；
Primary input module, for receiving initial signal；
First output module, is connected between the primary input module and the main outfan, for according to second clock
Signal output high level drive signal, the node between the primary input module and first output module are primary nodal point；
Second output module, is connected with the main outfan, drives letter for exporting low level according to the first clock signal
Number；
Also include：
First reseting module, for the first reset signal being input into according to reset signal input, makes the primary nodal point
Low level is reset to the main outfan；
Wherein, first reseting module includes：First reset transistor M1, the second reset transistor M2；Described first
The grid of reset transistor M1, the grid of the second reset transistor M2 are connected with the reset signal input, described
The first electrode of the first reset transistor M1 is connected with the primary nodal point, the first electrode of the second reset transistor M2 with
The main outfan connection；The second electrode of the first reset transistor M1, second electricity of the second reset transistor M2
Extremely it is connected with low level signal input；
Second reseting module, is connected between the primary nodal point and first reseting module, for receiving next stage
Second reset signal of shift-register circuit output, makes the primary nodal point and the main outfan be reset to low level.
A kind of shift register that above-described embodiment is provided, in every one-level shift register circuit, the first reseting module includes
First reset transistor M1 and the second reset transistor M2 can be realized in the switching transistor to every one-level shift register circuit
Before input initial signal, by primary nodal point and the voltage amplitude of main outfan so that the shift register circuit per one-level is produced
Gate drive signal do not affected by the drift of the threshold voltage of thin film transistor (TFT), it is ensured that the driven of shift register and
The normal display of display unit, relative to prior art, in the case where thin film transistor (TFT) is not increased, solves prior art
Present in thin film transistor (TFT) in gate drive apparatus abnormal because the drift of threshold voltage can be produced to the driving of display unit,
Cause the problem of the abnormal show of display unit.Additionally, in per one-level shift register circuit, the first reseting module includes first
Reset transistor M1 and the second reset transistor M2, additionally it is possible to realize the outfan output height of the shift register circuit when next stage
Level drive signal and to shift register circuit feedback reset signal when, the voltage of primary nodal point and main outfan is multiple
Position, so that this grade of shift register circuit is no longer to the grid output high level drive signal of display unit.
Further, first reseting module also includes：3rd reset transistor M0；
The grid of the 3rd reset transistor M0, first electrode connect the reset signal input, and second electrode connects
Connect grid, the grid of the second reset transistor M2 of the first reset transistor M1.The embodiment is in above-described embodiment
On the basis of increased the thin film transistor (TFT) M0 used as diode, for receiving the first reset signal and multiple according to first
The normal startup and closing of first reseting module of high and low Automatic level control of position signal.That is when the first reset signal is height
Level, or when receiving the first reset signal of high level, thin film transistor (TFT) M0 is used as diode current flow so that first resets
Transistor M1, the second reset transistor M2 are turned on, and are realized initial in the switching transistor input to every one-level shift register circuit
Before signal, by primary nodal point and the voltage amplitude of main outfan so that the grid that the shift register circuit per one-level is produced drives
Dynamic signal is not affected by the drift of the threshold voltage of thin film transistor (TFT), it is ensured that the driven of shift register and display unit
Normal display；First reset signal be low level, or high level the first reset signal disappear when, thin film transistor (TFT) M0 cut
Only so that the first reset transistor M1, the second reset transistor M2 end so that the first reseting module reset terminate so as to
Start receives input initial signal per the switching transistor of one-level shift register circuit, be that display unit is produced and exports grid drive
Dynamic signal.
Further, second reseting module includes the 4th reset transistor M7；
The grid of the 4th reset transistor M7 is connected with the main outfan of next stage shift-register circuit, the first electricity
Pole is connected with the first electrode of the first reset transistor M1, and second electrode is connected with low level control signal input.
Further, the primary input module includes switching transistor M3；
The grid of switching transistor M3 is connected with initial signal input, and first electrode is defeated with high-level control signal
Enter end connection, second electrode is connected with the primary nodal point.
Further, first output module includes the first electric capacity C1 and the M4 that pulls up transistor；
Wherein, the first electric capacity C1 is connected between the primary nodal point and the main outfan, the upper crystal pulling
The grid of pipe M4 is connected with the primary nodal point, and first electrode is connected with second clock signal input part, second electrode with described
Main outfan connection.
Further, second output module includes transistor M5；
The grid of the transistor M5 is connected with the first clock signal input terminal, and first electrode is connected with the main outfan
Connect, second electrode is connected with low level signal input.
Further, also accessing between the primary nodal point and first output module has drop-down module；Under described
Drawing-die block includes：Pull-down transistor M6 and the second electric capacity C2；
Wherein, the grid of the pull-down transistor M6 is connected with the primary nodal point, first electrode and second electric capacity
The first end connection of C2, second electrode is connected with low level signal input, second end of the second electric capacity C2 and described the
The second clock signal input part connection of one output module.
Based on a kind of shift register that above-described embodiment is provided, a kind of shift register is embodiments provided
Per the driving method of one-level shift register circuit, the method includes：
Every one-level shift register circuit includes the first reseting stage；
In the first reseting stage, the first reset signal is input in the reset signal input, cause described first to reset
First reset transistor M1 of module, the second reset transistor M2 are turned on, the electricity of the primary nodal point and the main outfan
Pressure is reset to low level.
In above-described embodiment, in the first reseting stage, in the first reset letter of the high level of reset signal input input
Number, the normal startup of the first reseting module is triggered, is realized after making the first reset transistor M1 and the second reset transistor M2 conductings
Before the switching transistor input initial signal to every one-level shift register circuit, by primary nodal point and the voltage of main outfan
Reset so that the gate drive signal that the shift register circuit per one-level is produced does not receive drifting about for the threshold voltage of thin film transistor (TFT)
Impact, it is ensured that the normal display of the driven of shift register and display unit.Relative to prior art, do not increasing
In the case of thin film transistor (TFT), the thin film transistor (TFT) present in prior art in gate drive apparatus is solved because of threshold voltage
Drift the driving of display unit can be produced abnormal, cause the problem of the abnormal show of display unit.
Further, in the first reseting stage, the first reset signal is input in the reset signal input, cause described
3rd reset transistor M0 of the first reseting module, the first reset transistor M1, the second reset transistor M2 conductings, cause described
The voltage amplitude of primary nodal point and the main outfan is low level.
In above-described embodiment, in the first reseting stage, in the first reset letter of the high level of reset signal input input
Number, make to turn on as the thin film transistor (TFT) M0 that diode is used, trigger the normal startup of the first reseting module, make the first reset brilliant
Realize after body pipe M1 and the second reset transistor M2 conductings initial in the switching transistor input to every one-level shift register circuit
Before signal, by primary nodal point and the voltage amplitude of main outfan so that the grid that the shift register circuit per one-level is produced drives
Dynamic signal is not affected by the drift of the threshold voltage of thin film transistor (TFT), it is ensured that the driven of shift register and display unit
Normal display.
Further, every one-level shift register circuit also includes:Level signal generation phase, low level drive signal
Output stage, high level drive signal output stage, the second reseting stage；
In level signal generation phase, initial signal is input at the primary input end, cause the primary nodal point for high electricity
Flat, the grid of the first reset transistor M1 and the second reset transistor M2 of first reseting module is low level；
The stage is exported in low level drive signal, in the first clock of the first clock signal input terminal input high level
Signal, causes the second output module to export low level drive signal to the main outfan；
The stage is exported in high level drive signal, in the second clock of the second clock signal input part input high level
Signal, causes the first output module to export high level drive signal to the main outfan；
In the second reseting stage, second reseting module receives the main outfan output of next stage shift-register circuit
The second reset signal of high level, cause the primary nodal point to be reset to low level, the first reset of first reseting module
The second clock signal of the grid input high level of transistor M1 and the second reset transistor M2, causes the main outfan to reset
For low level.In above-described embodiment, in the second reseting stage, the second reseting module receives the master of next stage shift-register circuit
Second reset signal of high level of outfan output, the second reseting module of triggering start, and make in every one-level shift register circuit the
The first reset transistor M1 and the second reset transistor M2 that one reseting module includes, realize the shift register circuit when next stage
Outfan output high level drive signal and to shift register circuit feedback reset signal when, will primary nodal point and master defeated
Go out the voltage amplitude at end, so that this grade of shift register circuit is no longer to the grid output high level drive signal of display unit.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to making needed for embodiment description
Accompanying drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, without having to pay creative labor, can be with according to these attached+- figure acquisitions
Other accompanying drawings.
Fig. 1 is a kind of circuit diagram of shift register circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of circuit diagram of every one-level shift register circuit of shift register provided in an embodiment of the present invention；
Fig. 3 is a kind of circuit diagram of every one-level shift register circuit of shift register provided in an embodiment of the present invention；
Fig. 4 is a kind of structural representation of shift register provided in an embodiment of the present invention；
Fig. 5 is a kind of shift register working timing figure provided in an embodiment of the present invention.
Specific embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with accompanying drawing the present invention is made into
One step ground is described in detail, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole enforcement
Example.Based on the design concept of the embodiment of the present invention, those of ordinary skill in the art are led under the premise of creative work is not made
Cross the type to thin film transistor (TFT) and the protection that all other embodiment that mode obtained should also fall into the present invention such as be replaced
Within the scope of.
In order to solve the thin film transistor (TFT) present in prior art in gate drive apparatus because of the drift meeting of threshold voltage
Exception is produced to the driving of display unit, causes the problem of the abnormal show of display unit, inventor to propose, by each shifting
Realized before shifting deposit unit produces drive signal as reseting module comprising multiple thin film transistor (TFT)s in the deposit unit of position
By the grid potential of thin film transistor (TFT) outfan and thin film transistor (TFT) again set, so that gate drive apparatus are to display unit
The drive signal of output is not affected by the drift of thin film transistor (TFT) threshold voltage, referring specifically to embodiment 1.
Embodiment 1
A kind of circuit diagram of shift register circuit as shown in Figure 1, which includes 9 thin film transistor (TFT)s, 2 electric capacity C1 and
C2, wherein, reseting module includes two thin film transistor (TFT)s M1 and M2, and switching thin-film transistor M3, for output drive signal
Thin film transistor (TFT) M4 and M5, for the thin film transistor (TFT) M6 of drop-down current potential, M7, M8, M9.Wherein primary nodal point be P, secondary nodal point
For Q, export based on Gout, primary input end STP, for being input into initial signal, Gn+1 is next stage shift register circuit outfan
The input of the signal of feedback, VGL are low level signal source, and reset signal Reset input, the first clock signal clk are input into
End, second clock signal CLKB inputs, wherein, the first clock signal clk and second clock signal CLKB are anti-phase.Such as Fig. 1 institutes
The shift register circuit for showing produces the driving process of drive signal：
First stage, before the initial signal of STP ends input high level, the Reset signals of input high level, thin film are brilliant
Body pipe M1 and M2 are turned on, and cause P points and main outfan Gout to be reset to low level；
Second stage, in the initial signal of primary input end STP input high levels, it is high level, M4 to cause M3 conductings, P points
Conducting, because P points are high level, causes pull-down thin film M6 to turn on, and Q points are connected with low level signal source, at the first half
In the clock cycle, the first clock signal clk of input high level causes Gout output low level drive signals, in the second half clock weeks
In phase, the second clock signal CLKB of input high level makes Gout export high level drive signal；
Phase III, after Gout exports the drive signal of a clock cycle to display unit, Gn+1 inputs are defeated
Enter the feedback signal of high level, cause thin film transistor (TFT) M7 to turn on, P points are connected with low level signal source, and P points are changed into low level,
Pull-down thin film M6 is caused to be ended, Q points are hanging (not being connected with low level signal source VGL), the second clock of high level
Signal CLKB makes Q points for high level by C2, and thin film transistor (TFT) M8 and M9 are turned on, and cause P points and Gout points and low level signal
Source VGL connects, and makes the main outfans of Gout no longer export gate drive signal to display unit in following clock cycle.
To sum up, shift register circuit as shown in Figure 1, by increasing reseting module, in primary input end STP input high levels
Initial signal before by the current potential set of main for Gout outfan be low level, gate drive apparatus is exported to display unit
Drive signal is not affected by the drift of thin film transistor (TFT) threshold voltage.But the reset of shift register circuit as shown in Figure 1
Module is made up of two thin film transistor (TFT)s M1 and M2, and two for newly increasing thin film transistor (TFT) and its wire frame can take larger sky
Between, it is unfavorable for the narrow frame and lightness of liquid crystal display.
In order to obtain more excellent embodiment, of the invention on the basis of shift register circuit as shown in Figure 1, by above-mentioned side
Case is improved and extends, and the thin film transistor (TFT) M1 and M2 of shift register circuit as shown in Figure 1 is removed, by reset signal
Reset inputs are accessed between thin film transistor (TFT) M8 and M9, are controlled thin film transistor (TFT) M8 and M9 by Reset reset signals and are existed
Before the initial signal of primary input end STP input high levels by the current potential set of main for Gout outfan be low level, make grid drive
Dynamic device is not affected by the drift of thin film transistor (TFT) threshold voltage to the drive signal that display unit is exported, and solves existing skill
Thin film transistor (TFT) present in art in gate drive apparatus can driving to display unit because of the drift of threshold voltage ' produce different
Often, cause the problem of the abnormal show of display unit.
The thin film transistor (TFT) M1 and M2 of shift register circuit as shown in Figure 1 are removed by the embodiment of the present invention, save shifting
Taking up room for bit register, is conducive to the narrow frame and lightness of liquid crystal display.
Additionally, the above-mentioned improvement of the embodiment of the present invention so that thin film transistor (TFT) M8 and M9 are in the first stage and the phase III
The effect of drop-down current potential has all been played, so as to improve the utilization rate of thin film transistor (TFT) M8 and M9.
Below in conjunction with the accompanying drawings to a kind of shift register provided in an embodiment of the present invention and each in shift register
Level shift register circuit is described in detail.
Embodiment 2
Provided in an embodiment of the present invention a kind of shift register as shown in Figure 2, the shift register include multi-stage cascade
Shift register circuit, per one-level shift register circuit, including：
Main outfan Gout, for output drive signal, including high level drive signal and low level drive signal；
Primary input module 201, for receiving initial signal STP；
First output module 202, is connected between the primary input module 201 and the main outfan Gout, for root
According to second clock signal output high level drive signal, between the primary input module 201 and first output module 202
Node is primary nodal point P points；
Second output module 203, is connected with the main outfan Gout, for exporting low level according to the first clock signal
Drive signal；
Also include：First reseting module 204, for the first reset signal RESET being input into according to reset signal input,
The primary nodal point P and the main outfan Gout is made to be reset to low level；Wherein, first reseting module 204 includes：The
One reset transistor M1, the second reset transistor M2；The grid of the first reset transistor M1, second reset transistor
The grid of M2 is connected with the reset signal input, the first electrode of the first reset transistor M1 and the first segment
Point connection, the first electrode of the second reset transistor M2 are connected with the main outfan Gout；The first reset crystal
The second electrode of pipe M1, the second electrode of the second reset transistor M2 are connected with low level signal VGL inputs；
Second reseting module 205, is connected between the primary nodal point P and first reseting module 204, for receiving
Second reset signal Gn+1 of next stage shift-register circuit output, makes the primary nodal point P and main outfan Gout
It is reset to low level.
In above-described embodiment, CLK clock signal of first clock signal for high level, second clock signal are high level
CLKB clock signals, second clock signal are the inverting clock signal of the first clock signal, the first clock signal and second clock
The cycle of signal is half clock cycle.
Preferably, in circuit as shown in Figure 2, the primary input module 201 includes switching transistor M3；The switch
The grid of transistor M3 is connected with initial signal input, and first electrode is connected with high-level control signal DIR1 input, the
Two electrodes are connected with the primary nodal point P.
First output module 202 includes the first electric capacity C1 and the M4 that pulls up transistor；Wherein, the first electric capacity C1 connects
It is connected between the primary nodal point P and the main outfan Gout, the grid of the M4 that pulls up transistor and the primary nodal point P
Connection, first electrode are connected with second clock signal input part, and second electrode is connected with the main outfan Gout.
Second output module 203 includes transistor M5；The grid of the transistor M5 and the first clock signal input
End connection, first electrode are connected with the main outfan Gout, and second electrode is connected with low level signal VGL inputs.
Second reseting module 205 includes the 4th reset transistor M7；The grid of the 4th reset transistor M7 with
The main outfan Gout connections of next stage shift-register circuit, first electrode are electric with the first of the first reset transistor M1
Pole connects, and second electrode is connected with low level control signal DIR2 input.
Also accessing between the primary nodal point P and first output module 202 has drop-down module 206；Described drop-down
Module 206 includes：Pull-down transistor M6 and the second electric capacity C2；Wherein, the grid of the pull-down transistor M6 and the first segment
Point P connects, and first electrode is connected with the first end of the second electric capacity C2, and second electrode is connected with low level signal VGL inputs
Connect, second end of the second electric capacity C2 is connected with the second clock signal input part of first output module 202.
A kind of shift register that above-described embodiment is provided, in every one-level shift register circuit, the first reseting module includes
First reset transistor M1 and the second reset transistor M2 can be realized in the switching transistor to every one-level shift register circuit
Before input initial signal, by primary nodal point and the voltage amplitude of main outfan so that the shift register circuit per one-level is produced
Gate drive signal do not affected by the drift of the threshold voltage of thin film transistor (TFT), it is ensured that the driven of shift register and
The normal display of display unit, relative to prior art, in the case where thin film transistor (TFT) is not increased, solves prior art
Present in thin film transistor (TFT) in gate drive apparatus abnormal because the drift of threshold voltage can be produced to the driving of display unit,
Cause the problem of the abnormal show of display unit.Additionally, in per one-level shift register circuit, the first reseting module includes first
Reset transistor M1 and the second reset transistor M2, additionally it is possible to realize the outfan output height of the shift register circuit when next stage
Level drive signal and to shift register circuit feedback reset signal when, the voltage of primary nodal point and main outfan is multiple
Position, so that this grade of shift register circuit is no longer to the grid output high level drive signal of display unit.
Embodiment 3
A kind of shift register a kind of provided in an embodiment of the present invention as shown in Figure 3, the shift register includes multistage
The shift register circuit of cascade, is on the basis of shift register circuit as shown in Figure 2, the per one-level shift register circuit
A thin film transistor (TFT) M0 is increased in one reseting module, as shown in figure 3, the shift register circuit includes：Main outfan Gout,
For output drive signal, including high level drive signal and low level drive signal；
Primary input module 201, for receiving initial signal STP；
First output module 202, is connected between the primary input module 201 and the main outfan Gout, for root
According to second clock signal output high level drive signal, between the primary input module 201 and first output module 202
Node is primary nodal point P points；
Second output module 203, is connected with the main outfan Gout, for exporting low level according to the first clock signal
Drive signal；
First reseting module 204, for the first reset signal RESET being input into according to reset signal input, makes described
Primary nodal point P and the main outfan Gout are reset to low level；Wherein, first reseting module 204 includes：First resets
Transistor M1, the second reset transistor M2, the 3rd reset transistor M0；The grid of the 3rd reset transistor M0, the first electricity
Pole connects the reset signal RESET input, second electrode connect the grid of the first reset transistor M1, described second
The grid of reset transistor M2；The first electrode of the first reset transistor M1 is connected with the primary nodal point P, and described second
The first electrode of reset transistor M2 is connected with the main outfan Gout；The second electrode of the first reset transistor M1,
The second electrode of the second reset transistor M2 is connected with low level signal VGL inputs；
Second reseting module 205, is connected between the primary nodal point P and first reseting module 204, for receiving
Second reset signal Gn+1 of next stage shift-register circuit output, makes the primary nodal point P and main outfan Gout
It is reset to low level.
In above-described embodiment, CLK clock signal of first clock signal for high level, second clock signal are high level
CLKB clock signals, second clock signal are the inverting clock signal of the first clock signal, the first clock signal and second clock
The cycle of signal is half clock cycle.
Preferably, in circuit as shown in Figure 3, the primary input module 201 includes switching transistor M3；The switch
The grid of transistor M3 is connected with initial signal STP input, and first electrode is connected with high-level control signal DIR1 input,
Second electrode is connected with the primary nodal point P.
First output module 202 includes the first electric capacity C1 and the M4 that pulls up transistor；Wherein, the first electric capacity C1 connects
It is connected between the primary nodal point P and the main outfan Gout, the grid of the M4 that pulls up transistor and the primary nodal point P
Connection, first electrode are connected with second clock signal input part, and second electrode is connected with the main outfan Gout.
Second output module 203 includes transistor M5；The grid of the transistor M5 and the first clock signal input
End connection, first electrode are connected with the main outfan Gout, and second electrode is connected with low level signal VGL inputs.
Second reseting module 205 includes the 4th reset transistor M7；The grid of the 4th reset transistor M7 with
The main outfan Gout connections of next stage shift-register circuit, first electrode are electric with the first of the first reset transistor M1
Pole connects, and second electrode is connected with low level control signal DIR2 input.
Also accessing between the primary nodal point P and first output module 202 has drop-down module 206；Described drop-down
Module 206 includes：Pull-down transistor M6 and the second electric capacity C2；Wherein, the grid of the pull-down transistor M6 and the first segment
Point P connects, and first electrode is connected with the first end of the second electric capacity C2, and second electrode is connected with low level signal VGL inputs
Connect, second end of the second electric capacity C2 is connected with the second clock signal input part of first output module 202.
The embodiment increased the thin film transistor (TFT) M0 used as diode on the basis of above-described embodiment, for connecing
Receive the first reset signal, and the normal startup and closing according to first reseting module of high and low Automatic level control of the first reset signal.
That is when the first reset signal is high level, or when receiving the first reset signal of high level, thin film transistor (TFT) M0
As diode current flow so that the first reset transistor M1, the second reset transistor M2 are turned on, realize posting to the displacement of every one-level
Before depositing the switching transistor input initial signal of circuit, by primary nodal point and the voltage amplitude of main outfan so that per one-level
Shift register circuit produce gate drive signal do not affected by the drift of the threshold voltage of thin film transistor (TFT), it is ensured that shift
The driven of depositor and the normal display of display unit；First reset signal is low level, or the first of high level is again
During the blackout of position, thin film transistor (TFT) M0 ends so that the first reset transistor M1, the second reset transistor M2 end so that
First reseting module resets and terminates, so as to start receives input to the switching transistor of every one-level shift register circuit initially believe
Number, it is that display unit is produced and exports gate drive signal.
Embodiment 4
Based on embodiment 2 and embodiment 3, a kind of structure of shift register is embodiments provided, such as Fig. 4 institutes
Show.
Shift register includes the shift register circuit of multi-stage cascade, produces raster data model letter per one-level shift register circuit
Number carry out the display of control display unit, aobvious equivalent to the drive signal control of the main outfan output of one-level shift-register circuit
Show the unlatching of the grid of unit one-row pixels unit.In the shift register 401 shown in Fig. 4, first order shift register circuit
Primary input end IN (grid of switching transistor M3) receive initial signal STP, the primary input end of (n+1)th grade of shift register circuit
IN is connected with the main outfan Gout of n-th grade of shift register circuit so that the output signal control per one-level shift register circuit
The unlatching of the primary input module of its next stage shift register circuit, for example, the primary input end IN of the 2nd grade of shift register circuit and
The main outfan Gout connections of 1 grade of shift register circuit, make output signal Gout (1) of the 1st grade of shift register circuit control the 2nd
The unlatching of the primary input module of level shift register circuit.The main outfan Gout of (n+1)th grade of shift register circuit and n-th grade of displacement
The second reset signal input Gn+1 connections of register circuit so that the output signal per one-level shift register circuit is controlled thereon
The unlatching of the second reseting module of one-level shift register circuit, for example, the main outfan Gout of the 2nd grade of shift register circuit and
The second reset signal input G2 connections of 1 grade of shift register circuit so that the output signal control of the 2nd grade of shift register circuit
The unlatching of the second reseting module of the 1st grade of shift register circuit；The second reset signal input of afterbody shift register circuit
End is connected with " END " signal source, for receiving " END " signal, controls the second reseting module of afterbody shift register circuit
Unlatching.Wherein, n is the positive integer more than or equal to 1.
Additionally, the shift register of the embodiment of the present invention should also include the shifting of the shift register circuit and even level of odd level
Position register circuit, in order to make it easy to understand, only giving the sketch of shift register structure in Fig. 4, the structure of shift register is thin
Root section determines according to the detail of device.Per one-level shift register circuit except with the first clock signal clk, second clock signal
CLKB connection outside, should also with low level VGL signal source, high level DIR1 control signals source, low level control DIR2 signal sources,
First reset RESET signal source connects, and omits the connection of above-mentioned signal in Fig. 4.
Embodiment 5
Based on a kind of shift register that above-described embodiment 2 is provided, and a kind of shift register work as shown in Figure 5
Sequential chart, embodiments provides a kind of driving method of every one-level shift register circuit of shift register, the method
Including：
First reseting stage, level signal generation phase, low level drive signal output stage, high level drive signal are defeated
Go out stage, the second reseting stage；
In the first reseting stage, the first reset signal RESET is input in the reset signal input, causes described first
First reset transistor M1 of reseting module 204, the second reset transistor M2 are turned on, and the primary nodal point P and the master are defeated
The voltage amplitude for going out to hold Gout be low level, i.e. primary nodal point P and the main outfan Gout with low level VGL signal source
Connection.Wherein, if the first reset transistor M1, the second reset transistor M2 are N-type metal-oxide-semiconductor, the input of the first reseting stage
First reset signal RESET is high level.The present embodiment so that all thin film transistor (TFT)s are N-type metal-oxide-semiconductor as an example, to
Lower each driving stage illustrates.
In level signal generation phase, initial signal is input at the primary input end, cause the primary nodal point P for high electricity
Flat, the grid of the first reset transistor M1 and the second reset transistor M2 of first reseting module is low level；Wherein, if
Shift register circuit is first order shift register circuit, then initial signal STP is original trigger signal, if shift register circuit is
The later shift register circuit in the second level or the second level, then initial signal is the height of upper level shift register circuit outfan output
Level signal.
Specifically, in level signal generation phase, because of the input of high level initial signal, primary nodal point P is made for high level,
Switching transistor M3 is caused to turn on, high-level control signal DIR1 of high-level control signal input input causes described opening
Close transistor M3 first electrode be high level, described pull up transistor M4 conducting, the pull-down transistor M6 conducting, described under
The conducting of pull transistor M6 causes the grid of the first reset transistor M1 and the second reset transistor M2 of first reseting module
Extremely low level, i.e. the first reset transistor M1 and the second reset transistor M2 are connected with low level VGL signal source.
The stage is exported in low level drive signal, in the first clock of the first clock signal input terminal input high level
Signal CLK, causes the second output module 203 to export low level drive signal to the main outfan Gout；
Specifically, in the first clock signal clk of the first clock signal input terminal input high level, described second
First clock signal clk B of clock signal input terminal input low level, causes the transistor M5 of second output module 203
Turn on, make the main outfan Gout export low level gate drive signal, i.e., main outfan Gout and low level VGL signal
Source connects.
The stage is exported in high level drive signal, in the second clock of the second clock signal input part input high level
Signal CLKB, causes the first output module 201 to export high level drive signal to the main outfan Gout；
Specifically, in the first clock signal clk of the first clock signal input terminal input low level, cause second defeated
Go out the transistor M5 cut-offs of module 203, in the second clock signal CLKB of the second clock signal input part input high level,
The main outfan Gout is caused to export the gate drive signal of high level.
In the second reseting stage, second reseting module 205 receives the main outfan of next stage shift-register circuit
Second reset signal Gn+1 of high level of output, causes the primary nodal point P to be reset to low level, first reseting module
The second clock signal CLKB of the grid input high level of 204 the first reset transistor M1 and the second reset transistor M2, causes
The main outfan Gout is made to be reset to low level；
Specifically, the grid of the 4th reset transistor M7 of second reseting module 205 receives next stage shift LD
Second reset signal Gn+1 of high level of the main outfan output of device circuit, causes the 4th reset transistor M7 to turn on, and the 4th is multiple
The conducting of bit transistor M7 connects low level control signal DIR2 of low level control signal input input and primary nodal point P
Connect, make primary nodal point P be reset to low level, cause the pull-down transistor M6 cut-offs, the second clock signal CLKB of high level
Through the grid that the second electric capacity C2 transmits the first reset transistor M1 and the second reset transistor M2 to the first reseting module 204
Pole, auxiliary reset module make the first reset transistor M1 and the second reset transistor M2 conductings, the first reset transistor M1 and the
The conducting of two reset transistor M2 causes Gout to be reset to low level, i.e., main outfan Gout is connected with low level VGL signal source.
In above-described embodiment, in the first reseting stage, in the first reset letter of the high level of reset signal input input
Number, the normal startup of the first reseting module is triggered, is realized after making the first reset transistor M1 and the second reset transistor M2 conductings
Before the switching transistor input initial signal to every one-level shift register circuit, by primary nodal point and the voltage of main outfan
Reset so that the gate drive signal that the shift register circuit per one-level is produced does not receive drifting about for the threshold voltage of thin film transistor (TFT)
Impact, it is ensured that the normal display of the driven of shift register and display unit.Relative to prior art, do not increasing
In the case of thin film transistor (TFT), the thin film transistor (TFT) present in prior art in gate drive apparatus is solved because of threshold voltage
Drift the driving of display unit can be produced abnormal, cause the problem of the abnormal show of display unit.
In above-described embodiment, in the second reseting stage, the second reseting module receives the master of next stage shift-register circuit
Second reset signal of high level of outfan output, the second reseting module of triggering start, and make in every one-level shift register circuit the
The first reset transistor M1 and the second reset transistor M2 that one reseting module includes, realize the shift register circuit when next stage
Outfan output high level drive signal and to shift register circuit feedback reset signal when, will primary nodal point and master defeated
Go out the voltage amplitude at end, so that this grade of shift register circuit is no longer to the grid output high level drive signal of display unit.
Embodiment 6
Based on a kind of shift register that above-described embodiment 3 is provided, and a kind of shift register work as shown in Figure 5
Sequential chart, embodiments provides a kind of driving method of every one-level shift register circuit of shift register, the method
Including：
First reseting stage, level signal generation phase, low level drive signal output stage, high level drive signal are defeated
Go out stage, the second reseting stage；
Preferably, in the first reseting stage, the first reset signal RESET is input in the reset signal input, is caused
3rd reset transistor M0 of first reseting module 204, the first reset transistor M1, the second reset transistor M2 conductings,
The voltage amplitude for causing the primary nodal point P and the main outfan is low level；
Specifically, in the first reseting stage, in the first reset signal of the reset signal input input high level
RESET, causes the 3rd reset transistor M0 of first reseting module 204 as diode current flow, the 3rd reset transistor
The conducting of M0 makes high level reset signal transmit to the first reset transistor M1, the grid of the second reset transistor M2, causes
One reset transistor M1, the second reset transistor M2 are turned on, after the first reset transistor M1, the second reset transistor M2 conducting,
The voltage amplitude of the primary nodal point P and the main outfan Gout is low level, i.e. primary nodal point P and the main output
End Gout is connected with low level VGL signal source.
Level signal generation phase in the present embodiment, low level drive signal output stage, high level drive signal are defeated
Go out the driving process of stage, the second reseting stage referring specifically to embodiment 3, be not repeated herein.
In above-described embodiment, in the first reseting stage, in the first reset letter of the high level of reset signal input input
Number, make to turn on as the thin film transistor (TFT) M0 that diode is used, trigger the normal startup of the first reseting module, make the first reset brilliant
Realize after body pipe M1 and the second reset transistor M2 conductings initial in the switching transistor input to every one-level shift register circuit
Before signal, by primary nodal point and the voltage amplitude of main outfan so that the grid that the shift register circuit per one-level is produced drives
Dynamic signal is not affected by the drift of the threshold voltage of thin film transistor (TFT), it is ensured that the driven of shift register and display unit
Normal display.
, but those skilled in the art once know basic creation although preferred embodiments of the present invention have been described
Property concept, then can make other change and modification to these embodiments.So, claims are intended to be construed to include excellent
Select embodiment and fall into the had altered of the scope of the invention and change.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of shift register, including the shift register circuit of multi-stage cascade, it is characterised in that per one-level shift LD electricity
Road, including：
Main outfan, for output drive signal；
Primary input module, for receiving initial signal；
First output module, is connected between the primary input module and the main outfan, for according to second clock signal
Output high level drive signal, the node between the primary input module and first output module are primary nodal point；
Second output module, is connected with the main outfan, for exporting low level drive signal according to the first clock signal；
Also include：
First reseting module, for the first reset signal being input into according to reset signal input, makes the primary nodal point and institute
State main outfan and be reset to low level；
Wherein, first reseting module includes：First reset transistor M1, the second reset transistor M2；Described first resets
The grid of transistor M1, the grid of the second reset transistor M2 are connected with the reset signal input, and described first
The first electrode of reset transistor M1 is connected with the primary nodal point, the first electrode of the second reset transistor M2 with described
Main outfan connection；The second electrode of the first reset transistor M1, the second reset transistor M2 second electrode equal
It is connected with low level signal input；
Second reseting module, is connected between the primary nodal point and first reseting module, for receiving next stage displacement
Second reset signal of register circuit output, makes the primary nodal point and the main outfan be reset to low level.
2. shift register as claimed in claim 1, it is characterised in that first reseting module also includes：3rd resets
Transistor M0；
The grid of the 3rd reset transistor M0, first electrode connect the reset signal input, and second electrode connects institute
State grid, the grid of the second reset transistor M2 of the first reset transistor M1.
3. shift register as claimed in claim 1 or 2, it is characterised in that second reseting module includes the 4th reset
Transistor M7；
The grid of the 4th reset transistor M7 is connected with the main outfan of next stage shift-register circuit, first electrode with
The first electrode connection of the first reset transistor M1, second electrode are connected with low level control signal input.
4. shift register as claimed in claim 1 or 2, it is characterised in that the primary input module includes switching transistor
M3；
The grid of switching transistor M3 is connected with initial signal input, first electrode and high-level control signal input
Connection, second electrode are connected with the primary nodal point.
5. shift register as claimed in claim 1 or 2, it is characterised in that first output module includes the first electric capacity
The C1 and M4 that pulls up transistor；
Wherein, the first electric capacity C1 is connected between the primary nodal point and the main outfan, the M4 that pulls up transistor
Grid be connected with the primary nodal point, first electrode is connected with second clock signal input part, and second electrode is defeated with the master
Go out end connection.
6. shift register as claimed in claim 1 or 2, it is characterised in that second output module includes transistor M5；
The grid of the transistor M5 is connected with the first clock signal input terminal, and first electrode is connected with the main outfan, the
Two electrodes are connected with low level signal input.
7. shift register as claimed in claim 1 or 2, it is characterised in that in the primary nodal point and first output
Also accessing between module has drop-down module；The drop-down module includes：Pull-down transistor M6 and the second electric capacity C2；
Wherein, the grid of the pull-down transistor M6 is connected with the primary nodal point, and first electrode is with the second electric capacity C2's
First end connects, and second electrode is connected with low level signal input, and second end of the second electric capacity C2 is defeated with described first
Go out the second clock signal input part connection of module.
8. a kind of driving of the every one-level shift register circuit for being applied to the shift register as described in any one of claim 1-7
Method, it is characterised in that every one-level shift register circuit includes the first reseting stage；
In the first reseting stage, the first reset signal is input in the reset signal input, causes first reseting module
The first reset transistor M1, the second reset transistor M2 conducting, the voltage of the primary nodal point and the main outfan is multiple
Position is low level.
9. driving method as claimed in claim 8, it is characterised in that
In the first reseting stage, the first reset signal is input in the reset signal input, causes first reseting module
The 3rd reset transistor M0, the first reset transistor M1, the second reset transistor M2 conducting, cause the primary nodal point and
The voltage amplitude of the main outfan is low level.
10. driving method as claimed in claim 8 or 9, it is characterised in that described also include per one-level shift register circuit:
Level signal generation phase, low level drive signal output stage, high level drive signal output stage and the second reseting stage；
In level signal generation phase, initial signal is input at the primary input end, cause the primary nodal point for high level, institute
The grid for stating the first reset transistor M1 and the second reset transistor M2 of the first reseting module is low level；
The stage is exported in low level drive signal, in the first clock signal of the first clock signal input terminal input high level, is caused
The second output module is made to export low level drive signal to the main outfan；
The stage is exported in high level drive signal, in the second clock signal of second clock signal input part input high level, is caused
The first output module is made to export high level drive signal to the main outfan；
In the second reseting stage, second reseting module receives the height of the main outfan output of next stage shift-register circuit
The second reset signal of level, causes the primary nodal point to be reset to low level, the first reset crystal of first reseting module
The second clock signal of the grid input high level of pipe M1 and the second reset transistor M2, causes the main outfan to be reset to low
Level.
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| CN110738953B (en) * | 2018-07-20 | 2022-12-06 | 深超光电（深圳）有限公司 | Gate driver and display device having the same |
| CN109637424A (en) * | 2019-01-24 | 2019-04-16 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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