CN105448258B - Gate drivers and display panel - Google Patents
Gate drivers and display panel Download PDFInfo
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- CN105448258B CN105448258B CN201510992177.9A CN201510992177A CN105448258B CN 105448258 B CN105448258 B CN 105448258B CN 201510992177 A CN201510992177 A CN 201510992177A CN 105448258 B CN105448258 B CN 105448258B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of gate drivers and display panel.The gate drivers include an at least shift register group, and shift register group includes cascade N grades of shift register cell；Shift register cell receives the first input signal, the second input signal and clock signal and provides an output signal according to the first input signal, the second input signal and clock signal；Received first input signal of m grades of shift register cells is the output signal of m-1 grade shift register cells, and received second input signal of m grades of shift register cells is the output signal of m+1 grades of shift register cells, and m is positive integer, and 1 < m < N；1st grade of received first input signal of shift register cell is one first initial signal, and at least the 1st grade to N-1 grades of shift register cells of output signal is both used as effective gated sweep signal, and provides an effective gated sweep signal using the first initial signal.The present invention can reduce the quantity of shift register cell.
Description
Technical field
The present invention relates to field of display technology, and in particular to a kind of gate drivers and showing using the gate drivers
Show panel.
Background technique
With the development of optical technology and semiconductor technology, liquid crystal display panel (Liquid Crystal Display,
) and the FPD face such as organic LED display panel (Organic Light Emitting Diode, OLED) LCD
Plate due to, cost more frivolous with body and energy consumption is lower, reaction speed faster, excitation purity and brightness is more excellent and contrast more
The features such as high, has been widely used in each electronic product.But there are still need to be changed for display product in the prior art
Into place.Such as:
Display panel mainly realizes by picture element matrix and shows that typically, each row pixel is both coupled to corresponding scanning
Grid line.In the display panel course of work, the signals such as the clock signal of input are passed through into shift register by gate drivers
The gated sweep signal that cell translation is turned on/off at control pixel, for example, grid open signal and gate turn-off signal；It will
Gated sweep signal is sequentially applied to the scanning grid line of each row pixel of display panel, can gate to each row pixel.
It as shown in fig. 1, is a kind of structural schematic diagram of gate drivers.The gate drivers include cascade 5 grades of shiftings
The first input end VIN1 of bit register cell S R1~SR5, shift register cell SR1 receive initial signal STV, and displacement is posted
The first input end VIN1 of storage cell S R2~SR5 receives the output signal of previous stage shift register cell, shift register
The second input terminal VIN2 of cell S R1~SR4 receives the output signal of rear stage shift register cell as reset signal；This
Outside, each shift register cell also receives the first clock signal CK1 and second clock signal CKB1.Each shift register list
Member provides an output signal in its output end VOUT according to received signal, therefore the gate drivers in Fig. 1 can provide 5 rows
Gate drive signal.
With the development of flat panel display, high-resolution and narrow frame product have obtained more and more concerns, on
Very big chip area can be occupied by stating shift register cell large number of in gate drivers, be unfavorable for increasing effective display
Area and narrow frame design.
Further, since the shift register cell of gate drivers most final stage, i.e. the second of shift register cell SR5 are defeated
Enter to hold VIN2 not to be used as reset signal input signal, thus its output end may output error signal.With reference to institute in Fig. 2
Show, is the analog waveform of the output signal of the shift register cell of gate drivers most final stage (such as the 5th grade), it can be obvious
Find out and has multiple output compared to previous stage (such as the 4th grade).
With reference to shown in Fig. 3, a solution is set after the shift register cell of gate drivers most final stage
Virtual (Dummy) shift register cell DSR1 is set, using the output signal DS1 of dummy shift register cells D SR1 to most
The shift register cell SR5 of final stage provides reset signal；Simultaneously as in reverse scan, the shift LD of the 1st grade of script
Device cell S R1 will become the shift register cell of most final stage, therefore, in the 1st grade of shift register cell of gate drivers
One dummy shift register cells D SR2 of setting is also needed before SR1.Gate drivers are undoubtedly further increased in this way
Area；And the output signal DS1 and DS2 of dummy shift register unit can not be input to as effective gated sweep signal
Display area, as invalid gated sweep signal, therefore also need for dummy shift register unit output signal DS1 and
Load is additionally arranged in DS2.
It should be noted that the information in the invention of above-mentioned background technology part is only used for reinforcing the reason to background of the invention
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The purpose of the present invention is to provide the display panels of a kind of gate drivers and the application gate drivers, are used for
Overcome the problems, such as at least to a certain extent one or more caused by the limitation and defect due to the relevant technologies.
Other characteristics and advantages of the invention will be apparent from by the following detailed description, or partially by the present invention
Practice and acquistion.
The one side of the embodiment of the present invention provides a kind of gate drivers, comprising:
An at least shift register group, each shift register group include cascade N grades of shift register cell,
In, N is positive integer, and N >=3；
The shift register cell receives the first input signal, the second input signal and clock signal and according to described
First input signal, the second input signal and clock signal provide an output signal；
Wherein, received first input signal of m grades of shift register cells is m-1 grades of shift register cells
Output signal, received second input signal of m grades of shift register cells be the m+1 grades of shift register lists
The output signal of member, wherein m is positive integer, and 1 < m < N；
Wherein, received first input signal of the 1st grade of shift register cell is one first initial signal, at least the
1 grade of output signal to the N-1 grades of shift register cells is both used as effective gated sweep signal, and utilizes described the
One initial signal provides effective gated sweep signal.
The another aspect of the embodiment of the present invention provides a kind of gate drivers, comprising:
An at least shift register group, each shift register group include cascade N grades of shift register cell,
In, N is positive integer, and N >=3；
The shift register cell receives input signal and clock signal and according to the input signal and clock
Signal provides an output signal；
Wherein, the received input signal of m grades of shift register cells for m-1 grades of shift register cells institute
State output signal, wherein m is positive integer, and 1 < m≤N；
Wherein, the 1st grade of received input signal of shift register cell is an initial signal, and all displacements are posted
The output signal of storage unit is both used as effective gated sweep signal, and provides effective grid using the initial signal
Pole scanning signal.
The another further aspect of the embodiment of the present invention provides a kind of display panel, including any one of the above gate drivers.
In conclusion in example embodiment of the invention, by providing effective gated sweep signal using initial signal,
The quantity of shift register cell can be effectively reduced, and then the chip area of gate drivers can be made to reduce, to realize
The display panel of higher resolution and more narrow frame provides technical support；Simultaneously as saving shift register cell
Quantity compresses preparation cost so as to simplify preparation process.
Detailed description of the invention
Its exemplary embodiment is described in detail by referring to accompanying drawing, above and other feature of the invention and advantage will become
It is more obvious.
Fig. 1 is a kind of structural schematic diagram of gate drivers in the prior art；
Fig. 2 is the waveform diagram of gate drivers part output signal in Fig. 1；
Fig. 3 is the structural schematic diagram of another gate drivers in the prior art；
Fig. 4 is a kind of structure chart of gate drivers provided in an embodiment of the present invention；
Fig. 5 is the waveform diagram of gate drivers output signal in Fig. 2；
Fig. 6 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention；
Figure 10 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention；
Figure 11 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention；
Figure 12 is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention.
Specific embodiment
Exemplary embodiment is described more fully with reference to the drawings.However, exemplary embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of exemplary embodiment comprehensively it is communicated to those skilled in the art.In the figure in order to clear
It is clear, exaggerate, deform or simplify geomery.Identical appended drawing reference indicates same or similar structure in figure, thus will
Omit their detailed description.
In addition, described feature, structure or step can be incorporated in one or more implementations in any suitable manner
In example.In the following description, many details are provided to provide and fully understand to the embodiment of the present invention.However,
It will be appreciated by persons skilled in the art that technical solution of the present invention can be practiced without one in the specific detail or more
It is more, or can be using other methods, step, structure etc..
A kind of gate drivers are provided firstly in this example embodiment.Gate drivers include that at least one displacement is posted
Storage group.It is a kind of structural schematic diagram of gate drivers provided in an embodiment of the present invention with reference to Fig. 4, Fig. 4, wherein grid drives
Dynamic device includes a shift register group, and shift register group includes cascade N grades of shift register cell, wherein N is positive whole
Number, and N >=3；It is illustrated so that N is equal to 5 as an example in Fig. 4, i.e., shift register group includes cascade 1st grade of shift register list
First SR1 to the 5th grades of shift register cell SR5；But it will be readily appreciated by those skilled in the art that N can actually be any
Positive integer greater than 2.
Each above-mentioned shift register cell includes first input end VIN1, the second input terminal VIN2, clock signal terminal
CK1, clock signal terminal CKB1 and output end VOUT, wherein the first input end VIN1 of each shift register cell can be with
One first input signal is received, the second input terminal VIN2 can receive one second input signal, clock signal terminal CK1 and clock
Signal end CKB1 can be used for receiving the first clock signal CK1 and second clock signal CKB1, also, each shift register
Unit based on the received believe in one output of its output end VOUT offer by the first input signal, the second input signal and clock signal
Number.In this example embodiment, shift register cell can be made of elements such as multiple switch transistor and capacitors, displacement
Register cell can be amorphous silicon (Alpha Silica) semiconductor shift register cell, i.e., switching transistor therein is
Amorphous silicon type thin film transistor (TFT) (a-Si TFT)；It is also possible to oxide (Oxide) semiconductor shift register cell, i.e., wherein
Switching transistor be oxide type thin film transistor (TFT) (oxide TFT)；Either low temperature polycrystalline silicon (LTPS) semiconductor displacement
Register cell, i.e., switching transistor therein are other kinds of shiftings such as low-temperature polysilicon thin film transistor (TFT) (LTPS-TFT)
Bit register unit does not do particular determination to this in the present exemplary embodiment.
Wherein, received first input signal of the first input end VIN1 of m grades of shift register cells is m-1 grades of shiftings
Second input terminal VIN2 received second of the output signal of bit register unit output end, m grades of shift register cells is defeated
Enter the output signal that signal is m+1 grades of shift register cell output end VOUT, wherein m is positive integer, and 1 < m < N.Example
Such as, received first input signal of the first input end VIN1 of the 2nd grade of shift register cell is the 1st grade of shift register cell
Received second input signal of the second input terminal VIN2 of the output signal of output end VOUT, the 2nd grade of shift register cell is
The output signal of 3rd level shift register cell output end VOUT；The first input end VIN1 of 3rd level shift register cell connects
The first input signal received is the output signal of the 2nd grade of shift register cell output end VOUT, 3rd level shift register cell
Received second input signal of the second input terminal VIN2 be the 4th grade of shift register cell output end VOUT output signal etc.
Deng.
With continued reference to Fig. 4, in this example embodiment, the first input end VIN1 of the 1st grade of shift register cell SR1 is connect
The first input signal received is one first initial signal STV1, and the 1st grade to the 5th grade shift register cell output end VOUT's is defeated
Signal is both used as effective gated sweep signal, i.e. gated sweep signal S2~S6 out；In this example embodiment, effective grid is swept
It retouches signal and refers to and be input to display area, for turning on/off the switch crystal in the pixel column connecting with gate driving circuit
The scanning signal of pipe, that is, the invalid gated sweep signal being different from background technique.Further, in this example embodiment also
It can use the first initial signal STV1 and one effective gated sweep signal be provided, be that grid drives in Fig. 2 with reference to Fig. 5, Fig. 5 therefore
The waveform diagram of dynamic device output signal, it can be seen that the gate drivers in Fig. 4 can use 5 grades of shift register lists
Member generates 6 effective gated sweep signal S1~S6.
Seen from the above description, the gate drivers in this example embodiment are by providing effective grid using initial signal
Pole scanning signal can effectively reduce the quantity of shift register cell, and then can make the chip area of gate drivers
Reduce, to realize that the display panel of higher resolution and more narrow frame provides technical support；It is posted simultaneously as saving displacement
The quantity of storage unit compresses preparation cost so as to simplify preparation process.
It is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention with reference to Fig. 6, Fig. 6, such as institute in figure
Show, in reverse scan, the 1st grade of shift register cell SR1 will become the shift register cell of most final stage originally；This
When, VIN2 is first input end in diagram, and VIN1 is the second input terminal, and the shift register cell SR5 of most final stage originally
The 1st grade of shift register cell will be become, input terminal VIN2 receives the first initial signal STV1.As described above, this example is real
It applies and the first initial signal STV1 offer effective gated sweep signal is provided in mode.I.e. no matter in forward scan or reversed
It is all to belong to protection scope of the present invention using the effective gated sweep signal of initial signal offer in scanning.
In other example embodiments of the invention, one second initial signal can also be utilized at the end of forward scan
STV2 is input to most final stage, i.e., the second input terminal VIN2 of N grades shift register cells.For example, Fig. 7 is this hair with reference to Fig. 7
The structural schematic diagram for another gate drivers that bright embodiment provides, wherein the 5th grade of shift register cell received second
Input signal is one second initial signal STV2.By using the second initial signal STV2 as most final stage shift register cell
The second input signal, then may not need after N grades of shift register cells be arranged dummy shift register unit provide
Second input signal, and then the chip area of gate drivers can be made further to reduce.
In this example embodiment, one frame (Frame) of the second initial signal STV2 and the first interval initial signal STV1, example
Such as, the first initial signal STV1 is the initial signal of X frame, and the second initial signal STV2 is the initial signal of+1 frame of X.Originally show
Example embodiment in, a frame refer to gate drivers from the 1st grade to N grade the forward scan of shift register cell whole once or
Person's whole reverse scan is primary.On picture is shown, it is primary to can be image refreshing.
Further, an effective gated sweep can also be provided in this example embodiment using the second initial signal to believe
Number, i.e., in addition to effective gated sweep signal that all shift registers itself export, can also be utilized in this example embodiment
First initial signal and the second initial signal are additionally provided two effective gated sweep signals.For example, the gate driving in Fig. 7
Device can use 5 grades of shift register cells and generate 7 effective gated sweep signals.Compared with prior art, it can avoid setting
While setting virtual (Dummy) shifting deposit unit, the quantity of shift register cell is further effectively reduced, grid can be made
The chip area of driver further reduces.
It is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention with reference to Fig. 8, Fig. 8；This example is real
Applying each shift register cell in mode can also include a reset signal end RST.Reset signal end RST is resetted for receiving one
Signal, so as to be resetted using reset signal to each shift register cell, for example, can start to sweep in present frame
Before retouching, the residual voltage signal of previous frame is removed using reset signal, avoids the gated sweep of gate drivers output error
Signal, and promote the waveform accuracy of the gated sweep signal of output.
In addition, gate drivers described in this example embodiment may not need setting dummy shift register unit, and
And shift register cells at different levels can be exported correctly, therefore each displacement is posted in the gate drivers of this example embodiment
The output end of memory cell can be electrically connected with a grid line in display panel, and the pixel column for grid line connection provides
Cut-in voltage avoids the waste of the signal generated.
In this exemplary above embodiment, said so that gate drivers include a shift register group as an example
It is bright.In this exemplary other embodiments, gate drivers also may include more than one shift register group.For example,
It is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention with reference to Fig. 9, Fig. 9, wherein gate drivers packet
Include the first shift register group and the second shift register group, the first shift register group include shift register cell SR1A extremely
SR5A, the second shift register group include shift register cell SR1B to SR5B, and the displacement in the first shift register group is posted
Storage unit is staggeredly alternatively arranged with the shift register cell in the second shift register group, and for example, grid drives in Fig. 9
In dynamic device shift register cell put in order can for SR1A, SR1B, SR2A, SR2B, SR3A, SR3B, SR4A, SR4B,
SR5A, SR5B are put in order by above-mentioned, can staggeredly be exported gated sweep signal, be reduced two neighboring gated sweep signal
Between time interval.But it will be readily appreciated by those skilled in the art that when gate drivers include three or three or more
When shift register group, above-mentioned arrangement mode is equally applicable, for example, gate drivers can also include third shift register
Group, third shift register group may include shift register cell SR1C to SR5C, then the arrangement of shift register cell is suitable
Sequence can be SR1A, SR1B, SR1C, SR2A, SR2B, SR2C etc..
Another gate drivers are additionally provided in this example embodiment.The gate drivers include at least one displacement
Register group.It is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention with reference to Figure 10, Figure 10, wherein
Gate drivers may include a shift register group, and shift register group may include cascade N grades of shift register list
Member, wherein N is positive integer, and N >=2；It is illustrated so that N is equal to 5 as an example in Figure 10, i.e., shift register group may include grade
The 1st grade of shift register cell SR1 to the 5th grades of shift register cell SR5 of connection；But skilled addressee readily understands that
It is that N can actually be any positive integer greater than 1.
Each shift register cell includes input terminal VIN, clock signal terminal CK1, clock signal terminal CKB1 and defeated
Outlet VOUT, wherein the input terminal VIN of each shift register cell can receive an input signal, clock signal terminal CK1 with
And clock signal terminal CKB1 can be used for receiving the first clock signal CK1 and second clock signal CKB1, also, each displacement
Input signal and clock signal in its output end VOUT provide an output signal to register cell based on the received.This example is real
It applies in mode, shift register cell can be made of elements such as multiple switch transistor and capacitors, shift register cell
It can be amorphous silicon (Alpha Silica) semiconductor shift register cell, be also possible to oxide semiconductor shift register
The other kinds of shift register cells such as unit, low temperature polycrystalline silicon shift register cell, to this in the present exemplary embodiment
Do not do particular determination.
Wherein, received first input signal of the input terminal VIN of m grades of shift register cells is that m-1 grades of displacements are posted
The output signal of storage unit output end VOUT, wherein m is positive integer, and 1 < m < N.For example, the 2nd grade of shift register cell
The received input signal of input terminal VIN be the 1st grade of shift register cell output end VOUT output signal, 3rd level displacement
The received input signal of input terminal VIN of register cell is the output signal of the 2nd grade of shift register cell output end VOUT
Etc..
Continue to refer to figure 10, in this example embodiment, the first input end VIN of the 1st grade of shift register cell SR1 is connect
The input signal of receipts is an initial signal STV, and the output signal of the 1st grade to the 5th grade shift register cell output end VOUT is equal
As effective gated sweep signal, i.e. gated sweep signal S2~S6.Further, starting is also utilized in this example embodiment
Signal STV provides an effective gated sweep signal, and therefore, the gate drivers in Figure 10 can use 5 grades of shift register lists
Member generates 6 effective gated sweep signals.
Seen from the above description, the gate drivers in this example embodiment using initial signal STV by being provided with
Gated sweep signal is imitated, the quantity of shift register cell can be effectively reduced, and then the domain of gate drivers can be made
Area reduces, to realize that the display panel of higher resolution and more narrow frame provides technical support；Simultaneously as saving shifting
The quantity of bit register unit compresses preparation cost so as to simplify preparation process.
It is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention with reference to Figure 11, Figure 11, wherein this
Each shift register cell can also include a reset signal end RST in example embodiment.Reset signal end RST is for receiving
One reset signal, so as to be resetted using reset signal to each shift register cell, so as in present frame
Before signal starts scanning, the residual voltage signal of previous frame signal is removed using reset signal, gate drivers is avoided to export
The gated sweep signal of mistake and the waveform accuracy for promoting the gated sweep signal exported.
In addition, gate drivers described in this example embodiment may not need setting dummy shift register unit, and
And shift register cells at different levels can be exported correctly, therefore each displacement is posted in the gate drivers of this example embodiment
The output end of memory cell can be electrically connected with a grid line in display panel, and the pixel column for grid line connection provides
Cut-in voltage avoids the waste of the signal generated.
In this exemplary above embodiment, said so that gate drivers include a shift register group as an example
It is bright.In this exemplary other embodiments, gate drivers also may include more than one shift register group.For example,
It is the structural schematic diagram of another gate drivers provided in an embodiment of the present invention with reference to Figure 12, Figure 12, wherein gate drivers
It may include the first shift register group and the second shift register group, the first shift register group may include shift register
Cell S R1A to SR5A, the second shift register group may include shift register cell SR1B to SR5B, the first shift LD
Shift register cell in device group is staggeredly alternatively arranged with the shift register cell in the second shift register group, citing and
Speech, in Figure 12 in gate drivers shift register cell put in order can for SR1A, SR1B, SR2A, SR2B, SR3A,
SR3B, SR4A, SR4B, SR5A, SR5B are put in order by above-mentioned, can staggeredly be exported gated sweep signal, be reduced adjacent two
Time interval between a gated sweep signal.But it will be readily appreciated by those skilled in the art that when gate drivers include three
When a or three or more shift register groups, above-mentioned arrangement mode is equally applicable, for example, gate drivers can also include the
Three shift register groups, third shift register group may include shift register cell SR1C to SR5C, then shift register
Putting in order for unit can be SR1A, SR1B, SR1C, SR2A, SR2B, SR2C etc..
Further, this example embodiment additionally provides a kind of display panel, which includes above-mentioned any
A kind of gate drivers, but not limited to this.Since the gate drivers used have smaller chip area, the display
The effective display area of panel is increased, and is conducive to the resolution ratio for promoting display panel；Meanwhile the frame of the display panel can
It is narrower with what is done.In the present exemplary embodiment, which can be liquid crystal display panel or OLED display panel, at this
Invention other exemplary embodiments in, the display panel be also likely to be PLED (Polymer Light-Emitting Diode,
Polymer LED) display panel, PDP (Plasma Display Panel, plasma are shown) display panel etc. other
Panel display board does not limit to the scope of application especially that is, in this example embodiment.
In conclusion in example embodiment of the invention, by providing effective gated sweep signal using initial signal,
The quantity of shift register cell can be effectively reduced, and then the chip area of gate drivers can be made to reduce, to realize
The display panel of higher resolution and more narrow frame provides technical support；Simultaneously as saving shift register cell
Quantity compresses preparation cost so as to simplify preparation process.
The present invention is described by above-mentioned related embodiment, however above-described embodiment is only to implement example of the invention.
It must be noted that the embodiment disclosed is not limiting as the scope of the present invention.On the contrary, do not depart from spirit of the invention and
It is changed and retouched made by range, belongs to scope of patent protection of the invention.
Claims (4)
1. a kind of gate drivers characterized by comprising
One or more shift register groups, the shift register group include cascade N grades of shift register cell, wherein N
For positive integer, and N >=3；
The shift register cell receives the first input signal, the second input signal and clock signal and according to described first
Input signal, the second input signal and clock signal provide an output signal；
Wherein, received first input signal of m grades of shift register cells is the defeated of m-1 grades of shift register cells
Signal out, received second input signal of m grades of shift register cells are the output of m+1 grades of shift register cells
Signal, wherein m is positive integer, and 1 < m < N；
Wherein, it is only located at received first input signal of the 1st grade of shift register cell of the gate drivers front end
For one first initial signal, at least the 1st grade to the N grades of shift register cells of output signal is both used as effective grid and sweeps
Signal is retouched, and provides effective gated sweep signal using first initial signal；
Received second input signal of N grades of shift register cells for being only located at the gate drivers end is one the
Two initial signals, at least the 1st grade to the N grades of shift register cells of output signal are both used as effective gated sweep letter
Number, and effective gated sweep signal is provided using second initial signal；
The shift register group generates the N+2 effective scanning signals using N grades of shift register cells；
The gate drivers also include a reset line, and the reset line is connect with the shift register cell, are used for as institute
It states shift register cell and reset signal is provided, to be resetted to the shifting deposit unit；And
The gate drivers do not include virtual shifting deposit unit.
2. gate drivers according to claim 1, which is characterized in that second initial signal and first starting
One frame of sigtnal interval.
3. gate drivers according to claim 1, which is characterized in that the gate drivers include the first shift LD
Device group and the second shift register group；Shift register cell in the first shift register group is posted with second displacement
Shift register cell in storage group is staggeredly alternatively arranged.
4. a kind of display panel, which is characterized in that including gate drivers described in claim 1-3 any one.
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| CN201510992177.9A CN105448258B (en) | 2015-12-25 | 2015-12-25 | Gate drivers and display panel |
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| CN201510992177.9A CN105448258B (en) | 2015-12-25 | 2015-12-25 | Gate drivers and display panel |
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| CN105448258B true CN105448258B (en) | 2019-01-04 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10796642B2 (en) * | 2017-01-11 | 2020-10-06 | Samsung Display Co., Ltd. | Display device |
| TWI649733B (en) * | 2018-02-26 | 2019-02-01 | 友達光電股份有限公司 | Display device and its gate driver |
| CN111210758B (en) * | 2020-02-28 | 2023-01-31 | 合肥鑫晟光电科技有限公司 | Grid driving circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101502361B1 (en) * | 2008-08-06 | 2015-03-16 | 삼성디스플레이 주식회사 | Liquid crystal display |
| KR101535819B1 (en) * | 2008-12-24 | 2015-07-10 | 엘지디스플레이 주식회사 | Display Device |
| CN102214428B (en) * | 2010-04-01 | 2013-12-18 | 瀚宇彩晶股份有限公司 | Gate driving circuit and driving method therefor |
| CN103927960B (en) * | 2013-12-30 | 2016-04-20 | 上海中航光电子有限公司 | A kind of gate drive apparatus and display device |
| US20150317018A1 (en) * | 2014-04-30 | 2015-11-05 | Himax Technologies Limited | Shift register adaptable to a gate driver |
| CN104575419B (en) * | 2014-12-04 | 2017-03-15 | 上海天马微电子有限公司 | A kind of shift register and its driving method |
| CN105047155B (en) * | 2015-08-17 | 2017-07-07 | 深圳市华星光电技术有限公司 | Liquid crystal display device and its GOA scanning circuits |
| CN105185342B (en) * | 2015-10-15 | 2018-03-27 | 武汉华星光电技术有限公司 | Raster data model substrate and the liquid crystal display using raster data model substrate |
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