CN110971192A - Crystal oscillator circuit capable of starting oscillation rapidly - Google Patents
Crystal oscillator circuit capable of starting oscillation rapidly Download PDFInfo
- Publication number
- CN110971192A CN110971192A CN201911313758.XA CN201911313758A CN110971192A CN 110971192 A CN110971192 A CN 110971192A CN 201911313758 A CN201911313758 A CN 201911313758A CN 110971192 A CN110971192 A CN 110971192A
- Authority
- CN
- China
- Prior art keywords
- switch
- gate
- output
- nth
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 78
- 230000010355 oscillation Effects 0.000 title claims abstract description 40
- 239000003990 capacitor Substances 0.000 claims description 18
- 230000005284 excitation Effects 0.000 abstract description 7
- 102100031024 CCR4-NOT transcription complex subunit 1 Human genes 0.000 description 6
- 102100031033 CCR4-NOT transcription complex subunit 3 Human genes 0.000 description 6
- 101000919674 Caenorhabditis elegans CCR4-NOT transcription complex subunit let-711 Proteins 0.000 description 6
- 101000919672 Homo sapiens CCR4-NOT transcription complex subunit 1 Proteins 0.000 description 6
- 101000919663 Homo sapiens CCR4-NOT transcription complex subunit 3 Proteins 0.000 description 6
- 230000000630 rising effect Effects 0.000 description 6
- 102100031025 CCR4-NOT transcription complex subunit 2 Human genes 0.000 description 5
- 101001092183 Drosophila melanogaster Regulator of gene activity Proteins 0.000 description 5
- 101000919667 Homo sapiens CCR4-NOT transcription complex subunit 2 Proteins 0.000 description 5
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 description 4
- 101100524516 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA2 gene Proteins 0.000 description 4
- 102100032981 CCR4-NOT transcription complex subunit 4 Human genes 0.000 description 3
- 101000942594 Homo sapiens CCR4-NOT transcription complex subunit 4 Proteins 0.000 description 3
- 210000004899 c-terminal region Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 101100294409 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NOT5 gene Proteins 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000010356 wave oscillation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B1/00—Details
- H03B1/04—Reducing undesired oscillations, e.g. harmonics
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
The invention discloses a crystal oscillator circuit with rapid oscillation starting, which comprises a basic oscillation circuit, a ring oscillator, a comparator, a logic counting circuit, a third switch to an Nth switch1Switch, N1Is a positive integer, and N1Not less than 3; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch from the third switch to the Nth switch1Switches connected in series in sequence, Nth1The output end of the switch is connected with the input end of the basic oscillating circuit; the input end and the output end of the basic oscillating circuit are connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives the power-on reset signal, and the output ends respectively output a third switch control signal to the Nth switch1A switch control signal for controlling the third switch to the Nth switch1The switch is closed or opened; the inventionAnd the ring oscillator outputs an excitation signal to the crystal oscillator basic circuit, so that the oscillation starting time is shortened.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a crystal oscillator circuit capable of starting oscillation rapidly.
Background
The crystal oscillator has good frequency accuracy and stability, small volume and low power consumption, is often used as a time frequency reference, and is widely applied to systems such as communication, radar, navigation and guidance. The crystal oscillator can provide high-precision clock signals for various electronic systems, wherein some application environments require that the oscillation starting time of the crystal oscillator is as short as possible, for example, in an internet of things system, switching between sleep and activation is required to be performed continuously, and in order to achieve the shorter switching time, the oscillation starting time of the crystal oscillator is required to be shorter. How to realize the rapid oscillation starting of the crystal oscillator becomes a technical problem to be solved by the technical personnel in the field.
Disclosure of Invention
The invention aims to provide a crystal oscillator circuit capable of starting oscillation quickly, which can realize quick oscillation starting.
For the purpose of the invention, the invention adopts a technical scheme as follows:
a fast start-up crystal oscillator circuit comprises a basic oscillation circuit, a ring oscillator, a comparator, a logic counting circuit, a first switch, a second switch, a third switch … … N1Switch, N1Is a positive integer, and N1Not less than 3; the input end of the first switch is connected with a power supply, and the output end of the first switch is connected with the power supply end of the basic oscillation circuit; the input end of the second switch is connected with a power supply, and the output end of the second switch is connected with the power supply end of the ring oscillator; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch, and the third switch is connected with the Nth switch1Switches connected in series in sequence, Nth1The output end of the switch is connected with the input end of the basic oscillating circuit; the input end and the output end of the basic oscillating circuit are respectively connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output end of the logic counting circuit respectively outputs a second switch control signal and a third switchOff control signal … … Nth1The switch control signal controls the second switch and the third switch … … to the Nth switch1The switch is closed or opened; the power-on reset signal controls the first switch to be switched on or switched off.
For the purpose of the invention, another technical scheme adopted by the invention is as follows:
a fast start-up crystal oscillator circuit comprises a basic oscillation circuit, a ring oscillator, a comparator, a logic counting circuit, a third switch to an Nth switch1Switch, N1Is a positive integer, and N1Not less than 3; the power supply end of the ring oscillator and the power supply end of the basic oscillation circuit are connected with a power supply; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch, and the third switch is connected with the Nth switch1Switches connected in series in sequence, Nth1The output end of the switch is connected with the input end of the basic oscillating circuit; the input end and the output end of the basic oscillating circuit are respectively connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output ends respectively output a third switch control signal to the Nth switch1A switch control signal for controlling the third switch to the Nth switch1The switch is closed or opened.
In a specific embodiment, the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate and (N)1-1) or (N)1-2) output NOT gates, one input of the AND gate receiving the clock signal output by the comparator, the other input receiving the power-on Reset signal, the output being connected to the clock signal input of a first D flip-flop, the D port of the first D flip-flop being connected to the output of the first NOT gate, the Q port being connected to the input of the first NOT gate and to the input of a second NOT gate, the output of the second NOT gate being connected to the clock signal input of a second D flip-flop, the D port of the second D flip-flop being connected to the Reset port,q ports are respectively connected with (N)1-1) or (N)1-2) input connections of output NOT-gates,
or, the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop … … Nth3A D flip-flop, a first NOT gate, a second NOT gate … … Nth3A NOT gate and (N)1-1) or (N)1-2) output not gates, N3Is a positive integer, and N3And more than or equal to 3, one input end of the AND gate receives the clock signal output by the comparator, the other input end of the AND gate receives the power-on reset signal, the output end of the AND gate is connected with the clock signal input end of the first D flip-flop, the D port of the nth D flip-flop is connected with the output end of the nth NOT gate, the Q port of the Nth NOT gate is connected with the input end of the nth NOT gate and the clock signal input end of the (N +1) th D flip-flop, and N is 1 to (N is)3-2), N3-1) D port of D flip-flop and (N)3-1) the output of the NOT gate is connected, the Q port is connected with the (N) th3-1) inputs of NOT gates and Nth3The input terminals of the NOT gates are connected, N3The output end of the NOT gate and the Nth gate3The clock signal input ends of the D flip-flops are connected, the Nth flip-flop3The D port of each D flip-flop is connected with the Reset port, and the Q port is respectively connected with (N)1-1) or (N)1-2) input connections of output not gates;
said (N)1-1) or (N)1-2) the output ends of the output NOT gates respectively control the second switch and the third switch … … Nth switch1Switches or third to Nth switches1A switch control signal for the switch; the Reset end of the first D flip-flop and the Reset end … … of the second D flip-flop are Nth3The Reset terminals of the D flip-flops all receive power-on Reset signals.
In a specific embodiment, the ring oscillator includes nand gate, first not gate, second not gate, third not gate … … Nth gate2NOT gate, N23, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th2The NOT gates are connected in series,(N) th2-1) the output of the not-gate is connected to the other input of the first not-gate, N2The output end of the NOT gate outputs an oscillation clock.
Further, the fast-start crystal oscillator circuit further comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.
Further, the fast-start crystal oscillator circuit further comprises a first resistor; the first resistor is connected into the Nth resistor1Between the switch and the basic crystal oscillator circuit, one end is connected with the Nth1The output end of the switch is connected, and the other end of the switch is connected with the input end of the basic crystal oscillator circuit.
In a specific embodiment, the ring oscillator includes nand gate, first not gate, second not gate, third not gate … … Nth gate2NOT gate, N23, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th2NOT gates connected in series, N2-1) the output of the not-gate is connected to the other input of the first not-gate, N2The output end of the NOT gate outputs an oscillation clock.
Further, the fast-start crystal oscillator circuit further comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.
Further, the fast-start crystal oscillator circuit further comprises a first resistor; the first resistor is connected into the Nth resistor1Between the switch and the basic crystal oscillator circuit, one end is connected with the Nth1The output end of the switch is connected with the baseThe input end of the crystal oscillator circuit is connected.
As a specific implementation mode, the crystal oscillator basic circuit comprises an inverting amplifier, a feedback resistor, a crystal oscillator, a first capacitor and a second capacitor; the input end of the inverting amplifier INV and the Nth1The output end of the switch, one input end of the comparator, one end of the feedback resistor, one end of the crystal oscillator and one end of the first capacitor are connected; the output end of the inverting amplifier is connected with the other input end of the comparator, the other end of the feedback resistor, the other end of the crystal oscillator and one end of the second capacitor; the power supply end of the inverting amplifier is connected with the other end of the first switch or directly connected with a power supply; and the grounding end of the inverting amplifier, the other end of the first capacitor and the other end of the second capacitor are grounded.
The invention has the beneficial effects that:
according to the technical scheme, the ring oscillator outputs the excitation signal to the input end of the basic crystal oscillator circuit, so that the oscillation starting time of the basic crystal oscillator circuit is shortened, the clock signal output by the basic crystal oscillator circuit is counted by the logic counting circuit, and the ring oscillator is controlled to stop outputting the excitation to the basic crystal oscillator circuit after the oscillation starting of the basic crystal oscillator circuit is stable. Meanwhile, after the crystal oscillator basic circuit starts oscillation and is stable, the second switch disconnects the power supply from the ring oscillator, so that the ring oscillator stops oscillation, power consumption is reduced, and the third switch is connected to the Nth switch1After the crystal oscillator basic circuit starts oscillation and is stable, the switch disconnects the connection between the ring oscillator and the crystal oscillator basic circuit, prevents the oscillation clock output by the ring oscillator from influencing the normal work of the crystal oscillator basic circuit, and reduces the interference of capacitive coupling on the crystal oscillator basic circuit. Furthermore, the clock driving capability is increased through the first buffer and the second buffer, so that the clock signal has good rising edge and falling edge. Furthermore, the invention reduces the large deviation of the working state of the crystal oscillator basic circuit caused by the strong driving capability of the excitation signal output to the crystal oscillator basic circuit through the voltage division of the first resistor, and the ring oscillator needs to reestablish the bias after stopping outputting the excitation signal to the crystal oscillator basic circuitThe voltage and the oscillation time of the basic crystal oscillation circuit are longer.
Drawings
In order to more clearly illustrate the embodiments of the present invention, the drawings used in the embodiments will be briefly described below. The drawings in the following description are only embodiments of the invention and other drawings may be derived from those drawings by a person skilled in the art without inventive effort.
FIG. 1 is a block diagram of a fast-start crystal oscillator circuit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a ring oscillator according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a logic counter circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example one
As shown in FIG. 1, a fast start-up crystal oscillator circuit includes a crystal oscillator basic circuit, a ring oscillator, a first buffer BUF1, a second buffer BUF2, a comparator CMP, a logic counter circuit, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; the crystal oscillator basic circuit comprises an inverting amplifier INV, a feedback resistor RF, a crystal oscillator XTAL, a first capacitor C1 and a second capacitor C2; the input end of the first switch S1 is connected with a power supply VDD, and the output end is connected with the power supply end of the inverting amplifier INV; the input end of the second switch S2 is connected with a power supply VDD, and the output end is connected with the power supply end of the ring oscillator; the input end of the ring oscillator receives the power-on enable signal EN, and the output end of the ring oscillator is connected with the input end of the first buffer BUF 1; the output end of the first buffer BUF1 is connected with the input end of a third switch S3, the output end of the third switch S3 is connected with the input end of a fourth switch S4, and the output end of the fourth switch S4 is connected with one end of a first resistor R1; the other end of the first resistor R1 is connected to the input end of the inverting amplifier INV, the inverting input end of the comparator CMP, one end of the feedback resistor RF, one end of the crystal oscillator XTAL, and one end of the first capacitor C1; the output end of the inverting amplifier INV is connected to the non-inverting input end of the comparator CMP, the other end of the feedback resistor RF, the other end of the crystal oscillator XTAL, and one end of the second capacitor C2; the grounding end of the inverting amplifier INV, the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded GND; the output terminal of the comparator CMP is connected to the input terminal of the second buffer BUF2 and to one input terminal of the logic counter circuit; an output terminal of the second buffer BUF2 outputs a clock signal CLKO; the other input end of the logic counting circuit receives a power-on reset signal EN, and the output end respectively outputs a second switch control signal SW2, a third switch control signal SW3 and a fourth switch control signal SW4 to a second switch S2, a third switch S3 and a fourth switch S4 to control the second switch S2, the third switch S3 and the fourth switch S4 to be switched on or switched off; the power-on reset signal EN is output to the first switch S1, which controls the first switch S1 to be closed or opened.
In this embodiment, the power-on reset signal EN is a signal that maintains a low level before the power supply is powered on and changes to a high level after the power supply is powered on; the ring oscillator outputs an oscillation clock CLkring with the same or similar working frequency as the crystal oscillator; after the oscillation clock CLKring is started by the power-on reset signal EN (i.e., the power-on reset signal changes from a low level to a high level), the oscillation clock CLKring is injected into the input end of the crystal oscillator basic circuit through the first buffer BUF1, the third switch S3, the fourth switch S4 and the first resistor R1, the comparator CMP converts the sine wave oscillation output by the crystal oscillator basic circuit into a clock signal CLK, and the clock signal CLK is a square wave signal; the logic counting circuit counts the clock signal CLK output by the comparator CMP; before the power-on reset signal EN is started, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3 and the fourth switch S4 to be turned off; after the power-on reset signal EN is started and before the count value of the logic counting circuit reaches a required value, namely when the oscillation starting of the crystal oscillator basic circuit is not stable, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3 and the fourth switch S4 to be closed; after the power-on reset signal EN is activated and the count value reaches the required value, that is, after the crystal oscillator basic circuit starts oscillation and stabilizes, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3 and the fourth switch S4 to be turned off.
In this embodiment, the second switch S2 disconnects the power supply VDD from the ring oscillator after the crystal oscillator basic circuit starts to oscillate stably, so that the ring oscillator stops oscillating and power consumption is reduced; the third switch S3 and the fourth switch S4 connected between the ring oscillator and the first resistor R1 are used for disconnecting the ring oscillator from the crystal oscillator basic circuit after the crystal oscillator basic circuit starts oscillation and is stable, so that the influence of the oscillation clock CLkring output by the ring oscillator on the normal operation of the crystal oscillator basic circuit is prevented, and the interference of capacitive coupling on the crystal oscillator basic circuit is reduced; the first buffer BUF1 and the second buffer BUF2 each include two inverters connected in series for increasing the clock driving capability so that the clock signal has good rising and falling edges; the first resistor R1 is used for reducing the probability that the deviation of the working state of the basic crystal oscillator circuit is too large due to too strong driving capability of the excitation signal output to the basic crystal oscillator circuit, and the bias voltage needs to be reestablished after the ring oscillator stops outputting the excitation signal to the basic crystal oscillator circuit, thereby causing the basic crystal oscillator circuit to start oscillation for a longer time.
In this embodiment, two switches are connected between the ring oscillator and the first resistor R1, and the isolation is better than the isolation formed by only one switch.
In the present embodiment, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are all transmission gate switches; the power-on reset signal EN is output to the C end of the first switch S1, and the power-on reset signal EN is inverted and then output to the C inverted end of the first switch S1; before power-on, the power-on reset signal EN is at low level, and the first switch S1 is turned off; after power-on, a power-on reset signal EN is at a high level, the first switch S1 is closed, and a power supply VDD supplies power to the inverting amplifier INV; the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 are respectively output to the C terminal of the second switch S2, the C terminal of the third switch S3 and the C terminal of the fourth switch S4, and the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 are respectively output to the C inverse terminal of the second switch S2, the C inverse terminal of the third switch S3 and the C inverse terminal of the fourth switch S4 after being inverted; before power-on, the power-on reset signal EN is at a low level, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 are all at a low level, and the second switch S2, the third switch S3 and the fourth switch S4 are turned off; after power-on, the power-on reset signal EN changes to a high level, and before the count value of the logic counting circuit reaches a required value, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 change to a high level, and the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be closed; after power-on, the power-on reset signal EN changes to high level, and after the count value of the logic counter circuit reaches the required value, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 change to low level, and the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be turned off.
As shown in fig. 2, in the present embodiment, the ring oscillator includes a NAND gate NAND, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, and a fifth NOT gate NOT 5; the power supply end of the NAND gate NAND, the power supply end of the first NOT gate NOT1, the power supply end of the second NOT gate NOT2, the power supply end of the third NOT gate NOT3, the power supply end of the fourth NOT gate NOT4 and the power supply end of the fifth NOT gate NOT5 are connected with the output end of the second switch S2, one input end of the NAND gate NAND receives a power-on reset signal EN, the output end of the NAND gate is connected with the input end of the first NOT gate 1, the output end of the first NOT gate 1 is connected with the input end of the second NOT gate NOT2, the output end of the second NOT gate 2 is connected with the input end of the third NOT gate 3, and the output end of the fourth NOT gate 4 is connected with the input end of the fifth NOT gate 5 and the other input end of the NAND gate; an output terminal of the fifth NOT gate NOT5 outputs an oscillation clock CLKring.
In the present embodiment, the ring oscillator outputs the oscillation clock CLKring only when the power-on reset signal EN becomes high level and the second switch S2 is closed and the power supply VDD is connected.
As shown in fig. 3, in the present embodiment, the logic counting circuit includes an AND gate AND, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a first NOT gate NOT _ D1, a second NOT gate NOT _ D2, a third NOT gate NOT _ D3, a fourth NOT gate NOT _ D4, a fifth NOT gate NOT _ D5, a sixth NOT gate NOT _ D6, AND three output NOT gates NOT; one input end of the AND gate AND is connected with the clock signal CLK output by the comparator CMP, the other input end of the AND gate AND is used for receiving the power-on reset signal EN, AND the output end of the AND gate AND is connected with the clock signal input end Clk of the first D flip-flop D1; the D port of the first D flip-flop D1 is connected with the output end of the first NOT _ D1, and the Q port is connected with the input end of the first NOT _ D1 and the clock signal input end Clk of the second D flip-flop D2; the D port of the second D flip-flop D2 is connected to the output terminal of the second NOT gate NOT _ D2, and the Q port is connected to the input terminal of the second NOT gate NOT _ D2 and the clock signal input terminal Clk of the third D flip-flop D3; the D port of the third D flip-flop D3 is connected with the output end of the third NOT _ D3, and the Q port is connected with the input end of the third NOT _ D3 and the clock signal input end Clk of the fourth D flip-flop D4; the D port of the fourth D flip-flop D4 is connected to the output terminal of the fourth NOT gate NOT _ D4, and the Q port is connected to the input terminal of the fourth NOT gate NOT _ D4 and the clock signal input terminal Clk of the fifth D flip-flop D5; the D port of the fifth D flip-flop D5 is connected to the output terminal of the fifth NOT gate NOT _ D5, the Q port is connected to the input terminal of the fifth NOT gate NOT _ D5 and the input terminal of the sixth NOT gate NOT _ D6, and the output terminal of the sixth NOT gate NOT _ D6 is connected to the clock signal input terminal Clk of the sixth D flip-flop D6; a D port of the sixth D flip-flop D6 is connected to a Reset port, a Q port is connected to input terminals of three NOT gates, and output terminals of the three NOT gates output a second switch control signal SW2, a third switch control signal SW3, and a fourth switch control signal SW4, respectively; the Reset terminal of the first D flip-flop D1, the Reset terminal of the second D flip-flop D2, the Reset terminal of the third D flip-flop D3, the Reset terminal of the fourth D flip-flop D4, the Reset terminal of the fifth D flip-flop D5 and the Reset terminal of the sixth D flip-flop D6 are all connected to the power-on Reset signal EN.
In the embodiment, the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, the fifth D flip-flop D5 and the sixth D flip-flop D6 are all rising edge flip-flops; the signal output from the Q port of the sixth D flip-flop D6 is 2 times the clock signal CLK(6-1)I.e. 25At one rising edge (i.e. logic counter circuit count value of 2)5One) from a low level to a high level, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the corresponding three output NOT gates NOT are changed from a high level to a low level, and the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be changed from a closed state to an open state.
Example two
The difference between this embodiment and the first embodiment is: does not include the fourth switch S4; the other end of the third switch S3 is directly connected to one end of the first resistor R1; the logic counter circuit includes only two output NOT gates NOT, which output the second switch control signal SW2 and the third switch control signal SW3 to the second switch S2 and the third switch S3 to control the second switch S2 and the third switch S3 to be turned on or off.
EXAMPLE III
The difference between this embodiment and the first or second embodiment is: comprises a first switch S1, a second switch S2, a third switch S3 … …, an Nth switch1Switch SN1，N1Is a positive integer, and N1Not less than 3; third switches S3 to nth1Switch SN1After being connected in series, the output end of the ring oscillator is connected between the output end of the ring oscillator and the first resistor R1; the logic counting circuit comprises (N)1-1) output NOT gates (N)1-1) NOT output the second switch control signal SW2 and the third switch control signal SW3 … …1Switch control signal SWN1For the second switch S2, the third switch S3 … …, the Nth1Switch SN1Controlling the second switch S2 and the third switch S3 … … to the Nth1Switch SN1Closed or open.
Example four
The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment is that: does not include the first switch S1 and the second switch S2; the power supply VDD is directly connected with the power supply end of the ring oscillator and the power supply end of the inverting amplifier INV.
In the present embodiment, the logic count circuit includes (N)1-2) output NOTs, (N)1-2) output NOTs respectively output the third switch control signals SW3 to Nth1Switch control signal SWN1To the third switches S3 to N1Switch SN1Controlling the third switches S3 to Nth1Switch SN1Closed or open.
EXAMPLE five
The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment is that: the ring oscillator does NOT include the fourth NOT gate NOT4 and the fifth NOT gate NOT 5; the first NOT gate 1, the second NOT gate 2 and the third NOT gate 3 are connected in series, the input end of the first NOT gate 1 is connected with the output end of the NAND gate, and the output end of the second NOT gate 2 is connected with the other input end of the NAND gate; an output terminal of the third NOT gate NOT3 outputs an oscillation clock CLKring.
EXAMPLE six
The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment or the fifth embodiment is that: the ring oscillator comprises a NAND gate, a first NOT1, a second NOT2, and an Nth NOT3 … …2NOTN gate2，N23, 5, 7, 9, 11 … …, i.e. N2Taking an odd number more than or equal to 3; one input end of the NAND gate is connected with the power-on reset signal EN, the output end of the NAND gate is connected with the input end of the first NOT1, and the first NOT1, the second NOT2 and the third NOT3 … … are connected with the Nth NOT3 … …2NOTN gate2Connected in series, no (N)2-1) NOT (N)2-1) is connected to another input of the first NOT gate NOT1, nth2NOTN gate2The output terminal of which outputs an oscillation clock CLKring.
EXAMPLE seven
The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment or the fifth embodiment or the sixth embodiment is that: the logic counting circuit comprises an AND gate AND, a first D flip-flop D1, a second D flip-flop D2, a first NOT _ D1, a second NOT _ D2 AND an output NOT; one input end of the AND gate AND is connected with the clock signal CLK output by the comparator CMP, the other input end of the AND gate AND is used for receiving the power-on reset signal EN, AND the output end of the AND gate AND is connected with the clock signal input end Clk of the first D flip-flop D1; the D port of the first D flip-flop D1 is connected to the output terminal of the first NOT gate NOT _ D1, the Q port is connected to the input terminal of the first NOT gate NOT _ D1 and the input terminal of the second NOT gate NOT _ D2, and the output terminal of the second NOT gate NOT _ D2 is connected to the clock signal input terminal Clk of the second D flip-flop D2; the D port of the second D flip-flop D2 is connected to the Reset port, and the Q ports are respectively connected to the inputs of the corresponding output NOT gates NOT.
In this embodiment, the signal output from the Q port of the second D flip-flop D2 changes from low level to high level at 2 rising edges of the clock signal CLK (i.e., the count value of the logic counter circuit is two), the switch control signal output from the corresponding output NOT gate changes from high level to low level, and the control switch changes from closed to open.
Example eight
The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment or the fifth embodiment or the sixth embodiment or the seventh embodiment is that: the logic counting circuit comprises an AND gate, a first D flip-flop D1, a second D flip-flop D2 … …, an Nth flip-flop3A D flip-flop DN3A first NOT _ D1, a second NOT _ D2 … …, an Nth NOT _ D13NOT _ DN of NOT gate3And an output NOT, N3Is a positive integer, and N3Not less than 3; one input end of the AND gate AND is connected with the clock signal CLK output by the comparator CMP, the other input end is connected with the power-on reset signal EN, AND the output end is connected with the first oneThe clock signal input end Clk of the D trigger D1 is connected; the D port of the nth D flip-flop Dn is connected to the output terminal of the nth NOT gate NOT _ Dn, the Q port is connected to the input terminal of the nth NOT gate NOT _ Dn and the clock signal input terminal Clk of the (N +1) th D flip-flop D (N +1), and N is 1 to (N +1)3-2); (N) th3D port of-1) D flip-flop D5 and (N)3-1) NOT _ D5 NOTs (N)3-1) output terminal connection, Q port and (N) th3-1) NOT _ D (N) NOTs3-1) input and Nth3NOT _ DN of NOT gate3Is connected to the input terminal of the N3NOT _ DN of NOT gate3And the output terminal of (1) and3a D flip-flop DN3The clock signal input terminal Clk of the first switching element is connected; n th3A D flip-flop DN3The D port of (1) is connected with the Reset port, and the Q port of (2) is respectively connected with the input end of the corresponding output NOT gate (NOT).
In this embodiment, the Nth3A D flip-flop DN32 of the clock signal CLK(N3-1)One rising edge (i.e. logic counter circuit count value of 2)(N3-1)And) the switch control signal output by the corresponding NOT gate NOT changes from high level to low level, and the control switch changes from closed to open.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. A fast start-up crystal oscillator circuit comprising a fundamental oscillator circuit, characterized by: also comprises a ring oscillator, a comparator, a logic counting circuit, a third switch to an Nth switch1Switch, N1Is a positive integer, and N1Not less than 3; the power supply end of the ring oscillator and the power supply end of the basic oscillation circuit are connected with a power supply; the input of the ring oscillator receives a power-up enableSignal, the output terminal is connected with the input terminal of the third switch, from the third switch to the Nth switch1Switches connected in series in sequence, Nth1The output end of the switch is connected with the input end of the basic oscillating circuit; the input end and the output end of the basic oscillating circuit are respectively connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output ends respectively output a third switch control signal to the Nth switch1A switch control signal for controlling the third switch to the Nth switch1The switch is closed or opened.
2. The fast start up crystal oscillator circuit of claim 1, further comprising: the device also comprises a first switch and a second switch; the first switch is connected between a power supply and the basic oscillating circuit, the input end of the first switch is connected with the power supply, and the output end of the first switch is connected with the power supply end of the basic oscillating circuit; the second switch is connected between a power supply and the ring oscillator, the input end of the second switch is connected with the power supply, and the output end of the second switch is connected with the power supply end of the ring oscillator; the output end of the logic counting circuit outputs a second switch control signal to control the second switch to be switched on or switched off; the power-on reset signal controls the first switch to be switched on or switched off.
3. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate and (N)1-1) or (N)1-2) output not gates, one input of the and gate receiving the clock signal output by the comparator, the other input receiving the power-on reset signal, the output being connected to the clock signal input of the first D flip-flop, the D port of the first D flip-flop being connected to the output of the first not gate, the Q port being connected to the input of the first not gate and to the input of the second not gate, the output of the second not gate being connected to the clock signal input of the second D flip-flop, the D port of the second D flip-flop being connected to the D port of the second D flip-flopConnected with Reset port, Q port is respectively connected with (N)1-1) or (N)1-2) input connections of output NOT-gates,
or, the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop … … Nth3A D flip-flop, a first NOT gate, a second NOT gate … … Nth3A NOT gate and (N)1-1) or (N)1-2) output not gates, N3Is a positive integer, and N3And more than or equal to 3, one input end of the AND gate receives the clock signal output by the comparator, the other input end of the AND gate receives the power-on reset signal, the output end of the AND gate is connected with the clock signal input end of the first D flip-flop, the D port of the nth D flip-flop is connected with the output end of the nth NOT gate, the Q port of the Nth NOT gate is connected with the input end of the nth NOT gate and the clock signal input end of the (N +1) th D flip-flop, and N is 1 to (N is)3-2), N3-1) D port of D flip-flop and (N)3-1) the output of the NOT gate is connected, the Q port is connected with the (N) th3-1) inputs of NOT gates and Nth3The input terminals of the NOT gates are connected, N3The output end of the NOT gate and the Nth gate3The clock signal input ends of the D flip-flops are connected, the Nth flip-flop3The D port of each D flip-flop is connected with the Reset port, and the Q port is respectively connected with (N)1-1) or (N)1-2) input connections of output not gates;
said (N)1-1) or (N)1-2) the output ends of the output NOT gates respectively control the second switch and the third switch … … Nth switch1Switches or third to Nth switches1A switch control signal for the switch; the Reset end of the first D flip-flop and the Reset end … … of the second D flip-flop are Nth3The Reset terminals of the D flip-flops all receive power-on Reset signals.
4. The fast start up crystal oscillator circuit of claim 3, wherein: the ring oscillator comprises a NAND gate, a first NOT gate, a second NOT gate and a third NOT gate … … Nth2NOT gate, N23, 7, 9, 11 … …; one input end of the NAND gate receives the power-on reset signal and outputsThe output end is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … Nth2NOT gates connected in series, N2-1) the output of the not-gate is connected to the other input of the first not-gate, N2The output end of the NOT gate outputs an oscillation clock.
5. The fast start up crystal oscillator circuit of claim 3, wherein: the device also comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.
6. The fast start up crystal oscillator circuit of claim 4, wherein: the circuit also comprises a first resistor; the first resistor is connected into the Nth resistor1Between the switch and the basic crystal oscillator circuit, one end is connected with the Nth1The output end of the switch is connected, and the other end of the switch is connected with the input end of the basic crystal oscillator circuit.
7. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the ring oscillator comprises a NAND gate, a first NOT gate, a second NOT gate and a third NOT gate … … Nth2NOT gate, N23, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th2NOT gates connected in series, N2-1) the output of the not-gate is connected to the other input of the first not-gate, N2The output end of the NOT gate outputs an oscillation clock.
8. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the device also comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.
9. The fast start up crystal oscillator circuit of claim 8, further comprising: the circuit also comprises a first resistor; the first resistor is connected into the Nth resistor1Between the switch and the basic crystal oscillator circuit, one end is connected with the Nth1The output end of the switch is connected, and the other end of the switch is connected with the input end of the basic crystal oscillator circuit.
10. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the crystal oscillator basic circuit comprises an inverting amplifier, a feedback resistor, a crystal oscillator, a first capacitor and a second capacitor; the input end of the inverting amplifier INV and the Nth1The output end of the switch, one input end of the comparator, one end of the feedback resistor, one end of the crystal oscillator and one end of the first capacitor are connected; the output end of the inverting amplifier is connected with the other input end of the comparator, the other end of the feedback resistor, the other end of the crystal oscillator and one end of the second capacitor; the power supply end of the inverting amplifier is connected with the other end of the first switch or directly connected with a power supply; and the grounding end of the inverting amplifier, the other end of the first capacitor and the other end of the second capacitor are grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911313758.XA CN110971192A (en) | 2019-12-17 | 2019-12-17 | Crystal oscillator circuit capable of starting oscillation rapidly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911313758.XA CN110971192A (en) | 2019-12-17 | 2019-12-17 | Crystal oscillator circuit capable of starting oscillation rapidly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110971192A true CN110971192A (en) | 2020-04-07 |
Family
ID=70035156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911313758.XA Pending CN110971192A (en) | 2019-12-17 | 2019-12-17 | Crystal oscillator circuit capable of starting oscillation rapidly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110971192A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111565041A (en) * | 2020-07-14 | 2020-08-21 | 恒玄科技(上海)股份有限公司 | Rapid oscillation starting circuit and rapid oscillation starting method |
| CN111817667A (en) * | 2020-08-31 | 2020-10-23 | 杭州优智联科技有限公司 | Crystal oscillation circuit capable of starting oscillation rapidly and oscillation starting method |
| CN113567761A (en) * | 2021-07-27 | 2021-10-29 | 成都通量科技有限公司 | CMOS full-integrated electromagnetic detection radio frequency front-end sensor |
| CN114024506A (en) * | 2022-01-06 | 2022-02-08 | 浙江赛思电子科技有限公司 | Open-loop crystal oscillator circuit |
| CN115208320A (en) * | 2022-09-16 | 2022-10-18 | 中国电子科技集团公司第十四研究所 | Crystal oscillator circuit with duty ratio calibration and quick start oscillation |
-
2019
- 2019-12-17 CN CN201911313758.XA patent/CN110971192A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111565041A (en) * | 2020-07-14 | 2020-08-21 | 恒玄科技(上海)股份有限公司 | Rapid oscillation starting circuit and rapid oscillation starting method |
| CN111565041B (en) * | 2020-07-14 | 2021-07-02 | 恒玄科技(上海)股份有限公司 | Rapid oscillation starting circuit and rapid oscillation starting method |
| CN111817667A (en) * | 2020-08-31 | 2020-10-23 | 杭州优智联科技有限公司 | Crystal oscillation circuit capable of starting oscillation rapidly and oscillation starting method |
| CN111817667B (en) * | 2020-08-31 | 2020-12-22 | 杭州优智联科技有限公司 | Crystal oscillation circuit capable of starting oscillation rapidly and oscillation starting method |
| CN113567761A (en) * | 2021-07-27 | 2021-10-29 | 成都通量科技有限公司 | CMOS full-integrated electromagnetic detection radio frequency front-end sensor |
| CN114024506A (en) * | 2022-01-06 | 2022-02-08 | 浙江赛思电子科技有限公司 | Open-loop crystal oscillator circuit |
| CN114024506B (en) * | 2022-01-06 | 2022-04-19 | 浙江赛思电子科技有限公司 | Open-loop crystal oscillator circuit |
| CN115208320A (en) * | 2022-09-16 | 2022-10-18 | 中国电子科技集团公司第十四研究所 | Crystal oscillator circuit with duty ratio calibration and quick start oscillation |
| CN115208320B (en) * | 2022-09-16 | 2023-02-14 | 中国电子科技集团公司第十四研究所 | Crystal oscillator circuit with duty ratio calibration and quick start oscillation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110971192A (en) | Crystal oscillator circuit capable of starting oscillation rapidly | |
| US6831494B1 (en) | Voltage compensated integrated circuits | |
| US11245360B2 (en) | Oscillator circuit, chip and electronic device | |
| US10707843B2 (en) | Relaxation oscillator | |
| US7710177B2 (en) | Latch device having low-power data retention | |
| CN107612545B (en) | Low-power-consumption oscillator circuit with selectable frequency | |
| JP3258923B2 (en) | Semiconductor integrated circuit device | |
| WO2013130934A1 (en) | System for a clock shifter circuit | |
| CN112929009A (en) | RC relaxation oscillator | |
| US20060158232A1 (en) | Bus driver circuit | |
| CN112994422A (en) | Semiconductor integrated circuit and method for controlling semiconductor integrated circuit | |
| US8008959B2 (en) | Flip-flop circuit that latches inputted data | |
| CN104518757A (en) | Relaxation oscillator | |
| CN210490799U (en) | SoC built-in oscillating circuit | |
| EP3736981A2 (en) | Current-controlled oscillator | |
| US8803619B1 (en) | Relaxation oscillator with self-biased comparator | |
| CN211606495U (en) | Crystal oscillator circuit capable of starting oscillation rapidly | |
| EP0403047B1 (en) | A frequency divider circuit | |
| CN112994660B (en) | Trigger circuit and oscillator | |
| CN115276615A (en) | Clock signal frequency multiplier circuit outputting burr-free low duty ratio error | |
| US6914494B1 (en) | Very low current oscillator with variable duty cycle | |
| KR100525896B1 (en) | Rc pulse oscillator | |
| CN111030598A (en) | Crystal oscillator circuit with oscillation amplitude limiting function | |
| CN217238254U (en) | Clock oscillator's logic signal detection circuitry, MCU chip and BMS chip | |
| CN111786655B (en) | Crystal oscillator enabling circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |