CN211606495U - Crystal oscillator circuit capable of starting oscillation rapidly - Google Patents

Abstract

The utility model discloses a crystal oscillator circuit that shakes fast, including crystal oscillation circuit, ring oscillator, comparator, logic count circuit, third switch to Nth₁Switch, N₁Is a positive integer, and N₁Not less than 3; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch from the third switch to the Nth switch₁Switches connected in series in sequence, Nth₁The output end of the switch is connected with the input end of the crystal oscillation circuit; the input and output of the crystal oscillation circuit are connected with two input ends of the comparatorConnecting; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives the power-on reset signal, and the output ends respectively output a third switch control signal to the Nth switch₁A switch control signal for controlling the third switch to the Nth switch₁The switch is closed or opened; this practicality gives crystal oscillation circuit through ring oscillator output excitation signal for the start-up time of shaking.

Description

Crystal oscillator circuit capable of starting oscillation rapidly

Technical Field

The utility model relates to the technical field of integrated circuits, especially, relate to a crystal oscillator circuit that shakes fast.

Background

The crystal oscillator has good frequency accuracy and stability, small volume and low power consumption, is often used as a time frequency reference, and is widely applied to systems such as communication, radar, navigation and guidance. The crystal oscillator can provide high-precision clock signals for various electronic systems, wherein some application environments require that the oscillation starting time of the crystal oscillator is as short as possible, for example, in an internet of things system, switching between sleep and activation is required to be performed continuously, and in order to achieve the shorter switching time, the oscillation starting time of the crystal oscillator is required to be shorter. How to realize the rapid oscillation starting of the crystal oscillator becomes a technical problem to be solved by the technical personnel in the field.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a quick crystal oscillator circuit that starts to shake realizes quick start to shake.

For the purpose of the present application, a technical solution adopted by the present application is as follows:

a fast start-up crystal oscillator circuit comprises a crystal oscillator circuit, and the fast start-up crystal oscillator circuit further comprises a ring oscillator, a comparator, a logic counting circuit, a first switch, a second switch, a third switch … … N₁Switch, N₁Is a positive integer, and N₁Not less than 3; the input end of the first switch is connected with a power supply, and the output end of the first switch is connected with the power supply end of the crystal oscillation circuit; the input end of the second switch is connected with a power supply, and the output end of the second switch is connected with the power supply end of the ring oscillator; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch, and the third switch is connected with the Nth switch₁Switches connected in series in sequence, Nth₁The output end of the switch is connected with the input end of the crystal oscillation circuitConnecting; the input end and the output end of the crystal oscillation circuit are respectively connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output end of the logic counting circuit respectively outputs a second switch control signal and a third switch control signal … … Nth₁The switch control signal controls the second switch and the third switch … … to the Nth switch₁The switch is closed or opened; the power-on reset signal controls the first switch to be switched on or switched off.

For the purpose of the present application, another technical solution adopted by the present application is as follows:

the crystal oscillator circuit capable of starting oscillation quickly comprises a crystal oscillator circuit, a ring oscillator, a comparator, a logic counting circuit, a third switch and an Nth switch₁Switch, N₁Is a positive integer, and N₁Not less than 3; the power supply end of the ring oscillator and the power supply end of the crystal oscillation circuit are connected with a power supply; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch, and the third switch is connected with the Nth switch₁Switches connected in series in sequence, Nth₁The output end of the switch is connected with the input end of the crystal oscillation circuit; the input end and the output end of the crystal oscillation circuit are respectively connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output ends respectively output a third switch control signal to the Nth switch₁A switch control signal for controlling the third switch to the Nth switch₁The switch is closed or opened.

In a specific embodiment, the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate and (N)₁-1) or (N)₁-2) output not gates, one input of the and gate receiving the clock signal output by the comparator, the other input receiving the power-on reset signal and the outputThe output end of the first D flip-flop is connected with a clock signal input end of a first D flip-flop, a D port of the first D flip-flop is connected with an output end of a first NOT gate, a Q port of the first D flip-flop is connected with an input end of the first NOT gate and an input end of a second NOT gate, an output end of the second NOT gate is connected with a clock signal input end of a second D flip-flop, a D port of the second D flip-flop is connected with a Reset port, and Q ports are respectively connected with (N)₁-1) or (N)₁-2) input connections of output NOT-gates,

or, the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop … … Nth₃A D flip-flop, a first NOT gate, a second NOT gate … … Nth₃A NOT gate and (N)₁-1) or (N)₁-2) output not gates, N₃Is a positive integer, and N₃And more than or equal to 3, one input end of the AND gate receives the clock signal output by the comparator, the other input end of the AND gate receives the power-on reset signal, the output end of the AND gate is connected with the clock signal input end of the first D flip-flop, the D port of the nth D flip-flop is connected with the output end of the nth NOT gate, the Q port of the Nth NOT gate is connected with the input end of the nth NOT gate and the clock signal input end of the (N +1) th D flip-flop, and N is 1 to (N is)₃-2), N₃-1) D port of D flip-flop and (N)₃-1) the output of the NOT gate is connected, the Q port is connected with the (N) th₃-1) inputs of NOT gates and Nth₃The input terminals of the NOT gates are connected, N₃The output end of the NOT gate and the Nth gate₃The clock signal input ends of the D flip-flops are connected, the Nth flip-flop₃The D port of each D flip-flop is connected with the Reset port, and the Q port is respectively connected with (N)₁-1) or (N)₁-2) input connections of output not gates;

said (N)₁-1) or (N)₁-2) the output ends of the output NOT gates respectively control the second switch and the third switch … … Nth switch₁Switches or third to Nth switches₁A switch control signal for the switch; the Reset end of the first D flip-flop and the Reset end … … of the second D flip-flop are Nth₃The Reset terminals of the D flip-flops all receive power-on Reset signals.

As a specific embodimentThe ring oscillator comprises a NAND gate, a first NOT gate, a second NOT gate, a third NOT gate … … Nth₂NOT gate, N₂3, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th₂NOT gates connected in series, N₂-1) the output of the not-gate is connected to the other input of the first not-gate, N₂The output end of the NOT gate outputs an oscillation clock.

Further, the fast-start crystal oscillator circuit further comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.

Further, the fast-start crystal oscillator circuit further comprises a first resistor; the first resistor is connected into the Nth resistor₁Between the switch and the crystal oscillation circuit, one terminal is connected to the Nth terminal₁The output end of the switch is connected, and the other end of the switch is connected with the input end of the crystal oscillation circuit.

In a specific embodiment, the ring oscillator includes nand gate, first not gate, second not gate, third not gate … … Nth gate₂NOT gate, N₂3, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th₂NOT gates connected in series, N₂-1) the output of the not-gate is connected to the other input of the first not-gate, N₂The output end of the NOT gate outputs an oscillation clock.

Further, the fast-start crystal oscillator circuit further comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.

Further, the fast-start crystal oscillator circuit further comprises a first resistor; the first resistor is connected into the Nth resistor₁Between the switch and the crystal oscillation circuit, one terminal is connected to the Nth terminal₁The output end of the switch is connected, and the other end of the switch is connected with the input end of the crystal oscillation circuit.

As a specific implementation mode, the crystal oscillation circuit comprises an inverting amplifier, a feedback resistor, a crystal oscillator, a first capacitor and a second capacitor; the input end of the inverting amplifier INV and the Nth₁The output end of the switch, one input end of the comparator, one end of the feedback resistor, one end of the crystal oscillator and one end of the first capacitor are connected; the output end of the inverting amplifier is connected with the other input end of the comparator, the other end of the feedback resistor, the other end of the crystal oscillator and one end of the second capacitor; the power supply end of the inverting amplifier is connected with the other end of the first switch or directly connected with a power supply; and the grounding end of the inverting amplifier, the other end of the first capacitor and the other end of the second capacitor are grounded.

This practical beneficial effect:

according to the technical scheme provided by the utility model, this practicality gives crystal oscillation circuit's input through ring oscillator output excitation signal for crystal oscillation circuit's the time of starting to vibrate, counts the clock signal of crystal oscillation circuit's output through logic counting circuit, and control ring oscillator stops output excitation after crystal oscillation circuit starts to vibrate stably and gives crystal oscillation circuit. Meanwhile, the second switch disconnects the power supply from the ring oscillator after the crystal oscillation circuit starts oscillation stably, so that the ring oscillator stops oscillation, power consumption is reduced, and the third switch is connected to the Nth switch₁After the crystal oscillation circuit starts oscillation stably, the switch disconnects the ring oscillator from the crystal oscillation circuit, so that the influence of an oscillation clock output by the ring oscillator on the normal work of the crystal oscillation circuit is prevented, and the interference of capacitive coupling on the crystal oscillation circuit is reduced. Furthermore, the utility model increases the first buffer and the second bufferThe clock driving capability is such that the clock signal has good rising and falling edges. Further, this practicality is through first resistance partial pressure, and it is too strong to reduce because the excitation signal driving force of exporting for crystal oscillation circuit, and the operating condition deviation that leads to crystal oscillation circuit is too big, and ring oscillator stops to export the excitation signal and need reestablish offset voltage for crystal oscillation circuit after, and then leads to crystal oscillation circuit to start the longer probability of shake time.

Drawings

In order to more clearly illustrate the embodiments of the present invention, the drawings used in the embodiments will be briefly described below. The drawings in the following description are only examples of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a block diagram of a fast-start crystal oscillator circuit according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a ring oscillator according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a logic counter circuit according to a first embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Example one

As shown in FIG. 1, a fast start-up crystal oscillator circuit includes a crystal oscillation circuit, a ring oscillator, a first buffer BUF1, a second buffer BUF2, a comparator CMP, a logic counter circuit, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; the crystal oscillation circuit comprises an inverting amplifier INV, a feedback resistor RF, a crystal oscillator XTAL, a first capacitor C1 and a second capacitor C2; the input end of the first switch S1 is connected with a power supply VDD, and the output end is connected with the power supply end of the inverting amplifier INV; the input end of the second switch S2 is connected with a power supply VDD, and the output end is connected with the power supply end of the ring oscillator; the input end of the ring oscillator receives the power-on enable signal EN, and the output end of the ring oscillator is connected with the input end of the first buffer BUF 1; the output end of the first buffer BUF1 is connected with the input end of a third switch S3, the output end of the third switch S3 is connected with the input end of a fourth switch S4, and the output end of the fourth switch S4 is connected with one end of a first resistor R1; the other end of the first resistor R1 is connected to the input end of the inverting amplifier INV, the inverting input end of the comparator CMP, one end of the feedback resistor RF, one end of the crystal oscillator XTAL, and one end of the first capacitor C1; the output end of the inverting amplifier INV is connected to the non-inverting input end of the comparator CMP, the other end of the feedback resistor RF, the other end of the crystal oscillator XTAL, and one end of the second capacitor C2; the grounding end of the inverting amplifier INV, the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded GND; the output terminal of the comparator CMP is connected to the input terminal of the second buffer BUF2 and to one input terminal of the logic counter circuit; an output terminal of the second buffer BUF2 outputs a clock signal CLKO; the other input end of the logic counting circuit receives a power-on reset signal EN, and the output end respectively outputs a second switch control signal SW2, a third switch control signal SW3 and a fourth switch control signal SW4 to a second switch S2, a third switch S3 and a fourth switch S4 to control the second switch S2, the third switch S3 and the fourth switch S4 to be switched on or switched off; the power-on reset signal EN is output to the first switch S1, which controls the first switch S1 to be closed or opened.

In this embodiment, the power-on reset signal EN is a signal that maintains a low level before the power supply is powered on and changes to a high level after the power supply is powered on; the ring oscillator outputs an oscillation clock CLkring with the same or similar working frequency as the crystal oscillator; after the oscillation clock CLKring is started by the power-on reset signal EN (i.e., the power-on reset signal changes from a low level to a high level), the oscillation clock CLKring is injected into the input end of the crystal oscillation circuit through the first buffer BUF1, the third switch S3, the fourth switch S4 and the first resistor R1, the comparator CMP converts the sine wave oscillation output by the crystal oscillation circuit into a clock signal CLK, and the clock signal CLK is a square wave signal; the logic counting circuit counts the clock signal CLK output by the comparator CMP; before the power-on reset signal EN is started, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3 and the fourth switch S4 to be turned off; after the power-on reset signal EN is started and before the count value of the logic counting circuit reaches a required value, namely the oscillation starting of the crystal oscillation circuit is not stable, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the logic counting circuit control the second switch S2, the third switch S3 and the fourth switch S4 to be closed; after the power-on reset signal EN is activated, when the count value reaches a desired value, that is, after the oscillation start of the crystal oscillation circuit is stable, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the logic count circuit control the second switch S2, the third switch S3 and the fourth switch S4 to be turned off.

In this embodiment, the second switch S2 disconnects the power supply VDD from the ring oscillator after the crystal oscillation circuit starts oscillation and stabilizes, so that the ring oscillator stops oscillating, thereby reducing power consumption; the third switch S3 and the fourth switch S4 connected between the ring oscillator and the first resistor R1 are used for disconnecting the ring oscillator from the crystal oscillator circuit after the crystal oscillator circuit starts oscillation and is stable, so that the influence of the oscillation clock CLkring output by the ring oscillator on the normal operation of the crystal oscillator circuit is prevented, and the interference of capacitive coupling on the crystal oscillator circuit is reduced; the first buffer BUF1 and the second buffer BUF2 each include two inverters connected in series for increasing the clock driving capability so that the clock signal has good rising and falling edges; the first resistor R1 is used to reduce the probability that the driving capability of the excitation signal output to the crystal oscillation circuit is too strong, which results in too large deviation of the operating state of the crystal oscillation circuit, and the ring oscillator needs to reestablish the bias voltage after stopping outputting the excitation signal to the crystal oscillation circuit, which results in longer oscillation starting time of the crystal oscillation circuit.

In this embodiment, two switches are connected between the ring oscillator and the first resistor R1, and the isolation is better than the isolation formed by only one switch.

In the present embodiment, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all transmission gate switches; the power-on reset signal EN is output to the C end of the first switch S1, and the power-on reset signal EN is inverted and then output to the C inverted end of the first switch S1; before power-on, the power-on reset signal EN is at low level, and the first switch S1 is turned off; after power-on, a power-on reset signal EN is at a high level, the first switch S1 is closed, and a power supply VDD supplies power to the inverting amplifier INV; the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 are respectively output to the C terminal of the second switch S2, the C terminal of the third switch S3 and the C terminal of the fourth switch S4, and the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 are respectively output to the C inverse terminal of the second switch S2, the C inverse terminal of the third switch S3 and the C inverse terminal of the fourth switch S4 after being inverted; before power-on, the power-on reset signal EN is at a low level, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 are all at a low level, and the second switch S2, the third switch S3 and the fourth switch S4 are turned off; after power-on, the power-on reset signal EN changes to a high level, and before the count value of the logic counting circuit reaches a required value, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 change to a high level, and the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be closed; after power-on, the power-on reset signal EN changes to high level, and after the count value of the logic counter circuit reaches the required value, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 change to low level, and the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be turned off.

As shown in fig. 2, in the present embodiment, the ring oscillator includes a NAND gate NAND, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, and a fifth NOT gate NOT 5; the power supply end of the NAND gate NAND, the power supply end of the first NOT gate NOT1, the power supply end of the second NOT gate NOT2, the power supply end of the third NOT gate NOT3, the power supply end of the fourth NOT gate NOT4 and the power supply end of the fifth NOT gate NOT5 are connected with the output end of the second switch S2, one input end of the NAND gate NAND receives a power-on reset signal EN, the output end of the NAND gate is connected with the input end of the first NOT gate 1, the output end of the first NOT gate 1 is connected with the input end of the second NOT gate NOT2, the output end of the second NOT gate 2 is connected with the input end of the third NOT gate 3, and the output end of the fourth NOT gate 4 is connected with the input end of the fifth NOT gate 5 and the other input end of the NAND gate; an output terminal of the fifth NOT gate NOT5 outputs an oscillation clock CLKring.

In the present embodiment, the ring oscillator outputs the oscillation clock CLKring only when the power-on reset signal EN becomes high level and the second switch S2 is closed and the power supply VDD is connected.

As shown in fig. 3, in the present embodiment, the logic counting circuit includes an AND gate AND, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a first NOT gate NOT _ D1, a second NOT gate NOT _ D2, a third NOT gate NOT _ D3, a fourth NOT gate NOT _ D4, a fifth NOT gate NOT _ D5, a sixth NOT gate NOT _ D6, AND three output NOT gates NOT; one input end of the AND gate AND is connected with the clock signal CLK output by the comparator CMP, the other input end of the AND gate AND is used for receiving the power-on reset signal EN, AND the output end of the AND gate AND is connected with the clock signal input end Clk of the first D flip-flop D1; the D port of the first D flip-flop D1 is connected with the output end of the first NOT _ D1, and the Q port is connected with the input end of the first NOT _ D1 and the clock signal input end Clk of the second D flip-flop D2; the D port of the second D flip-flop D2 is connected to the output terminal of the second NOT gate NOT _ D2, and the Q port is connected to the input terminal of the second NOT gate NOT _ D2 and the clock signal input terminal Clk of the third D flip-flop D3; the D port of the third D flip-flop D3 is connected with the output end of the third NOT _ D3, and the Q port is connected with the input end of the third NOT _ D3 and the clock signal input end Clk of the fourth D flip-flop D4; the D port of the fourth D flip-flop D4 is connected to the output terminal of the fourth NOT gate NOT _ D4, and the Q port is connected to the input terminal of the fourth NOT gate NOT _ D4 and the clock signal input terminal Clk of the fifth D flip-flop D5; the D port of the fifth D flip-flop D5 is connected to the output terminal of the fifth NOT gate NOT _ D5, the Q port is connected to the input terminal of the fifth NOT gate NOT _ D5 and the input terminal of the sixth NOT gate NOT _ D6, and the output terminal of the sixth NOT gate NOT _ D6 is connected to the clock signal input terminal Clk of the sixth D flip-flop D6; a D port of the sixth D flip-flop D6 is connected to a Reset port, a Q port is connected to input terminals of three NOT gates, and output terminals of the three NOT gates output a second switch control signal SW2, a third switch control signal SW3, and a fourth switch control signal SW4, respectively; the Reset terminal of the first D flip-flop D1, the Reset terminal of the second D flip-flop D2, the Reset terminal of the third D flip-flop D3, the Reset terminal of the fourth D flip-flop D4, the Reset terminal of the fifth D flip-flop D5 and the Reset terminal of the sixth D flip-flop D6 are all connected to the power-on Reset signal EN.

In the embodiment, the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, the fifth D flip-flop D5 and the sixth D flip-flop D6 are all rising edge flip-flops; the signal output from the Q port of the sixth D flip-flop D6 is 2 times the clock signal CLK^(6-1)I.e. 2⁵At one rising edge (i.e. logic counter circuit count value of 2)⁵One) from a low level to a high level, the second switch control signal SW2, the third switch control signal SW3 and the fourth switch control signal SW4 output by the corresponding three output NOT gates NOT are changed from a high level to a low level, and the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be changed from a closed state to an open state.

Example two

The difference between this embodiment and the first embodiment is: does not include the fourth switch S4; the other end of the third switch S3 is directly connected to one end of the first resistor R1; the logic counter circuit includes only two output NOT gates NOT, which output the second switch control signal SW2 and the third switch control signal SW3 to the second switch S2 and the third switch S3 to control the second switch S2 and the third switch S3 to be turned on or off.

EXAMPLE III

The difference between this embodiment and the first or second embodiment is: comprises a first switch S1, a second switch S2, a third switch S3 … …, an Nth switch₁Switch SN₁，N₁Is a positive integer, and N₁Not less than 3; third switches S3 to nth₁Switch SN₁After being connected in series, the output end of the ring oscillator is connected between the output end of the ring oscillator and the first resistor R1; the logic counting circuit comprises (N)₁-1) output NOT gates (N)₁-1) NOT output the second switch control signal SW2 and the third switch control signal SW3 … …₁Switch control signal SWN₁For the second switch S2, the third switch S3 … …, the Nth₁Switch SN₁Controlling the second switch S2 and the third switch S3 … … to the Nth₁Switch SN₁Closed or open.

Example four

The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment is that: does not include the first switch S1 and the second switch S2; the power supply VDD is directly connected with the power supply end of the ring oscillator and the power supply end of the inverting amplifier INV.

In the present embodiment, the logic count circuit includes (N)₁-2) output NOTs, (N)₁-2) output NOTs respectively output the third switch control signals SW3 to Nth₁Switch control signal SWN₁To the third switches S3 to N₁Switch SN₁Controlling the third switches S3 to Nth₁Switch SN₁Closed or open.

EXAMPLE five

The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment is that: the ring oscillator does NOT include the fourth NOT gate NOT4 and the fifth NOT gate NOT 5; the first NOT gate 1, the second NOT gate 2 and the third NOT gate 3 are connected in series, the input end of the first NOT gate 1 is connected with the output end of the NAND gate, and the output end of the second NOT gate 2 is connected with the other input end of the NAND gate; an output terminal of the third NOT gate NOT3 outputs an oscillation clock CLKring.

EXAMPLE six

The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment or the fifth embodiment is that: the ring oscillator comprises a NAND gate, a first NOT1, a second NOT2 and a third NOT3 … …N th₂NOTN gate₂，N₂3, 5, 7, 9, 11 … …, i.e. N₂Taking an odd number more than or equal to 3; one input end of the NAND gate is connected with the power-on reset signal EN, the output end of the NAND gate is connected with the input end of the first NOT1, and the first NOT1, the second NOT2 and the third NOT3 … … are connected with the Nth NOT3 … …₂NOTN gate₂Connected in series, no (N)₂-1) NOT (N)₂-1) is connected to another input of the first NOT gate NOT1, nth₂NOTN gate₂The output terminal of which outputs an oscillation clock CLKring.

EXAMPLE seven

The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment or the fifth embodiment or the sixth embodiment is that: the logic counting circuit comprises an AND gate AND, a first D flip-flop D1, a second D flip-flop D2, a first NOT _ D1, a second NOT _ D2 AND an output NOT; one input end of the AND gate AND is connected with the clock signal CLK output by the comparator CMP, the other input end of the AND gate AND is used for receiving the power-on reset signal EN, AND the output end of the AND gate AND is connected with the clock signal input end Clk of the first D flip-flop D1; the D port of the first D flip-flop D1 is connected to the output terminal of the first NOT gate NOT _ D1, the Q port is connected to the input terminal of the first NOT gate NOT _ D1 and the input terminal of the second NOT gate NOT _ D2, and the output terminal of the second NOT gate NOT _ D2 is connected to the clock signal input terminal Clk of the second D flip-flop D2; the D port of the second D flip-flop D2 is connected to the Reset port, and the Q ports are respectively connected to the inputs of the corresponding output NOT gates NOT.

In this embodiment, the signal output from the Q port of the second D flip-flop D2 changes from low level to high level at 2 rising edges of the clock signal CLK (i.e., the count value of the logic counter circuit is two), the switch control signal output from the corresponding output NOT gate changes from high level to low level, and the control switch changes from closed to open.

Example eight

The difference between this embodiment and the first embodiment or the second embodiment or the third embodiment or the fourth embodiment or the fifth embodiment or the sixth embodiment or the seventh embodiment is that: the logic counting circuit comprises an AND gate AND AND a first D flip-flopD1, second D flip-flop D2 … … Nth₃A D flip-flop DN₃A first NOT _ D1, a second NOT _ D2 … …, an Nth NOT _ D1₃NOT _ DN of NOT gate₃And an output NOT, N₃Is a positive integer, and N₃Not less than 3; one input end of the AND gate AND is connected with the clock signal CLK output by the comparator CMP, the other input end of the AND gate AND is used for receiving the power-on reset signal EN, AND the output end of the AND gate AND is connected with the clock signal input end Clk of the first D flip-flop D1; the D port of the nth D flip-flop Dn is connected to the output terminal of the nth NOT gate NOT _ Dn, the Q port is connected to the input terminal of the nth NOT gate NOT _ Dn and the clock signal input terminal Clk of the (N +1) th D flip-flop D (N +1), and N is 1 to (N +1)₃-2); (N) th₃D port of-1) D flip-flop D5 and (N)₃-1) NOT _ D5 NOTs (N)₃-1) output terminal connection, Q port and (N) th₃-1) NOT _ D (N) NOTs₃-1) input and Nth₃NOT _ DN of NOT gate₃Is connected to the input terminal of the N₃NOT _ DN of NOT gate₃And the output terminal of (1) and₃a D flip-flop DN₃The clock signal input terminal Clk of the first switching element is connected; n th₃A D flip-flop DN₃The D port of (1) is connected with the Reset port, and the Q port of (2) is respectively connected with the input end of the corresponding output NOT gate (NOT).

In this embodiment, the Nth₃A D flip-flop DN₃2 of the clock signal CLK^(N3-1)One rising edge (i.e. logic counter circuit count value of 2)^(N3-1)And) the switch control signal output by the corresponding NOT gate NOT changes from high level to low level, and the control switch changes from closed to open.

The above description is only the preferred embodiment of the present invention, the protection scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the present utility under the thought all belong to the protection scope of the present utility. It should be noted that modifications and embellishments within the scope of the present disclosure may be made by those skilled in the art without departing from the spirit of the present disclosure.

Claims (10)

1. A fast start-up crystal oscillator circuit, comprising a crystal oscillator circuit, characterized in that: also comprises a ring oscillator, a comparator, a logic counting circuit, a third switch to an Nth switch₁Switch, N₁Is a positive integer, and N₁Not less than 3; the power supply end of the ring oscillator and the power supply end of the crystal oscillation circuit are connected with a power supply; the input end of the ring oscillator receives the power-on enabling signal, the output end of the ring oscillator is connected with the input end of a third switch, and the third switch is connected with the Nth switch₁Switches connected in series in sequence, Nth₁The output end of the switch is connected with the input end of the crystal oscillation circuit; the input end and the output end of the crystal oscillation circuit are respectively connected with two input ends of the comparator; the output end of the comparator outputs a clock signal and outputs the clock signal to one input end of the logic counting circuit; the other input end of the logic counting circuit receives a power-on reset signal, and the output ends respectively output a third switch control signal to the Nth switch₁A switch control signal for controlling the third switch to the Nth switch₁The switch is closed or opened.

2. The fast start up crystal oscillator circuit of claim 1, further comprising: the device also comprises a first switch and a second switch; the first switch is connected between a power supply and the crystal oscillation circuit, the input end of the first switch is connected with the power supply, and the output end of the first switch is connected with the power supply end of the crystal oscillation circuit; the second switch is connected between a power supply and the ring oscillator, the input end of the second switch is connected with the power supply, and the output end of the second switch is connected with the power supply end of the ring oscillator; the output end of the logic counting circuit outputs a second switch control signal to control the second switch to be switched on or switched off; the power-on reset signal controls the first switch to be switched on or switched off.

3. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate and (N)₁-1) or (N)₁-2) output not gates, one input of said and gate receiving a comparisonThe other input end of the clock signal output by the D flip-flop receives a power-on Reset signal, the output end of the clock signal is connected with the clock signal input end of a first D flip-flop, the D port of the first D flip-flop is connected with the output end of a first NOT gate, the Q port of the clock signal input end of the first NOT gate is connected with the input end of the first NOT gate and the input end of a second NOT gate, the output end of the second NOT gate is connected with the clock signal input end of a second D flip-flop, the D port of the second D flip-flop is connected with a Reset port, and₁-1) or (N)₁-2) input connections of output NOT-gates,

or, the logic counting circuit comprises an AND gate, a first D flip-flop, a second D flip-flop … … Nth₃A D flip-flop, a first NOT gate, a second NOT gate … … Nth₃A NOT gate and (N)₁-1) or (N)₁-2) output not gates, N₃Is a positive integer, and N₃And more than or equal to 3, one input end of the AND gate receives the clock signal output by the comparator, the other input end of the AND gate receives the power-on reset signal, the output end of the AND gate is connected with the clock signal input end of the first D flip-flop, the D port of the nth D flip-flop is connected with the output end of the nth NOT gate, the Q port of the Nth NOT gate is connected with the input end of the nth NOT gate and the clock signal input end of the (N +1) th D flip-flop, and N is 1 to (N is)₃-2), N₃-1) D port of D flip-flop and (N)₃-1) the output of the NOT gate is connected, the Q port is connected with the (N) th₃-1) inputs of NOT gates and Nth₃The input terminals of the NOT gates are connected, N₃The output end of the NOT gate and the Nth gate₃The clock signal input ends of the D flip-flops are connected, the Nth flip-flop₃The D port of each D flip-flop is connected with the Reset port, and the Q port is respectively connected with (N)₁-1) or (N)₁-2) input connections of output not gates;

said (N)₁-1) or (N)₁-2) the output ends of the output NOT gates respectively control the second switch and the third switch … … Nth switch₁Switches or third to Nth switches₁A switch control signal for the switch; the Reset end of the first D flip-flop and the Reset end … … of the second D flip-flop are Nth₃The Reset ends of the D triggers all receive the power-on Reset signalNumber (n).

4. The fast start up crystal oscillator circuit of claim 3, wherein: the ring oscillator comprises a NAND gate, a first NOT gate, a second NOT gate and a third NOT gate … … Nth₂NOT gate, N₂3, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th₂NOT gates connected in series, N₂-1) the output of the not-gate is connected to the other input of the first not-gate, N₂The output end of the NOT gate outputs an oscillation clock.

5. The fast start up crystal oscillator circuit of claim 3, wherein: the device also comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.

6. The fast start up crystal oscillator circuit of claim 4, wherein: the circuit also comprises a first resistor; the first resistor is connected into the Nth resistor₁Between the switch and the crystal oscillation circuit, one terminal is connected to the Nth terminal₁The output end of the switch is connected, and the other end of the switch is connected with the input end of the crystal oscillation circuit.

7. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the ring oscillator comprises a NAND gate, a first NOT gate, a second NOT gate and a third NOT gate … … Nth₂NOT gate, N₂3, 7, 9, 11 … …; one input end of the NAND gate receives a power-on reset signal, the output end of the NAND gate is connected with the input end of the first NOT gate, and the first NOT gate, the second NOT gate and the third NOT gate … … are N-th₂NOT gates connected in series, the first(N₂-1) the output of the not-gate is connected to the other input of the first not-gate, N₂The output end of the NOT gate outputs an oscillation clock.

8. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the device also comprises a first buffer and/or a second buffer; the first buffer is connected between the ring oscillator and the third switch, the input end of the first buffer is connected with the output end of the ring oscillator, and the output end of the first buffer is connected with the input end of the third switch; the input end of the second buffer is connected with the output end of the comparator, and the output end of the second buffer outputs a clock signal.

9. The fast start up crystal oscillator circuit of claim 8, further comprising: the circuit also comprises a first resistor; the first resistor is connected into the Nth resistor₁Between the switch and the crystal oscillation circuit, one terminal is connected to the Nth terminal₁The output end of the switch is connected, and the other end of the switch is connected with the input end of the crystal oscillation circuit.

10. The fast start up crystal oscillator circuit of any of claims 1 or 2, further comprising: the crystal oscillation circuit comprises an inverting amplifier, a feedback resistor, a crystal oscillator, a first capacitor and a second capacitor; the input end of the inverting amplifier INV is connected with the output end of the N1 th switch, one input end of the comparator, one end of the feedback resistor, one end of the crystal oscillator and one end of the first capacitor; the output end of the inverting amplifier is connected with the other input end of the comparator, the other end of the feedback resistor, the other end of the crystal oscillator and one end of the second capacitor; the power end of the inverting amplifier is connected with a power supply; and the grounding end of the inverting amplifier, the other end of the first capacitor and the other end of the second capacitor are grounded.

Images