WO2022095799A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2022095799A1
WO2022095799A1 PCT/CN2021/127498 CN2021127498W WO2022095799A1 WO 2022095799 A1 WO2022095799 A1 WO 2022095799A1 CN 2021127498 W CN2021127498 W CN 2021127498W WO 2022095799 A1 WO2022095799 A1 WO 2022095799A1
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material layer
region
area
platform
semiconductor structure
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PCT/CN2021/127498
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English (en)
French (fr)
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汤召辉
张磊
周玉婷
乔思
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长江存储科技有限责任公司
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Priority to CN202180006818.2A priority Critical patent/CN116420437A/zh
Publication of WO2022095799A1 publication Critical patent/WO2022095799A1/zh
Priority to US18/083,927 priority patent/US20230121962A1/en

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Definitions

  • the embodiments of the present application relate to a method for fabricating a semiconductor device.
  • Memory is a widely used semiconductor device.
  • modern technology often adopts the method of stacking memory chips to achieve higher integration.
  • chips or structures with different functions can be formed into three-dimensional (3D) three-dimensional devices with three-dimensional integration and signal communication in the vertical direction through micromachining techniques such as stacking or via interconnection.
  • Three-dimensional memory is to use this technology to three-dimensionally arrange memory cells on the substrate, so as to achieve the purpose of improving the performance and storage density of the memory.
  • the technical problem to be solved by the embodiments of the present disclosure is to provide a manufacturing method of a semiconductor device.
  • An embodiment of the present disclosure provides a method for fabricating a semiconductor device, including the following steps: providing a semiconductor structure, the semiconductor structure including a stack structure including a first material layer and a second material layer alternately stacked, the stack structure including a mesa region and a second material layer.
  • a step area adjacent to the platform area, the platform area and the top of the step area are a second material layer; forming a third material layer covering the upper surface of the platform area and the surface of the step area; forming a filling the step area and the fourth material layer covering the platform area; the third material layer and the fourth material layer on the platform area are removed, and the third material layer located on the platform area close to the edge of the step area is retained Three material layers and a fourth material layer; a first planarization is performed, the first planarization removes the raised fourth material layer, and the second material layer and the third material stay on the upper surface of the platform area layer.
  • the method further includes: removing the third material layer on the upper surface of the platform region; removing the second material layer on the top of the platform region to expose the first material layer; and performing a second planarization , the second planarization removes a part of the thickness of the fourth material layer on the step region, and the first material layer stays on the top of the platform region.
  • the second planarization simultaneously removes a portion of the first material layer on top of the mesa region.
  • a method of forming a third material layer covering the upper surface of the platform area and the surface of the step area includes: forming a layer covering the upper surface of the platform area and the surface and sidewalls of the step area a third material layer; and removing the third material layer covering the sidewall of the step region.
  • the first planarization simultaneously removes a third material layer on the upper surface of the platform area far from the edge of the step area and a third material layer on the platform area close to the edge of the step area part of the third material layer.
  • the first material layer includes a dielectric layer
  • the second material layer includes a dummy gate layer
  • the material of the third material layer includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.
  • the material of the fourth material layer includes silicon oxide.
  • chemical mechanical polishing is used to perform the first planarization, and a polishing selection ratio of the fourth material layer relative to the third material layer is greater than 10.
  • dry etching is used to remove a third material layer on the upper surface of the platform region, and the third material layer is opposite to the first material layer and/or the second material
  • the etch selectivity of the layers is greater than 10.
  • a semiconductor device including: a stack structure in which a first material layer and a second material layer are alternately stacked, the stacked structure including a mesa region and a step region adjacent to the mesa region, wherein The top of the platform area is a first material layer, the top of the step area is a second material layer; a third material layer covering the surface of the step area; and a fourth material layer filling the step area; wherein, the The upper surface of the platform area is flush with the upper surface of the fourth material layer.
  • a substrate under the stacked structure is further included.
  • the first material layer includes a dielectric layer
  • the second material layer includes a dummy gate layer
  • the material of the third material layer includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.
  • the material of the fourth material layer includes silicon oxide.
  • the semiconductor device fabrication method of the present disclosure increases the connection window of the contact hole by forming the third material layer covering the upper surface of the terrace region of the semiconductor structure and the surface of the step region, and effectively avoids overgrinding at the edge of the terrace region.
  • 1 and 2 are schematic diagrams of a method for manufacturing a semiconductor device
  • 3 and 4 are schematic diagrams of a semiconductor device
  • FIG. 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure
  • 6 to 15 are schematic diagrams of process steps of a method for fabricating a semiconductor device according to an embodiment of the present disclosure
  • FIG. 16 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.
  • orientations such as “front, rear, top, bottom, left, right", “horizontal, vertical, vertical, horizontal” and “top, bottom” indicate the orientation Or the positional relationship is usually based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present disclosure and simplifying the description, and these orientations do not indicate or imply the indicated device or element unless otherwise stated. It must have a specific orientation or be constructed and operated in a specific orientation, so it should not be construed as a limitation on the protection scope of the present disclosure; the orientation words “inside and outside” refer to the inside and outside relative to the outline of each component itself.
  • spatially relative terms such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element shown in the figures or the relationship of a feature to other elements or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary words “below” and “below” can encompass both an orientation of above and below.
  • Devices may also have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
  • orientations rotated 90 degrees or at other orientations
  • spatially relative descriptors used herein should be interpreted accordingly.
  • a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include additional features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.
  • FIGS. 1 and 2 are schematic diagrams of a method of fabricating a semiconductor device.
  • a silicon nitride (SIN) hard mask As a stop layer during array planarization.
  • ETCH loading ETCH loading
  • CMP chemical mechanical polishing
  • the blocking effect of the silicon nitride hard mask is not good, often Causes damage to oxides and silicon nitrides.
  • the thickness of the silicon nitride hard mask cannot be infinitely increased due to the limitation of the "chamfer" height of the chemical mechanical polishing of the buffer oxide layer (Buffer OX) layer.
  • FIG. 3 and 4 are schematic diagrams of a semiconductor device.
  • the semiconductor structure formed by this method suffers from significant overgrinding at the edge of the mesa region.
  • the connection window of the contact hole of such a semiconductor structure is small.
  • the upper steps/steps are easily over-etched (Over Etch) and etch through (Punch Through) occurs, resulting in failure to meet process requirements and reducing product yield.
  • the following embodiments of the present disclosure propose a method for fabricating a semiconductor device, which increases the connection window of the contact hole and effectively avoids overgrinding at the edge of the platform region.
  • the method for fabricating a semiconductor device of the present disclosure includes the following steps: providing a semiconductor structure, the semiconductor structure including a stack structure consisting of a first material layer and a second material layer alternately stacked, the stack structure including a platform region and a step region adjacent to the platform region , the top of the platform area and the step area is a second material layer; a third material layer covering the upper surface of the platform area and the surface of the step area is formed; a fourth material layer filling the step area and covering the platform area is formed; removing the first material layer on the platform area The third material layer and the fourth material layer, and the third material layer and the fourth material layer located on the platform area near the edge of the step area are reserved; the first planarization is performed, and the first planarization removes the raised fourth material layer, and stay on the second material layer and the third material layer on the upper surface of the platform area.
  • FIG. 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.
  • 6 to 15 are schematic diagrams of process steps of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. The manufacturing method will be described below with reference to FIGS. 5 to 15 .
  • Step S10 providing a semiconductor structure.
  • the semiconductor structure 200 includes a stack structure in which the first material layers 110 and the second material layers 120 are alternately stacked. In the adjacent stair-step region, the top of the stair-step region and the second material layer 120 is the second material layer 120 .
  • the platform area can play the role of storage, and the step area can play the role of electrical connection.
  • the first material layer 110 includes a dielectric layer
  • the second material layer 120 includes a dummy gate layer
  • the material of the first material layer 110 may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.
  • the material of the second material layer 120 may be, for example, silicon nitride and silicon oxynitride (SiOxNx).
  • the deposition method for forming the first material layer 110 and the second material layer 120 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), Various methods such as thermal oxidation, evaporation, sputtering, etc.
  • the second material layer 120 (dummy gate layer) therein can also be replaced to obtain a gate electrode layer.
  • Alternative methods include, but are not limited to, wet etching.
  • the replacement material can be conductive materials such as metal tungsten, cobalt, nickel, titanium, etc., and can also be polysilicon, doped silicon, or any combination of the above.
  • the first material layer 110 and the second material layer 120 have different etch selectivities.
  • it may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like.
  • the second material layer 120 (dummy gate layer) of silicon nitride or silicon oxynitride is formed, it can be replaced with metal tungsten in subsequent process steps, but the present disclosure is not limited thereto.
  • the semiconductor structure 200 further includes a substrate 101 under the stacked structure.
  • the material of the substrate 101 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (SOI, Silicon on Insulator) or germanium on insulator (GOI, Germanium on Insulator) or the like.
  • the substrate 101 may also include other elements or compounds, such as GaAs, InP, or SiC, and the like.
  • the substrate 101 may also be a stacked structure, such as Si/SiGe, etc., or include other epitaxial structures, such as silicon germanium on insulator (SGOI), etc., the present disclosure is not limited thereto.
  • the semiconductor structure 100 also includes a stacked structure in which the first material layers 110 and the second material layers 120 are alternately stacked, and the stacked structure includes a mesa area and a step area adjacent to the mesa area.
  • the difference from the semiconductor structure 200 shown in FIG. 7 is that the first material layer 110 is located on the top of the terrace area and the step area of the semiconductor structure 100 .
  • the semiconductor structure 100 shown in FIG. 6 may be dry-etched to remove the first material layer 110 on top of the mesa region and the step region thereof, and expose the second material layer 120 below, thereby The semiconductor structure 200 shown in FIG. 7 is obtained, but the present disclosure is not limited thereto.
  • Step S20 forming a third material layer covering the upper surface of the platform area and the surface of the step area.
  • a third material layer 130 covering the upper surface of the mesa region and the surface of the step region is formed.
  • the third material layer 130 may be deposited and formed on the upper surface of the terrace region and the surface of the step region of the semiconductor structure 200 shown in FIG. 7 .
  • the material of the third material layer 130 includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.
  • the material of the third material layer 130 is silicon oxynitride (SiOxNy, such as SiON).
  • the deposition method for forming the third material layer 130 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering shooting and other methods.
  • CVD chemical vapor deposition
  • PECVD PECVD
  • LPCVD LPCVD
  • HDPCVD atomic layer deposition
  • MBE molecular beam epitaxy
  • thermal oxidation evaporation
  • sputtering shooting other methods.
  • the method of forming the third material layer 130 covering the upper surface of the mesa region and the surface of the step area includes: forming the upper surface and side surfaces of the mesa area and the step area.
  • the third material layer 130 (semiconductor structure 300 ) of the wall is removed, and then the third material layer 130 covering the sidewall of the step region is removed to form the semiconductor structure 400 .
  • a dry etching process may be used to directionally remove the third material layer 130 covering the sidewalls of the step regions in the semiconductor structure 300 by controlling the gas direction.
  • Step S30 forming a fourth material layer filling the step area and covering the step area.
  • a fourth material layer 140 filling the step area and covering the step area is formed.
  • the fourth material layer 140 may be deposited on the terrace area and the step area, so that the height of the fourth material layer 140 on the step area exceeds the surface of the terrace area to form the semiconductor structure 500 .
  • the material of the fourth material layer 140 includes silicon oxide.
  • TEOS tetraethyl orthosilicate
  • step S40 the third material layer and the fourth material layer on the platform region are removed, and the third material layer and the fourth material layer located on the platform region and close to the edge of the step region are retained.
  • the third material layer 130 and the fourth material layer 140 on the terrace region of the semiconductor structure 500 are removed, and the third material layers 130 and the fourth material layer 130 and the fourth material layer 130 and the fourth material layer on the terrace region near the edge of the step region remain.
  • the material layer 140 forms the semiconductor structure 600 .
  • the method for removing the third material layer 130 and the fourth material layer 140 includes, but is not limited to, dry etching.
  • the dry etching mainly uses reactive gas and plasma to etch the material to be etched.
  • a photoresist may be coated on the upper surface of the fourth material layer 140, and then patterned using a photolithography process to form a mask pattern. After that, the third material layer 130 and the fourth material layer 140 under the mask pattern are etched.
  • step S50 the first planarization is performed.
  • the first planarization removes the raised fourth material layer, and stays on the second material layer and the third material layer on the upper surface of the platform region.
  • the first planarization is performed.
  • the first planarization may remove the raised fourth material layer 140 , and the second material layer 120 and the third material layer 130 remaining on the upper surface of the platform area to form Semiconductor structure 700 .
  • the first planarization simultaneously removes the third material layer 130 on the upper surface of the platform region far from the edge of the step region and a part of the third material layer 130 on the platform region near the edge of the step region.
  • the second material layer 120 and the third material layer 130 remaining on the upper surface of the platform region are first planarized to retain at least a part of the third material layer 130 on the upper surface of the platform region close to the step region.
  • planarization the main purpose of planarization is to remove the raised fourth material layer 140 .
  • the third material layer 130 and a part of the second material layer 120 below the upper surface of the platform region far from the edge of the step region may also be removed at the same time.
  • a part of the third material layer 130 on the platform region near the edge of the step region can also be removed at the same time.
  • chemical mechanical polishing is used for the first planarization, and the polishing selection ratio of the fourth material layer 140 relative to the third material layer 130 is greater than 10.
  • Chemical mechanical polishing is a technique that combines chemical and mechanical action to obtain a surface that is flat and free from scratches and impurities.
  • the method further includes: removing the third material layer on the upper surface of the platform region; removing the second material layer on the top of the platform region to expose the first material layer; and performing a second planarization , the second planarization removes a part of the thickness of the fourth material layer on the step area, and the first material layer stays on the top of the step area.
  • the third material layer 130 on the upper surface of the mesa region is removed to form a semiconductor structure 800 .
  • dry etching may be used to remove the third material layer 130 on the upper surface of the mesa region, and the third material layer 130 is etched relative to the first material layer 110 and/or the second material layer 120
  • the eclipse selection ratio is greater than 10.
  • the second material layer 120 on the top of the mesa region is removed to expose the first material layer 110 to form a semiconductor structure 900 .
  • wet etching may be used to remove the second material layer 120 at the top of the mesa region to expose the first material layer 110 below it.
  • a second planarization is performed.
  • the second planarization removes part of the thickness of the fourth material layer 140 on the step area, and the first material layer 110 stays on the top of the step area to form a semiconductor Structure 1000.
  • the second planarization may also remove part of the first material layer 110 on the top of the mesa region at the same time.
  • the polishing options for the two are relatively small.
  • the previously formed “chamfer” can be repaired, so that the upper surface of the terrace region of the semiconductor structure 1000 is aligned with the upper surface of the fourth material layer 140 on the terrace region flat.
  • FIG. 16 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 16 , after the semiconductor structure 1000 is formed, the connection of the contact holes may also be performed, so that the contact holes may be connected to the second material layer 120 (eg, the gate layer) of each layer of the mesa region.
  • the second material layer 120 eg, the gate layer
  • the third material layer 130 is reserved as a barrier layer on each step of the step region, which forms a double barrier effect with the second material layer 120, thereby effectively increasing the contact.
  • the connection window of the hole avoids the phenomenon that the upper step is etched through in the contact hole etching step, and improves the product yield.
  • FIG. 5 is used herein to illustrate the steps/operations performed by the fabrication method according to the embodiment of the present disclosure. It should be understood that the steps/operations need not be performed in exact order. Rather, the various steps/operations may be processed in reverse order or concurrently. At the same time, other steps/actions are either added to these processes, or a step or steps/actions are removed from these processes.
  • the above embodiments of the present disclosure propose a method for fabricating a semiconductor device, which increases the connection window of the contact hole and effectively avoids over-grinding at the edge of the platform region.
  • Another aspect of the present disclosure proposes a semiconductor device with high reliability.
  • the semiconductor device of the present disclosure includes: a stack structure in which first material layers and second material layers are alternately stacked, the stack structure includes a platform area and a step area adjacent to the platform area, the top of the platform area is the first material layer, and the step area The top of the is a second material layer; a third material layer covering the surface of the step area; and a fourth material layer filling the step area; wherein, the upper surface of the platform area is flush with the upper surface of the fourth material layer.
  • the semiconductor device (eg, the semiconductor structure 1000 ) includes a stack structure in which the first material layers 110 and the second material layers 120 are alternately stacked, and the stack structure includes a mesa area and a step area adjacent to the mesa area.
  • the top of the region is the first material layer 110
  • the top of the stepped region is the second material layer 120 .
  • the semiconductor device (eg, the semiconductor structure 1000 ) further includes a third material layer 130 covering the surface of the step area and a fourth material layer 140 filling the step area. Wherein, the upper surface of the platform region is flush with the upper surface of the fourth material layer 140 .
  • the semiconductor device (eg, the semiconductor structure 1000 ) further includes a substrate 101 under the stacked structure.
  • the first material layer 110 includes a dielectric layer
  • the second material layer 120 includes a dummy gate layer
  • the material of the first material layer 110 may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.
  • the material of the second material layer 120 may be, for example, silicon nitride and silicon oxynitride (SiOxNx).
  • the material of the third material layer 130 includes one or more of silicon oxynitride, aluminum oxide, and titanium nitride.
  • the material of the fourth material layer 140 includes silicon oxide.
  • the third material layer 130 is reserved as a barrier layer on each step of the step region, which forms a double-layer barrier effect with the second material layer 120, which effectively increases the
  • the connection window of the contact hole avoids the phenomenon that the upper step is etched through in the contact hole etching step, and improves the product yield.
  • the semiconductor device of the present disclosure can be implemented by, for example, the manufacturing method of the semiconductor device shown in FIG. 5 , but the present disclosure is not limited thereto.
  • the above embodiments of the present disclosure propose a semiconductor device with high reliability.

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Abstract

本公开实施例公开了一种半导体器件的制作方法，包括以下步骤：提供半导体结构，半导体结构包括由第一材料层和第二材料层交替堆叠的堆叠结构，堆叠结构包括平台区和与平台区相邻的台阶区，平台区和台阶区的顶部为第二材料层；形成覆盖平台区上表面和台阶区表面的第三材料层；形成填充台阶区且覆盖平台区的第四材料层；去除平台区上的第三材料层和第四材料层，且保留位于平台区上靠近台阶区的边缘的第三材料层和第四材料层；进行第一次平坦化，第一次平坦化去除凸起的第四材料层，且停留在平台区上表面的第二材料层和第三材料层。

Description

半导体器件及其制作方法
相关申请的交叉引用
本申请基于申请号为202011208819.9，申请日为2020年11月03日，申请名称为“半导体器件及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及一种半导体器件的制作方法。
背景技术
半导体集成电路自诞生以来，经历了从小规模、中规模到大规模和超大规模集成的发展阶段，并日益成为现代科学技术中最为活跃的技术领域之一。
存储器是一种广泛使用的半导体器件。为了克服传统的二维存储器在存储容量方面的限制，现代工艺往往采用堆叠存储芯片的方式来实现更高的集成度。例如，可以将不同功能的芯片或结构，通过堆叠或孔互连等微机械加工技术，在垂直方向上形成立体集成、信号连通的三维(3D)立体器件。三维存储器就是利用这一技术将存储器单元三维地布置在衬底之上，进而实现提高存储器的性能和存储密度的目的。
发明内容
本公开实施例所要解决的技术问题是提供一种半导体器件的制作方法。
本公开实施例提供一种半导体器件的制作方法，包括以下步骤：提供半导体结构，所述半导体结构包括由第一材料层和第二材料层交替堆叠的堆叠结构，所述堆叠结构包括平台区和与所述平台区相邻的台阶区，所述平台区和所述台阶区的顶部为第二材料层；形成覆盖所述平台区上表面和所述台阶区表面的第三材料层；形成填充所述台阶区且覆盖所述平台区的第四材料层；去除所述平台区上的第三材料层和第四材料层，且保留位于所述平台区上靠近所述台阶区的边缘的第三材料层和第四材料层；进行第一次平坦化，所述第一次平坦化去除凸起的第四材料层，且停留在所述平台区上表面的第二材料层和第三材料层。
在本公开的一实施例中，还包括：去除所述平台区上表面的第三材料层；去除所述平台区顶部的第二材料层以露出第一材料层；以及进行第二次平坦化，所述第二次平坦化去除所述台阶区上的第四材料层的部分厚度，且停留在所述平台区顶部的第一材料层。
在本公开的一实施例中，所述第二次平坦化同时去除所述平台区顶部的部分第一材料层。
在本公开的一实施例中，形成覆盖所述平台区上表面和所述台阶区表面的第三材料层的方法包括：形成覆盖所述平台区上表面和所述台阶区表面及侧壁的第三材料层；以及去除覆盖在所述台阶区侧壁的第三材料层。
在本公开的一实施例中，所述第一次平坦化同时去除所述平台区上表面远离所述台阶区的边缘的第三材料层及所述平台区上靠近所述台阶区的边缘的第三材料层的一部分。
在本公开的一实施例中，所述第一材料层包括介质层，所述第二材料层包括伪栅极层。
在本公开的一实施例中，所述第三材料层的材料包括氮氧化硅、氧化铝、氮化钛中的一种或多种。
在本公开的一实施例中，所述第四材料层的材料包括氧化硅。
在本公开的一实施例中，使用化学机械抛光进行所述第一次平坦化，且所述第四材料层相对于所述第三材料层的抛光选择比大于10。
在本公开的一实施例中，使用干法刻蚀去除所述平台区上表面的第三材料层，且所述第三材料层相对于所述第一材料层和/或所述第二材料层的刻蚀选择比大于10。
本公开的另一方面提供一种半导体器件，包括：由第一材料层和第二材料层交替堆叠的堆叠结构，所述堆叠结构包括平台区和与所述平台区相邻的台阶区，所述平台区的顶部为第一材料层，所述台阶区的顶部为第二材料层；覆盖所述台阶区表面的第三材料层；以及填充所述台阶区的第四材料层；其中，所述平台区的上表面与所述第四材料层的上表面齐平。
在本公开的一实施例中，还包括位于所述堆叠结构下的衬底。
在本公开的一实施例中，所述第一材料层包括介质层，所述第二材料层包括伪栅极层。
在本公开的一实施例中，所述第三材料层的材料包括氮氧化硅、氧化铝、氮化钛中的一种或多种。
在本公开的一实施例中，所述第四材料层的材料包括氧化硅。
本公开明由于采用以上技术方案，使之与现有技术相比，具有如下显著优点：
本公开的半导体器件的制作方法通过形成覆盖半导体结构平台区上表面和台阶区 表面的第三材料层，增大了接触孔的连接窗口，有效避免了平台区边缘处的过磨。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1和图2是一种半导体器件的制作方法的示意图；
图3和图4是一种半导体器件的示意图；
图5是本公开一实施例的一种半导体器件的制作方法的流程图；
图6至图15是本公开一实施例的一种半导体器件的制作方法的工艺步骤示意图；
图16是本公开一实施例的一种半导体器件的示意图。
具体实施方式
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本公开的一些示例或实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本公开应用于其他类似情景。除非从语言环境中显而易见或另做说明，图中相同标号代表相同结构或操作。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是本公开还可以采用其它不同于在此描述的其它方式来实施，因此本公开不受下面公开的具体实施例的限制。
如本公开和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图 中被定义，则在随后的附图中不需要对其进行进一步讨论。
在详述本公开实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
在本公开的描述中，需要理解的是，方位词如“前、后、上、下、左、右”、“横向、竖向、垂直、水平”和“顶、底”等所指示的方位或位置关系通常是基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，在未作相反说明的情况下，这些方位词并不指示和暗示所指的装置或元件必须具有特定的方位或者以特定的方位构造和操作，因此不能理解为对本公开保护范围的限制；方位词“内、外”是指相对于各部件本身的轮廓的内外。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。例如，如果翻转附图中的器件，则被描述为在其他元件或特征“下方”或“之下”或“下面”的元件的方向将改为在所述其他元件或特征的“上方”。因而，示例性的词语“下方”和“下面”能够包含上和下两个方向。器件也可能具有其他朝向(旋转90度或处于其他方向)，因此应相应地解释此处使用的空间关系描述词。此外，还将理解，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
在本公开的上下文中，所描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
应当理解，当一个部件被称为“在另一个部件上”、“连接到另一个部件”、“耦合于另一个部件”或“接触另一个部件”时，它可以直接在该另一个部件之上、连接于或耦合于、或接触该另一个部件，或者可以存在插入部件。相比之下，当一个部件被称为“直接在另一个部件上”、“直接连接于”、“直接耦合于”或“直接接触”另一个部件时，不存在插入部件。
此外，需要说明的是，使用“第一”、“第二”等词语来限定零部件，仅仅是为了便于对相应零部件进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本公开保护范围的限制。此外，尽管本公开中所使用的术语是从公知公用的术语中 选择的，但是本公开说明书中所提及的一些术语可能是申请人按他或她的判断来选择的，其详细含义在本文的描述的相关部分中说明。此外，要求不仅仅通过所使用的实际术语，而是还要通过每个术语所蕴含的意义来理解本公开。
在半导体器件(例如3D NAND)的制作过程中，为了保证接触孔可以与核心区每层栅线相连，常常需要形成一种台阶结构，并引入阵列平坦化(Array Planarization,APL)工艺。随着3D NAND层数的增加，填充台阶的氧化物增厚，阵列平坦化的研磨时间增加，加之前层工艺变化，因而会带来一系列过磨或少磨的问题。
图1和图2是一种半导体器件的制作方法的示意图。参考图1和图2所示，对于多层(例如128层)的半导体结构，一种方法是在阵列平坦化时以氮化硅(SIN)硬掩模作为停止层。但是，由于在化学机械抛光(Chemical Mechanical Polishing，CMP)工艺中半导体结构平台区(Giant Block region)边缘处等位置的蚀刻负载(ETCH loading)差异，氮化硅硬掩模阻挡效果不佳，往往会造成氧化物和氮化硅的损伤。而且，由于受到缓冲氧化物层(Buffer OX)层化学机械抛光的“倒角”高度的限制，氮化硅硬掩模的厚度并非可以无限增加。
图3和图4是一种半导体器件的示意图。参考图3和图4所示，这种方法形成的半导体结构在平台区边缘处发生了明显的过磨。此外，这种半导体结构接触孔的连接窗口较小。这样，在接触孔刻蚀步骤中，上层阶梯/台阶容易被过刻蚀(Over Etch)，出现刻蚀穿通(Punch Through)，导致无法满足工艺要求，降低了产品良率。
针对以上的问题，本公开的以下实施例提出一种半导体器件的制作方法，该制作方法增大了接触孔的连接窗口，有效避免了平台区边缘处的过磨。
本公开的半导体器件的制作方法，包括以下步骤：提供半导体结构，半导体结构包括由第一材料层和第二材料层交替堆叠的堆叠结构，堆叠结构包括平台区和与平台区相邻的台阶区，平台区和台阶区的顶部为第二材料层；形成覆盖平台区上表面和台阶区表面的第三材料层；形成填充台阶区且覆盖平台区的第四材料层；去除平台区上的第三材料层和第四材料层，且保留位于平台区上靠近台阶区的边缘的第三材料层和第四材料层；进行第一次平坦化，第一次平坦化去除凸起的第四材料层，且停留在平台区上表面的第二材料层和第三材料层。
图5是本公开一实施例的一种半导体器件的制作方法的流程图。图6至图15是本公开一实施例的一种半导体器件的制作方法的工艺步骤示意图。下面结合图5至图15对该制作方法进行说明。
可以理解的是，下面所进行的描述仅仅示例性的，本领域技术人员可以在不脱离本公开的精神的情况下，进行各种变化。
步骤S10，提供半导体结构。
参考图7所示，提供半导体结构200，半导体结构200包括由第一材料层110和第二材料层120交替堆叠的堆叠结构，堆叠结构包括平台区(Giant Block region,GB)和与平台区相邻的台阶区(Stair-step region)，平台区和台阶区的顶部为第二材料层120。其中，平台区可以起到存储的作用，台阶区可以起到电连接的作用。
在本公开的一实施例中，第一材料层110包括介质层，第二材料层120包括伪栅极层。
第一材料层110的材料例如可以是氧化硅、氧化铝、氧化铪、氧化钽等。第二材料层120的材料例如可以是氮化硅和氮氧化硅(SiOxNx)。
形成第一材料层110和第二材料层120的沉积方法可以包括化学气相沉积(CVD、PECVD、LPCVD、HDPCVD)、原子层沉积(ALD)，或物理气相沉积方法如分子束外延(MBE)、热氧化、蒸发、溅射等各种方法。
在本公开的一实施例中，在形成SiOx-SiOxNx-SiOx堆栈(ONO stack)的多层堆叠结构之后，还可以对其中的第二材料层120(伪栅极层)进行替换来得到栅极层。替换的方法包括但不限于湿法刻蚀。替换材料可以为金属钨、钴、镍、钛等导电材料，也可以是多晶硅、掺杂硅或上述任意组合。
在一些示例中，第一材料层110和第二材料层120具有不同的刻蚀选择性。例如，其可以是氮化硅和氧化硅的组合、氧化硅与未掺杂的多晶硅或非晶硅的组合、氧化硅或氮化硅与非晶碳的组合等。举例来讲，形成氮化硅或氮氧化硅的第二材料层120(伪栅极层)后，可以在后续的工艺步骤中将其替换为金属钨，但本公开并非以此为限。
继续参考图7所示，在一些实施例中，半导体结构200还包括位于堆叠结构下的衬底101。
应当理解，衬底101的材料可以是硅(Si)、锗(Ge)、锗化硅(SiGe)、绝缘体上硅(SOI，Silicon on Insulator)或绝缘体上锗(GOI，Germanium on Insulator)等。衬底101还可以包括其他元素或化合物，如GaAs、InP或SiC等。衬底101也可以是叠层结构，例如Si/SiGe等，或者包括其他外延结构，例如绝缘体上锗硅(SGOI)等，本公开并非以此为限。
参考图6所示，对于半导体结构100，其同样包括由第一材料层110和第二材料层 120交替堆叠的堆叠结构，堆叠结构包括平台区和与平台区相邻的台阶区。与图7所示的半导体结构200的不同之处在于，半导体结构100的平台区和台阶区的顶部为第一材料层110。
在一些实施例中，可以对图6所示的半导体结构100进行干法刻蚀，以去除其平台区和台阶区的顶部的第一材料层110，且露出下方的第二材料层120，从而得到图7所示的半导体结构200，但本公开并非以此为限。
步骤S20，形成覆盖平台区上表面和台阶区表面的第三材料层。
参考图9所示，形成覆盖平台区上表面和台阶区表面的第三材料层130。
示例性的，可以在图7所示的半导体结构200的平台区上表面和台阶区表面沉积形成第三材料层130。
在本公开的一实施例中，第三材料层130的材料包括氮氧化硅、氧化铝、氮化钛中的一种或多种。
优选的，第三材料层130的材料为氮氧化硅(SiOxNy，例如SiON)。
形成第三材料层130的沉积方法可以包括化学气相沉积(CVD、PECVD、LPCVD、HDPCVD)、原子层沉积(ALD)，或物理气相沉积方法如分子束外延(MBE)、热氧化、蒸发、溅射等各种方法。
参考图8和图9所示，在本公开的一实施例中，形成覆盖平台区上表面和台阶区表面的第三材料层130的方法包括：形成覆盖平台区上表面和台阶区表面及侧壁的第三材料层130(半导体结构300)，然后去除覆盖在台阶区侧壁的第三材料层130，形成半导体结构400。
优选的，可以使用干刻工艺，通过控制气体方向，来定向去除半导体结构300中覆盖在台阶区侧壁的第三材料层130。
步骤S30，形成填充台阶区且覆盖平台区的第四材料层。
参考图10所示，形成填充台阶区且覆盖平台区的第四材料层140。例如，可以在平台区和台阶区上沉积第四材料层140，使得位于台阶区上的第四材料层140的高度超过平台区表面，形成半导体结构500。
在本公开的一实施例中，第四材料层140的材料包括氧化硅。
示例性的，可以利用CVD、PECVD或LPCVD等方法进行正硅酸乙酯(TEOS)源氧化硅的沉积。
步骤S40，去除平台区上的第三材料层和第四材料层，且保留位于平台区上靠近台 阶区的边缘的第三材料层和第四材料层。
参考图10和图11所示，去除半导体结构500的平台区上的第三材料层130和第四材料层140，且保留位于平台区上靠近台阶区的边缘的第三材料层130和第四材料层140，形成半导体结构600。
在图11所示的一个示例中，不仅保留了平台区上靠近台阶区的边缘的第三材料层130和第四材料层140，而且还保留了平台区上远离台阶区的边缘的一部分第三材料层130。在另一些示例中，还可以仅保留平台区上靠近台阶区的边缘的第三材料层130和第四材料层140，本公开并非以此为限。
去除第三材料层130和第四材料层140的方法包括但不限于干法刻蚀，干法刻蚀主要利用反应气体与等离子体对被刻蚀材料进行刻蚀。
示例性的，可以在第四材料层140的上表面涂覆光刻胶(PR,Photoresist)，然后利用光刻工艺对其进行图案化以形成掩模图案。之后，以掩模图案为掩模对其下方的第三材料层130和第四材料层140进行刻蚀。
步骤S50，进行第一次平坦化，第一次平坦化去除凸起的第四材料层，且停留在平台区上表面的第二材料层和第三材料层。
参考图12所示，进行第一次平坦化，第一次平坦化可以去除凸起的第四材料层140，且停留在平台区上表面的第二材料层120和第三材料层130，形成半导体结构700。
在本公开的一实施例中，第一次平坦化同时去除平台区上表面远离台阶区的边缘的第三材料层130及平台区上靠近台阶区的边缘的第三材料层130的一部分。
第一次平坦化停留在平台区上表面的第二材料层120和第三材料层130，以保留平台区上表面的靠近台阶区的第三材料层130的至少一部分。
应当理解，在此步骤中，平坦化的主要目的是去除凸起的第四材料层140。平坦化的过程中还可以同时去除平台区上表面远离台阶区的边缘的第三材料层130及其下方的一部分第二材料层120。或者还可以同时去除平台区上靠近台阶区的边缘的第三材料层130的一部分。
在本公开的一实施例中，使用化学机械抛光进行第一次平坦化，且第四材料层140相对于第三材料层130的抛光选择比大于10。
化学机械抛光(Chemical Mechanical Polishing，CMP)工艺。化学机械抛光是一种化学作用和机械作用相结合的技术，可以获得平坦且无划痕和杂质玷污的表面。
经过此步骤，平台区上靠近台阶区的边缘的第三材料层130的至少一部分仍然被保 留，有效避免了在平坦化过程中平台区边缘处发生过磨现象。
在本公开的一实施例中，在步骤S50之后还包括：去除平台区上表面的第三材料层；去除平台区顶部的第二材料层以露出第一材料层；以及进行第二次平坦化，第二次平坦化去除台阶区上的第四材料层的部分厚度，且停留在平台区顶部的第一材料层。
参考图12和图13所示，去除平台区上表面的第三材料层130，形成半导体结构800。
在本公开的一实施例中，可以使用干法刻蚀去除平台区上表面的第三材料层130，且第三材料层130相对于第一材料层110和/或第二材料层120的刻蚀选择比大于10。
参考图13和图14所示，去除平台区顶部的第二材料层120以露出第一材料层110，形成半导体结构900。
示例性的，可以使用湿法刻蚀去除平台区顶部的第二材料层120以露出其下方的第一材料层110。
经过以上步骤，在平台区靠近台阶区的边缘处形成了高度差较大的“倒角”。
参考图14和图15所示，进行第二次平坦化，第二次平坦化去除台阶区上的第四材料层140的部分厚度，且停留在平台区顶部的第一材料层110，形成半导体结构1000。
在本公开的一实施例中，第二次平坦化还可以同时去除平台区顶部的部分第一材料层110。
当第一材料层110和第四材料层140的材料均为氧化硅时，二者的抛光选择比较小。通过对平台区顶部的第一材料层110进行部分过磨从而可以修复之前形成的“倒角”，使得半导体结构1000的平台区的上表面与台阶区上的第四材料层140的上表面齐平。
图16是本公开一实施例的一种半导体器件的示意图。参考图16所示，在形成半导体结构1000之后，还可以进行接触孔的连接，使接触孔可以与平台区每层的第二材料层120(例如栅极层)相连。
本公开的半导体器件的制作方法由于在台阶区的每一个台阶上都保留了第三材料层130作为阻挡层，其与第二材料层120形成了双层阻挡的效果，有效地增大了接触孔的连接窗口，避免了在接触孔刻蚀步骤中出现的上层台阶被刻蚀穿通的现象，提高了产品良率。
应当注意，在此使用了图5所示的流程图来说明根据本公开的实施例的制作方法所执行的步骤/操作。应当理解的是，这些步骤/操作不一定按照顺序来精确地执行。相反，可以按照倒序或同时处理各种步骤/操作。同时，或将其他步骤/操作添加到这些过程中，或从这些过程移除某一步或数步步骤/操作。
本领域技术人员可以根据实际需要对该制作方法的具体操作步骤的优先顺序做出适当的调整，本公开并非以此为限。
本公开的以上实施例提出了一种半导体器件的制作方法，该制作方法增大了接触孔的连接窗口，有效避免了平台区边缘处的过磨。
本公开的另一方面提出一种半导体器件，该半导体器件的可靠性较高。
本公开的半导体器件包括：由第一材料层和第二材料层交替堆叠的堆叠结构，堆叠结构包括平台区和与平台区相邻的台阶区，平台区的顶部为第一材料层，台阶区的顶部为第二材料层；覆盖台阶区表面的第三材料层；以及填充台阶区的第四材料层；其中，平台区的上表面与第四材料层的上表面齐平。
参考图15所示，该半导体器件(例如半导体结构1000)包括由第一材料层110和第二材料层120交替堆叠的堆叠结构，堆叠结构包括平台区和与平台区相邻的台阶区，平台区的顶部为第一材料层110，台阶区的顶部为第二材料层120。该半导体器件(例如半导体结构1000)还包括覆盖台阶区表面的第三材料层130以及填充台阶区的第四材料层140。其中，平台区的上表面与第四材料层140的上表面齐平。
在本公开的一实施例中，该半导体器件(例如半导体结构1000)还包括位于堆叠结构下的衬底101。
在本公开的一实施例中，第一材料层110包括介质层，第二材料层120包括伪栅极层。
示例性的，第一材料层110的材料例如可以是氧化硅、氧化铝、氧化铪、氧化钽等。第二材料层120的材料例如可以是氮化硅和氮氧化硅(SiOxNx)。
在本公开的一实施例中，第三材料层130的材料包括氮氧化硅、氧化铝、氮化钛中的一种或多种。
在本公开的一实施例中，第四材料层140的材料包括氧化硅。
本公开的半导体器件在制作过程中由于在台阶区的每一个台阶上都保留了第三材料层130作为阻挡层，其与第二材料层120形成了双层阻挡的效果，有效地增大了接触孔的连接窗口，避免了在接触孔刻蚀步骤中出现的上层台阶被刻蚀穿通的现象，提高了产品良率。
应当注意，本公开的半导体器件可以通过例如图5所示的半导体器件的制作方法来实现，但本公开并不以此为限。
本实施例的半导体器件的其他实施细节可参考图5至图16所描述的实施例，在此 不再展开。
本公开的以上实施例提出了一种半导体器件，该半导体器件的可靠性较高。
可以理解，尽管上述披露中通过各种示例讨论了一些目前认为有用的发明实施例，但应当理解的是，该类细节仅起到说明的目的，附加的权利要求并不仅限于披露的实施例，相反，权利要求旨在覆盖所有符合本公开实施例实质和范围的修正和等价的任意组合。
上文已对基本概念做了描述，显然，对于本领域技术人员来说，上述发明披露仅仅作为示例，而并不构成对本公开的限定。虽然此处并没有明确说明，本领域技术人员可能会对本公开进行各种修改、改进和修正。该类修改、改进和修正在本公开中被建议，所以该类修改、改进、修正仍属于本公开示范实施例的精神和范围。
同时，本公开使用了特定词语来描述本公开的实施例。如“一个实施例”、“一实施例”、和/或“一些实施例”意指与本公开至少一个实施例相关的某一特征、结构或特点。因此，应强调并注意的是，本说明书中在不同位置两次或多次提及的“一实施例”或“一个实施例”或“一替代性实施例”并不一定是指同一实施例。此外，本公开的一个或多个实施例中的某些特征、结构或特点可以进行适当的组合。
此外，除非权利要求中明确说明，本公开所述处理元素和序列的顺序、数字字母的使用、或其他名称的使用，并非用于限定本公开流程和方法的顺序。尽管上述披露中通过各种示例讨论了一些目前认为有用的发明实施例，但应当理解的是，该类细节仅起到说明的目的，附加的权利要求并不仅限于披露的实施例，相反，权利要求旨在覆盖所有符合本公开实施例实质和范围的修正和等价组合。例如，虽然以上所描述的系统组件可以通过硬件设备实现，但是也可以只通过软件的解决方案得以实现，如在现有的服务器或移动设备上安装所描述的系统。
同理，应当注意的是，为了简化本公开披露的表述，从而帮助对一个或多个申请实施例的理解，前文对本公开实施例的描述中，有时会将多种特征归并至一个实施例、附图或对其的描述中。但是，这种披露方法并不意味着本公开对象所需要的特征比权利要求中提及的特征多。实际上，实施例的特征要少于上述披露的单个实施例的全部特征。
一些实施例中使用了描述成分、属性数量的数字，应当理解的是，此类用于实施例描述的数字，在一些示例中使用了修饰词“大约”、“近似”或“大体上”来修饰。除非另外说明，“大约”、“近似”或“大体上”表明所述数字允许有±20％的变化。相应地，在一些实施例中，说明书和权利要求中使用的数值参数均为近似值，该近似值根据个别 实施例所需特点可以发生改变。在一些实施例中，数值参数应考虑规定的有效数位并采用一般位数保留的方法。尽管本公开一些实施例中用于确认其范围广度的数值域和参数为近似值，在具体实施例中，此类数值的设定在可行范围内尽可能精确。
虽然本公开已参照当前的具体实施例来描述，但是本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来说明本公开，在没有脱离本公开精神的情况下还可作出各种等效的变化或替换，因此，只要在本公开的实质精神范围内对上述实施例的变化、变型都将落在本公开的权利要求书的范围内。

Claims (20)

  1. 一种半导体结构，包括：
    衬底；
    堆叠结构，位于所述衬底上，由第一材料层和栅极层交替堆叠形成；所述堆叠结构包括平台区和台阶区；
    第三材料层，覆盖在所述台阶区的上表面；
    至少一个接触孔，位于所述台阶区；所述接触孔贯穿所述第三材料层并连接与所述第三材料层相邻的所述栅极层。
  2. 如权利要求1所述的半导体结构，还包括：
    第四材料层，位于所述第三材料层上，且覆盖所述台阶区。
  3. 如权利要求2所述的半导体结构，其中，所述接触孔还贯穿所述第四材料层。
  4. 如权利要求1所述的半导体结构，其中，所述接触孔内填充有导电材料；所述栅极层的材料为所述导电材料。
  5. 如权利要求1所述的半导体结构，其中，所述台阶区包括：多个台阶；
    所述多个台阶由靠近所述平台区到远离所述平台区的方向依次降低。
  6. 如权利要求1所述的半导体结构，其中，所述第三材料层还覆盖所述台阶区外的部分衬底。
  7. 如权利要求1所述的半导体结构，其中，所述第三材料层的材料为氮氧化硅。
  8. 如权利要求1所述的半导体结构，其中，所述第三材料层为氧化铝或氮化钛。
  9. 如权利要求1所述的半导体结构，其中，所述平台区的上表面为第一材料层。
  10. 一种半导体结构的制造方法，包括：
    提供衬底；
    在所述衬底上形成堆叠结构，所述堆叠结构由第一材料层和栅极层交替堆叠形成；所述堆叠结构包括平台区和台阶区；
    在台阶区的上表面形成第三材料层；
    在所述台阶区形成至少一个接触孔；所述接触孔贯穿所述第三材料层并连接与所述第三材料层相邻的所述栅极层。
  11. 如权利要求10所述的方法，还包括：
    形成覆盖所述台阶区的第四材料层；所述第四材料层位于所述第三材料层上。
  12. 如权利要求11所述的方法，其中，在台阶区的上表面形成第三材料层，以及形成 覆盖所述台阶区的第四材料层，包括：
    形成覆盖所述平台区上表面和所述台阶区表面的第三材料层；
    形成填充所述台阶区且覆盖所述平台区的第四材料层；
    去除所述平台区上的至少部分第三材料层和至少部分第四材料层，且保留位于所述平台区靠近所述台阶区的边缘的第三材料层和第四材料层。
  13. 如权利要求12所述的方法，其中，所述形成覆盖所述平台区上表面和所述台阶区表面的第三材料层，包括：
    形成覆盖所述平台区上表面和所述台阶区的表面及台阶区的侧壁的第三材料层；以及
    去除覆盖在所述台阶区的侧壁的第三材料层。
  14. 如权利要求12所述的方法，还包括：
    进行第一次平坦化，将所述第四材料层减薄至与所述平台区表面保留的第三材料层平齐。
  15. 如权利要求14所述的方法，还包括：
    去除所述平台区表面保留的所述第三材料层；
    进行第二次平坦化，去除所述台阶区上的第四材料层的部分厚度，使所述台阶区上的第四材料层的表面与所述平台区顶部的第一材料层表面位于相同平面。
  16. 如权利要求15所述的方法，其中，所述第二次平坦化还用于去除所述平台区顶部的部分所述第一材料层。
  17. 如权利要求11所述的方法，其中，所述在所述台阶区形成接触孔，包括：
    贯穿所述台阶区的第四材料层和所述台阶区的第三材料层，形成所述接触孔。
  18. 如权利要求17所述的方法，还包括：
    在所述接触孔中填充导电材料；其中，所述导电材料与所述栅极层的材料相同。
  19. 如权利要求10所述的方法，其中，所述在所述衬底上形成堆叠结构，包括：
    在所述衬底上交替形成第一材料层和第二材料层；
    将所述第二材料层替换为所述栅极层。
  20. 如权利要求19所述的方法，其中，所述将所述第二材料层替换为所述栅极层，包括：
    通过所述接触孔刻蚀所述第二材料层；
    通过所述接触孔在去除所述第二材料层后的空隙中填充导电材料，形成所述栅极层。
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