WO2022089527A1 - 三维存储器及其制造方法 - Google Patents

三维存储器及其制造方法 Download PDF

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Publication number
WO2022089527A1
WO2022089527A1 PCT/CN2021/127009 CN2021127009W WO2022089527A1 WO 2022089527 A1 WO2022089527 A1 WO 2022089527A1 CN 2021127009 W CN2021127009 W CN 2021127009W WO 2022089527 A1 WO2022089527 A1 WO 2022089527A1
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Prior art keywords
insulating layer
gate
groove
layer
stacked structure
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PCT/CN2021/127009
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English (en)
French (fr)
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汤召辉
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长江存储科技有限责任公司
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Priority to CN202180006374.2A priority Critical patent/CN114667603A/zh
Publication of WO2022089527A1 publication Critical patent/WO2022089527A1/zh
Priority to US18/079,827 priority patent/US20230114522A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Definitions

  • the present disclosure mainly relates to the field of semiconductor design and manufacture, and in particular, to a three-dimensional memory and a manufacturing method thereof.
  • 3D NAND With the continuous development of 3D NAND technology, more and more layers of 3D memory can be vertically stacked, ranging from 24, 32, 64 to more than 100 layers of high-level stacking structures, which can greatly improve the storage density and reduce The price of a unit storage unit.
  • the existing memory generally includes several storage blocks (Block) and several finger storage areas (Finger) located in the storage block (Block).
  • the direction is spaced through the gate line gap of the stack structure.
  • the gate line gap is filled with an insulating layer for separating the gate electrode and an array common source electrode for drawing out the source electrode from the substrate.
  • part of the array common source of some three-dimensional memories is made into an "H"-shaped structure. Specifically, a plurality of sub-array common sources that penetrate the stack structure are firstly formed in the stack structure, adjacent sub-array common sources are separated by a partition structure formed in the stack structure, and then several sub-arrays are formed on the partition structure.
  • the upper part of the isolation structure is an insulating layer penetrating through the multi-layer gate layers and the dielectric layers for separating the gate layers on the top of the stack structure.
  • the insulating layer is formed by a step such as deposition, it is easy to form smaller depressions on the upper surface of the insulating layer.
  • the recesses tend to fill and leave material such as polysilicon. This residual material is prone to create hidden dangers, such as falling off in some processes, interfering with the current process.
  • the embodiments of the present disclosure provide a method for manufacturing a three-dimensional memory, including the steps of: providing a semiconductor structure, the semiconductor structure including a substrate and a stack structure on the substrate,
  • the stacked structure includes alternately stacked gate layers and dielectric layers; or, the stacked structure includes alternately stacked dummy gate layers and the dielectric layer, wherein the gate layer can replace the dummy gate a pole layer;
  • a groove is formed in the gate line gap region of the stacked structure, wherein the groove penetrates through multiple layers of the gate layer and the dielectric layer; or, the groove penetrates through multiple layers of the dielectric layer a dummy gate layer and the dielectric layer;
  • an insulating layer is formed on the surface of the stacked structure and in the groove, wherein the insulating layer above the groove has a recess relative to a surface away from the substrate; and
  • the insulating layer is ground to smooth the depressions.
  • the insulating layer includes a first insulating layer and a second insulating layer
  • first insulating layer and the second insulating layer in sequence on the surface of the stacked structure and in the groove;
  • Grinding the insulating layer to smooth the depressions includes:
  • the second insulating layer is ground to smooth the depressions.
  • grinding the insulating layer to smooth the recesses further includes: forming a gate line gap in the gate line gap region, the gate line gap being cut off by the groove; The gate line gaps are filled with conductive material to form the array common source.
  • the method further includes: forming a connection bridge across the insulating layer in the groove, and the connection bridge communicates with the insulating layer.
  • the separated arrays have a common source.
  • the thickness of the insulating layer on the surface of the stacked structure is 150-250 nm.
  • the step of grinding the insulating layer to smooth the depressions includes controlling the grinding thickness by controlling the grinding time.
  • the groove is located in the core region of the stacked structure.
  • the above method further includes forming a top select gate tangent in the stacked structure, and filling the top select gate tangent with an insulating layer, wherein the top select gate tangent and the groove are at the same etch
  • the insulating layer in the top select gate tangent line and the insulating layer in the groove are formed in the same filling process.
  • the above method further includes forming an array of channel structures in a core region of the stacked structure, the array of channel structures being divided into regions by the gate line gap region.
  • the above method further includes forming a conductive plug on top of each channel structure of the array of channel structures.
  • the stacked structure includes a stack or a plurality of stacked stacks.
  • a three-dimensional memory including a substrate, a stacked structure, a gate line gap, and an insulating layer.
  • the stacked structure is located on the substrate and includes alternately stacked gate layers and dielectric layers.
  • the gate line gap penetrates the stack structure to reach the substrate, and the gate line gap is cut off by the blocking structure.
  • the insulating layer is arranged on the upper part of the partition structure, wherein the surface of the insulating layer relatively far from the substrate is flat.
  • the insulating layer includes a first insulating layer on the isolation structure, and a second insulating layer on the first insulating layer, wherein the second insulating layer is relatively far from the The surface of the first insulating layer is flat.
  • the three-dimensional memory further includes an array common source located in the gate line gap.
  • the three-dimensional memory further includes a connecting bridge across the insulating layer, the connecting bridge connecting the array common sources separated by the insulating layer.
  • the plurality of insulating layers are located in the core region of the stacked structure.
  • the three-dimensional memory further includes: a top select gate tangent line penetrating through the multi-layer gate layers and dielectric layers in the stacked structure; an insulating layer filled in the top select gate tangent line, wherein the top The insulating layer in the select gate tangent line and the insulating layer on the upper part of the isolation structure are formed in the same filling process.
  • the manufacturing method of the three-dimensional memory according to the embodiment of the present disclosure can reduce hidden dangers, such as falling off of residual materials.
  • FIG. 1 is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
  • 2A-2D are schematic top views of an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present disclosure.
  • 3A-3G are schematic cross-sectional views along the Y direction during an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present disclosure.
  • 4A-4E are schematic cross-sectional views along the X direction during an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present disclosure.
  • orientations such as “front, rear, top, bottom, left, right", “horizontal, vertical, vertical, horizontal” and “top, bottom” indicate the orientation Or the positional relationship is usually based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present disclosure and simplifying the description, and these orientations do not indicate or imply the indicated device or element unless otherwise stated. It must have a specific orientation or be constructed and operated in a specific orientation, so it should not be construed as a limitation on the protection scope of the present disclosure; the orientation words “inside and outside” refer to the inside and outside relative to the outline of each component itself.
  • spatially relative terms such as “on”, “over”, “on the surface”, “above”, etc., may be used herein to describe what is shown in the figures.
  • spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “above” or “over” other devices or features would then be oriented “below” or “over” the other devices or features under other devices or constructions”.
  • the exemplary term “above” can encompass both an orientation of "above” and “below.”
  • the device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.
  • Flow diagrams are used in this disclosure to illustrate operations performed by a system according to an embodiment of the present disclosure. It should be understood that the preceding or following operations are not necessarily performed in exact order. Rather, the various steps may be processed in reverse order or concurrently. At the same time, other actions are either added to these processes, or a step or steps are removed from these processes.
  • Embodiments of the present disclosure describe a method for manufacturing a three-dimensional memory.
  • the method forms common sources of several sub-arrays running through in the stack structure, and the common sources of adjacent sub-arrays are separated by partition structures formed in the stack structure.
  • the upper part of the isolation structure is an insulating layer penetrating through the multi-layer gate layers and the dielectric layers for separating the gate layers on the top of the stack structure.
  • the method can reduce the material residue of the upper insulating layer of the isolation structure.
  • FIG. 1 is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
  • 2A-2D are schematic top views of an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present disclosure.
  • 3A-3G are schematic cross-sectional views along the Y direction during an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present disclosure.
  • 4A-4E are schematic cross-sectional views along the X direction during an exemplary manufacturing process of a three-dimensional memory in an embodiment of the present disclosure. The manufacturing method of the embodiment of the present disclosure is described below with reference to FIGS. 1-4E .
  • a semiconductor structure including a substrate and a stacked structure on the substrate, the stacked structure including alternately stacked gate layers and dielectric layers.
  • FIG. 3A is a cross-sectional view taken along line A-A of FIG. 2A .
  • the semiconductor structure includes a substrate 201 and a stack structure including a first stack 210 and a second stack 220 on the substrate. For simplicity, only the semiconductor structure used to form the core region of the three-dimensional memory is shown. The core area is used to form an array of memory cells.
  • the stacked structure includes a plurality of dummy gate layers 211 and a plurality of dielectric layers 212 which are alternately stacked.
  • the dummy gate layer 211 may include a top select dummy gate layer 211 a on the top layer or layers of the second stack 220 , and may further include a bottom select dummy gate layer 211 b on the bottom of the first stack 210 .
  • the substrate 201 may be a silicon substrate (Si), a germanium substrate (Ge), a silicon germanium substrate (SiGe), silicon on insulator (SOI, Silicon on Insulator) or germanium on insulator (GOI, Germanium on Insulator) Wait.
  • the substrate 201 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. It can also be a stacked structure, such as Si/SiGe and the like. Other epitaxial structures may also be included, such as silicon germanium on insulator (SGOI), and the like.
  • the substrate 201 may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer, among others.
  • the dummy gate layer 211 and the dielectric layer 212 may be selected from the following materials and include at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like. combination.
  • the dummy gate layer 211 and the dielectric layer 212 have different etch selectivities. For example, it may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like.
  • the deposition method of the dummy gate layer 211 and the insulating layer 212 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, Various methods such as evaporation and sputtering are used.
  • CVD chemical vapor deposition
  • PECVD PECVD
  • LPCVD atomic layer deposition
  • ALD atomic layer deposition
  • MBE molecular beam epitaxy
  • thermal oxidation Various methods such as evaporation and sputtering are used.
  • the gate last fabrication technique uses a dummy gate layer to facilitate formation of the channel structure of the memory cell and replaces the dummy gate layer with the gate of the memory cell after the formation of the channel structure.
  • the dummy gate layer is removed and then the gate layer is formed.
  • Gate first fabrication techniques form the gate of the memory cell earlier than the channel structure of the memory cell.
  • the material used as the gate layer may be a conductive material such as metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon, or any combination thereof.
  • the first channel hole 215 has been previously formed in the bottom first stack 210 and filled with the sacrificial layer 214 .
  • the material of the sacrificial layer 214 may be polysilicon.
  • the array of the first channel holes 215 is divided into a plurality of memory blocks (eg, 202 and 203 ), and each memory block is separated by a gate line gap region 204 .
  • conductive parts 217 are respectively formed at the bottoms of the first channel holes 215 .
  • the conductive portion 217 is, for example, silicon formed by a selective epitaxial growth (SEG) process.
  • FIG. 3A shows a stack structure including 2 stacks, more or less stacks are within the scope of the present disclosure. In other examples, a single stack may be used, and in this case, there will be no pre-formed structures such as the first channel hole 215 , the sacrificial layer 214 , the conductive portion 217 and the like in the stack structure.
  • step 102 a plurality of grooves are formed spaced apart in the gate line gap region of the planarized and unpolished stack structure, each groove penetrating through the multi-layer gate layer and the dielectric layer.
  • FIG. 3B is a cross-sectional view taken along line A-A of FIG. 2B .
  • a plurality of grooves 221 a are spaced apart in the gate line gap region 204 . It can be understood that the grooves 221a are distributed in the core area of the three-dimensional memory. The grooves 221a penetrate through the stack of multiple gate layers and dielectric layers. There are still many stacks of gate layers and dielectric layers below the recess 221a.
  • a top select gate tangent 221b extending in the X direction is also formed in the stack structure in this step.
  • the top select gate tangent line 221b is used to divide a plurality of finger memory areas in one memory block.
  • Each top select gate tangent line 221b faces a lower row of dummy first channel holes 215 . Therefore, the top select gate line 221b and the groove 221a are formed in the same etching process. In this way, the formation of the grooves 221a can be completed by relying on the existing process, only the photomask pattern originally used for etching the top selection gate tangent line needs to be changed, and additional photomask and etching processes are not required.
  • the depths of recess 221a and top select gate tangent 221b are the same. In one embodiment, the width of the groove 221a in the Y direction is greater than the width of the top select gate tangent line 221b in the Y direction.
  • the polishing is typically chemical mechanical polishing (Chemical Mechanical Polishing, CMP).
  • CMP Chemical Mechanical Polishing
  • the inventors of the present disclosure found that removing the CMP step here can alleviate the problem of uneven layer thickness, and further make the process window of the aforementioned etching (usually dry etching) wider and the depth of etching stay deeper. Consistent.
  • step 103 an insulating layer is covered on the surface of the stacked structure and the plurality of grooves, wherein the surface of the insulating layer above the plurality of grooves has depressions.
  • FIG. 3C is a cross-sectional view taken along line A-A of FIG. 2C.
  • a first insulating layer 222a is covered on the surface of the stacked structure and in the plurality of grooves 221a.
  • the first insulating layer 222a may be formed using a furnace tube process.
  • a second insulating layer 222b is covered on the surface of the stacked structure and the plurality of grooves 221a.
  • the second insulating layer 222b may be formed using a physical vapor deposition (Physical Vapor Deposition, PVD) process.
  • PVD Physical Vapor Deposition
  • the top select gate tangent line 221b is also filled with an insulating layer, more specifically, the first insulating layer 222a.
  • the insulating layer in the top select gate tangent line 221b and the insulating layer in the groove 221a are formed in the same filling process.
  • the thickness of the insulating layer 222 (including the first insulating layer and the second insulating layer) on the surface of the stacked structure is between 150-250 nm.
  • the material of the insulating layer 222 is, for example, silicon oxide.
  • the stacked structure has recesses 223 on the surface of the insulating layer above the grooves 221a and the top select gate tangent lines 221b.
  • the insulating layer is ground to smooth the depressions.
  • FIG. 4A is a cross-sectional view taken along line B-B of FIG. 2C .
  • the insulating layer is ground using a CMP process to smooth the depressions 223 to obtain a flat surface of the insulating layer.
  • the grinding time is controlled to control the grinding thickness.
  • the polishing thickness can be set to 20 nm, and the polishing time can be set accordingly.
  • grinding can be performed after forming the insulating layer, which can eliminate recesses, thereby avoiding material residues in subsequent processes.
  • step 105 an array of channel structures is formed in the core region of the stack structure, and the array of channel structures is divided into a plurality of regions by the gate line gap region.
  • a plurality of channel structures 216 are formed vertically through the stack structure.
  • the memory layer and the channel layer are arranged in order from the outside to the inside along the radial direction of the channel hole.
  • the memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed from outside to inside along a radial direction of the channel hole.
  • a filling layer may also be provided in the channel layer.
  • the filling layer can function as a support.
  • the material of the filling layer may be silicon oxide.
  • the filling layer can be solid or hollow without affecting the reliability of the device.
  • the formation of the vertical channel structure can be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, etc., or any combination thereof.
  • conductive plugs are formed on top of each channel structure of the array of channel structures.
  • a portion of the material is removed on top of each channel structure, and then the conductive material 218a is covered.
  • the conductive material 218a is, for example, polysilicon. Then, as shown in FIG. 3G , the conductive material on the surface of the stacked structure is removed, and the conductive material on the top of the channel structure is retained as the conductive plug 218 .
  • a gate line gap is formed in the gate line gap region, and the gate line gap is separated by a plurality of grooves.
  • FIG. 4B is a cross-sectional view taken along line B-B of FIG. 2D .
  • the gate line gap 205 is formed by vertical etching in the region of the gate line gap region 204 without the groove 221 a and the insulating layer 222 .
  • the gate line gap 205 is cut off by the insulating layer in the groove 221a and the isolation structure formed by the stacked layer under the groove 221a.
  • the stack structure Due to the support function of the partition structure, the stack structure is not easily collapsed when the gate line gap 205 is formed, which improves the stability of the stack structure.
  • the dummy gate layer 211 in the stacked layers can be removed through the gate line gap 205 to form a gap, and the dummy gate is replaced by the gate layer 211g Pole layer 211 .
  • the material of the gate layer 211g is, for example, metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon, or any combination thereof.
  • the gate line gaps are filled with conductive material to form an array common source.
  • the gate line gap 205 is covered with the spacer 225 first, and then filled with conductive material to form the array common source 226 .
  • the material of the spacer 225 is silicon oxide, and the conductive material is polysilicon, for example.
  • the array common source 226 is still separated by the insulating layer in the groove 221a and the isolation structure formed by the stacked layer under the groove 221a.
  • connecting bridges are formed across the insulating layers in each groove, the connecting bridges connecting the array common sources separated by the insulating layers.
  • an insulating layer 227 is covered on the surface of the semiconductor structure, and then the insulating layer above the gate line gap 205 is removed to form an opening. Subsequently, as shown in FIG. 4E , the opening of the gate line gap 205 is covered with a conductive material as a connecting bridge 228 .
  • the conductive material is, for example, metal tungsten, cobalt, copper, nickel, and the like.
  • a flowchart is used herein to illustrate the operations performed by a method according to an embodiment of the present disclosure. It should be understood that the preceding operations are not necessarily performed in exact order. Rather, the various steps may be processed in reverse order or concurrently. At the same time, other actions are either added to these processes, or a step or steps are removed from these processes.
  • the structure of a three-dimensional memory according to an embodiment of the present disclosure is described below with reference to FIGS. 3G and 4E .
  • the three-dimensional memory includes a substrate 201 and a stacked structure 206 on the substrate 201 .
  • the stacked structure 206 includes alternately stacked gate layers 211 g and dielectric layers 212 .
  • the gate line gap 205 penetrates the stack structure 206 to reach the substrate 201 .
  • the gate line gap 205 is partitioned by a plurality of spaced isolation structures.
  • each isolation structure is an insulating layer 222 , and below the insulating layer 222 are alternately stacked gate layers 211 g and dielectric layers 212 .
  • Each insulating layer 222 penetrates through the multilayer gate layer 211 g and the dielectric layer 212 .
  • the upper surface of each insulating layer 222 is flat without small recesses, and thus does not accommodate impurity particles such as polysilicon.
  • the three-dimensional memory also includes an array common source 226 located in each gate line gap 205 .
  • a connecting bridge 228 is provided across each insulating layer 222, thereby connecting the array common sources 226 separated by the partition structure.
  • the three-dimensional memory further includes a top select gate tangent line 221b penetrating through the multi-layer gate layers and the dielectric layers in the stacked structure.
  • the insulating layer is filled in the groove 221a and the top select gate tangent line 221b at the same time.
  • the insulating layer in the top select gate tangent line and the insulating layer above the isolation structure are formed in the same filling process, thereby saving process.
  • the three-dimensional storage device may be a 3D flash memory, such as a 3D NAND flash memory.
  • 3D flash memory such as a 3D NAND flash memory.

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Abstract

本公开实施例提供了一种三维存储器及其制造方法。该方法包括以下步骤：提供半导体结构，所述半导体结构包括衬底和位于所述衬底上的堆叠结构，所述堆叠结构包括交替层叠的栅极层和介电层；或者，所述堆叠结构包括交替层叠的伪栅极层和所述介电层，其中，所述栅极层可替代所述伪栅极层；在所述堆叠结构的栅线隙区中形成凹槽，其中，所述凹槽贯穿多层所述栅极层和所述介电层；或者，所述凹槽贯穿多层所述伪栅极层和所述介电层；在所述堆叠结构表面及所述凹槽中形成绝缘层，其中，所述凹槽上方的绝缘层相对远离所述衬底的表面具有凹陷；以及对所述绝缘层进行研磨以磨平所述凹陷。

Description

三维存储器及其制造方法
相关申请的交叉引用
本申请基于申请号为202011174467.X、申请日为2020年10月28日、发明名称为“三维存储器及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开主要涉及半导体设计及制造领域，尤其涉及一种三维存储器及其制造方法。
背景技术
随着3D NAND技术的不断发展，三维存储器可以垂直堆叠的层数越来越多，从24层、32层、64层到超过100层的高阶堆叠结构，可以大幅度提高存储的密度并降低单位存储单元的价格。
现有的存储器一般包括若干存储块(Block)以及位于存储块(Block)中的若干指存储区(Finger)，存储块与存储块之间以及指存储区与指存储区之间一般通过沿垂直方向贯穿堆叠结构的栅线隙隔开。栅线隙内填充用于隔开栅极的绝缘层和用于从衬底引出源极的阵列共源极。为了提高堆叠结构的强度，防止堆叠结构倾斜或倒塌，一些三维存储器的部分阵列共源极被做成“H”型结构。具体地，先在堆叠结构中形成贯穿堆叠结构的若干子阵列共源极，相邻子阵列共源极之间通过堆叠结构中形成的隔断结构隔开，然后在隔断结构上形成将若干子阵列共源极连接的连接桥。隔断结构上部是贯穿多层栅极层和介电层的绝缘层，用于隔开堆叠结构顶部的栅极层。在通过诸如沉积的步骤形成该绝缘层时，容易在绝缘层上表面形成较小的凹陷。在后续工艺中，此凹陷容易填入并残留例如多 晶硅的材料。这一残留材料容易形成隐患，例如在某些工艺中脱落，干扰当前工艺的进行。
发明内容
根据本公开实施例的第一方面，本公开实施例提供了一种三维存储器的制造方法，包括以下步骤：提供半导体结构，所述半导体结构包括衬底和位于所述衬底上的堆叠结构，所述堆叠结构包括交替层叠的栅极层和介电层；或者，所述堆叠结构包括交替层叠的伪栅极层和所述介电层，其中，所述栅极层可替代所述伪栅极层；在所述堆叠结构的栅线隙区中形成凹槽，其中，所述凹槽贯穿多层所述栅极层和所述介电层；或者，所述凹槽贯穿多层所述伪栅极层和所述介电层；在所述堆叠结构表面及所述凹槽中形成绝缘层，其中，所述凹槽上方的绝缘层相对远离所述衬底的表面具有凹陷；以及对所述绝缘层进行研磨以磨平所述凹陷。
在一些实施例中，所述绝缘层包括第一绝缘层和第二绝缘层；
所述在所述堆叠结构表面及所述凹槽中形成绝缘层，其中，所述凹槽上方的绝缘层相对远离所述衬底的表面具有凹陷，包括：
在所述堆叠结构表面及所述凹槽中依次形成所述第一绝缘层和所述第二绝缘层；
对所述绝缘层进行研磨以磨平所述凹陷，包括：
对所述第二绝缘层进行研磨以磨平所述凹陷。
在一些实施例中，对所述绝缘层进行研磨以磨平所述凹陷后还包括：在所述栅线隙区形成栅线隙，所述栅线隙被所述凹槽隔断；在所述栅线隙中填充导电材料以形成阵列共源极。
在一些实施例中，在所述栅线隙中填充导电材料以形成阵列共源极后还包括：形成跨越所述凹槽中的绝缘层的连接桥，所述连接桥连通被所述绝缘层隔开的阵列共源极。
在一些实施例中，所述堆叠结构表面的绝缘层的厚度为150-250nm。
在一些实施例中，对所述绝缘层进行研磨以磨平所述凹陷的步骤，包括通过控制所述研磨的时间来控制研磨厚度。
在一些实施例中，所述凹槽位于所述堆叠结构的核心区。
在一些实施例中，上述方法还包括在所述堆叠结构中形成顶部选择栅切线，且在所述顶部选择栅切线中填充绝缘层，其中所述顶部选择栅切线和所述凹槽在同一刻蚀工艺中形成，且所述顶部选择栅切线中的绝缘层和所述凹槽中的绝缘层在同一填充工艺中形成。
在一些实施例中，上述方法还包括在所述堆叠结构的核心区中形成沟道结构阵列，所述沟道结构阵列被所述栅线隙区分隔为多个区域。
在一些实施例中，上述方法还包括形成位于所述沟道结构阵列的各个沟道结构顶部的导电插塞。
在一些实施例中，所述堆叠结构包括一个堆栈或多个堆叠的堆栈。
根据本公开实施例的第二方面，提出一种三维存储器，包括衬底、堆叠结构、栅线隙和绝缘层。堆叠结构位于所述衬底上，包括交替层叠的栅极层和介电层。栅线隙贯穿堆叠结构到达衬底，栅线隙被隔断结构隔断。绝缘层设于隔断结构上部，其中，所述绝缘层相对远离所述衬底的表面是平坦的。
在一些实施例中，所述绝缘层包括位于所述隔断结构上的第一绝缘层，以及位于所述第一绝缘层上的第二绝缘层，其中，所述第二绝缘层的相对远离所述第一绝缘层的表面是平坦的。
在一些实施例中，三维存储器还包括位于所述栅线隙中的阵列共源极。
在一些实施例中，三维存储器还包括跨越所述绝缘层的连接桥，所述连接桥连通被所述绝缘层隔开的阵列共源极。
在一些实施例中，所述多个绝缘层位于所述堆叠结构的核心区。
在一些实施例中，三维存储器还包括：顶部选择栅切线，贯穿所述堆叠结构中的多层栅极层和介电层；填充于所述顶部选择栅切线中的绝缘层，其中所述顶部选择栅切线中的绝缘层和所述隔断结构上部的绝缘层在同一填充工艺中形成。
与现有技术相比，本公开实施例的三维存储器的制造方法，在形成覆盖栅线隙区的凹槽的绝缘层后再进行研磨，可以消除绝缘层表面的凹陷，从而避免后续工艺中材料的残留。因此本公开实施例提供的三维存储器的制造方法可以降低残留材料的脱落等隐患。
附图说明
包括附图是为提供对本公开进一步的理解，它们被收录并构成本公开的一部分，附图示出了本公开的实施例，并与本说明书一起起到解释本公开原理的作用。附图中：
图1是本公开一实施例的三维存储器的制造方法流程图。
图2A-2D是本公开一实施例中的三维存储器的示例性制造过程中的俯视示意图。
图3A-3G是本公开一实施例中的三维存储器的示例性制造过程中沿Y方向的剖面示意图。
图4A-4E是本公开一实施例中的三维存储器的示例性制造过程中沿X方向的剖面示意图。
具体实施方式
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本公开的一些示例或实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本公开应用于其 他类似情景。除非从语言环境中显而易见或另做说明，图中相同标号代表相同结构或操作。
如本公开和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
在本公开的描述中，需要理解的是，方位词如“前、后、上、下、左、右”、“横向、竖向、垂直、水平”和“顶、底”等所指示的方位或位置关系通常是基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，在未作相反说明的情况下，这些方位词并不指示和暗示所指的装置或元件必须具有特定的方位或者以特定的方位构造和操作，因此不能理解为对本公开保护范围的限制；方位词“内、外”是指相对于各部件本身的轮廓的内外。
为了便于描述，在这里可以使用空间相对术语，如“在……之上”、 “在……上方”、“在……上表面”、“上面的”等，用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如，如果附图中的器件被倒置，则描述为“在其他器件或构造上方”或“在其他器件或构造之上”的器件之后将被定位为“在其他器件或构造下方”或“在其他器件或构造之下”。因而，示例性术语“在……上方”可以包括“在……上方”和“在……下方”两种方位。该器件也可以其他不同方式定位(旋转90度或处于其他方位)，并且对这里所使用的空间相对描述作出相应解释。
此外，需要说明的是，使用“第一”、“第二”等词语来限定零部件，仅仅是为了便于对相应零部件进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本公开保护范围的限制。此外，尽管本公开中所使用的术语是从公知公用的术语中选择的，但是本公开说明书中所提及的一些术语可能是申请人按他或她的判断来选择的，其详细含义在本文的描述的相关部分中说明。此外，要求不仅仅通过所使用的实际术语，而是还要通过每个术语所蕴含的意义来理解本公开。
应当理解，当一个部件被称为“在另一个部件上”、“连接到另一个部件”、“耦合于另一个部件”或“接触另一个部件”时，它可以直接在该另一个部件之上、连接于或耦合于、或接触该另一个部件，或者可以存在插入部件。相比之下，当一个部件被称为“直接在另一个部件上”、“直接连接于”、“直接耦合于”或“直接接触”另一个部件时，不存在插入部件。同样的，当第一个部件被称为“电接触”或“电耦合于”第二个部件，在该第一部件和该第二部件之间存在允许电流流动的电路径。该电路径可以包括电容器、耦合的电感器和/或允许电流流动的其它部件，甚至在导电部件之间没有直接接触。
本公开中使用了流程图用来说明根据本公开的实施例的系统所执行的操作。应当理解的是，前面或下面操作不一定按照顺序来精确地执行。相反，可以按照倒序或同时处理各种步骤。同时，或将其他操作添加到这些过程中，或从这些过程移除某一步或数步操作。
本公开实施例描述一种三维存储器的制造方法。该方法在堆叠结构中形成贯穿的若干子阵列共源极，相邻子阵列共源极之间通过堆叠结构中形成的隔断结构隔开。隔断结构上部是贯穿多层栅极层和介电层的绝缘层，用于隔开堆叠结构顶部的栅极层。该方法可以减少隔断结构上部绝缘层的材料残留。
图1是本公开一实施例的三维存储器的制造方法流程图。图2A-2D是本公开一实施例中的三维存储器的示例性制造过程中的俯视示意图。图3A-3G是本公开一实施例中的三维存储器的示例性制造过程中沿Y方向的剖面示意图。图4A-4E是本公开一实施例中的三维存储器的示例性制造过程中沿X方向的剖面示意图。下面参考图1-图4E描述本公开实施例的制造方法。
在步骤101，提供半导体结构，包括衬底和位于衬底上的堆叠结构，堆叠结构包括交替层叠的栅极层和介电层。
图3A是图2A的A-A剖视图。参考图2A和3A所示，半导体结构包括衬底201和位于衬底上的包括第一堆栈210和第二堆栈220的堆叠结构。为简化起见，仅显示用于形成三维存储器的核心区的半导体结构。核心区用于形成存储单元阵列。堆叠结构包括交替堆叠的多个伪栅极层211以及多个介电层212。伪栅极层211可包括位于第二堆栈220的顶部一层或多层的顶部选择伪栅极层211a，还可包括位于第一堆栈210的底部的底部选择伪栅极层211b。
该衬底201可以是硅衬底(Si)、锗衬底(Ge)、锗化硅衬底(SiGe)、 绝缘体上硅(SOI，Silicon on Insulator)或绝缘体上锗(GOI，Germanium on Insulator)等。在一些实施例中，该衬底201还可以为包括其他元素半导体或化合物半导体的衬底，如GaAs、InP或SiC等。还可以是叠层结构，例如Si/SiGe等。还可以包括其他外延结构，例如绝缘体上锗硅(SGOI)等。在一些实施例中，衬底201可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆等。
伪栅极层211以及介电层212可以是选自以下材料并且至少包括一种绝缘介质，例如氮化硅、氧化硅、非晶碳、类金刚石无定形碳、氧化锗、氧化铝等及其组合。伪栅极层211以及介电层212具有不同的刻蚀选择性。例如可以是氮化硅和氧化硅的组合、氧化硅与未掺杂的多晶硅或非晶硅的组合、氧化硅或氮化硅与非晶碳的组合等。伪栅极层211以及绝缘层212的沉积方法可以包括化学气相沉积(CVD、PECVD、LPCVD、HDPCVD)、原子层沉积(ALD)，或物理气相沉积方法如分子束外延(MBE)、热氧化、蒸发、溅射等其各种方法。
各种制造技术(诸如栅极首先制造技术、栅极最后制造技术等)可以用于制造三维存储器。如图3A所示，栅极最后制造技术使用伪栅极层来便于存储器单元的沟道结构的形成，并在沟道结构的形成之后利用存储器单元的栅极代替伪栅极层。为了利用栅极代替伪栅极层，移除伪栅极层并随后形成栅极层。栅极首先制造技术比存储器单元的沟道结构更早地形成存储器单元的栅极。在此制造技术中，作为栅极层的材料可以是导电材料例如金属钨、钴、铜、镍等，也可以是多晶硅、掺杂硅或其任何组合。
继续参考图2A和3A所示，在底部的第一堆栈210中已事先形成第一沟道孔215并填充牺牲层214。牺牲层214的材料可以是多晶硅。如图2A所示，第一沟道孔215的阵列被分为多个存储块(如202和203)， 每个存储块之间以栅线隙区204隔开。
另外，在第一沟道孔215底部分别形成了导电部217。导电部217例如是以选择性外延生长(Selective Epitaxial Growth,SEG)工艺形成的硅。
需要指出是，尽管图3A的示例图中显示了包括2个堆栈的堆叠结构，但是更多或更少堆栈也在本公开的实施范围内。在其他示例中，可以使用单个堆栈，此时，堆叠结构中不会有预先形成的第一沟道孔215、牺牲层214、导电部217等结构。
在步骤102，在经过平坦化且未经研磨的堆叠结构的栅线隙区中间隔形成多个凹槽，每一凹槽贯穿多层栅极层和介电层。
图3B是图2B的A-A剖视图。参考图2B和3B所示，在对堆叠结构的第二堆栈220平坦化后，且在研磨之前，在栅线隙区204中间隔形成多个凹槽221a。可以理解，凹槽221a分布在三维存储器的核心区。凹槽221a贯穿多层栅极层和介电层的叠层。凹槽221a下方仍然有许多栅极层和介电层的叠层。
在一个实施例中，在此步骤中还在堆叠结构中形成在X方向延伸的顶部选择栅切线221b。顶部选择栅切线221b用于在一个存储块中划分多个指存储区。每一顶部选择栅切线221b对着下方的一排虚设的第一沟道孔215。因此，顶部选择栅切线221b和凹槽221a在同一刻蚀工艺中形成。这种做法使得凹槽221a的形成依靠已有工艺即可完成，只需改变原本用于刻蚀顶部选择栅切线的光掩模图案，无需额外的光掩模和刻蚀工艺。在一个实施例中，凹槽221a和顶部选择栅切线221b的深度是相同的。在一个实施例中，凹槽221a在Y方向上的宽度大于顶部选择栅切线221b在Y方向的宽度。
在此，研磨典型地为化学机械研磨(Chemical Mechanical Polishing,CMP)。常规上，平坦化后会有CMP步骤。本公开的发明人发现，移除 此处的CMP步骤，可以缓解层厚不均匀的问题，进一步使得前述刻蚀(通常使用干法刻蚀)的工艺窗宽更大，刻蚀停留的深度更一致。
在步骤103，在堆叠结构表面及多个凹槽中覆盖绝缘层，其中多个凹槽上方的绝缘层表面具有凹陷。
图3C是图2C的A-A剖视图。如图2C和3C所示，在堆叠结构表面及多个凹槽221a中覆盖第一绝缘层222a。第一绝缘层222a可以使用炉管工艺形成。接着，如图3D所示，在堆叠结构表面及多个凹槽221a中覆盖第二绝缘层222b。第二绝缘层222b可以使用物理气相沉积(Physical Vapor Deposition,PVD)工艺形成。第一绝缘层222a和第二绝缘层222b共同构成绝缘层222。
在同时形成了顶部选择栅切线的示例中，也在顶部选择栅切线221b中填充绝缘层，更具体为第一绝缘层222a。顶部选择栅切线221b中的绝缘层和凹槽221a中的绝缘层在同一填充工艺中形成。
在一个实施例中，堆叠结构表面的绝缘层222(包括第一绝缘层和第二绝缘层)的厚度在150-250nm之间。绝缘层222的材料例如是氧化硅。
参考图3D所示，堆叠结构在凹槽221a及顶部选择栅切线221b上方的绝缘层表面具有凹陷223。
在步骤104，对绝缘层进行研磨以磨平凹陷。
图4A是图2C的B-B剖视图。参考2C、图3E和图4A所示，使用CMP工艺对绝缘层进行研磨，以磨平凹陷223，得到平坦的绝缘层表面。在一个实施例中，控制研磨的时间来控制研磨厚度。举例来说，可将研磨厚度设定为20nm，并据此设置研磨时间。
与常规技术相比，在形成绝缘层后再进行研磨，可以消除凹陷，从而避免后续工艺中材料的残留。
在步骤105，在堆叠结构的核心区中形成沟道结构阵列，沟道结构阵 列被栅线隙区分隔为多个区域。
参考图3F所示，形成垂直贯穿堆叠结构的多个沟道结构216。整体来看，在沟道结构中，沿沟道孔的径向从外向内依次设置的是存储器层和沟道层。存储器层可以包括沿沟道孔的径向从外向内依次设置的阻挡层、电荷捕获层和隧穿层。沟道层内还可设有填充层。填充层可以起到支撑物的作用。填充层的材料可以是氧化硅。填充层可以是实心的，在不影响器件可靠性的前提下也可以是中空的。垂直沟道结构的形成可以采用一个或多个薄膜沉积工艺来实现，例如ALD、CVD、PVD等或其任意组合。
在步骤106，形成位于沟道结构阵列的各个沟道结构顶部的导电插塞。
参考图3F所示，在各个沟道结构顶部去除部分材料，再覆盖导电材料218a。导电材料218a例如是多晶硅。然后如图3G所示，去除堆叠结构表面的导电材料，保留沟道结构顶部的导电材料作为导电插塞218。
在此，由于导电材料218a之下的绝缘层已经是平整的，因此不会有残留的导电材料留在绝缘层表面，造成隐患。
在步骤107，在栅线隙区形成栅线隙，栅线隙被多个凹槽隔断。
图4B是图2D的B-B剖视图。参考2D和图4B所示，在栅线隙区204没有凹槽221a及绝缘层222的区域垂直进行刻蚀，形成栅线隙205。在此，栅线隙205会被凹槽221a中绝缘层及凹槽221a之下的堆叠层所组成的隔断结构隔断。
由于隔断结构的支撑作用，形成栅线隙205时不易造成堆叠结构垮塌，提高了堆叠结构的稳定性。
参考图4B所示，在栅极最后制造技术中，在形成栅线隙205后，可通过栅线隙205去除堆叠层中的伪栅极层211，形成间隙，并用栅极层211g代替伪栅极层211。栅极层211g的材料例如是金属钨、钴、铜、镍 等，也可以是多晶硅、掺杂硅或其任何组合。
在步骤108，在栅线隙中填充导电材料以形成阵列共源极。
参考步骤4C所示，在栅线隙205中先覆盖间隙壁225，再填充导电材料，形成形成阵列共源极226。在一个实施例中，间隙壁225的材料是氧化硅，导电材料例如是多晶硅。阵列共源极226仍然会被凹槽221a中绝缘层及凹槽221a之下的堆叠层所组成的隔断结构隔开。
在步骤109，形成跨越每个凹槽中的绝缘层的连接桥，连接桥连通被绝缘层隔开的阵列共源极。
参考图4D所示，在半导体结构表面覆盖绝缘层227，然后去除栅线隙205之上的绝缘层，形成开口。随后如图4E所示，在栅线隙205的开口处覆盖导电材料，作为连接桥228。导电材料例如是金属钨、钴、铜、镍等。
在此使用了流程图用来说明根据本公开的实施例的方法所执行的操作。应当理解的是，前面的操作不一定按照顺序来精确地执行。相反，可以按照倒序或同时处理各种步骤。同时，或将其他操作添加到这些过程中，或从这些过程移除某一步或数步操作。
在上述方法之后，再进行常规的步骤，即可得到根据本公开一实施例的三维存储器。下面结合参考图3G和图4E描述根据本公开一实施例的三维存储器的结构。三维存储器包括衬底201和位于衬底201上的堆叠结构206。堆叠结构206包括交替层叠的栅极层211g和介电层212。栅线隙205贯穿堆叠结构206而到达衬底201。栅线隙205被多个间隔的隔断结构隔断，每一隔断结构上部为绝缘层222，绝缘层222之下为交替层叠的栅极层211g和介电层212。每一绝缘层222贯穿多层栅极层211g和介电层212。如前文参考图3E所描述的，每一绝缘层222的上表面是平坦的，没有小的凹陷，因此不会容纳例如多晶硅等杂质颗粒。
继续参考图4E所示，三维存储器还包括位于各个栅线隙205中的阵列共源极226。在每个栅线隙处，设有跨越每个绝缘层222的连接桥228，从而连通被隔断结构隔开的阵列共源极226。
参考图3G所示，三维存储器还包括顶部选择栅切线221b，贯穿堆叠结构中的多层栅极层和介电层。绝缘层同时填充于凹槽221a和顶部选择栅切线221b中。在一个实施例中，顶部选择栅切线中的绝缘层和隔断结构上部的绝缘层在同一填充工艺中形成，从而节省工艺。
在本公开实施例的上下文中，三维存储器件可以是3D闪存，例如3D NAND闪存。上文已对基本概念做了描述，显然，对于本领域技术人员来说，上述公开披露仅仅作为示例，而并不构成对本公开的限定。虽然此处并没有明确说明，本领域技术人员可能会对本公开进行各种修改、改进和修正。该类修改、改进和修正在本公开中被建议，所以该类修改、改进、修正仍属于本公开示范实施例的精神和范围。
同时，本公开使用了特定词语来描述本公开的实施例。如“一个实施例”、“一实施例”、和/或“一些实施例”意指与本公开至少一个实施例相关的某一特征、结构或特点。因此，应强调并注意的是，本说明书中在不同位置两次或多次提及的“一实施例”或“一个实施例”或“一替代性实施例”并不一定是指同一实施例。此外，本公开的一个或多个实施例中的某些特征、结构或特点可以进行适当的组合。
同理，应当注意的是，为了简化本公开披露的表述，从而帮助对一个或多个公开实施例的理解，前文对本公开实施例的描述中，有时会将多种特征归并至一个实施例、附图或对其的描述中。但是，这种披露方法并不意味着本公开对象所需要的特征比权利要求中提及的特征多。实际上，实施例的特征要少于上述披露的单个实施例的全部特征。
一些实施例中使用了描述成分、属性数量的数字，应当理解的是， 此类用于实施例描述的数字，在一些示例中使用了修饰词“大约”、“近似”或“大体上”来修饰。除非另外说明，“大约”、“近似”或“大体上”表明所述数字允许有±20％的变化。相应地，在一些实施例中，说明书和权利要求中使用的数值参数均为近似值，该近似值根据个别实施例所需特点可以发生改变。在一些实施例中，数值参数应考虑规定的有效数位并采用一般位数保留的方法。尽管本公开一些实施例中用于确认其范围广度的数值域和参数为近似值，在具体实施例中，此类数值的设定在可行范围内尽可能精确。
虽然本公开已参照当前的具体实施例来描述，但是本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来说明本公开，在没有脱离本公开精神的情况下还可作出各种等效的变化或替换，因此，只要在本公开的实质精神范围内对上述实施例的变化、变型都将落在本公开的权利要求书的范围内。

Claims (17)

  1. 一种三维存储器的制造方法，包括以下步骤：
    提供半导体结构，所述半导体结构包括衬底和位于所述衬底上的堆叠结构，所述堆叠结构包括交替层叠的栅极层和介电层；或者，所述堆叠结构包括交替层叠的伪栅极层和所述介电层，其中，所述栅极层可替代所述伪栅极层；
    在所述堆叠结构的栅线隙区中形成凹槽，其中，所述凹槽贯穿多层所述栅极层和所述介电层；或者，所述凹槽贯穿多层所述伪栅极层和所述介电层；
    在所述堆叠结构表面及所述凹槽中形成绝缘层，其中，所述凹槽上方的绝缘层相对远离所述衬底的表面具有凹陷；以及
    对所述绝缘层进行研磨以磨平所述凹陷。
  2. 如权利要求1所述的方法，其中，所述绝缘层包括第一绝缘层和第二绝缘层；
    所述在所述堆叠结构表面及所述凹槽中形成绝缘层，其中，所述凹槽上方的绝缘层相对远离所述衬底的表面具有凹陷，包括：
    在所述堆叠结构表面及所述凹槽中依次形成所述第一绝缘层和所述第二绝缘层；
    对所述绝缘层进行研磨以磨平所述凹陷，包括：
    对所述第二绝缘层进行研磨以磨平所述凹陷。
  3. 如权利要求1所述的方法，其中，对所述绝缘层进行研磨以磨平所述凹陷后还包括：
    在所述栅线隙区形成栅线隙，所述栅线隙被所述凹槽隔断；
    在所述栅线隙中填充导电材料以形成阵列共源极。
  4. 如权利要求3所述的方法，其中，在所述栅线隙中填充导电材料 以形成阵列共源极后还包括：
    形成跨越所述凹槽中的绝缘层的连接桥，所述连接桥连通被所述绝缘层隔开的阵列共源极。
  5. 如权利要求1所述的方法，其中，所述堆叠结构表面的绝缘层的厚度为150-250nm。
  6. 如权利要求1所述的方法，其中，对所述绝缘层进行研磨以磨平所述凹陷的步骤，包括通过控制所述研磨的时间来控制研磨厚度。
  7. 如权利要求1所述的方法，其中，所述凹槽位于所述堆叠结构的核心区。
  8. 如权利要求1所述的方法，其中，还包括在所述堆叠结构中形成顶部选择栅切线，且在所述顶部选择栅切线中填充绝缘层，其中所述顶部选择栅切线和所述凹槽在同一刻蚀工艺中形成，且所述顶部选择栅切线中的绝缘层和所述凹槽中的绝缘层在同一填充工艺中形成。
  9. 如权利要求1所述的方法，其中，还包括在所述堆叠结构的核心区中形成沟道结构阵列，所述沟道结构阵列被所述栅线隙区分隔为多个区域。
  10. 如权利要求9所述的方法，其中，还包括形成位于所述沟道结构阵列的各个沟道结构顶部的导电插塞。
  11. 如权利要求1所述的方法，其中，所述堆叠结构包括一个堆栈或多个堆叠的堆栈。
  12. 一种三维存储器，包括：
    衬底；
    位于所述衬底上的堆叠结构，所述堆叠结构包括交替层叠的栅极层和介电层；
    贯穿堆叠结构到达所述衬底的栅线隙，所述栅线隙被隔断结构隔断； 以及
    绝缘层，设于所述隔断结构上部，其中，所述绝缘层相对远离所述衬底的表面是平坦的。
  13. 如权利要求12所述的三维存储器，其中，所述绝缘层包括位于所述隔断结构上的第一绝缘层，以及位于所述第一绝缘层上的第二绝缘层，其中，所述第二绝缘层的相对远离所述第一绝缘层的表面是平坦的。
  14. 如权利要求12所述的三维存储器，其中，还包括位于所述栅线隙中的阵列共源极。
  15. 如权利要求14所述的三维存储器，其中，还包括跨越所述绝缘层的连接桥，所述连接桥连通被所述绝缘层隔开的阵列共源极。
  16. 如权利要求12所述的三维存储器，其中，所述多个绝缘层位于所述堆叠结构的核心区。
  17. 如权利要求12所述的三维存储器，其中，还包括：
    顶部选择栅切线，贯穿所述堆叠结构中的多层栅极层和介电层；
    填充于所述顶部选择栅切线中的绝缘层，其中所述顶部选择栅切线中的绝缘层和所述隔断结构上部的绝缘层在同一填充工艺中形成。
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