WO2022147986A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2022147986A1
WO2022147986A1 PCT/CN2021/104190 CN2021104190W WO2022147986A1 WO 2022147986 A1 WO2022147986 A1 WO 2022147986A1 CN 2021104190 W CN2021104190 W CN 2021104190W WO 2022147986 A1 WO2022147986 A1 WO 2022147986A1
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Prior art keywords
trench structure
layer
trench
dielectric layer
material layer
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PCT/CN2021/104190
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English (en)
French (fr)
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尤康
白杰
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长鑫存储技术有限公司
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Priority to US17/449,687 priority Critical patent/US11881428B2/en
Publication of WO2022147986A1 publication Critical patent/WO2022147986A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • Shallow Trench Isolation (STI) structure has many advantages such as good isolation effect and simple process, especially suitable for the sub-micron integrated circuit process, and is widely used in the production of insulating structures between active regions.
  • conventional STI structures generally include an oxide layer for insulating protection, resulting in wet etching processes or other etching processes used during the fabrication of the STI structure or during the fabrication of other semiconductor structures using the STI structure.
  • the process allows excessive etching of the oxide layer in the STI structure, causing defects and affecting the performance and yield of fabricated semiconductor devices.
  • a method of fabricating a semiconductor structure and a semiconductor structure are provided.
  • a method of fabricating a semiconductor structure comprising:
  • a protective layer is formed in the trench structure, and the protective layer at least covers the surface of the first dielectric layer and a part of the sidewall of the trench structure.
  • a trench structure is first formed in the substrate, then a first dielectric layer is formed in the trench structure, and the top surface of the first dielectric layer is set lower than the the top surface of the trench structure to form a protective layer covering at least the surface of the first dielectric layer and part of the sidewall of the trench structure in the trench structure, so that the protective layer covers and protects all
  • the top sidewall of the trench structure is described to avoid excessive etching of the oxide layer in the STI structure by the wet etching process or other etching process during the manufacturing process of the STI structure or the process of manufacturing other semiconductor structures using the STI structure. corrosion, thereby effectively improving the performance and yield of fabricated semiconductor devices.
  • a semiconductor structure includes a substrate, a trench structure, a first dielectric layer and a protective layer, the trench structure is located in the substrate; the first dielectric layer covers the bottom and part of the side of the trench structure wall, and the top surface of the first dielectric layer is lower than the top surface of the trench structure; the protective layer is located in the trench structure and covers at least the surface of the first dielectric layer and the trench Part of the sidewall of the slot structure.
  • the top surface of the first dielectric layer in the trench structure in the substrate is set lower than the top surface of the trench structure, so as to form at least a cover in the trench structure.
  • a protective layer on the surface of the first dielectric layer and part of the sidewalls of the trench structure so that the protective layer covers and protects the top sidewalls of the trench structure, and avoids being used in the manufacturing process or use of the STI structure.
  • the wet etching process or other etching process used to etch the oxide layer in the STI structure excessively, thereby effectively improving the performance and yield of the fabricated semiconductor device.
  • FIG. 1 shows a flowchart of a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIGS. 2a to 2b are schematic cross-sectional structural diagrams of the structure obtained in step S2 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIGS. 2 c to 2 d are schematic cross-sectional structural diagrams of the structure obtained in step S4 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • 2e to 2h are schematic cross-sectional structural diagrams of the structure obtained in step S6 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIGS. 3 a to 3 b are schematic cross-sectional structural diagrams of the structure obtained in step S2 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIGS. 3 c to 3 d are schematic cross-sectional structural diagrams of the structure obtained in step S4 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • 3e to 3g are schematic cross-sectional structural diagrams of the structure obtained in step S6 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing, the regions shown in the figures are schematic in nature and their shapes are not intended to The actual shapes of the regions of the device are shown and are not intended to limit the scope of this application.
  • a method for manufacturing a semiconductor structure provided in an embodiment of the present application includes the following steps:
  • Step S2 providing a substrate, and forming a trench structure in the substrate;
  • Step S4 forming a first dielectric layer in the trench structure, and the top surface of the first dielectric layer is lower than the top surface of the trench structure;
  • Step S6 forming a protective layer in the trench structure, the protective layer covering at least the surface of the first dielectric layer and a part of the sidewall of the trench structure.
  • a trench structure is first formed in a substrate, then a first dielectric layer is formed in the trench structure, and a top surface of the first dielectric layer is disposed lower than the top surface of the trench structure, so that a protective layer covering at least the surface of the first dielectric layer and part of the sidewall of the trench structure is formed in the trench structure, so that the protective layer covers And protect the top sidewall of the trench structure, to avoid the wet etching process or other etching process used in the manufacturing process of the STI structure or the process of using the STI structure to manufacture other semiconductor structures to the oxide in the STI structure.
  • the layer is over-etched, thereby effectively improving the performance and yield of the fabricated semiconductor device.
  • step S2 referring to step S2 in FIG. 1 , FIG. 2 a and FIG. 2 b , a substrate 100 is provided, and the trench structure 12 is formed in the substrate 100 .
  • the substrate 100 may include, but is not limited to, a silicon substrate, a silicon germanium substrate, a silicon-on-insulator (SOI) substrate, and the like.
  • the material of the substrate is silicon, germanium or silicon germanium.
  • Those skilled in the art can select the type of the substrate according to the type of transistors formed on the substrate. Therefore, the type of the substrate should not limit the protection scope of the present application.
  • forming the trench structure 12 in the substrate 100 may include the following steps:
  • Step S21 forming a first patterned mask layer (not shown) on the upper surface of the substrate 100 , a first opening (not shown) is formed in the patterned mask layer, and the first opening defines a The location and shape of the trench structure 12 .
  • Step S22 Etch the upper surface of the substrate 100 by using a dry etching process or a wet etching process based on the first patterned mask layer to obtain the trench structure 12 .
  • the etching process may include a plasma dry etching process.
  • the parameters of the dry etching process used include: a gas including fluorocarbon gas, one or more of HBr and Cl 2 , and a carrier gas, the fluorocarbon gas including CF 4 , CHF 3 , CH 2 F 2 or CH 3 F, the carrier gas is an inert gas, such as He, the gas flow is 50 sccm-400 sccm, and the pressure is 3 mtorr-8 mtorr.
  • the number of trench structures 12 in step S22 may be multiple, and the depth of each trench structure 12 may be the same or different; the width of each trench structure 12 may be the same or different; the trench structures 12 The depth is smaller than the thickness of the substrate 100 .
  • forming the first patterned mask layer on the upper surface of the substrate 100 in step S21 may include the following steps:
  • Step S211 forming a first mask layer (not shown) on the upper surface of the substrate 100 ;
  • Step S212 Coating a first photoresist layer (not shown) on the upper surface of the first mask layer (not shown), and performing patterning treatment to form a first patterned photoresist layer (not shown) not shown);
  • Step S213 etching the first mask layer based on the first patterned photoresist layer to form the first patterned mask layer (not shown), the first patterned mask layer A first opening pattern (not shown) is formed in the (not shown), and the first opening pattern defines the position and shape of the trench structure 12;
  • Step S214 removing the first patterned photoresist layer.
  • the first patterned mask layer formed may include a hard mask layer, and the hard mask layer may be a single-layer structure or a multi-layer stack structure, and its material may be silicon oxide;
  • the film layer is coated with photoresist, and after a series of steps such as exposure and development, a patterned photoresist layer is formed.
  • the patterned photoresist layer defines the position and shape of the trench structure 12, and then based on the patterned photoresist layer
  • the hard mask layer is etched from the photoresist layer to form a patterned mask layer, and then the patterned photoresist layer is removed.
  • the patterned photoresist layer may also be retained in the process of forming the first patterned mask layer, and after the substrate 100 is etched, the patterned photoresist layer is removed. resist layer.
  • step S4 referring to step S4 in FIG. 1, FIG. 2c and FIG. 2d, forming the first dielectric layer 13 in the trench structure 12 may include the following steps:
  • Step S42 forming a first dielectric material layer 131 , and the first dielectric material layer 131 covers the sidewall and bottom of the trench structure 12 and the upper surface of the substrate 100 ;
  • Step S44 removing the first dielectric material layer 131 on the upper surface of the substrate 100 and part of the first dielectric material layer 131 in the trench structure 12 , and the remaining first dielectric material layer 131 constitutes the first dielectric layer 13 .
  • the first dielectric layer 13 may include, but is not limited to, a silicon oxide layer.
  • a thermal oxidation process may be used to form the first dielectric layer 13 on the bottom and part of the sidewalls of the trench structure 12 .
  • the damage to the surface of the substrate 100 during the previous etching process can be repaired.
  • the first dielectric layer 13 can also protect the surface of the substrate 100 in subsequent processes.
  • the thickness of the first dielectric layer 13 formed by the thermal oxidation process may be 4.5 nm-5.5 nm. In an embodiment of the present application, the thickness of the first dielectric layer 13 formed by the thermal oxidation process may be 4.5 nm, 5 nm or 5.5 nm.
  • an etching process may be used to remove the first dielectric material layer 131 on the upper surface of the substrate 100 and a part of the first dielectric material layer in the trench structure 12 131 , the first dielectric material layer 131 remaining in the trench structure 12 constitutes the first dielectric layer 13 .
  • the height of the top of the first dielectric layer 13 lower than the top of the trench structure 12 may be 1 nm-50 nm.
  • the height of the top of the first dielectric layer 13 lower than the top of the trench structure 12 may be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.
  • a protective layer 14 is formed in the trench structure 12 , and the protective layer 14 covers at least the surface of the first dielectric layer 13 and part of the trench structure 12 side wall.
  • forming the protective layer 14 in the trench structure 12 in step S6 may include the following steps:
  • Step S62 forming a protective material layer 141 , and the protective material layer 141 covers the sidewall and bottom of the trench structure 12 and the upper surface of the substrate 100 ;
  • Step S64 removing the protective material layer 141 on the surface of the substrate 100 , and the remaining protective material layer 141 constitutes the protective layer 14 .
  • the formation process of the protective layer 14 may be a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, One or more of ALD), high density plasma deposition (High Density Plasma, HDP) process, plasma enhanced deposition process.
  • CVD chemical Vapor Deposition
  • ALD atomic layer deposition
  • HDP high density plasma deposition
  • plasma enhanced deposition process plasma enhanced deposition process.
  • an atomic layer deposition process is preferably used to form the protective layer 14 on the surface of the first dielectric layer 13 .
  • the protective layer 14 includes, but is not limited to, a silicon nitride layer.
  • the thickness of the protective layer 14 formed by the deposition process in step S6 may be 9.5nm-10.5nm, for example, the thickness of the protective layer 14 may be 9.5nm, 10.0nm or 10.5nm.
  • step S62 after forming the protective material layer 141 in step S62, the following steps are further included:
  • Step S631 forming a second dielectric material layer 151 , the second dielectric material layer 151 fills the trench structure 12 and covers the surface of the protective material layer 141 ;
  • Step S632 remove the protective material layer 141 and the second dielectric material layer 151 on the surface of the substrate 100 and the protective material layer 141 and the second dielectric material layer 151 on the trench structure 12 and keep them in the trench structure 12
  • the protective material layer 141 formed of the protective layer 14 constitutes the protective layer 14
  • the second dielectric material layer 151 remaining in the trench structure 12 constitutes the second dielectric layer 15 .
  • a low pressure chemical vapor deposition (LPCVD) process may be used to deposit a second dielectric material layer 151 in the trench structure 12, and the second dielectric material layer 151 fills the trench structure 12 and covers The surface of the protective material layer 141 is protected.
  • LPCVD low pressure chemical vapor deposition
  • a chemical mechanical polishing process may be used in step S632 to planarize the upper surface of the substrate 100 to optimize the performance and reliability of the device.
  • the upper surface of the substrate 100 can be set as a stop layer to perform a chemical mechanical polishing process, so as to remove the protective material layer 141 and the second dielectric material layer 151 located on the surface of the substrate 100 and the trench structure 12, and remain in the trench structure.
  • the protective material layer 141 in 12 constitutes the protective layer 14
  • the second dielectric material layer 151 remaining in the trench structure 12 constitutes the second dielectric layer 15 , so that the upper surface of the substrate 100 is planarized.
  • the first dielectric layer 13 is subjected to steam annealing to relieve stress and densify the first dielectric layer 13 , to repair voids in the trench structure.
  • the substrate 100 provided in step S2 includes an array area 101 and a peripheral area 102 located at the periphery of the array area 101 ; trenches formed in the substrate 100
  • the structure includes a first trench structure 121, a second trench structure 122, a third trench structure 123 and a fourth trench structure 124; the first trench structure 121 and the second trench structure 122 are both located in the array region 101; Both the third trench structure 123 and the fourth trench structure 124 are located in the peripheral region 102 .
  • the width of the first trench structure 121 is smaller than the width of the second trench structure 122 , and the depth of the first trench structure 121 is smaller than that of the second trench
  • the depth of the trench structure 122; the width of the third trench structure 123 is smaller than the width of the fourth trench structure 124, the depth of the third trench structure 123 and the depth of the fourth trench structure 124 and the depth of the second trench structure 122 are the same.
  • the step of forming the first dielectric layer 13 in the trench structure 12 includes:
  • Step S421 forming a first dielectric material layer 131 in the first trench structure 121 , in the second trench structure 122 , in the third trench structure 123 , in the fourth trench structure 124 and on the surface of the substrate 100 .
  • a dielectric material layer 131 fills the first trench structure 121 and covers the sidewalls and bottoms of the second trench structure 122, the third trench structure 123 and the fourth trench structure 124;
  • Step S441 Remove the first dielectric material layer located on the surface of the substrate, and remove part of the first dielectric material layer located in the trench structure to form the first dielectric layer.
  • step S421 at least one of an atomic layer deposition process, an in-situ water vapor growth process, and a rapid thermal oxidation process may be used to form the first trench structure 121, the second trench structure 122, and the third trench
  • a first dielectric material layer 131 is formed in the structure 123 , in the fourth trench structure 124 and on the surface of the substrate 100 .
  • the first dielectric material layer 131 may include, but is not limited to, a silicon oxide layer.
  • an etching process may be used to remove the first dielectric material layer 131 on the upper surface of the substrate 100 , and inside the first trench structure 121 , the second trench structure 122 , and the third trench structure 123 . and a part of the first dielectric material layer 131 in the fourth trench structure 124 , and the remaining first dielectric material layer 131 constitutes the first dielectric layer 13 .
  • the top of the first dielectric layer 13 in the first trench structure 121 is lower than the top of the first trench structure 121 ; the top of the first dielectric layer 13 in the second trench structure 122 is lower than the top of the second trench structure 122 top; the top of the first dielectric layer 13 in the third trench structure 123 is lower than the top of the third trench structure 123; the top of the first dielectric layer 13 in the fourth trench structure 124 is lower than the fourth trench structure 124 top.
  • the height of the top of the first dielectric layer 13 in the first trench structure 121 lower than the top of the first trench structure 121 is 1 nm-50 nm;
  • the height of the top of a dielectric layer 13 lower than the top of the second trench structure 122 is 1 nm-50 nm;
  • the height of the top of the first dielectric layer 13 in the third trench structure 123 is lower than the top of the third trench structure 123 is 1 nm-50 nm;
  • the height of the top of the first dielectric layer 13 in the fourth trench structure 124 lower than the top of the fourth trench structure 124 is 1 nm-50 nm.
  • the height of the top of the first dielectric layer 13 in the first trench structure 121 lower than the top of the first trench structure 121 may be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm .
  • step S6 please refer to step S6 in FIG. 1, FIG. 3e, FIG. 3f and FIG. 3g.
  • forming the protective layer 14 in the trench structure may include the following steps:
  • Step S621 forming a protective material layer 141 in the first trench structure 121 , in the second trench structure 122 , in the third trench structure 123 , in the fourth trench structure 124 and on the surface of the substrate 100 , the protective material layer 141 fills the first trench structure 121 , the second trench structure 122 and the third trench structure 123 , and covers the surface of the first dielectric layer 13 in the fourth trench structure 124 .
  • step S6 please refer to step S6 in FIG. 1, FIG. 3e and FIG. 3f, after forming the protective material layer, it further includes:
  • Step S63 forming a second dielectric material layer 151 on the surface of the protective material layer 141 , the second dielectric material layer 151 covers the surface of the protective material layer 141 and fills the fourth trench structure 124 ;
  • Step S641 remove the protective material layer 141 on the surface of the substrate 100 and the second dielectric material layer 151 on the surface of the substrate 100 , the remaining protective material layer 141 constitutes the protective layer 14 , and the remaining second dielectric material layer 151 The second dielectric layer 15 is formed.
  • an atomic layer deposition process may be used to deposit a protective material layer 141 in the trench structure 12 , and the protective material layer 141 fills the first trench structure 121 and the second trench
  • the structure 122 and the third trench structure 123 cover the surface of the first dielectric layer 13 in the fourth trench structure 124 .
  • a high-density plasma chemical vapor deposition process may be used to form a second dielectric material layer 151 on the surface of the protective material layer 141 , and the second dielectric material layer 151 covers the protective material
  • the surface of the layer 141 is filled and the fourth trench structure 124 is filled; after that, the protective material layer 141 located on the surface of the substrate 100 and the second dielectric material layer 151 located on the surface of the substrate 100 can be removed by a chemical mechanical polishing process.
  • the remaining protective material layer 141 constitutes the protective layer 14
  • the remaining second dielectric material layer 151 constitutes the second dielectric layer 15 .
  • the upper surface of the substrate 100 is planarized by a chemical mechanical polishing process.
  • the present application also provides a semiconductor structure, which can be fabricated by using the manufacturing method described in any of the embodiments of the present application.
  • the semiconductor structure includes a substrate 100, a trench structure 12.
  • the first dielectric layer 13 and the protective layer 14, the trench structure 12 is located in the substrate 100;
  • the first dielectric layer 13 covers the bottom and part of the sidewall of the trench structure 12, and the top surface of the first dielectric layer 13 is lower than
  • the protective layer 14 is located in the trench structure 12 and covers at least the surface of the first dielectric layer 13 and part of the sidewall of the trench structure 12 .
  • the semiconductor structure in the above-mentioned embodiment by setting the top surface of the first dielectric layer 13 in the trench structure 12 to be lower than the top surface of the trench structure 12, in the trench structure 12 A protective layer 14 covering at least the surface of the first dielectric layer 13 and part of the sidewalls of the trench structure 12 is formed inside, so that the protective layer 14 covers and protects the top sidewalls of the trench structure 12 to avoid the manufacturing process of the STI structure or In the process of using the STI structure to manufacture other semiconductor structures, the wet etching process or other etching process used to over-etch the oxide layer in the STI structure, thereby effectively improving the performance and yield of the fabricated semiconductor device.
  • the semiconductor structure further includes a second dielectric layer 15, and the second dielectric layer 15 is filled in the trench structure 12 without gaps.
  • the trench structure 12 is filled with the second dielectric layer 15, so as to facilitate subsequent operations on the upper surface of the substrate 100. Flattening.
  • the substrate 100 includes an array region 101 and a peripheral region 102 located at the periphery of the array region 101;
  • the trench structure 12 includes a first trench structure 121, The second trench structure 122, the third trench structure 123 and the fourth trench structure 124; the first trench structure 121 and the second trench structure 122 are both located in the array region 101; the third trench structure 123 and the fourth trench structure 122
  • the trench structures 124 are all located in the peripheral region 102 .
  • the width of the first trench structure 121 is smaller than the width of the second trench structure 122, and the depth of the first trench structure 121 is smaller than that of the second trench
  • the depth of the structure 122; the width of the third trench structure 123 is smaller than the width of the fourth trench structure 124, the depth of the third trench structure 123 and the depth of the fourth trench structure 124 are equal to the depth of the second trench structure 122 same.
  • the first dielectric layer 13 fills the first trench structure 121 without gaps, and covers the second trench structure 122, the third trench structure 123 and the third trench structure 121.
  • the height of the top of the first dielectric layer 13 in the first trench structure 121 lower than the top of the first trench structure 121 is 1 nm-50 nm;
  • the height of the top of a dielectric layer 13 lower than the top of the second trench structure 122 is 1 nm-50 nm;
  • the height of the top of the first dielectric layer 13 in the third trench structure 123 is lower than the top of the third trench structure 123
  • the height of the top of the first dielectric layer 13 in the fourth trench structure 124 lower than the top of the fourth trench structure 124 is 1 nm-50 nm.
  • the height of the top of the first dielectric layer 13 in the first trench structure 121 lower than the top of the first trench structure 121 may be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm .
  • the protective layer 14 fills the first trench structure 121, the second trench structure 122 and the third trench structure 123, and covers the fourth trench The surface of the first dielectric layer 13 and a part of the sidewall of the fourth trench structure 124 in the structure 124 .
  • the first dielectric layer 13 is formed in the second trench structure 122 , the third trench structure 123 and the fourth trench structure 124 .
  • the first dielectric layer 13 may include, but is not limited to, a silicon oxide layer.
  • an atomic layer deposition process may be used to form the protective layer 14 on the surface of the first dielectric layer 13 .
  • the protective layer 14 includes, but is not limited to, a silicon nitride layer.
  • a deposition process may be used to form a second dielectric material layer 151 on the surface of the protective material layer 141.
  • the second dielectric material layer 151 covers the surface of the protective material layer 141 and fills the fourth trench structure 124 .
  • the second dielectric material layer 151 may be formed on the surface of the protective material layer 141 by using a low pressure chemical vapor deposition process. The formed second dielectric material layer 151 covers the surface of the protective material layer 141 and fills the fourth trench structure 124 .
  • the second dielectric material layer 151 includes, but is not limited to, a silicon oxide layer.
  • a chemical mechanical polishing process may be used to planarize the surface of the substrate 100 to remove the first trench structures 121 located on the surface of the substrate 100
  • the protective material layer 141 and the second dielectric material layer 151 on the top, the second trench structure 122 , the third trench structure 123 and the fourth trench structure 124 remain in the first trench structure 121 and the second
  • the protective material layers 141 in the trench structure 122 , the third trench structure 123 and the fourth trench structure 124 constitute the protective layer 14
  • the second dielectric material layer 151 remaining in the fourth trench structure 124 constitutes the second
  • the dielectric layer 15 flattens the upper surface of the substrate 100 .
  • the top surface of the first dielectric layer in the trench structure in the substrate is set lower than the top surface of the trench structure, so that the trench structure can be formed in the trench structure.
  • a protective layer covering at least the surface of the first dielectric layer and part of the sidewall of the trench structure is formed inside, so that the protective layer covers and protects the top sidewall of the trench structure, avoiding the fabrication of the STI structure During the process or in the process of using the STI structure to manufacture other semiconductor structures, the wet etching process or other etching process used to over-etch the oxide layer in the STI structure, thereby effectively improving the performance and quality of the semiconductor device. Rate.
  • steps described are not strictly limited to the order in which they are performed, and that the steps may be performed in other orders, unless explicitly stated herein. Moreover, at least a part of the described steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The order of execution is also not necessarily sequential, but may be performed alternately or alternately with other steps or sub-steps of other steps or at least a portion of a phase.

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Abstract

本申请涉及一种半导体结构及其制造方法。所述方法包括：提供衬底，于所述衬底内形成沟槽结构；于所述沟槽结构内形成第一介质层，所述第一介质层的顶面低于所述沟槽结构的顶面；于所述沟槽结构内形成保护层，所述保护层至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁。

Description

半导体结构及其制造方法
相关申请的交叉引用
本申请要求于2021年01月05日提交中国专利局、申请号为2021100079441、申请名称为“半导体结构的制备方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，特别是涉及一种半导体结构及其制造方法。
背景技术
随着集成电路制程的快速发展，对半导体产品的集成度的要求越来越高。而随着半导体产品的集成化，半导体器件的尺寸及半导体器件的隔离结构的尺寸也随之减小，导致在半导体制程中，半导体器件隔离结构的工艺复杂度不断增加。
浅沟槽隔离(Shallow Trench Isolation，STI)结构具备隔离效果好、制程简单等诸多优点，特别适用于次微米以下的集成电路制程，被广泛应用于制作主动区域之间的绝缘结构。
然而，传统的STI结构中一般包括氧化物层以起到绝缘保护的作用，导致在STI结构的制造过程中或使用STI结构制造其他半导体结构的过程中，采用的湿法刻蚀工艺或者其他腐蚀工艺容对STI结构中的氧化物层过度刻蚀，造成缺陷，影响制成半导体器件的性能及良品率。
发明内容
根据一些实施例，提供一种半导体结构的制造方法及半导体结构。
一种半导体结构制造方法，包括：
提供衬底，于所述衬底内形成沟槽结构；
于所述沟槽结构内形成第一介质层，所述第一介质层的顶面低于所述沟槽结构的顶面；及
于所述沟槽结构内形成保护层，所述保护层至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁。
于上述实施例中的半导体结构制造方法中，首先于衬底内形成沟槽结构，然后于所述沟槽结构内形成第一介质层，并设置所述第一介质层的顶面低于所述沟槽结构的顶面，以在所述沟槽结构内形成至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁的保护层，使得所述保护层覆盖并保护所述沟槽结构的顶部侧壁，避免在STI结构的制造过程中或使用STI结构制造其他半导体结构的过程中，采用的湿法刻蚀工艺或者其他腐蚀工艺对STI结构中的氧化物层过度刻蚀，从而有效地提高了制成半导体器件的性能及良品率。
一种半导体结构，包括衬底、沟槽结构、第一介质层及保护层，所述沟槽结构位于所述衬底内；所述第一介质层覆盖所述沟槽结构的底部及部分侧壁，且所述第一介质层的顶面低于所述沟槽结构的顶面；所述保护层位于所述沟槽结构内，且至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁。
于上述实施例中的半导体结构中，通过设置位于衬底内沟槽结构内的第一介质层的顶面低于所述沟槽结构的顶面，以在所述沟槽结构内形成至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁的保护层，使得所述保护层覆盖并保护所述沟槽结构的顶部侧壁，避免在STI结构的制造过程中或使用STI结构制造其他半导体结构的过程中，采用的湿法刻蚀工艺或者其他腐蚀工艺对STI结构中的氧化物层过度刻蚀，从而有效地提高了制成半导体器件的性能及良品率。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1显示为本申请实施例中提供的一种半导体结构制造方法的流程图。
图2a至图2b显示为本申请实施例中提供的一种半导体结构制造方法中步骤S2所得结构的截面结构示意图。
图2c至图2d显示为本申请实施例中提供的一种半导体结构制造方法中步骤S4所得结构的截面结构示意图。
图2e至图2h显示为本申请实施例中提供的一种半导体结构制造方法中步骤S6所得结构的截面结构示意图。
图3a至图3b显示为本申请实施例中提供的一种半导体结构制造方法中步骤S2所得结构的截面结构示意图。
图3c至图3d显示为本申请实施例中提供的一种半导体结构制造方法中步骤S4所得结构的截面结构示意图。
图3e至图3g显示为本申请实施例中提供的一种半导体结构制造方法中步骤S6所得结构的截面结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、 步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
请参阅图1-图3g。需要说明的是，本实施例中所提供的图示仅以示意方式说明本申请的基本构想，虽图示中仅显示与本申请中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1，在本申请的一个实施例中提供的一种半导体结构制造方法中，包括如下步骤：
步骤S2：提供衬底，于所述衬底内形成沟槽结构；
步骤S4：于所述沟槽结构内形成第一介质层，所述第一介质层的顶面低于所述沟槽结构的顶面；
步骤S6：于所述沟槽结构内形成保护层，所述保护层至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁。
具体地，于上述实施例中的半导体结构制造方法中，首先于衬底内形成沟槽结构，然后于所述沟槽结构内形成第一介质层，并设置所述第一介质层的顶面低于所述沟槽结构的顶面，以在所述沟槽结构内形成至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁的保护层，使得所述保护层覆盖并保护所述沟槽结构的顶部侧壁，避免在STI结构的制造过程中或使用STI结构制造其他半导体结构的过程中，采用的湿法刻蚀工艺或者其他腐蚀工艺对STI结构中的氧化物层过度刻蚀，从而有效地提高了制成半导体器件的性能及良品率。
在步骤S2中，请参阅图1中的S2步骤、图2a及图2b，提供衬底100，于衬底100内形成沟槽结构12。
作为示例，衬底100可以包括但不仅限于硅衬底、硅锗衬底及绝缘体上硅(SOI)衬底等。所述衬底的材料为硅、锗或硅锗，本领域的技术人员可以根据衬底上形成的晶体管类型选择衬底类型，因此衬底的类型不应限制本申请的保护范围。
作为示例，请继续参阅图1中的S2步骤、图2a及图2b，于衬底100内形成沟槽结构12可以包括如下步骤：
步骤S21：于衬底100的上表面形成第一图形化掩膜层(未图示)，所述图形化掩膜层内形成有第一开口(未示出)，所述第一开口定义出沟槽结构12的位置及形状。
步骤S22：基于所述第一图形化掩膜层采用干法刻蚀工艺或湿法刻蚀工艺对衬底100的上表面进行刻蚀，以得到沟槽结构12。
在本实施例中，刻蚀工艺可以包括等离子体干法刻蚀工艺。采用的干法刻蚀工艺的参数包括：气体包括碳氟气体、HBr和Cl 2中的一种或多种、以及载气，所述碳氟气体包括CF 4、CHF 3、CH 2F 2或CH 3F，所述载气为惰性气体，例如He，气体流量为50sccm-400sccm，压力为3毫托-8毫托。作为示例，步骤S22中的沟槽结构12的数量可以为多个，各沟槽结构12的深度可以相同，也可以不同；各沟槽结构12的宽度可以相同，也可以不同；沟槽结构12的深度小于衬底100的厚度。
作为示例，步骤S21中于衬底100的上表面形成第一图形化掩膜层可以包括如下步骤：
步骤S211：于衬底100的上表面形成第一掩膜层(未图示)；
步骤S212：于所述第一掩膜层(未图示)的上表面涂覆第一光刻胶层(未图示)，并进行图形化处理，以形成第一图形化光刻胶层(未图示)；
步骤S213：基于所述第一图形化光刻胶层刻蚀所述第一掩膜层，以形成所述第一图形化掩膜层(未图示)，所述第一图形化掩膜层(未图示)内形成有第一开口图形(未图示)，所述第一开口图形定义出沟槽结构12的位置及形状；
步骤S214：去除所述第一图形化光刻胶层。
作为示例，形成的第一图形化掩膜层可以包括硬掩膜层，硬掩膜层可以是单层结构，也可以是多层堆叠结构，其材质可以是氧化硅；之后在所述硬掩膜层上涂覆光刻胶，并经曝光、显影等一系列步骤，形成图形化的光刻胶层，图形化的光刻胶层定义出沟槽结构12的位置及形状，再基于图形化的光刻胶层刻蚀硬掩膜层以形成图形化掩膜层，然后去除图形化的光刻胶层。当然，在本申请的其他实施例中，也可以在形成第一图形化掩膜层的过程中保留图形化的光刻胶层，在刻蚀衬底100后，再去除所述图形化的光刻胶层。
在步骤S4中，请参阅图1中的S4步骤、图2c及图2d，于沟槽结构12内形成第一介质层13，可以包括如下步骤：
步骤S42：形成第一介质材料层131，第一介质材料层131覆盖沟槽结构12的侧壁、底部及衬底100的上表面；
步骤S44：去除衬底100的上表面的第一介质材料层131及沟槽结构12内的部分第一介质材料层131，剩余的第一介质材料层131构成第一介质层13。
作为示例，可以采用原子层沉积工艺、原位水汽生长工艺及快速热氧化工艺中的至少一种于沟槽结构12内形成第一介质层13。第一介质层13可以包括但不仅限于氧化硅层。
作为示例，可以采用热氧化工艺于沟槽结构12的底部及部分侧壁形成第一介质层13。热氧化形成第一介质层13的过程中能够修复衬底100表面在前序刻蚀工艺过程中受到的损伤。而且，第一介质层13还能够在后续制程中保护衬底100的表面。
作为示例，请继续参考图2c，采用热氧化工艺形成第一介质层13的厚度可以为4.5nm-5.5nm。在本申请的一个实施例中，采用热氧化工艺形成的第一介质层13的厚度可以为4.5nm、5nm或5.5nm。
作为示例，请继续参考图2d，在本申请的一个实施例中，可以采用刻蚀工艺去除衬底100的上表面的第一介质材料层131及沟槽结构12内的部分第一介质材料层131，保留于沟槽结构12内的第一介质材料层131构成第一介质层13。第一介质层13的顶部低于沟槽结构12的顶部的高度可以为1nm-50nm。作为示例，第一介质层13的顶部低于沟槽结构12的顶部的高度可以为1nm、10nm、20nm、30nm、40nm或50nm。
在步骤S6中，请参阅图1中的S6步骤、图2e及图2f，于沟槽结构12内形成保护层14，保护层14至少覆盖第一介质层13的表面及沟槽结构12的部分侧壁。
作为示例，请继续参阅图1中的S6步骤、图2e及图2f，步骤S6中于沟槽结构12内形成保护层14可以包括如下步骤：
步骤S62：形成保护材料层141，保护材料层141覆盖沟槽结构12的侧壁、底部及衬底100的上表面；
步骤S64：去除位于衬底100的表面上的保护材料层141，剩余的保护材料层141构成保护层14。
作为示例，请继续参考图2e及图2f，在本申请的一个实施例中，保护层14的形成工艺可以为化学气相沉积工艺(Chemical Vapor Deposition，CVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)、高密度等离子沉积(High Density Plasma，HDP)工艺、等离子体增强沉积工艺中的一种或多种。本申请中优选采用原子层沉积工艺于第一介质层13的表面形成保护层14。保护层14包括但不仅限于氮化硅层。
作为示例，在本申请的一个实施例中，步骤S6中采用沉积工艺形成保护层14的厚度 可以为9.5nm-10.5nm，例如，保护层14的厚度可以为9.5nm、10.0nm或10.5nm。
作为示例，请参考图2g及图2h，在本申请的一个实施例中，步骤S62中形成保护材料层141之后，还包括如下步骤：
步骤S631：形成第二介质材料层151，第二介质材料层151填满沟槽结构12并覆盖保护材料层141的表面；
步骤S632：去除位于衬底100的表面上的保护材料层141、第二介质材料层151及位于沟槽结构12上的保护材料层141、第二介质材料层151，保留于沟槽结构12内的保护材料层141构成保护层14，保留于沟槽结构12内的第二介质材料层151构成第二介质层15。
作为示例，步骤S631可以采用低压力化学气相沉积工艺(Low Pressure Chemical Vapor Deposition，LPCVD)于沟槽结构12内沉积第二介质材料层151，第二介质材料层151填满沟槽结构12并覆盖保护材料层141的表面。
作为示例，请继续参考图2h，在本申请的一个实施例中，步骤S632中可以采用化学机械研磨工艺使得衬底100的上表面平坦化，以优化器件的工作性能及可靠性。可以设置衬底100的上表面为停止层进行化学机械研磨工艺，以去除位于衬底100表面上及位于沟槽结构12上的保护材料层141及第二介质材料层151，保留于沟槽结构12内的保护材料层141构成保护层14，保留于沟槽结构12内的第二介质材料层151构成第二介质层15，使得衬底100的上表面平坦化。
较佳的，在本申请的一个实施例中，在采用沉积工艺形成保护层14之前，对第一介质层13进行水蒸汽退火，以释放应力，并使第一介质层13致密(densify)化，修复沟槽结构中的空隙。
作为示例，请参阅图1中的S2步骤、图3a及图3b，步骤S2中提供的衬底100包括阵列区101及位于阵列区101外围的外围区102；于衬底100内形成的沟槽结构包括第一沟槽结构121、第二沟槽结构122、第三沟槽结构123及第四沟槽结构124；第一沟槽结构121及第二沟槽结构122均位于阵列区101内；第三沟槽结构123及第四沟槽结构124均位于外围区102内。
作为示例，请继续参阅图1中的S2步骤、图3a及图3b，第一沟槽结构121的宽度小于第二沟槽结构122的宽度，且第一沟槽结构121的深度小于第二沟槽结构122的深度；第三沟槽结构123的宽度小于第四沟槽结构124的宽度，第三沟槽结构123的深度及第四沟槽结构124的深度与第二沟槽结构122的深度均相同。
作为示例，请继续参阅图1中的S4步骤、图3c及图3d，所述于沟槽结构12内形成第一介质层13的步骤包括：
步骤S421：于第一沟槽结构121内、第二沟槽结构122内、第三沟槽结构123内、第四沟槽结构124内及衬底100的表面形成第一介质材料层131，第一介质材料层131填满第一沟槽结构121，并覆盖第二沟槽结构122、第三沟槽结构123及第四沟槽结构124的侧壁及底部；
步骤S441：去除位于所述衬底的表面的所述第一介质材料层，并去除位于所述沟槽结构内的部分所述第一介质材料层，以形成所述第一介质层。
作为示例，步骤S421中可以采用原子层沉积工艺、原位水汽生长工艺及快速热氧化工艺中的至少一种，于第一沟槽结构121内、第二沟槽结构122内、第三沟槽结构123内、第四沟槽结构124内及衬底100的表面形成第一介质材料层131。第一介质材料层131可以包括但不仅限于氧化硅层。
作为示例，步骤S441中可以采用刻蚀工艺去除衬底100的上表面的第一介质材料层131，及第一沟槽结构121内、第二沟槽结构122内、第三沟槽结构123内、第四沟槽结构124内的部分第一介质材料层131，剩余的第一介质材料层131构成第一介质层13。第 一沟槽结构121内的第一介质层13的顶部低于第一沟槽结构121的顶部；第二沟槽结构122内的第一介质层13的顶部低于第二沟槽结构122的顶部；第三沟槽结构123内的第一介质层13的顶部低于第三沟槽结构123的顶部；第四沟槽结构124内的第一介质层13的顶部低于第四沟槽结构124的顶部。
作为示例，请继续参考图3d，第一沟槽结构121内的第一介质层13的顶部低于第一沟槽结构121的顶部的高度为1nm-50nm；第二沟槽结构122内的第一介质层13的顶部低于第二沟槽结构122的顶部的高度为1nm-50nm；第三沟槽结构123内的第一介质层13的顶部低于第三沟槽结构123的顶部的高度为1nm-50nm；第四沟槽结构124内的第一介质层13的顶部低于第四沟槽结构124的顶部的高度为1nm-50nm。以第一沟槽结构121为例，第一沟槽结构121内的第一介质层13的顶部低于第一沟槽结构121的顶部的高度可以为1nm、10nm、20nm、30nm、40nm或50nm。
在步骤S6中，请参阅图1中的S6步骤、图3e、图3f及图3g，步骤S6中于沟槽结构内形成保护层14可以包括如下步骤：
步骤S621：于第一沟槽结构121内、第二沟槽结构122内、第三沟槽结构123内、第四沟槽结构124内及衬底100的表面形成保护材料层141，保护材料层141填满第一沟槽结构121、第二沟槽结构122及第三沟槽结构123，并覆盖位于第四沟槽结构124内的第一介质层13的表面。
在步骤S6中，请参阅图1中的S6步骤、图3e及图3f，形成所述保护材料层后，还包括：
步骤S63：于保护材料层141的表面形成第二介质材料层151，第二介质材料层151覆盖保护材料层141的表面，并填满第四沟槽结构124；
步骤S641：去除位于衬底100的表面的保护材料层141及位于衬底100的表面上的第二介质材料层151，剩余的保护材料层141构成保护层14，剩余的第二介质材料层151构成第二介质层15。
作为示例，请继续参考图3e、图3f和图3g，可以采用原子层沉积工艺于沟槽结构12内沉积保护材料层141，保护材料层141填满第一沟槽结构121、第二沟槽结构122及第三沟槽结构123，并覆盖位于第四沟槽结构124内的第一介质层13的表面。
作为示例，请继续参考图3e、图3f和图3g，可以采用高密度等离子体化学气相淀积工艺于保护材料层141的表面形成第二介质材料层151，第二介质材料层151覆盖保护材料层141的表面，并填满第四沟槽结构124；之后，可以采用化学机械研磨工艺去除位于衬底100的表面的保护材料层141及位于衬底100的表面上的第二介质材料层151，剩余的保护材料层141构成保护层14，剩余的第二介质材料层151构成第二介质层15。通过化学机械研磨工艺使得衬底100的上表面平坦化。
在一些实施例中，本申请还提供了一种半导体结构，可以采用如任一本申请实施例中所述的制造方法制成，参考图2f,所述半导体结构包括衬底100、沟槽结构12、第一介质层13及保护层14，沟槽结构12位于衬底100内；第一介质层13覆盖沟槽结构12的底部及部分侧壁，且第一介质层13的顶面低于沟槽结构12的顶面；保护层14位于沟槽结构12内，且至少覆盖第一介质层13的表面及沟槽结构12的部分侧壁。
具体地，请继续参考图2f，于上述实施例中的半导体结构中，通过设置沟槽结构12内第一介质层13的顶面低于沟槽结构12的顶面，以在沟槽结构12内形成至少覆盖第一介质层13的表面及沟槽结构12的部分侧壁的保护层14，使得保护层14覆盖并保护沟槽结构12的顶部侧壁，避免在STI结构的制造过程中或使用STI结构制造其他半导体结构的过程中，采用的湿法刻蚀工艺或者其他腐蚀工艺对STI结构中的氧化物层过度刻蚀，从而有效地提高了制成半导体器件的性能及良品率。
作为示例，请参考图2g，在本申请的一个实施例中,所述半导体结构还包括第二介质 层15，第二介质层15无间隙填充于沟槽结构12内。以在沟槽的宽度较小且第一介质层13没有无间隙填充沟槽结构12的情况下，利用第二介质层15填满沟槽结构12，以便于后续对衬底100的上表面进行平坦化处理。
作为示例，请参考图3a和图3g，在本申请的一个实施例中，衬底100包括阵列区101及位于阵列区101外围的外围区102；沟槽结构12包括第一沟槽结构121、第二沟槽结构122、第三沟槽结构123及第四沟槽结构124；第一沟槽结构121及第二沟槽结构122均位于阵列区101内；第三沟槽结构123及第四沟槽结构124均位于外围区102内。
作为示例，请继续参考图3g，在本申请的一个实施例中，第一沟槽结构121的宽度小于第二沟槽结构122的宽度，且第一沟槽结构121的深度小于第二沟槽结构122的深度；第三沟槽结构123的宽度小于第四沟槽结构124的宽度，第三沟槽结构123的深度及第四沟槽结构124的深度与第二沟槽结构122的深度均相同。
作为示例，请继续参考图3g，在本申请的一个实施例中，第一介质层13无间隙填充第一沟槽结构121，并覆盖第二沟槽结构122、第三沟槽结构123及第四沟槽结构124的底部及部分侧壁；第一沟槽结构121内的第一介质层13的顶部低于第一沟槽结构121的顶部；第二沟槽结构122内的第一介质层13的顶部低于第二沟槽结构122的顶部；第三沟槽结构123内的第一介质层13的顶部低于第三沟槽结构123的顶部；第四沟槽结构124内的第一介质层13的顶部低于第四沟槽结构124的顶部。
作为示例，请继续参考图3g，第一沟槽结构121内的第一介质层13的顶部低于第一沟槽结构121的顶部的高度为1nm-50nm；第二沟槽结构122内的第一介质层13的顶部低于第二沟槽结构122的顶部的高度为1nm-50nm；第三沟槽结构123内的第一介质层13的顶部低于第三沟槽结构123的顶部的高度为1nm-50nm；第四沟槽结构124内的第一介质层13的顶部低于第四沟槽结构124的顶部的高度为1nm-50nm。以第一沟槽结构121为例，第一沟槽结构121内的第一介质层13的顶部低于第一沟槽结构121的顶部的高度可以为1nm、10nm、20nm、30nm、40nm或50nm。
作为示例，请继续参考图3g，在本申请的一个实施例中，保护层14填满第一沟槽结构121、第二沟槽结构122及第三沟槽结构123，并覆盖第四沟槽结构124内第一介质层13的表面及第四沟槽结构124的部分侧壁。
作为示例，请继续参考图3g，在本申请的一个实施例中，可以采用原子层沉积工艺、原位水汽生长工艺及快速热氧化工艺中的至少一种，于第一沟槽结构121内、第二沟槽结构122内、第三沟槽结构123内及第四沟槽结构124内形成第一介质层13。第一介质层13可以包括但不仅限于氧化硅层。
作为示例，请继续参考图3g，在本申请的一个实施例中，可以采用原子层沉积工艺于第一介质层13的表面形成保护层14。保护层14包括但不仅限于氮化硅层。
作为示例，请继续参考图3f，在本申请的一个实施例中，可以在形成保护材料层141之后，采用沉积工艺于保护材料层141的表面形成第二介质材料层151，第二介质材料层151覆盖保护材料层141的表面，并填满第四沟槽结构124。例如，可以在形成保护材料层141之后，采用低压力化学气相沉积工艺于保护材料层141的表面形成第二介质材料层151。形成的第二介质材料层151覆盖保护材料层141的表面，并填满第四沟槽结构124。
作为示例，请继续参考图3f，在本申请的一个实施例中，第二介质材料层151包括但不限于氧化硅层。
作为示例，请继续参考图3g，在形成第二介质材料层151之后，可以采用化学机械研磨工艺对衬底100的表面平坦化处理，以去除位于衬底100表面上、第一沟槽结构121上、第二沟槽结构122上、第三沟槽结构123上及第四沟槽结构124上的保护材料层141及第二介质材料层151，保留于第一沟槽结构121内、第二沟槽结构122内、第三沟槽结构123内及第四沟槽结构124内的保护材料层141构成保护层14，保留于第四沟槽结构 124内的第二介质材料层151构成第二介质层15，使得衬底100的上表面平坦化。
上述实施例中的半导体结构的制造方法及半导体结构，通过设置位于衬底内沟槽结构内的第一介质层的顶面低于所述沟槽结构的顶面，以在所述沟槽结构内形成至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁的保护层，使得所述保护层覆盖并保护所述沟槽结构的顶部侧壁，避免在STI结构的制造过程中或使用STI结构制造其他半导体结构的过程中，采用的湿法刻蚀工艺或者其他腐蚀工艺对STI结构中的氧化物层过度刻蚀，从而有效地提高了制成半导体器件的性能及良品率。
请注意，上述实施例仅出于说明性目的而不意味对本申请的限制。
应该理解的是，除非本文中有明确的说明，所述的步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，所述的步骤的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种半导体结构的制造方法，包括：
    提供衬底，于所述衬底内形成沟槽结构；
    于所述沟槽结构内形成第一介质层，所述第一介质层的顶面低于所述沟槽结构的顶面；及
    于所述沟槽结构内形成保护层，所述保护层至少覆盖所述第一介质层的表面及所述沟槽结构的部分侧壁。
  2. 根据权利要求1所述的方法，其中，所述衬底包括阵列区及位于所述阵列区外围的外围区；
    所述沟槽结构包括第一沟槽结构、第二沟槽结构、第三沟槽结构及第四沟槽结构；
    所述第一沟槽结构及所述第二沟槽结构均位于所述阵列区内；
    所述第三沟槽结构及所述第四沟槽结构均位于所述外围区内。
  3. 根据权利要求2所述的方法，其中，所述第一沟槽结构的宽度小于所述第二沟槽结构的宽度，且所述第一沟槽结构的深度小于所述第二沟槽结构的深度；
    所述第三沟槽结构的宽度小于所述第四沟槽结构的宽度，所述第三沟槽结构的深度及所述第四沟槽结构的深度与所述第二沟槽结构的深度均相同。
  4. 根据权利要求2或3所述的方法，其中，所述于所述沟槽结构内形成第一介质层包括：
    于所述第一沟槽结构内、所述第二沟槽结构内、所述第三沟槽结构内、所述第四沟槽结构内及所述衬底的表面形成第一介质材料层，所述第一介质材料层填满所述第一沟槽结构，并覆盖所述第二沟槽结构、所述第三沟槽结构及所述第四沟槽结构的底部及侧壁；
    去除位于所述衬底的表面的所述第一介质材料层，并去除位于所述沟槽结构内的部分所述第一介质材料层，以形成所述第一介质层。
  5. 根据权利要求4所述的方法，其中，于所述沟槽结构内形成保护层包括：
    于所述第一沟槽结构内、所述第二沟槽结构内、所述第三沟槽结构内、所述第四沟槽结构内及所述衬底的表面形成保护材料层，所述保护材料层填满所述第一沟槽结构、所述第二沟槽结构及所述第三沟槽结构，并覆盖位于所述第四沟槽结构内的所述第一介质层的表面。
  6. 根据权利要求5所述的方法，其中，形成所述保护材料层后，所述方法还包括：
    于所述保护材料层的表面形成第二介质材料层，所述第二介质材料层覆盖所述保护材料层的表面，并填满所述第四沟槽结构；
    去除位于所述衬底的表面上的所述保护材料层及位于所述衬底的表面上的所述第二介质材料层，剩余的所述保护材料层构成所述保护层，剩余的所述第二介质材料层构成第二介质层。
  7. 根据权利要求1-3任一项所述的方法，其中，采用原子层沉积工艺、原位水汽生长工艺及快速热氧化工艺中的至少一种于所述沟槽结构内形成氧化硅层作为所述第一介质层。
  8. 根据权利要求1-3任一项所述的方法，其中，于所述沟槽结构内形成氮化硅层作为所述保护层。
  9. 一种半导体结构，包括：
    衬底；
    沟槽结构，所述沟槽结构位于所述衬底内；
    第一介质层，所述第一介质层覆盖所述沟槽结构的底部及部分侧壁，且所述第一介质层的顶面低于所述沟槽结构的顶面；及
    保护层，所述保护层位于所述沟槽结构内，且至少覆盖所述第一介质层的表面及所述 沟槽结构的部分侧壁。
  10. 根据权利要求9所述的半导体结构，其中，
    所述衬底包括阵列区及位于所述阵列区外围的外围区；
    所述沟槽结构包括第一沟槽结构、第二沟槽结构、第三沟槽结构及第四沟槽结构；
    所述第一沟槽结构及所述第二沟槽结构均位于所述阵列区内；
    所述第三沟槽结构及所述第四沟槽结构均位于所述外围区内。
  11. 根据权利要求10所述的半导体结构，其中，
    所述第一沟槽结构的宽度小于所述第二沟槽结构的宽度，且所述第一沟槽结构的深度小于所述第二沟槽结构的深度；
    所述第三沟槽结构的宽度小于所述第四沟槽结构的宽度，所述第三沟槽结构的深度及所述第四沟槽结构的深度与所述第二沟槽结构的深度均相同。
  12. 根据权利要求10或11所述的半导体结构，其中，
    所述第一介质层无间隙填充于所述第一沟槽结构内，并覆盖所述第二沟槽结构、所述第三沟槽结构及所述第四沟槽结构的底部及部分侧壁；
    所述第一沟槽结构内的所述第一介质层的顶部低于所述第一沟槽结构的顶部；
    所述第二沟槽结构内的所述第一介质层的顶部低于所述第二沟槽结构的顶部；
    所述第三沟槽结构内的所述第一介质层的顶部低于所述第三沟槽结构的顶部；
    所述第四沟槽结构内的所述第一介质层的顶部低于所述第四沟槽结构的顶部。
  13. 根据权利要求12所述的半导体结构，其中，所述保护层填满所述第一沟槽结构、所述第二沟槽结构及所述第三沟槽结构，并覆盖所述第四沟槽结构内的所述第一介质层的表面及所述第四沟槽结构的部分侧壁。
  14. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括第二介质层，所述第二介质层填满所述第四沟槽结构内。
  15. 根据权利要求9-11任一项所述的半导体结构，其中，所述第一介质层包括二氧化硅。
  16. 根据权利要求9-11任一项所述的半导体结构，其中，所述保护层包括氮化硅。
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