WO2022085765A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022085765A1
WO2022085765A1 PCT/JP2021/038941 JP2021038941W WO2022085765A1 WO 2022085765 A1 WO2022085765 A1 WO 2022085765A1 JP 2021038941 W JP2021038941 W JP 2021038941W WO 2022085765 A1 WO2022085765 A1 WO 2022085765A1
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Prior art keywords
vgs
semiconductor device
region
effect transistor
field effect
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PCT/JP2021/038941
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English (en)
French (fr)
Japanese (ja)
Inventor
朋成 太田
晶英 田口
佑介 中山
浩尚 中村
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Application filed by Nuvoton Technology Corp Japan filed Critical Nuvoton Technology Corp Japan
Priority to EP21882905.9A priority Critical patent/EP4187617A4/en
Priority to JP2022543605A priority patent/JP7179236B2/ja
Priority to CN202180050391.6A priority patent/CN115956297B/zh
Publication of WO2022085765A1 publication Critical patent/WO2022085765A1/ja
Priority to US18/175,196 priority patent/US11735655B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/154—Dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • the present disclosure relates to semiconductor devices, and more particularly to chip size package type semiconductor devices.
  • the vertical field effect transistor is required to reduce the on-resistance and improve the resistance to destruction due to thermal runaway when it is on.
  • the structure of the orthogonal type vertical field effect transistor disclosed in Patent Document 1 is more effective in reducing the on-resistance than the parallel type structure, and is advantageous in improving the withstand capacity at the time of on.
  • it is generally difficult to satisfy both the reduction of the on-resistance and the improvement of the withstand voltage at the time of on.
  • An N-channel single-configuration vertical field-effect transistor will be described as an example.
  • a voltage VDS [V] drain-source voltage
  • a threshold value threshold
  • Vth [V] the definition will be described later
  • the total gate width of the conduction channel is Wg [cm]
  • the conduction channel length in the depth direction is Lch [cm]
  • the carrier mobility in the conduction channel is ⁇ [cm 2 / V / sec].
  • the gate oxide film capacity is Cox [F / cm 2 ]
  • IDS-VGS temperature coefficient of VGS dependence of IDS
  • Vth1 straddling VGS
  • Vztc [V] Vztc
  • a technique for expanding the condition that the temperature coefficient of IDS-VGS is negative to a range in which VGS is small is disclosed by creating ⁇ a region that becomes Vztc and a region that becomes Vth2> Vztc).
  • positive feedback does not occur under the condition of driving with VGS larger than Vth2 because the temperature coefficient of IDS-VGS is negative, and the withstand capacity at the time of turning on can be improved.
  • the object of the present disclosure is to provide a semiconductor device that can achieve both reduction of on-resistance and improvement of resistance to fracture due to positive feedback at on-time.
  • the semiconductor device is a chip size package type semiconductor device capable of face-down mounting, which is a semiconductor substrate made of silicon and containing a first conductive type impurity, and the above-mentioned. Formed in contact with the semiconductor substrate and formed on the surface of the low-concentration impurity layer containing the first conductive type impurities having a concentration lower than the concentration of the first conductive type impurities of the semiconductor substrate and the surface of the low-concentration impurity layer. A second conductive type body region different from the first conductive type, a source region of the first conductive type formed on the surface of the body region, and a source electrode electrically connected to the source region.
  • the semiconductor substrate extends from the upper surface of the low-concentration impurity layer to the body region at equal intervals in the second direction orthogonal to the first direction and extends in the first direction parallel to the upper surface of the semiconductor substrate.
  • a plurality of trenches formed to a depth up to a part of the low-concentration impurity layer, a gate insulating film formed so as to cover at least a part of the surface of the trench, and a gate formed on the gate insulating film.
  • a vertical electric field effect transistor including a conductor and a connection portion for electrically connecting the body region and the source electrode is provided, and a part of the semiconductor substrate and the low concentration impurity layer is the vertical electric field effect transistor.
  • the vertical electric field effect transistor functions as a drain region of the above, and the source region and the connection portion are alternately and periodically installed in the first direction in the first direction.
  • the ratio of LS to LB (LS / LB) is 1/7 or more 1 LB ⁇ ⁇ 0.024 ⁇ (VGS) 2 +0 with respect to the voltage VGS [V] which is 3/3 or less and is applied to the gate conductor with reference to the potential of the source electrode and is the value of the specification of the semiconductor device. It is characterized in that .633 ⁇ VGS-0.721 holds.
  • the present disclosure provides a semiconductor device capable of both reducing on-resistance and improving the resistance to fracture due to positive feedback when on.
  • it is possible to achieve both an expansion of the safe operation range at the time of turn-on and a low on-resistance during normal operation in a circuit that requires a soft start.
  • FIG. 1 is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment.
  • FIG. 2A is a schematic plan view showing an example of the structure of the semiconductor device according to the embodiment.
  • FIG. 2B is a schematic cross-sectional view showing the main current flowing through the semiconductor device according to the embodiment.
  • FIG. 3A is a schematic plan view of a substantially unit configuration of the first transistor according to the embodiment.
  • FIG. 3B is a schematic perspective view of a substantially unit configuration of the first transistor according to the embodiment.
  • FIG. 4A is a schematic plan view of a substantially unit configuration of the first transistor according to Comparative Example 1.
  • FIG. 4B is a schematic perspective view of a substantially unit configuration of the first transistor according to Comparative Example 1.
  • FIG. 4A is a schematic plan view of a substantially unit configuration of the first transistor according to Comparative Example 1.
  • FIG. 5 is a graph showing the relationship between the thickness of the semiconductor device and the thermal resistance according to the embodiment.
  • FIG. 6A is a schematic cross-sectional view showing an example of the structure of the first transistor according to the embodiment.
  • FIG. 6B is a schematic plan view showing an example of the structure of the first transistor according to the embodiment.
  • FIG. 6C is a schematic cross-sectional view showing an example of the structure of the first transistor according to the embodiment.
  • FIG. 6D is a schematic plan view showing an example of the structure of the first transistor according to the embodiment.
  • FIG. 6E is a schematic cross-sectional view showing an example of the structure of the first transistor according to the embodiment.
  • FIG. 6F is a schematic plan view showing an example of the structure of the first transistor according to the embodiment.
  • FIG. 7A-1 is a diagram showing a structure used for simulating the current density at the time of driving the first transistor according to the embodiment.
  • FIG. 7A-2 is a diagram showing a result of simulating the current density at the time of driving the first transistor according to the embodiment.
  • FIG. 7A-3 is a superposed view of FIGS. 7A-1 and 7A-2.
  • FIG. 7B-1 is a diagram showing a structure used for simulating the current density at the time of driving the first transistor according to the embodiment.
  • FIG. 7B-2 is a diagram showing a result of simulating the current density at the time of driving the first transistor according to the embodiment.
  • FIG. 7B-3 is a superposed view of FIG. 7B-1 and FIG. 7B-2.
  • FIG. 8 is a diagram showing a graph showing the relationship between the expansion of the conduction region from the source region during driving and the voltage applied to the gate conductor.
  • FIG. 9 is a diagram showing a graph showing the relationship between the length of the source region and the length of the connection portion in the first direction, which is preferable for obtaining the effect of the semiconductor device according to the embodiment.
  • FIG. 10 is a diagram showing an example of the on-resistance shown in the specifications of the first transistor according to the embodiment.
  • FIG. 11 is a diagram showing an example according to an embodiment and a graph showing the VGS dependence of IDS of Comparative Example 1 and Comparative Example 2.
  • a dual configuration will be described as an example of an orthogonal structure of a vertical field effect transistor (more specifically, a vertical MOS transistor), which is an example of a semiconductor device in the present disclosure. It is not essential that the dual configuration is used, and the vertical field-effect transistor having a single configuration may be used, or the vertical field-effect transistor having a triple configuration or more may be used.
  • FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device.
  • FIG. 2A is a plan view thereof. The size and shape of the semiconductor device and the arrangement of the electrode pads shown in these figures are examples.
  • FIG. 2B is a cross-sectional view schematically showing the main current flowing through the semiconductor device. 1 and 2B are cut planes in I-I of FIG. 2A.
  • the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, and a first vertical field effect transistor 10 (hereinafter referred to as a vertical field effect transistor 10) formed in a first region A1 in the semiconductor layer 40. , Also referred to as “transistor 10”) and a second vertical field effect transistor 20 (hereinafter, also referred to as “transistor 20”) formed in the second region A2 in the semiconductor layer 40.
  • a first vertical field effect transistor 10 hereinafter referred to as a vertical field effect transistor 10
  • transistor 20 second vertical field effect transistor 20
  • the first region A1 and the second region A2 are adjacent to each other in the plan view (that is, the top view) of the semiconductor layer 40.
  • the virtual boundary 90C between the first region A1 and the second region A2 is shown by a broken line.
  • the semiconductor layer 40 is configured by laminating a semiconductor substrate 32 and a low-concentration impurity layer 33.
  • the semiconductor substrate 32 is arranged on the back surface side of the semiconductor layer 40 and is made of silicon containing first conductive type impurities.
  • the low-concentration impurity layer 33 is arranged on the surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and has a concentration of first conductive type impurities lower than the concentration of the first conductive type impurities of the semiconductor substrate 32. include.
  • the low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.
  • the low-concentration impurity layer 33 is also a drift layer of the transistor 10 and the transistor 20, and may be referred to as a drift layer in the present specification.
  • the metal layer 30 is formed in contact with the back surface side of the semiconductor layer 40 and is made of silver (Ag) or copper (Cu).
  • the metal layer 30 may contain a trace amount of an element other than the metal mixed as an impurity in the manufacturing process of the metal material. Further, the metal layer 30 may or may not be formed on the entire surface of the back surface side of the semiconductor layer 40.
  • a first body region 18 containing impurities of a second conductive type different from the first conductive type is formed in the first region A1 of the low concentration impurity layer 33.
  • a first source region 14, a first gate conductor 15, and a first gate insulating film 16 containing first conductive type impurities are formed in the first body region 18.
  • the gate insulating film may be referred to as a gate oxide film.
  • the first gate conductor 15 and the first gate insulating film 16 extend in the first direction (Y-axis direction) parallel to the upper surface of the semiconductor substrate 32 and are orthogonal to the first direction (Y direction).
  • a plurality of first trenches formed at equal intervals in two directions (X direction) from the upper surface of the semiconductor layer 40 to a depth of a part of the low concentration impurity layer 33 penetrating the first body region 18. It is formed inside 17 respectively.
  • the first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13.
  • the first gate conductor 15 is an embedded gate electrode embedded inside the semiconductor layer 40 and is electrically connected to the first gate electrode pad 119.
  • the portion 12 of the first source electrode 11 is a layer bonded to the solder during reflow in face-down mounting, and is a metal material containing, as an example, not limited to, one or more of nickel, titanium, tungsten, and palladium. It may be composed of.
  • the surface of the portion 12 may be plated with gold or the like.
  • the portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40, and is not limited to a metal material containing one or more of aluminum, copper, gold, and silver. It may be configured.
  • a second body region 28 containing a second conductive type impurity is formed in the second region A2 of the low-concentration impurity layer 33.
  • a second source region 24 containing first conductive type impurities, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28.
  • the second gate conductor 25 and the second gate insulating film 26 are formed at a depth from the upper surface of the semiconductor layer 40 to a part of the low-concentration impurity layer 33 through the second body region 28.
  • Each is formed inside the second trench 27.
  • the second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.
  • the second gate conductor 25 is an embedded gate electrode embedded inside the semiconductor layer 40 and is electrically connected to the second gate electrode pad 129.
  • the portion 22 of the second source electrode 21 is a layer that is bonded to the solder during reflow in face-down mounting and, as an example, is not limited to a metal material containing one or more of nickel, titanium, tungsten, and palladium. It may be composed of.
  • the surface of the portion 22 may be plated with gold or the like.
  • the portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40, and is not limited to a metal material containing one or more of aluminum, copper, gold, and silver. It may be configured.
  • the semiconductor substrate 32 functions as a common drain region in which the first drain region of the transistor 10 and the second drain region of the transistor 20 are shared.
  • a part of the low-concentration impurity layer 33 on the side in contact with the semiconductor substrate 32 may also function as a common drain region.
  • the metal layer 30 functions as a common drain electrode in which the drain electrode of the transistor 10 and the drain electrode of the transistor 20 are shared.
  • the first body region 18 is covered with an interlayer insulating layer 34 having an opening, and the first source electrode 11 is connected to the first source region 14 through the opening of the interlayer insulating layer 34.
  • Part 13 is provided.
  • the interlayer insulating layer 34 and the portion 13 of the first source electrode are covered with a passivation layer 35 having an opening, and a portion 12 connected to the portion 13 of the first source electrode through the opening of the passivation layer 35 is provided. ..
  • the second body region 28 is covered with an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 connected to the second source region 24 through the opening of the interlayer insulating layer 34 is provided. There is.
  • the interlayer insulating layer 34 and the portion 23 of the second source electrode are covered with a passivation layer 35 having an opening, and a portion 22 connected to the portion 23 of the second source electrode through the opening of the passivation layer 35 is provided. ..
  • the plurality of first source electrode pads 111 and the plurality of second source electrode pads 121 are regions in which the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, respectively. Refers to the so-called terminal part.
  • one or more first gate electrode pads 119 and one or more second gate electrode pads 129 are the first gate electrode 19 (not shown in FIGS. 1, 2A, 2B) and 1, respectively.
  • the second gate electrode 29 (not shown in FIGS. 1, 2A, 2B) refers to a region partially exposed on the surface of the semiconductor device 1, a so-called terminal portion.
  • the first conductive type is N-type and the second conductive type is P-type
  • the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 are It is an N-type semiconductor
  • the first body region 18 and the second body region 28 may be P-type semiconductors.
  • the first conductive type is P-type and the second conductive type is N-type
  • the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer are used.
  • 33 is a P-type semiconductor
  • the first body region 18 and the second body region 28 may be an N-type semiconductor.
  • the conduction operation of the semiconductor device 1 will be described as a case where the transistor 10 and the transistor 20 are so-called N-channel type transistors in which the first conductive type is N type and the second conductive type is P type.
  • the transistor 10 and the transistor 20 are described on the premise that they have symmetry with no difference in function, characteristics, structure, etc.
  • FIGS. 1, 2A, and 2B are also drawn on the premise of symmetry, symmetry is not always a necessary condition in the chip size package type, dual configuration vertical field effect transistor in the present disclosure.
  • Orthogonal configuration 3A and 3B are a plan view and a perspective view of a substantially unit configuration of a transistor 10 (or a transistor 20) repeatedly formed in the X direction and the Y direction of the semiconductor device 1, respectively.
  • the semiconductor substrate 32 and the first source electrode 11 (or the second source electrode 21) are not shown for the sake of clarity.
  • the Y direction is a direction (first direction) in which the first trench 17 and the second trench 27 extend in parallel with the upper surface of the semiconductor layer 40.
  • the X direction means a direction (second direction) parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction.
  • the transistor 10 is provided with a first connection portion 18A that electrically connects the first body region 18 and the first source electrode 11.
  • the first connection portion 18A is a region of the first body region 18 in which the first source region 14 is not formed, and contains the same second conductive type impurities as the first body region 18.
  • the first source region 14 and the first connecting portion 18A are alternately and periodically and repeatedly arranged along the Y direction. The same applies to the transistor 20.
  • a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and the second gate electrode 29 (second gate conductor 25) is applied with reference to the second source electrode 21.
  • a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28.
  • the main current flows through the path of the conduction channel formed in the body region 28 of the semiconductor device, the second source region 24, and the second source electrode 21, and the semiconductor device 1 is brought into a conduction state.
  • the contact surface between the second body region 28 and the low-concentration impurity layer 33 has a PN junction and functions as a body diode. Further, since this main current flows through the metal layer 30, by making the metal layer 30 thicker, the cross-sectional area of the main current path can be expanded and the on-resistance of the semiconductor device 1 can be reduced.
  • a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and the first gate electrode 19 (first gate electrode 19) with the first source electrode 11 as a reference.
  • a voltage equal to or higher than the threshold value is applied to the gate conductor 15
  • a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18.
  • the main current flows through the path of the conduction channel formed in the body region 18 of the above, the first source region 14, and the first source electrode 11, and the semiconductor device 1 is brought into a conduction state.
  • the contact surface between the first body region 18 and the low-concentration impurity layer 33 has a PN junction and functions as a body diode.
  • the length of the first source region 14 in the Y direction is referred to as LS1
  • the length of the second source region 24 in the Y direction is referred to as LS2.
  • the length of the source area when the first source area 14 and the second source area 24 cannot be distinguished, they are referred to as LS.
  • the length of the first connecting portion 18A in the Y direction is referred to as LB1
  • the length of the second connecting portion 28A in the Y direction is referred to as LB2.
  • the length of the connection portion when the first connection portion 18A and the second connection portion 28A cannot be distinguished, they are referred to as LB.
  • the single-structured vertical field-effect transistor is formed by only one side (transistor 10) of the dual-structured vertical field-effect transistor.
  • the voltage expressed as the source-source voltage (VSS) when the semiconductor device 1 is a dual configuration N-channel vertical field effect transistor is a drain-source voltage when the semiconductor device 1 is a single configuration vertical field effect transistor. It becomes the inter-voltage (VDS). Further, when the semiconductor device 1 is a dual configuration P-channel type vertical field effect transistor, it may have a drain-drain voltage (ldap).
  • the drive is a state in which a voltage is applied to the gate conductor to conduct a current between the source and the source (or between the drain and the source, or between the drain and the drain), and unless otherwise specified, it is linear. It is meant to be conducted under the conditions of the region.
  • the soft start method is to first charge the capacitors provided in the circuit in stages and then shift to the normal operating state. May be required. Normally, the capacitor is charged instantaneously on the order of msec.
  • a large VDS is applied between the drain and the source of the transistor 10
  • a small VGS is applied to the first gate conductor 15, which is specified. It is required to control the energization so that it becomes an electric current.
  • the temperature of the transistor 10 rises due to heat generated by energization, but when the VGS is small, the temperature coefficient of IDS-VGS of the transistor 10 is positive, so the threshold value decreases and the current increases even if the VGS does not change. The state changes to do. Then, the heat generated by the transistor 10 may cause the transistor 10 to become hot again, and positive feedback may occur in which the current further increases.
  • the gm of the transistor 10 is large, the current value at which the temperature coefficient of IDS-VGS changes from positive to negative becomes large, and the temperature of the transistor 10 exceeds the specified temperature and is destroyed before reaching the specified time. There is a high risk of reaching.
  • the total gate width of the conduction channel is Wg [cm]
  • the conduction channel length in the Z direction is Lch [cm]
  • the carrier mobility in the conduction channel is ⁇ [cm 2 / V / sec]
  • the condition that needs to increase the withstand power at the time of turning on is the driving condition of the soft start carried out in the place where the VGS is small although it is above the threshold value, and in this case, the reduction of the on-resistance is not always emphasized.
  • the driving condition of the normal operation in which the reduction of the on-resistance is emphasized is that the VGS is large, and it is not always necessary to improve the withstand capacity at this time. That is, by realizing gm reduction in a place where VGS is small and RDS (on) reduction in a place where VGS is large, a semiconductor device 1 capable of achieving both gm reduction and RDS (on) reduction has been realized.
  • the total gate width Wg is adjusted.
  • the Wg in the transistor 10 having an orthogonal structure is approximately proportional to the number of the plurality of first trenches 17 provided in the effective region in which the conduction channel is formed. Further, in one first trench 17, it is proportional to the total length of the first source region 14 in contact with the trench 17 in the Y direction. However, it should be noted that the first source region 14 touches on both sides of one first trench 17. Since the first source region 14 and the first connection portion 18A are installed alternately and periodically along the Y direction, the total length of the first source region 14 in the Y direction is LS1 /. It is determined by the size of (LS1 + LB1).
  • LS1 / (LS1 + LB1) is increased, Wg can be increased and RDS (on) can be reduced, but in the present disclosure, LS1 / (LS1 + LB1) is decreased to reduce Wg and gm. do.
  • LS1 / (LS1 + LB1) is in the range of 1/8 or more and 1/4 or less. I got the result of.
  • LS1 / LB1 LS1 / LB1 is equivalent to the range of 1/7 or more and 1/3 or less.
  • the contact plug is in contact with the first source region 14 and the first body region 18, and at the time of turn-off of the transistor 10, carriers accumulated in the vicinity of the first gate insulating film 16 are passed through the contact plug. It can be dissipated to the source electrode 11 of No. 1 by the shortest path. That is, the first source electrode 11 has a contact plug that extends to a depth that reaches the first body region 18. Therefore, in the parallel type structure in which the contact plugs are installed at all the intermediate positions sandwiched between the adjacent first trenches 17, it is possible to show an excellent feature of improving the load resistance at the time of turn-off.
  • the examination levels 2, 3 and 4 in Table 1 include the first groove portion 110 for filling the contact plug as in the parallel type structure, while the first source region 14 and the first source region 14 and the first as in the orthogonal type structure.
  • the connecting portion 18A has a structure in which the connecting portions 18A are alternately and periodically installed along the Y direction. This is expressed as parallel type + orthogonal type. According to the study by the present inventors, if LS1 / LB1 is 1/7 (level 2), Wg is about 1/8 and gm is halved from 20S to 10S as compared with the parallel type (level 1) structure.
  • This disclosure is a technique for reducing the condition that the transistor 10 is destroyed by positive feedback by optimizing Wg and reducing gm. Although it does not prevent positive feedback itself, it is possible to moderate the positive feedback by appropriately adjusting gm according to the desired conditions for which safe operation is required.
  • Vth the threshold value in the present disclosure. In this disclosure, it refers to the value described as the threshold value (Vth) in the product specifications of the transistor. There are various measurement conditions when defining Vth depending on the product specifications, but the conditions are not limited. Unless otherwise specified in the present disclosure, Vth may be regarded as described in the product specifications of the transistor.
  • the present inventors have determined that the size (also referred to as chip area) and shape of the semiconductor device 1 in a plan view are a square having a size of 3.05 mm ⁇ 3.05 mm. If the power input to the circuit on which the semiconductor device 1 is mounted is large, the power controlled by the semiconductor device 1 (power loss) also increases, so that the area of the semiconductor device 1 must also be increased. However, in the present disclosure, it is emphasized that the area occupied by the semiconductor device 1 in the circuit is not excessively increased even if the electric power input to the circuit becomes large.
  • the shape of the semiconductor device 1 does not necessarily have to be square, but it is preferably rectangular. This is because of the ease of arrangement when the semiconductor device 1 is mounted on the circuit.
  • the semiconductor device 1 has a rectangular shape in a plan view, the ratio of LS1 to LB1 (LS1 / LB1) is 1/7 or more and 1/3 or less, and a specified current is instantaneously applied to the vertical field effect transistor.
  • the power loss area ratio obtained by dividing the power loss [W] by the chip area [mm 2 ] of the semiconductor device 1 may be 6.40 [W / mm 2 ] or more.
  • 6.40 W / mm 2 is a value obtained by dividing 60.0 W by an area of 3.05 mm ⁇ 3.05 mm.
  • the semiconductor device 1 may have a square shape, and when the semiconductor device 1 has a square shape, the effect of suppressing the warp of the semiconductor device 1 can be enjoyed.
  • FIG. 5 shows the results of the thermal resistance Rth when the thickness of the semiconductor device 1 is changed with the level 1 in Table 1 as the basic structure.
  • the semiconductor device 1 should be thicker in order to reduce Rth. Since Rth ⁇ 2.08 ° C./W is the thickness of the semiconductor device 1 of 343 ⁇ m, it is desirable that the thickness of the semiconductor device 1 is approximately 345 ⁇ m or more.
  • FIG. 6A, 6C, and 6E are schematic views of a cross section in which the vicinity of the first trench 17 is cut along the Y direction when the transistor 10 is driven.
  • 6B, 6D, and 6F are transistors 10 and are plan views showing the first source electrode 11, the interlayer insulating layer 34, and the passivation layer 35 omitted.
  • VGS voltage applied to the first gate conductor 15
  • FIG. 6A shows energization when VGS is small. The state is schematically represented. However, since it is in a conductive state, the VGS exceeds the threshold value.
  • the broken line arrow in the figure schematically represents the flow of current passing through the inverted layer generated in the first body region 18 as a conduction channel.
  • this is represented in a plan view of the semiconductor layer 40, it becomes as shown by the thick line portion in FIG. 6B. Only the inversion layer formed just below the first source region 14 along the first trench 17 contributes to conduction as a conduction channel.
  • An inversion layer is also formed in the vicinity of the first trench 17 in the first body region 18 directly below the first connection portion 18A, but this portion is directly above the first connection portion 18A and is the first. Since it is not the source region 14 of the above, the inversion layer does not connect the drain region (low concentration impurity layer 33) and the first source region 14 in the Z direction, and does not become a conduction channel. However, only in the portion very close to the first source region 14 in the Y direction, the inversion layer can diagonally connect the drain region (low concentration impurity layer 33) and the first source region 14 to contribute to conduction. The region contributing to continuity expands along the Y direction as the VGS increases.
  • FIG. 6C and 6D are schematic views when the VGS is large, and the dashed arrow in FIG. 6C represents an enlarged portion of this conduction region.
  • This expansion of the conduction region is captured as shown in FIG. 6D in a plan view. That is, the conduction region expands on both sides along the Y direction slightly more than the length of the first source region 14.
  • FIGS. 7A-1 to 7A-3 show a cross section in which the vicinity of the first trench 17 of the transistor 10 is cut along the Y direction, as in FIGS. 6A, 6C, and 6E.
  • the upper part shows the structure used in the simulation.
  • the first body region 18 is not divided into directly under the first source region 14 and directly under the first connecting portion 18A, but a boundary line is provided here for convenience.
  • the middle row (Fig. 7A-2, Fig. 7B-2) shows the current density when conducting under the condition that VGS is large
  • the lower row (Fig. 7A-3, Fig. 7B-3) shows the upper and middle rows. It is shown by superimposing.
  • the length LB1 of the first connection portion 18A is long (horizontal arrow in the figure), so that the first connection portion 18A It can hardly be seen that the first body region 18 immediately below the above contributes to the continuity. However, a portion where the current density becomes finite can be seen slightly in the vicinity of the first source region 14. Further, as shown by the round frame A in the figure, since it can be confirmed that there are portions where the current density is high at both ends of the first source region 14 in the Y direction, the first connection portion 18A is directly below the first connection portion 18A. It can be seen that there is a current that has passed through the body region 18 of 1.
  • FIG. 8 shows an example of calculating the VGS dependence of the length in the Y direction of the conduction region extending from the first source region 14 to the first body region 18 directly below the first connection portion 18A. The calculation was performed by the present inventors using a calculation model of an N-channel single-structured vertical field-effect transistor adjusted to the measured value.
  • the structure is an orthogonal type shown in FIGS. 3A to 3B, the internal width of the trench is 0.20 ⁇ m, the distance between the trenches is 0.90 ⁇ m, and the other parameters are the values shown in Table 1. ..
  • the maximum voltage specified between the drain and the source is 40.0V.
  • the length of the conduction region extending from both sides of one first source region 14 in the Y direction is plotted.
  • the length of the expanding conduction region increases as the VGS increases.
  • first connection portion 18A sandwiched between the first source regions 14 from both sides in the Y direction, when the length LB1 is 3.20 ⁇ m or less, it is directly below the first connection portion 18A.
  • the entire length of the first body region 18 in the Y direction can contribute to conduction.
  • VGS ⁇ 12.0V the relationship shown in FIG. 8 is established when VGS ⁇ 12.0V. This is because the approximate expression of the plot shown in FIG. 8 is a quadratic function, and VGS becomes maximum around 12.0V or 13.0V. Although it depends on other parameters such as VDS, it can be considered that VGS ⁇ 12.0V can be expected to significantly expand the conduction region. Further, regarding the expansion of the conduction region, since the increase range of VGS is large between 3.0V and 4.0V, the effect of expansion of the conduction region can be effectively used when VGS ⁇ 4.0V. Therefore, it can be said that it is effective to utilize the effect of the present disclosure in the range of 4.0 V ⁇ VGS ⁇ 12.0 V. Corresponding to this range, LB1 is preferably 1.50 ⁇ m ⁇ LB1 ⁇ 3.50 ⁇ m.
  • FIG. 9 shows a desirable installation range of LB1 and LS1 with the horizontal axis as LB1 and the vertical axis as LS1. 1/7 ⁇ LS1 / LB1 ⁇ 1/3 is required to improve the withstand capacity when on (soft start), and 1.50 ⁇ m ⁇ to reduce RDS (on) during normal operation.
  • LB1 ⁇ 3.50 ⁇ m is desirable, and more preferably 2.50 ⁇ m ⁇ LB1 ⁇ 3.20 ⁇ m.
  • the VGS in this relational expression may be regarded as a voltage having a value described in the specifications of the semiconductor device 1. The specifications are the product specifications of the transistor, and FIG.
  • VGS on-resistance
  • the specified value of the voltage VGS applied to the first gate conductor 15 is 2.5V, 3.1V, 3.8V, 4.5V, or in this range. It is an arbitrary value. Therefore, in the example of FIG. 10, it suffices if there is a VGS in which LB1 ⁇ ⁇ 0.024 ⁇ (VGS) 2 +0.633 ⁇ VGS ⁇ 0.721 is established in the range of 2.5V ⁇ VGS ⁇ 4.5V. ..
  • the fact that the VGS is small means that it is driven by a VGS that is lower than the minimum VGS shown in the specifications.
  • VGS the minimum VGS shown in the specifications.
  • it although it is higher than the threshold value, it means a condition of driving with VGS ⁇ 2.5V.
  • a large VGS means that the vehicle is driven by a VGS equal to or higher than the minimum VGS specified in the specifications.
  • it refers to the condition of driving with VGS ⁇ 2.5V.
  • the condition in which the transistor 10 is actually used is considered to be the condition in which the VGS is large.
  • the specifications in the above description are based on the characteristics at room temperature (mainly 25 ° C.).
  • the effect of contributing the total length in the Y direction to continuity is obtained by setting the length LB1 of the first connection portion 18A to a certain length or less, but at this time, the on-resistance is the first. It is characteristic that the dependency of the length LS1 of the source region 14 is lost. This is because the entire length along the first trench is an effective conduction channel, so that the driving state is the same regardless of whether the length LS1 of the first source region 14 is long or short. In the semiconductor device 1 that uses a certain finite area, the length LB1 of the first connection portion 18A cannot be changed independently, and if the LB1 is shortened, in most cases, the first one is used.
  • the on-resistance of the transistor 10 is no longer significantly reduced regardless of the length LS1 of the first source region 14 even if the length LB1 of the first connection portion 18A is further shortened. It is characterized by being in a convergent region that does not occur.
  • the length LS1 of the first source region 14 can be shortened without deteriorating the on-resistance. As will be described later, for this reason, even if 1/7 ⁇ LS1 / LB1 ⁇ 1/3, it is possible to reduce the on-resistance at the same time.
  • the parameters are shown in Table 1.
  • Comparative Example 1 (circle) is the same as Level 1 in Table 1
  • Comparative Example 2 (diamond) is the same as Level 3 in Table 1.
  • VDS is 0.1V and Vth is about 2.0V.
  • Each point is a calculation result, and the line connecting each point is an approximation.
  • VGS Vth
  • VGS Vth
  • VGS Vth
  • VGS the relationship between IDS and VGS is roughly divided into three sections and changes.
  • the first section includes a range in which the VGS is small, and the IDS has a downwardly convex non-linear relationship with the VGS.
  • VGS> Vth since VDS is as small as 0.1 V in FIG. 11, the transistor 10 operates in the linear region, and in principle, IDS increases with respect to VGS as a linear function.
  • this embodiment triangle
  • the first body region 18 directly below the first connection portion 18A gradually continues to expand as a conduction region, and the second section is up to the point where the entire length in the Y direction finally becomes the conduction region.
  • the second section is 2.5V to 3.0V ⁇ VGS ⁇ 9.0V. You can see it.
  • Wg is increased by the quadratic function of VGS in the second section.
  • the transistor 10 in the second section operates in the linear region, and considering that gm is IDS / VGS and gm is proportional to Wg, in principle.
  • IDS in the second section is likely to increase due to the cubic function of VGS, but in FIG. 11, due to the limitation of the area of the semiconductor device 1, the current that can be physically energized also tends to be limited. Therefore, the relationship of IDS with respect to VGS in the second interval is regarded as an upwardly convex nonlinear relationship.
  • the third section is a section in which the entire length in the Y direction is the conduction region.
  • the VGS dependence of the IDS is dominated by the limitation by the area of the semiconductor device 1 and shows a convergence tendency, and the IDS has a linear relationship with a small slope with respect to the VGS (in FIG. 11 in this embodiment (triangle)).
  • the RDS (on) is in the most reduced operating state, and it is desirable that the normal operation of the semiconductor device 1 is driven under the conditions corresponding to the third section.
  • this embodiment intentionally separates the small range of VGS that requires improvement of the withstand capacity at the time of on (soft start) from the large range of VGS that requires reduction of RDS (on).
  • the first section and the second section are widened, and the VGS at which the third section starts is made as large as possible.
  • VGS 9.0V
  • VGS ⁇ 9.0V it may be more important to reduce gm than to reduce RDS (on). This is especially useful when the emphasis is on improving the withstand capacity when on.
  • the third section has a driving condition separated from Vth by 2.0V or more via the first section and the second section. It is preferable that the threshold value is adjusted so as to be. That is, it is desirable that VGSy-Vth ⁇ 2.0V. Further, since the condition typically used is 7.0V ⁇ VGS ⁇ 10.0V, the third section is driven at a distance of 5.0V or more from the threshold value (Vth) via the first section and the second section. It may be adjusted so that the condition (that is, VGSy-Vth ⁇ 5.0V) is satisfied.
  • the IDS finally shows a convergence tendency with respect to the VGS in the third section.
  • RDS on
  • there is no tendency of IDS to converge on VGS until just before VGSy and finally there is a tendency of convergence (linear relationship with a small slope) near VGSy.
  • the convergence tendency or the linear relationship with a small slope means that the differential value of IDS with respect to VGS is less than 0.1 A / V (dotted line dIDS / dVGS ⁇ 0.1 in FIG. 11).
  • the differential value of IDS with respect to VGS does not fall below 0.1 A / V up to the vicinity of VGSy (at least VGSy-1.0 V), and when VGS ⁇ VGSy, the differential value of IDS with respect to VGS is 0. It will be less than 1 A / V.
  • Comparative Example 1 (circle) and Comparative Example 2 (diamond) the drive voltage corresponding to VGSy cannot be defined, but the convergence tendency of IDS with respect to VGS begins to appear relatively faster than in this embodiment (triangle).
  • Comparative Example 2 (diamond) the convergence tendency that the differential value of IDS with respect to VGS is less than 0.1 A / V cannot be obtained.
  • the difference in the behavior of IDS-VGS between this example (triangle) and Comparative Example 1 (circle) and Comparative Example 2 (diamond) is due to the difference in the effective VGS dependence of Wg.
  • the first source region 14 and the first connecting portion 18A in which the first body region 18 is connected to the first source electrode 11 are first.
  • the length of one source region 14 in the first direction is LS. [ ⁇ m], where the length of the first connecting portion 18A in the first direction is LB [ ⁇ m], the ratio of LS to LB is 1/7 or more and 1/3 or less, and the ratio of the first source electrode 11 is 1.
  • VGS voltage
  • the Wg when the VGS is small, the Wg is limited to improve the withstand voltage at the time of turning on, and when the VGS is large, the effective Wg is expanded to reduce the on-resistance. Can be done.
  • Patent Document 2 there is no need to create separate regions for Vth1 and Vth2 so that Vztc is inserted between Vth1 and Vth2, and further expand the space between the Vth1 value and the Vth2 value to a certain extent.
  • the transistor 10 in the present disclosure does not have to have different regions in the plane of the semiconductor device 1 for the threshold value of the voltage applied to the first gate conductor 15 when the transistor 10 is energized.
  • the semiconductor device of the present disclosure has been described above based on the embodiment, the present disclosure is not limited to this embodiment. As long as the gist of the present disclosure is not deviated, various modifications that can be conceived by those skilled in the art are applied to the present embodiment, and other forms constructed by combining some components in the embodiment are also within the scope of the present disclosure. Included in.
  • the semiconductor device provided with the vertical field effect transistor according to the present disclosure can be widely used as a device for controlling the conduction state of the current path.

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