WO2022057539A1 - 一种列选择信号单元电路、位线感测电路及存储器 - Google Patents

一种列选择信号单元电路、位线感测电路及存储器 Download PDF

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Publication number
WO2022057539A1
WO2022057539A1 PCT/CN2021/112609 CN2021112609W WO2022057539A1 WO 2022057539 A1 WO2022057539 A1 WO 2022057539A1 CN 2021112609 W CN2021112609 W CN 2021112609W WO 2022057539 A1 WO2022057539 A1 WO 2022057539A1
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WIPO (PCT)
Prior art keywords
column selection
selection unit
memory cell
sense amplifier
bit line
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PCT/CN2021/112609
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English (en)
French (fr)
Inventor
池性洙
王佳
汪瑛
金书延
张凤琴
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长鑫存储技术有限公司
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Priority to EP21868367.0A priority Critical patent/EP4198982A4/en
Publication of WO2022057539A1 publication Critical patent/WO2022057539A1/zh
Priority to US17/743,497 priority patent/US20220277785A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Definitions

  • the embodiments of the present application relate to, but are not limited to, a column selection signal unit circuit, a bit line sensing circuit, and a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell includes a transistor and a capacitor.
  • the transistor acts as a switch between the capacitor and the bit line and can be activated by a word line coupled to the control terminal of the transistor.
  • the memory cell is capable of storing binary information as a charge on the capacitor.
  • the sense amplifier is connected with the storage unit, and can amplify the weak signal stored in the storage unit, so that the data stored in the storage unit can be correctly written or read.
  • DRAM can correct data errors in memory through an error detection and correction circuit (Error Correcting Code, ECC), but ECC can only correct one bit error (1 bit error), and the above two-bit error exceeds the error correction capability of ECC.
  • ECC Error Correcting Code
  • an embodiment of the present application provides a column selection signal unit circuit, including: a first column selection unit, a second column selection unit, a third column selection unit, and a fourth column selection unit, each including 4*N input and output ports, 4*N bit line connection ports and one control port; wherein, the control ports of the first column selection unit and the fourth column selection unit are electrically connected to the first column selection signal, the second column selection unit The control ports of the column selection unit and the third column selection unit are electrically connected to the second column selection signal, and the bit line connection ports of the first column selection unit and the third column selection unit are respectively connected with the first memory cell group The 8*N bit lines are connected, the bit line connection ports of the second column selection unit and the fourth column selection unit are respectively connected to the 8*N bit lines of the second storage unit group, and the first storage unit The unit group and the second storage unit group are arranged adjacently, and the N is an integer greater than or equal to 1.
  • an embodiment of the present application further provides a column selection signal unit circuit, including: a fifth column selection unit, a sixth column selection unit, a seventh column selection unit, and an eighth column selection unit, all of which include 4*N input and output ports, 4*N bit line connection ports and one control port; wherein the fifth column selection unit is electrically connected to the first column selection signal, the sixth column selection unit and the seventh column selection unit The control port of the unit is electrically connected to the second column selection signal, the eighth column selection unit is electrically connected to the third column selection signal, and the bit line connection port of the fifth column selection unit is respectively connected to the 4*N of the first memory cell group.
  • the bit line connection ports of the sixth column selection unit are respectively connected to 4*N bit lines of the second memory cell group, and the bit line connection ports of the seventh column selection unit are respectively connected to the first memory cell group.
  • the 4*N bit lines of the cell group are connected, the bit line connection ports of the eighth column selection unit are respectively connected to the 4*N bit lines of the second memory cell group, the first memory cell group and the
  • the two storage unit groups are arranged adjacently, and the N is an integer greater than or equal to 1.
  • an embodiment of the present application further provides a bit line sensing circuit, including: L memory cell groups, each of the memory cell groups including H bit lines, and the L and the H are both greater than A positive integer equal to 2; M sense amplifier groups configured to write storage data to or read storage data from bit lines in the storage cell group, the M sense amplifier groups The sense amplifier group is electrically connected to the L memory cell groups, and the M is an integer multiple of the L or the L is an integer multiple of the M; the sense amplifier group includes any of the embodiments of the present application.
  • the column selection signal unit circuit wherein, two adjacent bit lines in the H bit lines are connected to different sets of the sense amplifiers.
  • an embodiment of the present application provides a memory, the memory includes the bit line sensing circuit in any of the embodiments; each of the memory cell groups further includes one word line, and the one word line H transistors and H capacitors corresponding to the H bit lines, the 1 word line controls the turning on or off of the H transistors, and the H bit lines correspond to the H transistors
  • the first terminals of the H transistors are connected to the corresponding first terminals of the H capacitors, and the second terminals of the H capacitors are connected to a fixed voltage.
  • FIG. 1 is a schematic circuit diagram of a bit line sensing circuit storage array provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a bit line sensing circuit storage array provided by an embodiment of the present application
  • Fig. 3 is the partial enlarged schematic diagram of area A in Fig. 2;
  • Fig. 4 is the partial enlarged schematic diagram of area A in Fig. 1;
  • FIG. 5 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a comparative example of a bit line sensing circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a first sense amplifier or a second sense amplifier provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a column selection signal unit circuit provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another column selection signal unit circuit provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a memory provided by an embodiment of the present application.
  • the memory includes a memory cell array
  • the memory cell array includes memory cells arranged in the word line direction and the bit line direction, the memory cells connected to the same word line, and each adjacent multi-bit memory cell forms A memory cell group, for example, adjacent 8 memory cells form one memory cell group.
  • the word line and the bit line are intersected, each word line is connected with a corresponding row of memory cells to turn on the memory cells in the row, and each bit line is connected with a corresponding column of memory cells to write or read data.
  • FIG. 11 is a schematic structural diagram of a column selection signal unit circuit provided by an embodiment of the present application.
  • the column selection signal unit circuit includes:
  • the first column selection unit 1411, the second column selection unit 1412, the third column selection unit 1413 and the fourth column selection unit 1414 include 4*N input and output ports, 4*N bit line connection ports and one control port .
  • the control ports of the first column selection unit 1411 and the fourth column selection unit 1414 are electrically connected to the first column selection signal, and the control ports of the second column selection unit 1412 and the third column selection unit 1413 are electrically connected to the second column selection signal Signal;
  • the bit line connection ports of the first column selection unit 1411 and the third column selection unit 1413 are respectively connected to the 8*N bit lines of the first memory cell group 15, the second column selection unit 1412 and the fourth column selection unit 1414
  • the bit line connection ports are respectively connected to the 8*N bit lines of the second memory cell group 16; the first memory cell group 15 and the second memory cell group 16 are arranged adjacently; N is an integer greater than or equal to 1.
  • the column selection signal unit circuit includes four types of column selection units: a first column selection unit 1411 , a second column selection unit 1412 , a third column selection unit 1413 and a fourth column selection unit 1414 .
  • Each column selection unit may include 4*N input and output ports, 4*N bit line connection ports and one control port, and the 4*N bit line connection ports are respectively connected to 4*N bit lines in the memory cell group,
  • the 4*N input and output ports correspond to the 4*N bit line connection ports one-to-one, which can output the read data obtained from the corresponding bit line by the corresponding bit line connection port, or write data to the bit line through the corresponding bit line connection port .
  • each column selection unit may include 4*N switch tubes T1, and the above N may be 1, then each column selection unit may include 4 switch tubes T1, and the first end of each switch tube T1 As a bit line connection port, the second terminal is used as an input and output port, and the control terminals of the four switches T1 are connected to each other to form a control port, which can receive a column selection signal that controls the switch T1 to be turned on or off.
  • the control ports of the first column selection unit 1411 and the fourth column selection unit 1414 are electrically connected to the first column selection signal CSL ⁇ n+1>, the second column selection unit 1412 and The control port of the third column selection unit 1413 is electrically connected to the second column selection signal CSL ⁇ n>, then the first column selection unit 1411 and the fourth column selection unit 1414 work simultaneously, the second column selection unit 1412 and the third column selection unit 1412 Unit 1413 works simultaneously.
  • bit line connection ports of the first column selection unit 1411 and the third column selection unit 1413 are respectively connected to the 8*N bit lines of the first memory cell group 15, so the bit lines in the first memory cell group 15 are connected differently (column selection units in the same sense amplifier group are connected to the same column selection signal), when a read error occurs on two adjacent bit lines at the same time, the erroneous data can be detected by different sense amplifier groups It is convenient to lock the two bit lines with errors, and then lock the two memory cells with errors in the first memory cell group 15 .
  • bit line connection ports of the second column selection unit 1412 and the fourth column selection unit 1414 are respectively connected to the 8*N bit lines of the second memory cell group 16, so as to facilitate locking the error occurred in the second memory cell group 16.
  • two storage units The technical solution provided by the present application realizes the detection and correction of adjacent two-bit errors in the memory without changing the error correction capability of the existing ECC, and improves the performance of the memory.
  • the first memory cell group 15 and the second memory cell group 16 are arranged adjacent to each other.
  • each memory cell group contains 8 bit lines, so N can take a value of 1.
  • N can also be is 2, 3 and other numerical values, which are not limited in the embodiments of the present application.
  • even-numbered bit lines in the first memory cell group 15 are connected to the bit line connection ports of the first column selection unit 1411 , and odd-numbered bit lines in the first memory cell group 15 are connected
  • the bit line connection port of the third column selection unit 1413; the bit line numbered even in the second memory cell group 16 is connected to the bit line connection port of the second column selection unit 1412, and the numbered odd number in the second memory cell group 16
  • the bit line of is connected to the bit line connection port of the fourth column selection unit 1414 .
  • the bit line connection port of the first column selection unit 1411 can be controlled to connect to the even-numbered bit lines in the first memory cell group 15, and the bit line connection port of the third column selection unit 1413 can be controlled to connect to the first memory cell group.
  • the labels of the bit lines in the first memory cell group 15 are BL ⁇ 0> to BL ⁇ 7> in sequence from the start to the end, and the bit line connection ports of the first column selection unit 1411 are respectively connected to BL ⁇ 0>, BL ⁇ 0> and BL ⁇ 7>.
  • bit line connection ports of the third column selection unit 1413 are respectively connected to BL ⁇ 1>, BL ⁇ 3>, BL ⁇ 5> and BL ⁇ 7>, then the bit line In the lines BL ⁇ 0> ⁇ BL ⁇ 7>, errors between every two adjacent bit lines can be located and corrected, which further improves the error correction performance of the memory.
  • the labels of the bit lines in the second memory cell group 16 are sequentially BL ⁇ 8> to BL ⁇ 15> from the start to the end, and the bit line connection ports of the second column selection unit 1412 are respectively connected to BL ⁇ 8> and BL ⁇ 10 >, BL ⁇ 12> and BL ⁇ 14>, the bit line connection ports of the fourth column selection unit 1414 are respectively connected to BL ⁇ 9>, BL ⁇ 11>, BL ⁇ 13> and BL ⁇ 15>, then the bit line BL ⁇ In 8> to BL ⁇ 15>, errors between every two adjacent bit lines can be located and corrected.
  • the first column selection unit 1411 and the second column selection unit 1412 are arranged side by side; the third column selection unit 1413 and the fourth column selection unit 1414 are arranged side by side; the first column selection unit 1411 and the third column selection unit 1414 are arranged side by side;
  • the column selection unit 1413 is disposed on opposite sides of the first memory cell group 15 ;
  • the second column selection unit 1412 and the fourth column selection unit 1414 are disposed on opposite sides of the second memory cell group 16 .
  • the first column selection unit 1411 and the second column selection unit 1412 are arranged side by side, located on the first side of the storage unit, and the third column selection unit 1413 and the fourth column selection unit 1414 are arranged side by side, located between the storage unit and the first column selection unit 1414.
  • One side is opposite to the second side, and the first column selection unit 1411 and the third column selection unit 1413 are arranged on opposite sides of the first memory cell group 15 to facilitate the connection of the bit lines of the first memory cell group 15, the second column
  • the selection unit 1412 and the fourth column selection unit 1414 are disposed on opposite sides of the second memory cell group 16 to facilitate connection to the bit lines of the second memory cell group 16 . That is, two column selection units of the same sense amplifier group (connected to the same control port) are arranged crosswise, and each column selection unit is arranged close to the memory cell group where the connected bit line is located, which is convenient for simplifying the wiring of the column selection unit.
  • the first column selection unit 1411 and the second column selection unit 1412 share 2*N input and output ports; the third column selection unit 1413 and the fourth column selection unit 1414 share 2*N inputs output port.
  • the first column selection unit 1411 and the second column selection unit 1412 arranged side by side may share 2*N input and output ports, and each input and output port is connected with two switch transistors T1.
  • N 1
  • the first column selection unit 1411 and the second column selection unit 1412 can share two input and output ports.
  • the switch tube connected to the bit line BL ⁇ 4> in the first column selection unit 1411 T1 and the switch T1 connected to the bit line BL ⁇ 10> in the second column selection unit 1412 are connected to each other and share one input and output port IO ⁇ 2>.
  • the first column selection unit 1411 and the second column selection unit 1412 also share the same I/O port IO ⁇ 3> is enabled.
  • the third column selection unit 1413 and the fourth column selection unit 1414 arranged side by side share the input and output ports IO ⁇ 6> and IO ⁇ 7>.
  • the setting of the shared input and output ports of two adjacent column selection units can simplify the fabrication process of the column selection signal unit circuit and save the fabrication cost.
  • FIG. 12 is a schematic structural diagram of a column selection signal unit circuit provided by an embodiment of the present application.
  • the column selection signal unit circuit includes:
  • the fifth column selection unit 1415, the sixth column selection unit 1416, the seventh column selection unit 1417 and the eighth column selection unit 1418 each include 4*N input and output ports, 4*N bit line connection ports and one control port .
  • the fifth column selection unit 1415 is electrically connected to the first column selection signal
  • the control ports of the sixth column selection unit 1416 and the seventh column selection unit 1417 are electrically connected to the second column selection signal
  • the eighth column selection unit 1418 is electrically connected In the third column selection signal
  • the bit line connection ports of the fifth column selection unit 1415 are respectively connected to the 4*N bit lines of the first memory cell group 15, and the bit line connection ports of the sixth column selection unit 1416 are respectively connected to the second
  • the 4*N bit lines of the memory cell group 16 are connected
  • the bit line connection ports of the seventh column selection unit 1417 are respectively connected to the 4*N bit lines of the first memory cell group 15, and the bit lines of the eighth column selection unit 1418 are respectively connected
  • the connection ports are respectively connected with 4*N bit lines of the
  • the column selection signal unit circuit includes four types of column selection units: the fifth column selection unit 1415 , the sixth column selection unit 1416 , the seventh column selection unit 1417 and the eighth column selection unit 1418 .
  • Each column selection unit may include 4*N input and output ports, 4*N bit line connection ports and one control port, and the 4*N bit line connection ports are respectively connected to 4*N bit lines in the memory cell group,
  • the 4*N input and output ports correspond to the 4*N bit line connection ports one-to-one, which can output the read data obtained from the corresponding bit line by the corresponding bit line connection port, or write data to the bit line through the corresponding bit line connection port .
  • each column selection unit may include 4*N switch tubes T1, and the above N may be 1, then each column selection unit may include 4 switch tubes T1, and the first end of each switch tube T1 As a bit line connection port, the second terminal is used as an input and output port, and the control terminals of the four switches T1 are connected to each other to form a control port, which can receive a column selection signal that controls the switch T1 to be turned on or off.
  • the fifth column selection unit 1415 is electrically connected to the first column selection signal CSL ⁇ n+1>, and the control ports of the sixth column selection unit 1416 and the seventh column selection unit 1417 are electrically connected to is connected to the second column selection signal CSL ⁇ n-1>, the control port of the eighth column selection unit 1418 is electrically connected to the third column selection signal CSL ⁇ n>, then among the above four column selection units, the fifth column selects
  • the unit 1415 first works independently, the sixth column selection unit 1416 and the seventh column selection unit 1417 work simultaneously, and the eighth column selection unit 1418 works independently.
  • bit line connection ports of the fifth column selection unit 1415 and the seventh column selection unit 1417 are respectively connected to the 8*N bit lines of the first memory cell group 15.
  • the sixth column selection unit 1416 and the eighth column The bit line connection ports of the selection unit 1418 are respectively connected to the 8*N bit lines of the second memory cell group 16, then the bit lines in the first memory cell group 15 are connected to different sense amplifier groups (in the same sense amplifier group).
  • the column selection unit is connected to the same column selection signal), and the bit lines in the second memory cell group 16 are connected to different sense amplifier groups.
  • the erroneous data can be detected by different sense amplifier groups, which facilitates locking of the two bit lines with errors, and further locking of the two memory cells with errors in the first memory cell group 15 .
  • the technical solution provided by the present application realizes the detection and correction of adjacent two-bit errors in the memory without changing the error correction capability of the existing ECC, and improves the performance of the memory.
  • the first memory cell group 15 and the second memory cell group 16 are arranged adjacent to each other.
  • each memory cell group contains 8 bit lines, so N can take a value of 1.
  • N can also be is 2, 3 and other numerical values, which are not limited in the embodiments of the present application.
  • even-numbered bit lines in the first memory cell group 15 are connected to the bit line connection ports of the fifth column selection unit 1415 , and odd-numbered bit lines in the first memory cell group 15 are connected
  • the bit line connection port of the seventh column selection unit 1417; the bit line numbered even in the second memory cell group 16 is connected to the bit line connection port of the sixth column selection unit 1416, and the second memory cell group 16 is numbered odd-numbered
  • the bit line of is connected to the bit line connection port of the eighth column selection unit 1418 .
  • bit line connection port of the fifth column selection unit 1415 can be controlled to connect to the even-numbered bit line in the first memory cell group 15, and the bit line connection port of the seventh column selection unit 1417 can be controlled to connect to the first memory cell group.
  • the bit line labels in the first memory cell group 15 are sequentially BL ⁇ 0> to BL ⁇ 7> from the start to the end, and the bit line connection ports of the fifth column selection unit 1415 are respectively connected to BL ⁇ 0>, BL ⁇ 2>, and BL ⁇ 4> and BL ⁇ 6>, the bit line connection ports of the seventh column selection unit 1417 are respectively connected to BL ⁇ 1>, BL ⁇ 3>, BL ⁇ 5> and BL ⁇ 7>, then the bit lines BL ⁇ 0> ⁇ In BL ⁇ 7>, errors between every two adjacent bit lines can be located and corrected, further improving the error correction performance of the memory.
  • bit line labels in the second memory cell group 16 are sequentially BL ⁇ 8> to BL ⁇ 15> from the beginning to the end, and the bit line connection ports of the sixth column selection unit 1416 are respectively connected to BL ⁇ 8> and BL ⁇ 10 >, BL ⁇ 12> and BL ⁇ 14>, the bit line connection ports of the eighth column selection unit 1418 are respectively connected to BL ⁇ 9>, BL ⁇ 11>, BL ⁇ 13> and BL ⁇ 15>, then the bit line BL ⁇ In 8> to BL ⁇ 15>, errors between every two adjacent bit lines can be located and corrected.
  • the fifth column selection unit 1415 and the sixth column selection unit 1416 are arranged side by side; the seventh column selection unit 1417 and the eighth column selection unit 1418 are arranged side by side; the fifth column selection unit 1415 and the seventh column selection unit 1415 are arranged side by side
  • the column selection units 1417 are disposed on opposite sides of the first memory cell group 15 ; the sixth column selection unit 1416 and the eighth column selection unit 1418 are disposed on opposite sides of the second memory cell group 16 .
  • the fifth column selection unit 1415 and the sixth column selection unit 1416 are arranged side by side, located on the first side of the storage unit, and the seventh column selection unit 1417 and the eighth column selection unit 1418 are arranged side by side, between the storage unit and the first column selection unit 1418.
  • One side is opposite to the second side, and the fifth column selection unit 1415 and the seventh column selection unit 1417 are arranged on opposite sides of the first memory cell group 15 to facilitate the connection of the bit lines of the first memory cell group 15, the sixth column
  • the selection unit 1416 and the eighth column selection unit 1418 are disposed on opposite sides of the second memory cell group 16 to facilitate connection to the bit lines of the second memory cell group 16 .
  • the two column selection cells of the same sense amplifier group are in the arrangement direction of the first memory cell group 15 and the second memory cell group 16, etc. (in the word line direction of the memory cell array) At least one memory cell group is staggered, and each column selection unit is arranged close to the memory cell group where the connected bit line is located, so as to simplify the wiring of the column selection unit.
  • the fifth column selection unit 1415 and the sixth column selection unit 1416 share 2*N input and output ports; the seventh column selection unit 1417 and the eighth column selection unit 1418 share 2*N inputs output port.
  • the fifth column selection unit 1415 and the sixth column selection unit 1416 arranged side by side can share 2*N input and output ports, and each input and output port is connected with two switch transistors T1.
  • N 1
  • the fifth column selection unit 1415 and the sixth column selection unit 1416 can share two input and output ports.
  • the switch tube connected to the bit line BL ⁇ 4> in the fifth column selection unit 1415 T1 and the switch T1 connected to the bit line BL ⁇ 10> in the sixth column selection unit 1416 are connected to each other and share one input and output port IO ⁇ 2>.
  • the fifth column selection unit 1415 and the sixth column selection unit 1416 also share the same I/O port IO ⁇ 3> is enabled.
  • the seventh column selection unit 1417 and the eighth column selection unit 1418 arranged side by side share the input and output ports IO ⁇ 6> and IO ⁇ 7>.
  • the setting of the shared input and output ports of two adjacent column selection units can simplify the fabrication process of the column selection signal unit circuit and save the fabrication cost.
  • bit line sensing circuit including:
  • L memory cell groups each of which includes H bit lines, L and H are both positive integers greater than or equal to 2; and M sense amplifier groups, configured to provide input to the memory cells
  • the bit lines in the group write storage data or read storage data from the bit lines in the storage cell group, the M sense amplifier groups are electrically connected to the L storage cell groups, and the M is the The integer multiple of L or the L is the integer multiple of the M; the sense amplifier group includes the column selection signal unit circuit described in any embodiment of the present application; wherein, two adjacent two of the H bit lines The bit lines are connected to different sets of the sense amplifiers.
  • the bit line sensing circuit includes a memory cell array arranged along the word line direction X and the bit line direction Y , the memory cell array includes a plurality of memory cells 11 .
  • the bit line sensing circuit further includes a plurality of word lines 12 and a plurality of bit lines 13 , the word lines 12 extend along the word line direction X, and each word line 12 corresponds to the memory cell 11 .
  • the word line 12 is used to turn on the corresponding memory cell 11
  • the bit line 13 extends along the bit line direction Y
  • each bit line 13 is connected to the corresponding memory cell 11 to write or read data to the corresponding memory cell 11 .
  • each word line 12 and multiple bit lines 13 intersect to define the area of each memory cell 11.
  • the bit line sensing circuit in FIG. The six word lines WL0 to WL5 arranged and the sixteen bit lines BL0 to BL15 arranged in sequence along the word line direction X define the respective memory cells 11 by crossing them.
  • memory cells 11 connected to the same word line 12 may be defined, and each adjacent n-bit memory cell 11 forms a memory cell group, where n is an integer greater than 1.
  • each row of memory cells refers to memory cells 11 arranged in sequence along the extending direction of the word line direction X, and each memory cell may be arranged directly or in a curved line.
  • FIG. 2 is a schematic structural diagram of a bit line sensing circuit memory array provided by an embodiment of the present application.
  • FIG. 1 only a simplified illustration of each memory cell is shown in the form of circuit symbols, while FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit symbols. form presented.
  • FIG. 2 shows the circuit layout in the form of circuit
  • FIG. 3 is a partially enlarged schematic diagram of the area A in FIG. 2
  • FIG. 4 is a partially enlarged schematic diagram of the area A in FIG. 1 , in FIG. storage unit 11.
  • each memory cell 11 may include a second transistor T2 and a capacitor C1; the second transistor T2 includes a control terminal, a first terminal and a second terminal; the second The control end of the transistor T2 is connected to the corresponding word line 12, namely WL1, and is used to turn on and off under the control of the level on the word line 12; the first end of the second transistor T2 is connected to the corresponding bit line 13, and the first end of the transistor T2 is connected to the corresponding bit line 13.
  • the second end of the two transistors T2 is connected to the capacitor C1 of the storage unit 11, and is used to connect the bit line 13 to the capacitor C1 in the on state, so as to write the data on the bit line 13 into the capacitor C1, or The data stored in the read capacitor C1 is transferred to the bit line 13 .
  • the memory cell 11 is connected to the bit line BL1 through a BLC (Bit Line Contact, bit line contact hole).
  • an embodiment of the present application provides a bit line sensing circuit, including: L memory cell groups 15 , each of the memory cell groups 15 includes H bit lines 13 , the L and the H is a positive integer greater than or equal to 2; M sense amplifier groups 14 are configured to write storage data to the bit lines in the memory cell group 15 or read out from the bit lines in the memory cell group 15 To store data, the M sense amplifier groups 14 are electrically connected to the L memory cell groups 15, and the M is an integer multiple of the L or the L is an integer multiple of the M; wherein, the Adjacent two of the H bit lines are connected to different sets of the sense amplifiers 14 .
  • the H is an integer multiple of 8, and the M is equal to the L. In one embodiment, H is equal to 8, and both M and L are equal to 2 as an example.
  • each of the sense amplifier groups 14 includes a first sense amplifier 14a and a second sense amplifier 14b; the L memory cell groups 15 are arranged side by side along the word line 12 direction, The word line 12 is perpendicular to the bit line 13 ; the first sense amplifier 14 a is located on one side of the memory cell group 15 , and the second sense amplifier 14 b is located on the opposite side of the memory cell group 15 The other side.
  • FIG. 5 is a schematic structural diagram of a bit line sensing circuit provided by an embodiment of the present application.
  • the bit line sensing circuit further includes a plurality of sense amplifier groups 14 , and each sense amplifier group 14 corresponds to a plurality of sense amplifier groups 14 .
  • the bit lines 13 are connected, and the sense amplifier group 14 is connected to the corresponding plurality of bit lines 13 , so as to amplify the data stored in the memory cells 11 connected to the bit lines 13 .
  • the sense amplifier group Sense Amplifier ⁇ n> corresponds to 8 bit lines 13 (BL2, BL4, BL6, BL8, BL9, BL11, BL13 and BL15), and is connected to the corresponding 8 bit lines 13;
  • the sense amplifier group Sense Amplifier ⁇ n-1> corresponds to the other 8 bit lines 13 ( BL1 , BL3 , BL5 , BL7 , BL10 , BL12 , BL14 and BL16 ), and is connected to the corresponding other 8 bit lines 13 .
  • every two adjacent bit lines 13 are connected to different sense amplifier groups 14 .
  • the memory cell BL10, BL12, BL14, BL16 corresponding to group 15 are connected to the sense amplifier group Sense Amplifier ⁇ n-1>
  • BL9, BL11, BL13, BL15 are connected to the sense amplifier group Sense Amplifier ⁇ n>.
  • DRAM when DRAM is read, it is performed in units of 14 sense amplifier groups.
  • the sense amplifier group Sense Amplifier ⁇ n-1> reads 8 bits (BL1, BL3, BL5, BL7, BL10, BL12 , BL14, BL16), and then the sense amplifier group Sense Amplifier ⁇ n-1> sends the output data to the ECC module or to the ECC module after other processing circuits.
  • ECC has the ability to detect and correct one-bit errors.
  • the two-bit error can be read twice, and only one bit error is read at a time, so that one bit at a time Errors can be detected and corrected so that adjacent two-bit errors are detected and corrected.
  • FIG. 6 is a schematic structural diagram of a comparative example of a bit line sensing circuit provided by an embodiment of the present application.
  • BL9, BL10, BL11, BL12, BL13, BL14, BL15 corresponding to the memory cell group 15' , BL16 are connected to the sense amplifier group Sense Amplifier ⁇ n>.
  • the above two error data are connected to the sense amplifier group Sense Amplifier ⁇ n>.
  • DRAM when DRAM is read, it is carried out in units of 14 sense amplifier groups.
  • ECC has the ability to detect and correct one-bit errors. Then, when two adjacent bit errors occur, the detection and correction capabilities of the existing ECC are exceeded, resulting in DRAM read errors.
  • each sense amplifier group 14 may include a first sense amplifier 14a and a second sense amplifier 14b; the first sense amplifier 14a is located along the memory cell array. The first side in the line direction X; the second sense amplifier 14b is located on the second side of the memory cell array opposite the first side in the word line direction X.
  • the first sense amplifier and the second sense amplifier are both connected to the P bit lines, and the H is a positive even multiple of the P, for example, the first sense amplifier 14a of Sense Amplifier ⁇ n> It is connected to four bit lines of BL9, BL11, BL13, and BL15, and the second sense amplifier 14b of Sense Amplifier ⁇ n> is connected to four bit lines of BL2, BL4, BL6, and BL8.
  • the sense amplifier group 14 can be divided into two parts: the first sense amplifier 14a and the second sense amplifier 14b, the first sense amplifier 14b. 14a and the second sense amplifier 14b are disposed on opposite sides of the memory cell array in the word line direction X, respectively.
  • the first sense amplifier 14a is disposed on the first side of the memory cell array
  • the second sense amplifier 14b is disposed on the second side of the memory cell array
  • the first sense amplifier 14a is connected to the sense amplifier group 14 (Sense Amplifier ⁇ n- 1>)
  • the second sense sensor 14b is connected to the other half of the bit lines corresponding to the sense amplifier group 14 (Sense Amplifier ⁇ n-1>), such as BL10, BL12 , BL14, BL16.
  • the first sense amplifier 14a of the sense amplifier group Sense Amplifier ⁇ n> is connected to the four bit lines 13 of bit lines BL2, BL4, BL6 and BL8, and the sense amplifier group Sense Amplifier ⁇ n>
  • the second sense amplifier 14b connects the four bit lines 13 of the bit lines BL9, BL11, BL13 and BL15.
  • the staggered arrangement of the first sense amplifier 14a and the second sense amplifier 14b of each sense amplifier group 14 is convenient for each The first sense amplifier 14a and the second sense amplifier 14b of the sense amplifier group 14 are connected to the bit lines 13 of different memory cell groups. Referring to FIG.
  • the first sense amplifier 14a of Sense Amplifier ⁇ n> is connected to 4 bit lines of BL9, BL11, BL13 and BL15
  • the second sense amplifier 14b of Sense Amplifier ⁇ n> is connected to BL2
  • BL4, BL6 and BL8 have a total of 4 bit lines, project the first sense amplifier 14a and the second sense amplifier 14b of Sense Amplifier ⁇ n> to the word line WL0, the two do not overlap, that is, they are staggered along the word line direction X
  • the first sense amplifier 14a and the second sense amplifier 14b of Sense Amplifier ⁇ n-1> are projected onto the word line WL0, and the two do not overlap, that is, they are staggered along the word line direction X.
  • the number of sense amplifier groups 14 and the number of memory cell groups in each row may be the same; the first sense amplifier 14a of each sense amplifier group 14 is the same as the The odd-numbered or even-numbered columns in the bit lines of the corresponding memory cell groups are connected, and the second sense amplifiers 14b of each sense amplifier group 14 are connected to the even-numbered or odd-numbered columns in the bit lines of the corresponding memory cell groups in each row; In the same row of memory cell groups, the memory cell group corresponding to the first sense amplifier 14a of each sense amplifier group 14 is different from the memory cell group corresponding to the second sense amplifier 14b.
  • a certain memory cell group 16 corresponds to bit lines BL1 to BL8
  • another memory cell group 15 corresponds to bit lines BL9 to BL16 .
  • the number of sense amplifier groups 14 is related to each row. The number of memory cell groups can be the same, the first sense amplifiers 14a of the sense amplifier group 14 can be connected to the odd-numbered columns in the bit lines of the corresponding memory cell group, and the second sense amplifier 14b is connected to the corresponding memory cell group.
  • the even-numbered columns in the bit lines are connected, or, the first sense amplifiers 14a of the sense amplifier group 14 can be connected to the even-numbered columns in the bit lines of the corresponding memory cell group, then the second sense amplifiers 14b are connected to the corresponding memory cell groups. Odd column connections in bit lines.
  • the memory cell group connected to the first sense amplifier 14a of each sense amplifier group 14 is different from the memory cell group connected to the second sense amplifier 14b, thereby transmitting adjacent 2-bit errors to different In the sense amplifier group, for example, the first sense amplifier 14a of Sense Amplifier ⁇ n> is connected to the memory cell group 15, and the second sense amplifier 14b of Sense Amplifier ⁇ n> is connected to the memory cell group 16.
  • the first sense amplifier 14a of the sense amplifier group Sense Amplifier ⁇ n-1> is connected to the corresponding bit lines BL2, BL4, BL6 and BL8 of a memory cell group, and the sense amplifier group Sense Amplifier ⁇ n-1>
  • the second sense amplifier 14b is connected to the corresponding bit lines BL9, BL11, BL13 and BL15 of another memory cell group.
  • FIG. 7 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • the first sense amplifier 14a is disposed at The first side of the memory cell array, and set sequentially, for example, set Sense Amplifier ⁇ n-2>, Sense Amplifier ⁇ n-1>, Sense Amplifier ⁇ n>, Sense Amplifier ⁇ n+1> in sequence;
  • the second sense amplifier 14b is set on the second side opposite to the first side, and set in sequence, for example, set Sense Amplifier ⁇ n-1>, Sense Amplifier ⁇ n>, Sense Amplifier ⁇ n+1>, Sense Amplifier ⁇ n+2> in sequence .
  • the same sense amplifier group 14, such as Sense Amplifier ⁇ n> includes the first sense amplifier and the second amplifier are still staggered in the word line direction X.
  • the first sense amplifiers 14a of the nth sense amplifier group 14 are connected to the odd-numbered columns or the bit lines of the nth memory cell group along the word line direction X Even-numbered columns; the second sense amplifiers 14b of the n+i-th sense amplifier group 14 are connected to the even-numbered or odd-numbered columns in the bit lines connected to the n-th memory cell group along the word line direction X.
  • n and i are integers. For example, when i is 1, as shown in FIG. 7 , it should be noted that i may also be 2 or 3 or other integers, which are not limited here.
  • the first sense amplifiers 14a of the nth sense amplifier group 14 can be connected to the odd or even columns of the bit lines of the nth memory cell group, n+1th
  • the second sense amplifiers 14b of the sense amplifier groups 14 are connected to the even or odd columns of bit lines of the nth memory cell group.
  • the first sense amplifier 14a and the second sense amplifier 14b of each sense amplifier group 14 are staggered along the word line direction X. As shown in FIG.
  • the first sense amplifiers 14a of the sense amplifier group Sense Amplifier ⁇ n> and the second sense amplifiers 14b of the sense amplifier group Sense Amplifier ⁇ n> do not overlap in the word line direction x, that is, they are arranged staggered.
  • FIG. 8 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • the first sense amplifier of the nth sense amplifier group 14 14a connects the odd-numbered or even-numbered columns in the bit lines of the n-1 th memory cell group along the word line direction;
  • the second sense amplifier 14b of the n-1 th sense amplifier group 14 connects the second sense amplifiers 14 b along the word line direction.
  • the second sense amplifier 14b of the n-th sense amplifier group 14 is connected to the bit lines of the n-th memory cell group along the word line direction X
  • the first sense amplifiers 14a of the n-1th sense amplifier group 14 connect the odd-numbered or even-numbered columns in the bit lines of the nth memory cell group along the word line direction X; wherein n is a positive integer.
  • the first sense amplifier 14a of Sense Amplifier ⁇ n> is connected to the even columns (BL2, BL4, BL6 and BL8) of the n-1th memory cell group, and the second sense amplifier of Sense Amplifier ⁇ n-1> 14b is connected to the odd-numbered columns (BL1, BL3, BL5 and BL7) of the n-1th memory cell group; the second sense amplifier 14b of Sense Amplifier ⁇ n> is connected to the odd-numbered columns (BL9, BL11) of the n-th memory cell group , BL13 and BL15) are connected, and the first sense amplifier 14a of the Sense Amplifier ⁇ n> is connected to the even columns (BL10, BL12, BL14 and BL16) of the nth memory cell group.
  • FIG. 9 is a schematic structural diagram of another bit line sensing circuit provided by an embodiment of the present application.
  • a plurality of memory cells are sequentially arranged Array AA; along the bit line direction Y, the opposite sides of each memory cell array AA are respectively provided with a first sense amplifier 14a and a second sense amplifier 14b; along the bit line direction Y, the t-th memory cell array
  • the first sense amplifier 14a of AA can be multiplexed into the second sense amplifier 14a of the t+1th memory cell array AA, for example, the first sense amplifier 14a of the sense amplifier group Sense Amplifier ⁇ n> in FIG.
  • the first sense amplifier 14a as a whole can be multiplexed by its upper and lower memory cell arrays AA; the first sense amplifier 14a of the t+1th memory cell array AA is multiplexed into the t+2th memory cell Second sense amplifier 14b of array AA; t is a positive integer.
  • FIG. 10 is a schematic structural diagram of a first sense amplifier or a second sense amplifier provided by an embodiment of the present application
  • FIGS. 11 and 12 are schematic structural diagrams of a column selection unit provided by an embodiment of the present application.
  • both the first sense amplifier and the second sense amplifier include a column selection unit 141 (represented by CSL ⁇ n> in FIG. 10 ) and a sense amplifier 142 (represented by Amplifier in FIG.
  • the column selection unit 141 may include a control terminal, a first terminal and a second terminal; the first terminal of the column selection unit 141 is electrically connected to the corresponding sensitive amplifier 142, and the second terminal of the column selection unit 141 is connected to other circuits, such as the second terminal A stage-sensitive amplifier or conversion circuit, and the control terminal of the column selection unit 141 is connected to the decoding circuit.
  • the column selection unit 141 may include first transistors T1; each of the first transistors T1 includes a control terminal, a first terminal and a second terminal. Taking FIG. 10 as an example, the column selection unit 141 includes four first transistors T1 , and each transistor T1 is connected to the sense amplifier 142 .
  • the column selection unit 141 is provided with the first terminals corresponding to the four bit lines of the corresponding memory cell group one-to-one or the four input and output terminals of the sense amplifier 142 are connected, It is configured to control the input and output of data of the sense amplifier 142 .
  • a memory is also provided. Referring to FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , and FIG. 13 , it includes the technical features of the bit line sensing circuit provided by any embodiment of the present application, and has the benefits of the technical features. Effect.
  • Each of the memory cell groups further includes 1 word line, the 1 word line and the H bit lines also correspond to H transistors and H capacitors, and the 1 word line controls the H transistors is turned on or off, the H bit lines are connected to the corresponding first ends of the H transistors, the second ends of the H transistors are connected to the corresponding first ends of the H capacitors, so The second terminals of the H capacitors are connected to a fixed voltage.
  • H is an integer of 8, and both M and the L are 2.
  • an error detection and correction circuit connected to the sense amplifier group (Sense Amplifier), and configured to detect the stored data output by the sense amplifier group. correctness and correct errors in the stored data.
  • ECC error detection and correction circuit
  • the embodiments of the present application realize the detection and correction of two-bit errors in the memory without changing the existing ECC error correction capability, thereby improving the performance of the memory.
  • Embodiments of the present application provide a column selection signal unit circuit, a bit line sensing circuit, and a memory.
  • the column selection signal unit circuit includes: a first column selection unit, a second column selection unit, a third column selection unit, and a fourth column selection unit
  • the units include 4*N input and output ports, 4*N bit line connection ports and a control port; the control ports of the first column selection unit and the fourth column selection unit are connected to the first column selection signal, and the second column selection
  • the control ports of the unit and the third column selection unit are connected to the second column selection signal, the bit line connection ports of the first column selection unit and the third column selection unit are connected to the 8*N bit lines of the first memory cell group, and the second column
  • the bit line connection ports of the selection unit and the fourth column selection unit are connected to the 8*N bit lines of the second memory cell group, and the first memory cell group and the second memory cell group are arranged adjacently.
  • the technical solution provided by the present application enables two adjacent bit lines to be connected to different sense amplifier groups, and when a read error occurs on the two adjacent bit lines at the same time, the erroneous data can be detected and corrected by an error detection and correction circuit.
  • the technical solution provided by the present application realizes the detection and correction of two-bit errors in the memory without changing the existing ECC error correction capability, and improves the performance of the memory.

Abstract

一种列选择信号单元电路、位线感测电路及存储器，列选择信号单元电路包括：四个列选择单元；均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口；第一列选择单元和第四列选择单元的控制端口接第一列选择信号，第二列选择单元和第三列选择单元的控制端口接第二列选择信号，第一列选择单元和第三列选择单元的位线连接端口连接第一存储单元组的8*N条位线，第二列选择单元和第四列选择单元的位线连接端口连接第二存储单元组的8*N条位线，第一存储单元组和第二存储单元组相邻设置。上述技术方案，使得相邻两条位线连接到不同的感测放大器组，当相邻两条位线同时出现读取错误时，错误数据可以被检错纠错电路检测和纠正。

Description

一种列选择信号单元电路、位线感测电路及存储器
相关申请的交叉引用
本申请基于申请号为202010986823.1、申请日为2020年09月18日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种列选择信号单元电路、位线感测电路及存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)包括阵列排布的存储单元(存储位)。每个存储单元包括一个晶体管和一个电容器，晶体管作为电容器和位线之间的开关，并可以被耦合到晶体管的控制端的字线激活，存储单元能够将二进制信息存储为电容器上的电荷。并且感测放大器与存储单元连接，能够对存储单元中存储的微弱信号进行放大，使得存储单元中存储的数据可以被正确的写入或者读出。
但是在存储器存储阵列的制造过程中，由工艺原因导致相邻存储单元的电容容易同时产生缺陷，称为两比特错误(2 bits error)。
DRAM可通过检错纠错电路(Error Correcting Code，ECC)来纠正存储器中的数据错误，但ECC只能纠正一比特错误(1 bit error)，而上述两比特错误超出了ECC的纠错能力。
发明内容
第一方面，本申请实施例提供了一种列选择信号单元电路，包括：第一列选择单元、第二列选择单元、第三列选择单元和第四列选择单元，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口；其中，所述第一列选择单元和所述第四列选择单元的控制端口电连接于第一列选择信号，所述第二列选择单元和所述第三列选择单元的控制端口电连接于第二列选择信号，所述第一列选择单元和所述第三列选择单元的位线连接端口分别与第一存储单元组的8*N条位线连接，所述第二列选择单元和所述第四列选择单元的位线连接端口分别与第二存储单元组的8*N条位线连接，所述第一存储单元组和所述第二存储单元组相邻设置，所述N为大于等于1的整数。
第二方面，本申请实施例还提供了一种列选择信号单元电路，包括：第五列选择单元、第六列选择单元、第七列选择单元和第八列选择单元，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口；其中，所述第五列选择单元电连接于第一列选择信号，所述第六列选择单元和所述第七 列选择单元的控制端口电连接于第二列选择信号，第八列选择单元电连接于第三列选择信号，所述第五列选择单元的位线连接端口分别与第一存储单元组的4*N条位线连接，所述第六列选择单元的位线连接端口分别与第二存储单元组的4*N条位线连接，所述第七列选择单元的位线连接端口分别与第一存储单元组的4*N条位线连接，所述第八列选择单元的位线连接端口分别与第二存储单元组的4*N条位线连接，所述第一存储单元组和所述第二存储单元组相邻设置，所述N为大于等于1的整数。
第三方面，本申请实施例还提供了一种位线感测电路，包括：L个存储单元组，每个所述存储单元组包括H条位线，所述L和所述H均为大于等于2的正整数；M个感测放大器组，被配置为向所述存储单元组中的位线写入存储数据或从所述存储单元组中的位线读出存储数据，所述M个感测放大器组与所述L个存储单元组电连接，所述M为所述L的整数倍或所述L为所述M的整数倍；所述感测放大器组包括本申请任意实施例所述的列选择信号单元电路；其中，所述H条位线中的相邻两条位线连接到不同的所述感测放大器组。
第四方面，本申请实施例提供了一种存储器，所述存储器包括任一实施例中的位线感测电路；每个所述存储单元组还包括1条字线，所述1条字线和所述H条位线还对应的H个晶体管和H个电容，所述1条字线控制所述H个晶体管的开启或关断，所述H条位线与对应的所述H个晶体管的第一端连接，所述H个晶体管的第二端与对应的所述H个电容的第一端连接，所述H个电容的第二端接一固定电压。
附图说明
图1是本申请实施例提供的一种位线感测电路存储阵列的电路示意图；
图2是本申请实施例提供的一种位线感测电路存储阵列的结构示意图；
图3是图2中区域A的局部放大示意图；
图4是图1中区域A的局部放大示意图；
图5是本申请实施例提供的另一种位线感测电路的结构示意图；
图6是本申请实施例提供的一种位线感测电路的对比实施例的结构示意图；
图7是本申请实施例提供的另一种位线感测电路的结构示意图；
图8是本申请实施例提供的另一种位线感测电路的结构示意图；
图9是本申请实施例提供的另一种位线感测电路的结构示意图；
图10是本申请实施例提供的一种第一感测放大器或第二感测放大器的结构示意图；
图11是本申请实施例提供的一种列选择信号单元电路的结构示意图；
图12是本申请实施例提供的另一种列选择信号单元电路的结构示意图；
图13是本申请实施例提供的存储器示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
在本申请的一些实施例中，存储器包括存储单元阵列，存储单元阵列包括沿字线方向和位线方向排布的存储单元，连接到同一字线的存储单元，每相邻多位存储单元形成存储单元组，例如相邻的8个存储单元形成1个存储单元组。字线和位线相交设置，每条字线与对应的一行存储单元连接以开启该行存储单元，每条位线与对应的一列存储单元连接以写入或读取数据。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种列选择信号单元电路，如图11所示，图11是本申请实施例提供的一种列选择信号单元电路的结构示意图，列选择信号单元电路包括：
第一列选择单元1411、第二列选择单元1412、第三列选择单元1413和第四列选择单元1414，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口。其中，第一列选择单元1411和第四列选择单元1414的控制端口电连接于第一列选择信号，第二列选择单元1412和第三列选择单元1413的控制端口电连接于第二列选择信号；第一列选择单元1411和第三列选择单元1413的位线连接端口分别与第一存储单元组15的8*N条位线连接，第二列选择单元1412和第四列选择单元1414的位线连接端口分别与第二存储单元组16的8*N条位线连接；第一存储单元组15和第二存储单元组16相邻设置；N为大于等于1的整数。
本申请实施例中列选择信号单元电路包括四种列选择单元：第一列选择单元1411、第二列选择单元1412、第三列选择单元1413和第四列选择单元 1414。每个列选择单元可以包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口，4*N个位线连接端口分别连接存储单元组中的4*N条位线，4*N个输入输出端口与4*N个位线连接端口一一对应，能够输出对应位线连接端口从对应位线获取的读取数据，或者通过对应位线连接端口向位线写入数据。控制端口能够控制4*N个输入输出端口和4*N个位线连接端口是否进行读取或写入的工作。示例性的，每个列选择单元可以包括4*N个开关管T1，上述N可取值为1，则每个列选择单元可以包括4个开关管T1，每个开关管T1的第一端作为位线连接端口，第二端作为输入输出端口，4个开关管T1的控制端相互连接形成一个控制端口，能够接收控制开关管T1导通或关断的列选择信号。
如图11所示，本申请实施例中，第一列选择单元1411和第四列选择单元1414的控制端口电连接于第一列选择信号CSL<n+1>，第二列选择单元1412和第三列选择单元1413的控制端口电连接于第二列选择信号CSL<n>，则第一列选择单元1411和第四列选择单元1414同时工作，第二列选择单元1412和第三列选择单元1413同时工作。并且，第一列选择单元1411和第三列选择单元1413的位线连接端口分别与第一存储单元组15的8*N条位线连接，则第一存储单元组15中的位线连接不同的感测放大器组(同一感测放大器组中的列选择单元连接相同的列选择信号)，则当相邻两条位线同时出现读取错误时，错误数据可以被不同的感测放大器组检测到，便于锁定出现错误的两条位线，进而锁定第一存储单元组15中出现错误的两个存储单元。同理，第二列选择单元1412和第四列选择单元1414的位线连接端口分别与第二存储单元组16的8*N条位线连接，便于锁定第二存储单元组16中出现错误的两个存储单元。本申请提供的技术方案，在不改变现有ECC纠错能力的情况下，实现了对存储器中的相邻两比特错误的检测和纠正，提高了存储器性能。本申请实施中，第一存储单元组15和第二存储单元组16相邻设置，一般情况下，每个存储单元组包含8条位线，则N可取值为1，当然，N还可以为2，3等其他数值，本申请实施例对此不进行限定。
在本申请的一些实施例中，第一存储单元组15中编号为偶数的位线连接 于第一列选择单元1411的位线连接端口，第一存储单元组15中编号为奇数的位线连接于第三列选择单元1413的位线连接端口；第二存储单元组16中编号为偶数的位线连接于第二列选择单元1412的位线连接端口，第二存储单元组16中编号为奇数的位线连接于第四列选择单元1414的位线连接端口。
继续参考图11，可控制第一列选择单元1411的位线连接端口连接第一存储单元组15中编号为偶数的位线，第三列选择单元1413的位线连接端口连接第一存储单元组15中编号为奇数的位线。如图11所示，第一存储单元组15中位线标号从始端到末端依次为BL<0>～BL<7>，第一列选择单元1411的位线连接端口分别连接BL<0>、BL<2>、BL<4>和BL<6>，第三列选择单元1413的位线连接端口分别连接BL<1>、BL<3>、BL<5>和BL<7>，则位线BL<0>～BL<7>中，每相邻两个位线之间的错误均能够被定位并纠正，进一步提高存储器的纠错性能。同理，第二存储单元组16中位线标号从始端到末端依次为BL<8>～BL<15>，第二列选择单元1412的位线连接端口分别连接BL<8>、BL<10>、BL<12>和BL<14>，第四列选择单元1414的位线连接端口分别连接BL<9>、BL<11>、BL<13>和BL<15>，则位线BL<8>～BL<15>中，每相邻两个位线之间的错误均能够被定位并纠正。
在本申请的一些实施例中，第一列选择单元1411和第二列选择单元1412并排设置；第三列选择单元1413和第四列选择单元1414并排设置；第一列选择单元1411和第三列选择单元1413设置于第一存储单元组15的相对两侧；第二列选择单元1412和第四列选择单元1414设置于第二存储单元组16的相对两侧。
继续参考图11，第一列选择单元1411和第二列选择单元1412并排设置，位于存储单元的第一侧，第三列选择单元1413和第四列选择单元1414并排设置，位于储单元与第一侧相对的第二侧，并且第一列选择单元1411和第三列选择单元1413设置于第一存储单元组15的相对两侧，便于连接第一存储单元组15的位线，第二列选择单元1412和第四列选择单元1414设置于第二存储单元组16的相对两侧，便于连接第二存储单元组16的位线。也即，同一感测放大器组(连接同一控制端口)的两个列选择单元交叉设置，各列选 择单元靠近所连位线所处的存储单元组设置，便于简化列选择单元的布线。
在本申请的一些实施例中，第一列选择单元1411和第二列选择单元1412共用2*N个输入输出端口；第三列选择单元1413和第四列选择单元1414共用2*N个输入输出端口。
继续参考图11，并排设置的第一列选择单元1411和第二列选择单元1412可共用2*N个输入输出端口，每个输入输出端口上连接两个开关管T1。当N为1时，第一列选择单元1411和第二列选择单元1412可共用2个输入输出端口，如图11所示，第一列选择单元1411中连接位线BL<4>的开关管T1与第二列选择单元1412中连接位线BL<10>的开关管T1相互连接，共用一个输入输出端口IO<2>,此外，第一列选择单元1411和第二列选择单元1412还共用了输入输出端口IO<3>。同理，并排设置的第三列选择单元1413和第四列选择单元1414共用了输入输出端口IO<6>和IO<7>。本申请实施中相邻两个列选择单元共用输入输出端口的设置能够简化列选择信号单元电路的制作工艺，并节约制作成本。
本申请实施例还提供了一种列选择信号单元电路，如图12所示，图12是本申请实施例提供的一种列选择信号单元电路的结构示意图，列选择信号单元电路包括：
第五列选择单元1415、第六列选择单元1416、第七列选择单元1417和第八列选择单元1418，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口。其中，第五列选择单元1415电连接于第一列选择信号，第六列选择单元1416和第七列选择单元1417的控制端口电连接于第二列选择信号，第八列选择单元1418电连接于第三列选择信号；第五列选择单元1415的位线连接端口分别与第一存储单元组15的4*N条位线连接，第六列选择单元1416的位线连接端口分别与第二存储单元组16的4*N条位线连接，第七列选择单元1417的位线连接端口分别与第一存储单元组15的4*N条位线连接，第八列选择单元1418的位线连接端口分别与第二存储单元组16的4*N条位线连接；第一存储单元组15和第二存储单元组16相邻设置；N为大于等于1的整数。
本申请实施中列选择信号单元电路包括四种列选择单元：第五列选择单元1415、第六列选择单元1416、第七列选择单元1417和第八列选择单元1418。每个列选择单元可以包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口，4*N个位线连接端口分别连接存储单元组中的4*N条位线，4*N个输入输出端口与4*N个位线连接端口一一对应，能够输出对应位线连接端口从对应位线获取的读取数据，或者通过对应位线连接端口向位线写入数据。控制端口能够控制4*N个输入输出端口和4*N个位线连接端口是否进行读取或写入的工作。示例性的，每个列选择单元可以包括4*N个开关管T1，上述N可取值为1，则每个列选择单元可以包括4个开关管T1，每个开关管T1的第一端作为位线连接端口，第二端作为输入输出端口，4个开关管T1的控制端相互连接形成一个控制端口，能够接收控制开关管T1导通或关断的列选择信号。
如图12所示，本申请实施例中，第五列选择单元1415电连接于第一列选择信号CSL<n+1>，第六列选择单元1416和第七列选择单元1417的控制端口电连接于第二列选择信号CSL<n-1>，第八列选择单元1418的控制端口电连接于第三列选择信号CSL<n>，则在上述四个列选择单元中，第五列选择单元1415首单独进行工作，第六列选择单元1416和第七列选择单元1417同时进行工作，第八列选择单元1418单独进行工作。并且，第五列选择单元1415和第七列选择单元1417的位线连接端口分别与第一存储单元组15的8*N条位线连接，同理，第六列选择单元1416和第八列选择单元1418的位线连接端口分别与第二存储单元组16的8*N条位线连接，则第一存储单元组15中的位线连接不同的感测放大器组(同一感测放大器组中的列选择单元连接相同的列选择信号)，第二存储单元组16中的位线连接不同的感测放大器组，当第一存储单元组15或第二存储单元组16中相邻两条位线同时出现读取错误时，错误数据可以被不同的感测放大器组检测到，便于锁定出现错误的两条位线，进而锁定第一存储单元组15中出现错误的两个存储单元。本申请提供的技术方案，在不改变现有ECC纠错能力的情况下，实现了对存储器中的相邻两比特错误的检测和纠正，提高了存储器性能。本申请实施中，第一存 储单元组15和第二存储单元组16相邻设置，一般情况下，每个存储单元组包含8条位线，则N可取值为1，当然，N还可以为2，3等其他数值，本申请实施例对此不进行限定。
在本申请的一些实施例中，第一存储单元组15中编号为偶数的位线连接于第五列选择单元1415的位线连接端口，第一存储单元组15中编号为奇数的位线连接于第七列选择单元1417的位线连接端口；第二存储单元组16中编号为偶数的位线连接于第六列选择单元1416的位线连接端口，第二存储单元组16中编号为奇数的位线连接于第八列选择单元1418的位线连接端口。
继续参考图12，可控制第五列选择单元1415的位线连接端口连接第一存储单元组15中编号为偶数的位线，第七列选择单元1417的位线连接端口连接第一存储单元组15中编号为奇数的位线。第一存储单元组15中位线标号从始端到末端依次为BL<0>～BL<7>，第五列选择单元1415的位线连接端口分别连接BL<0>、BL<2>、BL<4>和BL<6>，第七列选择单元1417的位线连接端口分别连接BL<1>、BL<3>、BL<5>和BL<7>，则位线BL<0>～BL<7>中，每相邻两个位线之间的错误均能够被定位并纠正，进一步提高存储器的纠错性能。同理，第二存储单元组16中位线标号从始端到末端依次为BL<8>～BL<15>，第六列选择单元1416的位线连接端口分别连接BL<8>、BL<10>、BL<12>和BL<14>，第八列选择单元1418的位线连接端口分别连接BL<9>、BL<11>、BL<13>和BL<15>，则位线BL<8>～BL<15>中，每相邻两个位线之间的错误均能够被定位并纠正。
在本申请的一些实施例中，第五列选择单元1415和第六列选择单元1416并排设置；第七列选择单元1417和第八列选择单元1418并排设置；第五列选择单元1415和第七列选择单元1417设置于第一存储单元组15的相对两侧；第六列选择单元1416和第八列选择单元1418设置于第二存储单元组16的相对两侧。
继续参考图12，第五列选择单元1415和第六列选择单元1416并排设置，位于存储单元的第一侧，第七列选择单元1417和第八列选择单元1418并排设置，位于储单元与第一侧相对的第二侧，并且第五列选择单元1415和第七 列选择单元1417设置于第一存储单元组15的相对两侧，便于连接第一存储单元组15的位线，第六列选择单元1416和第八列选择单元1418设置于第二存储单元组16的相对两侧，便于连接第二存储单元组16的位线。也即，同一感测放大器组(连接同一控制端口)的两个列选择单元在第一存储单元组15和第二存储单元组16等的排布方向上(存储单元阵列的字线方向上)均错开至少一个存储单元组，各列选择单元靠近所连位线所处的存储单元组设置，便于简化列选择单元的布线。
在本申请的一些实施例中，第五列选择单元1415和第六列选择单元1416共用2*N个输入输出端口；第七列选择单元1417和第八列选择单元1418共用2*N个输入输出端口。
继续参考图12，并排设置的第五列选择单元1415和第六列选择单元1416可共用2*N个输入输出端口，每个输入输出端口上连接两个开关管T1。当N为1时，第五列选择单元1415和第六列选择单元1416可共用2个输入输出端口，如图12所示，第五列选择单元1415中连接位线BL<4>的开关管T1与第六列选择单元1416中连接位线BL<10>的开关管T1相互连接，共用一个输入输出端口IO<2>,此外，第五列选择单元1415和第六列选择单元1416还共用了输入输出端口IO<3>。同理，并排设置的第七列选择单元1417和第八列选择单元1418共用了输入输出端口IO<6>和IO<7>。本申请实施中相邻两个列选择单元共用输入输出端口的设置能够简化列选择信号单元电路的制作工艺，并节约制作成本。
在上述实施例的基础上，本申请实施例还提供了一种位线感测电路，包括：
L个存储单元组，每个所述存储单元组包括H条位线，所述L和所述H均为大于等于2的正整数；M个感测放大器组，被配置为向所述存储单元组中的位线写入存储数据或从所述存储单元组中的位线读出存储数据，所述M个感测放大器组与所述L个存储单元组电连接，所述M为所述L的整数倍或所述L为所述M的整数倍；所述感测放大器组包括本申请任意实施例所述的列选择信号单元电路；其中，所述H条位线中的相邻两条位线连接到不同的 所述感测放大器组。
图1是本申请实施例提供的一种位线感测电路存储阵列的电路示意图，如图1所示，位线感测电路包括沿字线方向X和位线方向Y排布的存储单元阵列，存储单元阵列包括多个存储单元11。位线感测电路还包括多条字线12和多条位线13，字线12沿字线方向X延伸，每条字线12对应存储单元11。字线12用于开启对应的存储单元11，位线13沿位线线方向Y延伸，每条位线13与对应的存储单元11连接，以对相对应的存储单元11写入或读取数据。上述多条字线12和多条位线13交叉限定出各个存储单元11的区域，示例性的，如图1所示，图1中位线感测电路示出了沿位线方向Y依次排布的6条字线WL0～WL5和沿字线方向X依次排布的16条位线BL0～BL15，其交叉限定出各个存储单元11。本申请实施例中，可限定连接到同一字线12的存储单元11，每相邻n位存储单元11组成一个存储单元组，n为大于1的整数，例如，在通过位线感测电路实现数据存储时，往往每8位存储单元进行一个数据的存储，所以本申请实施例可限定每相邻8位存储单元11组成一个存储单元组，便于进行检测和放大处理。也即，每行存储单元11中每相邻8位存储单元11组成一个存储单元组。需要注意的是，每行存储单元指的是排布方向沿字线方向X的延伸方向依次排布的存储单元11，各个存储单元可以呈直接排布，也可以呈曲线排布。
图2是本申请实施例提供的一种位线感测电路存储阵列的结构示意图，图1中仅对各个存储单元进行简化图示，以电路符号的形式呈现，而图2则以电路版图的形式呈现。实际位线感测电路的制作过程中，其结构示意图如图2所示，可知图1中示出的相邻的两个存储单元实际上并不是连接在同一字线或同一位线。在图2中，在Y方向上，相邻两个存储单元实际上连接相邻的两条位线上，例如A区域上部的存储单元连接位线BL1，而在Y方向上其相邻的存储单元连接位线BL2，再例如B区域的存储单元B1连接到位线BL2，B区域的存储单元B2连接到位线BL3，存储单元B1和存储单元B2为Y方向的相邻存储单元。如图3和图4所示，图3是图2中区域A的局部放大示意图，图4是图1中区域A的局部放大示意图，图4中连接同一条位线 BL1的相邻设置的两个存储单元11。
如图4所示，在本申请的一些实施例中，每个存储单元11可以包括一个第二晶体管T2和一个电容器C1；第二晶体管T2包括控制端、第一端和第二端；第二晶体管T2的控制端与对应的字线12即WL1连接，用于在字线12上电平的控制下导通和关断；第二晶体管T2的第一端与对应的位线13连接，第二晶体管T2的第二端与所处存储单元11的电容器C1连接，用于在导通状态下，将位线13与电容器C1连接，从而将位线13上的数据写入电容器C1中，或者读取电容器C1中存储的数据传到位线13。如图3和图4所示，存储单元11通过BLC(Bit Line Contact，位线接触孔)连接在位线BL1上。
如图5所示，本申请实施例提供了一种位线感测电路，包括：L个存储单元组15，每个所述存储单元组15包括H条位线13，所述L和所述H均为大于等于2的正整数；M个感测放大器组14，被配置为向所述存储单元组15中的位线写入存储数据或从所述存储单元组15中的位线读出存储数据，所述M个感测放大器组14与所述L个存储单元组15电连接，所述M为所述L的整数倍或所述L为所述M的整数倍；其中，所述H条位线中的相邻两条位线连接到不同的所述感测放大器组14。
在本申请的一些实施例中，所述H为8的整数倍，所述M等于所述L，在一种实施例中，将以H等于8，M和L均等于2为例。
在本申请的一些实施例中，每个所述感测放大器组14均包括第一感测放大器14a和第二感测放大器14b；所述L个存储单元组15沿字线12方向并排设置，所述字线12与所述位线13垂直；所述第一感测放大器14a位于所述存储单元组15的一侧，所述第二感测放大器14b位于所述存储单元组15的相对的另一侧。
图5是本申请实施例提供的一种位线感测电路的结构示意图，如图5所示，位线感测电路还包括多个感测放大器组14，每个感测放大器组14对应多条位线13，并且感测放大器组14与对应的多条位线13连接，从而对位线13所连接的存储单元11存储的数据进行放大处理。以图5为例，感测放大器组Sense Amplifier<n>对应8条位线13(BL2、BL4、BL6、BL8、BL9、BL11、 BL13和BL15)，并与对应的8条位线13连接；感测放大器组Sense Amplifier<n-1>对应另外8条位线13(BL1、BL3、BL5、BL7、BL10、BL12、BL14和BL16)，并与对应的另外8条位线13连接。以图5为例，存储单元组15对应的8条位线13(BL9～BL16)中，每相邻两条位线13连接到不同的感测放大器组14，如图5所示，存储单元组15对应的BL10、BL12、BL14、BL16连接到感测放大器组Sense Amplifier<n-1>，而BL9、BL11、BL13、BL15连接到感测放大器组Sense Amplifier<n>。如此设置，当存储单元组15中出现相邻两位错误数据时，例如BL10和BL11同时出错，上述两位错误数据连接不同的感测放大器组14。以DRAM为例，在DRAM读取时，是以敏感放大器组14为单位进行的，例如敏感放大器组Sense Amplifier<n-1>一次性读取8bit(BL1、BL3、BL5、BL7、BL10、BL12、BL14、BL16)，然后敏感放大器组Sense Amplifier<n-1>将输出数据送到ECC模块或经过其他处理电路后送到ECC模块，ECC具有检测和纠正一比特错误的能力。那么当出现相邻两比特错误时，因为相邻两条位线连接到不同的敏感放大器组，就可以将两比特错误分两次读取，一次只读取一比特错误，这样每次一比特错误都可以被检测和纠正，从而使得相邻两比特错误被检测和纠正。
图6是本申请实施例提供的一种位线感测电路的对比实施例的结构示意图，在对比实施例中，存储单元组15’对应的BL9、BL10、BL11、BL12、BL13、BL14、BL15、BL16均连接到感测放大器组Sense Amplifier<n>。当出现相邻两比特错误时，例如BL10和BL11同时出错，上述两位错误数据都连接到感测放大器组Sense Amplifier<n>。以DRAM为例，在DRAM读取时，是以敏感放大器组14为单位进行的，例如敏感放大器组Sense Amplifier<n>一次性读取8bit(BL9、BL10、BL11、BL12、BL13、BL14、BL15、BL16)，然后敏感放大器组Sense Amplifier<n>将输出数据送到ECC模块或经过其他处理电路后送到ECC模块，ECC具有检测和纠正一比特错误的能力。那么当出现相邻两比特错误时，就超出了现有ECC的检测和纠正能力，从而导致DRAM读取错误。
继续参考图5，在本申请的一些实施例中，每个感测放大器组14均可以 包括第一感测放大器14a和第二感测放大器14b；第一感测放大器14a位于存储单元阵列沿字线方向X上的第一侧；第二感测放大器14b位于存储单元阵列沿字线方向X上与第一侧相对的第二侧。所述第一感测放大器与所述第二感测放大器均连接P条所述位线，所述H为所述P的正偶数倍，例如，Sense Amplifier<n>的第一感测放大器14a连接到BL9、BL11、BL13、BL15共4条位线，Sense Amplifier<n>的第二感测放大器14b连接到BL2、BL4、BL6、BL8共4条位线。
为了防止感测放大器组14与位线13连接的输入端设置过于密集，可将感测放大器组14分为两部分：第一感测放大器14a和第二感测放大器14b，第一感测放大器14a和第二感测放大器14b分别设置于存储单元阵列字线方向X的的相对两侧。第一感测放大器14a设置于存储单元阵列的第一侧，第二感测放大器14b设置于存储单元阵列的第二侧，第一感测放大器14a连接感测放大器组14(Sense Amplifier<n-1>)对应的一半位线，例如BL1、BL3、BL5、BL7，第二感测传感器14b连接感测放大器组14(Sense Amplifier<n-1>)对应的另一半位线，例如BL10、BL12、BL14、BL16。再例如，如图5所示，感测放大器组Sense Amplifier<n>的第一感测放大器14a连接位线BL2、BL4、BL6和BL8四条位线13，感测放大器组Sense Amplifier<n>的第二感测放大器14b连接位线BL9、BL11、BL13和BL15四条位线13。
在本申请的一些实施例中，继续参考图5，在沿字线方向X上，每个感测放大器组14的第一感测放大器14a和第二感测放大器14b的错开设置，便于每个感测放大器组14的第一感测放大器14a和第二感测放大器14b连接不同存储单元组的位线13。参考图5，例如Sense Amplifier<n>的第一感测放大器14a连接到BL9、BL11、BL13、BL15共4条位线，Sense Amplifier<n>的第二感测放大器14b连接到BL2、BL4、BL6、BL8共4条位线，将Sense Amplifier<n>的第一感测放大器14a和第二感测放大器14b投影到字线WL0上，二者不重叠，即沿字线方向X上错开设置；Sense Amplifier<n-1>的第一感测放大器14a和第二感测放大器14b投影到字线WL0上，二者也不重叠，即沿字线方向X上错开设置。
在本申请的一些实施例中，继续参考图5，感测放大器组14的个数与每行中存储单元组的个数可以相同；每个感测放大器组14的第一感测放大器14a与对应存储单元组的位线中的奇数列或偶数列连接，每个感测放大器组14的第二感测放大器14b与每行中对应存储单元组的位线中的偶数列或奇数列连接；在同一行存储单元组中，每个感测放大器组14的第一感测放大器14a对应的存储单元组，与第二感测放大器14b对应的存储单元组不同。
如图5所示，在每行存储单元中，某一存储单元组16对应位线BL1～BL8，另一存储单元组15对应位线BL9～BL16，感测放大器组14的个数与每行中存储单元组的个数可以相同，感测放大器组14的第一感测放大器14a可与对应存储单元组的位线中的奇数列连接，则第二感测放大器14b与对应存储单元组的位线中的偶数列连接，或者，感测放大器组14的第一感测放大器14a可与对应存储单元组的位线中的偶数列连接，则第二感测放大器14b与对应存储单元组的位线中的奇数列连接。需要注意的是，每个感测放大器组14的第一感测放大器14a连接的存储单元组与第二感测放大器14b连接的存储单元组是不同的，从而将相邻2比特错误传输到不同的感测放大器组中，例如Sense Amplifier<n>的第一感测放大器14a的连接到存储单元组15，Sense Amplifier<n>的第二感测放大器14b的连接到存储单元组16。示例性的，感测放大器组Sense Amplifier<n-1>的第一感测放大器14a与一存储单元组对应位线BL2、BL4、BL6和BL8连接，感测放大器组Sense Amplifier<n-1>的第二感测放大器14b与另一存储单元组对应位线BL9、BL11、BL13和BL15连接。
参考图7，图7是本申请实施例提供的另一种位线感测电路的结构示意图，在本申请的一些实施例中，在沿字线方向X上，第一感测放大器14a设置于存储单元阵列的第一侧，并顺序设置，例如依次设置Sense Amplifier<n-2>、Sense Amplifier<n-1>、Sense Amplifier<n>、Sense Amplifier<n+1>；第二感测放大器14b设置于与第一侧相对位置的第二侧，并顺序设置，例如依次设置Sense Amplifier<n-1>、Sense Amplifier<n>、Sense Amplifier<n+1>、Sense Amplifier<n+2>。同一感测放大器组14，例如Sense Amplifier<n>，包括的第一感测放大器和第二放大器在字线方向X上仍然错开设置。
继续参考图7，在本申请的一些实施例中，第n个感测放大器组14的第一感测放大器14a连接沿字线方向X上第n个存储单元组的位线中的奇数列或偶数列；第n+i个感测放大器组14的第二感测放大器14b连接沿字线方向X上第n个存储单元组所连位线中的偶数列或奇数列。其中，n和i均为整数，例如i为1时则如图7所示，需要注意的是，i也可以为2或3或其他整数，在此不做限制。
继续参考图7，沿字线方向X上，可使得第n个感测放大器组14的第一感测放大器14a连接第n个存储单元组的位线的奇数列或偶数列，第n+1个感测放大器组14的第二感测放大器14b连接第n个存储单元组的位线的偶数列或奇数列。每个感测放大器组14的第一感测放大器14a和第二感测放大器14b在沿字线方向X上错开设置。例如，感测放大器组Sense Amplifier<n>的第一感测放大器14a与感测放大器组Sense Amplifier<n>的第二感测放大器14b在沿字线方向x上不重叠，即错开设置。
如图8所示，图8是本申请实施例提供的另一种位线感测电路的结构示意图，在本申请的一些实施例中，第n个感测放大器组14的第一感测放大器14a连接沿字线方向上第n-1个存储单元组的位线中的奇数列或偶数列；第n-1个感测放大器组14的第二感测放大器14b连接沿字线方向上第n-1个存储单元组的位线中的偶数列或奇数列；第n个感测放大器组14的第二感测放大器14b连接沿字线方向X上第n个存储单元组的位线中的偶数列或奇数列；第n-1个感测放大器组14的第一感测放大器14a连接沿字线方向X上第n个存储单元组的位线中的奇数列或偶数列；其中n为正整数。例如，Sense Amplifier<n>的第一感测放大器14a与第n-1个存储单元组的偶数列(BL2、BL4、BL6和BL8)连接，Sense Amplifier<n-1>的第二感测放大器14b与第n-1个存储单元组的奇数列(BL1、BL3、BL5和BL7)连接；Sense Amplifier<n>的第二感测放大器14b与第n个存储单元组的奇数列(BL9、BL11、BL13和BL15)连接，Sense Amplifier<n>的第一感测放大器14a与第n个存储单元组的偶数列(BL10、BL12、BL14和BL16)连接。
图9是本申请实施例提供的另一种位线感测电路的结构示意图，在本申 请的一些实施例中，如图9所示，沿位线方向Y上，依次设置有多个存储单元阵列AA；沿位线方向Y上，每个存储单元阵列AA的相对两侧分别设置有第一感测放大器14a和第二感测放大器14b；沿位线方向Y上，第t个存储单元阵列AA的第一感测放大器14a可复用为第t+1个存储单元阵列AA的第二感测放大器14a，例如图9中的感测放大器组Sense Amplifier<n>的第一感测放大器14a中有8个敏感放大器，其中4个敏感放大器与其上方存储单元阵列AA区的4条位线连接，另外4个敏感放大器与其下方存储单元阵列AA区的4条位线连接，Sense Amplifier<n>的第一感测放大器14a作为一个整体可以被其上下两个存储单元阵列AA进行复用；第t+1个存储单元阵列AA的第一感测放大器14a复用为第t+2个存储单元阵列AA的第二感测放大器14b；t为正整数。
图10是本申请实施例提供的一种第一感测放大器或第二感测放大器的结构示意图，图11和图12是本申请实施例提供的一种列选择单元的结构示意图。在本申请的一些实施例中，第一感测放大器与第二感测放大器均包括列选择单元141(图10中以CSL<n>表示)和敏感放大器142(图10中以Amplifier表示)；列选择单元141可以包括控制端、第一端和第二端；列选择单元141的第一端与对应的敏感放大器142电连接，列选择单元141的第二端连接于其他电路，例如第二级敏感放大器或转换电路，列选择单元141的控制端连接于译码电路。列选择单元141可以包括第一晶体管T1；每个第一晶体管T1包括控制端、第一端和第二端。以图10为例，列选择单元141包括4个第一晶体管T1，每一个晶体管T1均与敏感放大器142连接。再例如，若每个存储单元组包括8个存储单元，列选择单元141设置有与对应存储单元组的4条位线一一对应的第一端或敏感放大器142的4个输入输出端连接，被配置为控制敏感放大器142的数据的输入输出。
示例性的，还提供一种存储器，参考图1、图2、图3、图4和图13，包括本申请任意实施例提供的位线感测电路的技术特征，具备技术特征所具备的有益效果。每个所述存储单元组还包括1条字线，所述1条字线和所述H条位线还对应的H个晶体管和H个电容，所述1条字线控制所述H个晶体管 的开启或关断，所述H条位线与对应的所述H个晶体管的第一端连接，所述H个晶体管的第二端与对应的所述H个电容的第一端连接，所述H个电容的第二端接一固定电压。其中H为8的整数，M和所述L均为2。
示例性的，继续参考图11，还包括检错纠错电路(ECC)，与所述感测放大器组(Sense Amplifier)连接，被配置为检测所述感测放大器组输出的所述存储数据的正确性，并纠正错误的所述存储数据。本申请实施例在不改变现有ECC纠错能力的情况下，实现了对存储器中的两比特错误的检测和纠正，提高了存储器性能。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。
工业实用性
本申请实施例提供一种列选择信号单元电路、位线感测电路及存储器，列选择信号单元电路包括：第一列选择单元、第二列选择单元、第三列选择单元和第四列选择单元，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口；第一列选择单元和第四列选择单元的控制端口接第一列选择信号，第二列选择单元和第三列选择单元的控制端口接第二列选择信号，第一列选择单元和第三列选择单元的位线连接端口连接第一存储单元组的8*N条位线，第二列选择单元和第四列选择单元的位线连接端口连接第二存储单元组的8*N条位线，第一存储单元组和第二存储单元组相邻设置。
本申请提供的技术方案，使得相邻两条位线连接到不同的感测放大器组，当相邻两条位线同时出现读取错误时，错误数据可以被检错纠错电路检测和纠正。本申请提供的技术方案，在不改变现有ECC纠错能力的情况下，实现 了对存储器中的两比特错误的检测和纠正，提高了存储器性能。

Claims (24)

  1. 一种列选择信号单元电路，包括：
    第一列选择单元、第二列选择单元、第三列选择单元和第四列选择单元，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口；其中，所述第一列选择单元和所述第四列选择单元的控制端口电连接于第一列选择信号，所述第二列选择单元和所述第三列选择单元的控制端口电连接于第二列选择信号，所述第一列选择单元和所述第三列选择单元的位线连接端口分别与第一存储单元组的8*N条位线连接，所述第二列选择单元和所述第四列选择单元的位线连接端口分别与第二存储单元组的8*N条位线连接，所述第一存储单元组和所述第二存储单元组相邻设置，所述N为大于等于1的整数。
  2. 根据权利要求1所述的列选择信号单元电路，其中，所述第一存储单元组中编号为偶数的位线连接于所述第一列选择单元的位线连接端口，所述第一存储单元组中编号为奇数的位线连接于所述第三列选择单元的位线连接端口；
    所述第二存储单元组中编号为偶数的位线连接于所述第二列选择单元的位线连接端口，所述第二存储单元组中编号为奇数的位线连接于所述第四列选择单元的位线连接端口。
  3. 根据权利要求2所述的列选择信号单元电路，其中，所述第一列选择单元和所述第二列选择单元并排设置；
    所述第三列选择单元和所述第四列选择单元并排设置；
    所述第一列选择单元和所述第三列选择单元设置于所述第一存储单元组的相对两侧；
    所述第二列选择单元和所述第四列选择单元设置于所述第二存储单元组的相对两侧。
  4. 根据权利要求3所述的列选择信号单元电路，其中，所述第一列选择 单元和所述第二列选择单元共用2*N个所述输入输出端口；
    所述第三列选择单元和所述第四列选择单元共用2*N个所述输入输出端口。
  5. 一种列选择信号单元电路，包括：
    第五列选择单元、第六列选择单元、第七列选择单元和第八列选择单元，均包括4*N个输入输出端口、4*N个位线连接端口和一个控制端口；其中，所述第五列选择单元电连接于第一列选择信号，所述第六列选择单元和所述第七列选择单元的控制端口电连接于第二列选择信号，第八列选择单元电连接于第三列选择信号，所述第五列选择单元的位线连接端口分别与第一存储单元组的4*N条位线连接，所述第六列选择单元的位线连接端口分别与第二存储单元组的4*N条位线连接，所述第七列选择单元的位线连接端口分别与第一存储单元组的4*N条位线连接，所述第八列选择单元的位线连接端口分别与第二存储单元组的4*N条位线连接，所述第一存储单元组和所述第二存储单元组相邻设置，所述N为大于等于1的整数。
  6. 根据权利要求5所述的列选择信号单元电路，其中，所述第一存储单元组中编号为偶数的位线连接于所述第五列选择单元的位线连接端口，所述第一存储单元组中编号为奇数的位线连接于所述第七列选择单元的位线连接端口；
    所述第二存储单元组中编号为偶数的位线连接于所述第六列选择单元的位线连接端口，所述第二存储单元组中编号为奇数的位线连接于所述第八列选择单元的位线连接端口。
  7. 根据权利要求6所述的列选择信号单元电路，其中，所述第五列选择单元和所述第六列选择单元并排设置；
    所述第七列选择单元和所述第八列选择单元并排设置；
    所述第五列选择单元和所述第七列选择单元设置于所述第一存储单元组的相对两侧；
    所述第六列选择单元和所述第八列选择单元设置于所述第二存储单元组的相对两侧。
  8. 根据权利要求7所述的列选择信号单元电路，其中，所述第五列选择单元和所述第六列选择单元共用2*N个所述输入输出端口；
    所述第七列选择单元和所述第八列选择单元共用2*N个所述输入输出端口。
  9. 一种位线感测电路，包括：
    L个存储单元组，每个所述存储单元组包括H条位线，所述L和所述H均为大于等于2的正整数；
    M个感测放大器组，被配置为向所述存储单元组中的位线写入存储数据或从所述存储单元组中的位线读出存储数据，所述M个感测放大器组与所述L个存储单元组电连接，所述M为所述L的整数倍或所述L为所述M的整数倍；所述感测放大器组包括权利要求1-8任一项所述的列选择信号单元电路；
    其中，所述H条位线中的相邻两条位线连接到不同的所述感测放大器组。
  10. 根据权利要求9所述的位线感测电路，其中，所述H为8的整数倍，所述M等于所述L。
  11. 根据权利要求9所述的位线感测电路，其中，每个所述感测放大器组均包括第一感测放大器和第二感测放大器；
    所述L个存储单元组沿字线方向并排设置，所述字线与所述位线垂直；
    所述第一感测放大器位于所述存储单元组的一侧，所述第二感测放大器位于所述存储单元组的相对的另一侧。
  12. 根据权利要求11所述的位线感测电路，其中，所述第一感测放大器与所述第二感测放大器均连接P条所述位线，所述H为所述P的正偶数倍。
  13. 根据权利要求11所述的位线感测电路，其中，位于同一所述感测放大器组的所述第一感测放大器和所述第二感测放大器，沿所述字线方向错开设置。
  14. 根据权利要求11所述的位线感测电路，其中，位于不同所述感测放大器组的所述第一感测放大器，沿所述字线方向并排设置；位于不同所述感测放大器组的所述第二感测放大器，沿所述字线方向并排设置；位于同一所述感测放大器组的所述第一感测放大器和所述第二感测放大器，沿所述字线方向错开设置。
  15. 根据权利要求14所述的位线感测电路，其中，位于不同所述感测放大器组的所述第一感测放大器，沿所述字线方向上顺序排布；位于不同所述感测放大器组的所述第二感测放大器，沿所述字线方向上顺序排布。
  16. 根据权利要求14所述的位线感测电路，其中，位于两个所述感测放大器组的相邻的两个所述第一感测放大器与相邻的两个所述第二感测放大器呈交叉排布。
  17. 根据权利要求14所述的位线感测电路，其中，同一所述感测放大器组的第一感测放大器与对应的所述位线中的奇数列或偶数列连接，同一所述感测放大器组的第二感测放大器与对应的所述位线中的偶数列或奇数列连接。
  18. 根据权利要求11所述的位线感测电路，其中，连接于同一条所述字线的所述存储单元组中，所述第一感测放大器对应的存储单元组，与同一所述感测放大器组的所述第二感测放大器对应的存储单元组不同。
  19. 根据权利要求11所述的位线感测电路，其中，第n个所述感测放大器组的第一感测放大器沿所述字线方向上连接第n个所述存储单元组的位线中的奇数列或偶数列；第n+i个所述感测放大器组的第二感测放大器沿所述字线方向上连接第n个存储单元组所连位线中的偶数列或奇数列；所述n和i均为大于等于1且小于等于L的整数。
  20. 根据权利要求11所述的位线感测电路，其中，第n个所述感测放大器组的第一感测放大器沿所述字线方向上连接第n个存储单元组的位线中的奇数列或偶数列；第n-1个所述感测放大器组的第二感测放大器沿所述字线方向上连接第n个存储单元组的位线中的偶数列或奇数列；第n-1个所述感测放 大器组的第一感测放大器沿所述字线方向上连接第n-1个存储单元组的位线中的奇数列或偶数列；第n个所述感测放大器组的第二感测放大器沿所述字线方向上连接第n-1个存储单元组的位线中的偶数列或奇数列；所述n为大于等于2且小于等于L的整数。
  21. 根据权利要求11所述的位线感测电路，其中，所述第一感测放大器与所述第二感测放大器均包括H/2个列选择单元和H/2个敏感放大器，所述H为偶数，所述敏感放大器与所述位线一一对应，所述敏感放大器与所述列选择单元一一对应；
    所述敏感放大器与所述位线连接，被配置为对所述写入存储数据进行放大或对所述读出存储数据进行放大；
    所述列选择单元与所述敏感放大器连接，被配置为控制所述存储数据的传输。
  22. 一种存储器，包括：
    上述权利要求9-21任一项所述的位线感测电路；
    每个所述存储单元组还包括1条字线，所述1条字线和所述H条位线还对应的H个晶体管和H个电容，所述1条字线控制所述H个晶体管的开启或关断，所述H条位线与对应的所述H个晶体管的第一端连接，所述H个晶体管的第二端与对应的所述H个电容的第一端连接，所述H个电容的第二端接一固定电压。
  23. 根据权利要求22所述的存储器，其中，还包括：
    检错纠错电路，与所述感测放大器组连接，被配置为检测所述感测放大器组输出的所述存储数据的正确性，并纠正错误的所述存储数据。
  24. 根据权利要求22所述的存储器，其中，所述H为8的整数，所述M和所述L均为2。
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CN114203230A (zh) 2022-03-18

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