WO2023115953A1 - 一种存储块及存储器 - Google Patents

一种存储块及存储器 Download PDF

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Publication number
WO2023115953A1
WO2023115953A1 PCT/CN2022/109220 CN2022109220W WO2023115953A1 WO 2023115953 A1 WO2023115953 A1 WO 2023115953A1 CN 2022109220 W CN2022109220 W CN 2022109220W WO 2023115953 A1 WO2023115953 A1 WO 2023115953A1
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Prior art keywords
array
storage
read
write control
data bus
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PCT/CN2022/109220
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English (en)
French (fr)
Inventor
尚为兵
李红文
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长鑫存储技术有限公司
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Priority to US18/154,292 priority Critical patent/US20230206994A1/en
Publication of WO2023115953A1 publication Critical patent/WO2023115953A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to but not limited to a memory block and memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM can be divided into double data rate synchronous (Double Data Rate, DDR) dynamic random memory block, GDDR (Graphics Double Data Rate) dynamic random memory block, low power double rate synchronous (Low Power Double Data Rate, LPDDR) dynamic random memory block storage block.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • the disclosure provides a storage block and a memory.
  • a first aspect of the present disclosure provides a storage block, comprising: .
  • each of the storage arrays is divided into at least two array units along the second direction, the first direction and the second direction are perpendicular to each other;
  • a read-write control circuit the read-write control circuit is arranged between two adjacent storage arrays;
  • a data signal line for electrically connecting the read-write control circuit and the array unit
  • different array units of each memory array are electrically connected to different read/write control circuits through different data signal lines.
  • the plurality of storage arrays are used to store data and check codes; the storage block further includes: a plurality of error detection and correction units arranged in the two adjacent storage arrays The arrays are electrically connected with the plurality of read-write control circuits, and are used for detecting and/or correcting the data according to the check code.
  • the plurality of error detection and correction units at least include: a first error detection and correction unit, connected to each of the array units through the read-write control circuit, for Part of the output data of the unit is used for error detection and error correction; the second error detection and error correction unit is connected to each of the array units through the read-write control circuit, and is used to detect the remaining part of the output data of the array unit Error correction.
  • the data signal lines corresponding to each of the array units include an even number of block data buses, and the block data buses are numbered sequentially from zero according to natural numbers, and the odd-numbered block data buses O are connected to the
  • the first error detection and correction unit is connected to the second error detection and correction unit with an even-numbered block data bus E.
  • each of the array units includes a local conversion circuit and an even number of local data buses, the local data buses are divided into a local data bus O and a local data bus E, and the local data bus O passes through
  • the local conversion circuit is connected to the block data bus O, and the local data bus E is connected to the block data bus E through the local conversion circuit.
  • each of the local data buses is connected to a plurality of sense amplifiers through a gate switch, and the sense amplifiers are set in one-to-one correspondence with the bit lines in the memory array.
  • the output data on two adjacent bit lines respectively enter the local data bus O and the local data bus E through the sense amplifier and the gate switch.
  • the block data bus is 2*4*(16*N), the local data bus is 2*4*M*(16*N); the block data bus O 4*(16*N), the block data bus E is 4*(16*N); the local data bus O is 4*M*(16*N), and the local data bus E It is 4*M*(16*N); the block data bus O of one block corresponds to the local data bus O of the M blocks, and the block data bus E of one block corresponds to the local data bus E of the M blocks Corresponding; the local data bus is divided into the local data bus O of the M*(16*N) group and the local data bus E of the M*(16*N) group with 4 adjacent ones as a group .
  • multiple read-write control circuits there are multiple read-write control circuits, and they are divided into a first type of read-write control circuit and a second type of read-write control circuit;
  • Each of the first-type read-write control circuits corresponds to two of the array units, and the first-type read-write control circuits include: a first read-write control unit and a second read-write control unit;
  • the write control unit is connected between the odd-numbered block data bus O of the corresponding array unit and the first error detection and correction unit, and the second read-write control unit is connected to the corresponding array unit. between the even-numbered block data bus E and the second error detection and correction unit;
  • Each of the second-type read-write control circuits corresponds to one of the array units, and the second-type read-write control circuits are used for integrally connecting all block data buses of the corresponding array units with the first Between the error detection and correction unit and the second error detection and correction unit.
  • the plurality of storage arrays include a storage array U, a storage array V, and a storage array W arranged in sequence along the first direction; each of the storage arrays is divided into two along the second direction Array unit; two array units located on the same side in the second direction in the storage array U and the storage array V share the same word line address;
  • the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage unit of the same word line address in the two array units on the same side of the storage array U and the storage array V .
  • the two array units located on the first side in the storage array U and the storage array V share the same word line address; the read and write control circuits corresponding to the storage array U and the storage array V are controlled by The association is configured to simultaneously access the memory cells of the same word line address in the two array cells on the first side of the memory array U and the memory array V; or,
  • the two array cells located on the second side in the storage array U and the storage array V share the same word line address, and the first side and the second side are opposite sides in the second direction;
  • the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the storage cells with the same word line address in the two array units on the second side of the storage array U and the storage array V.
  • the two array units located on the first side in the storage array U and the storage array V share the same word line address
  • the two array units on the second side share the same word line address
  • the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the two array units on the second side of the storage array U and the storage array V;
  • the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the two array units on the first side of the storage array U and the storage array V.
  • the two array units located on the first side in the storage array U and the storage array V share the same word line address and/or the two array units located on the second side
  • the two array units located on the first side and the second side in the memory array W share the same word line address
  • the read-write control circuit corresponding to the storage array W is associated and configured to simultaneously access the array units on the first side and the second side of the storage array W.
  • a row decoding circuit configured to send a row decoding signal to locate and select word lines in different array units.
  • a second aspect of the present disclosure provides a memory, including the memory block described in the first aspect above.
  • a storage block with superior structural performance including a storage array divided into at least two array units, a read-write control circuit, and a read-write control circuit for electrically connecting and the data signal lines of the array unit.
  • each read-write control circuit only needs to access one array unit in the corresponding storage array, and the read-write control circuit and each array unit in the storage array are connected through different data signal lines
  • each data signal line is only electrically connected to one array unit, that is, it has an electrical contact point. Therefore, the electrical contact points during a single read and write operation are reduced, and the parasitic resistance and parasitic capacitance of this memory block are also reduced.
  • the read-write control circuit is arranged between two adjacent memory arrays, the distance from the read-write control circuit to the corresponding array unit can be greatly shortened, thereby reducing the length of the data signal line and improving the efficiency of data transmission.
  • the storage array is used to store data and a check code; the storage block also includes an error detection and correction unit for performing error detection and/or error correction on the data according to the check code. Since the error detection and correction unit is arranged between two adjacent memory arrays where the read-write control circuit is located, the layout between the read-write control circuit and the error detection and correction unit can be compacted, reducing the layout area; Write the distance between the control circuit and the error detection and correction unit, thereby reducing the length of the data signal line between the two and improving the efficiency of data transmission.
  • the output data on two adjacent bit lines respectively enter the local data bus O and the local data bus E through the sense amplifier and the strobe switch, so that the data corresponding to the physically adjacent local data buses respectively enter the first error detection and correction An error unit and a second error detection and correction unit, so when the data corresponding to adjacent bit lines is processed to make an error at the same time, the error can also be corrected, further improving the error detection and error correction capability of the memory.
  • several storage arrays include storage array U, storage array V and storage array W, and each storage array is divided into two array units;
  • the same word line address is shared, and the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the two array units on the same side in the storage array U and the storage array V, so that the two array units on the same side of the storage array U and the storage array V can be accessed through the shared word line
  • the address simultaneously accesses two memory arrays, reducing word line overhead and energy consumption.
  • Fig. 1 is a structural schematic diagram of a DARM
  • FIG. 2 is a schematic structural diagram of a storage block provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a layout top view structure of a memory
  • Fig. 4 is a structural schematic diagram of a memory
  • FIG. 5 is a schematic structural diagram of a storage block provided by another embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a storage block provided by another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of connection of signal lines in a local area of the memory in FIG. 6;
  • Fig. 8 is a schematic structural diagram of a storage block provided by another embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a DARM.
  • a DRAM is composed of multiple memory blocks (banks, also called memory banks), each memory block includes several memory arrays, and each memory array includes a memory array (array) and a sense amplifier array.
  • the memory blocks are divided into a high-order group and a low-order group according to the output pin (DQ) . That is to say, each bank can also be divided into two half banks, one of which is the first module M1, the first module M1 provides low-level output pins, and the other half bank is the second module M2, the second module M2 provides a high output pin.
  • the data signal line YIO is used to transmit data between the selected memory array and the read/write control circuit. Regardless of whether it is a low-level half bank or a high-level half bank, in order to successfully complete the read and write operations, the data signal line YIO line and each memory array in the half bank have electrical contacts, resulting in parasitic capacitance ; The data signal line YIO line is very long, resulting in a large parasitic resistance, which will cause the problem of large power consumption for each read and write, resulting in high power consumption of DRAM.
  • parasitic resistance and parasitic capacitance are also one of the main reasons for the large power consumption of DARM.
  • For the data signal line YIO during each read operation or write operation, there are parasitic capacitances and parasitic resistances at the electrical contact points between each group of data signal lines YIO and each memory array. Due to the large number of electrical contacts, the corresponding parasitic resistance and parasitic resistance are large, resulting in large power consumption of the DRAM.
  • the embodiments of the present disclosure provide a memory block with superior structural performance. Through the design of the special structure, the parasitic resistance and parasitic capacitance of the memory block are reduced, thereby reducing the power consumption of the memory block.
  • FIG. 2 is a schematic structural diagram of a storage block provided by an embodiment of the present disclosure.
  • the memory block includes several memory arrays 101 arranged along the first direction (X), and each memory array 101 is divided into at least two array units (such as arrays) along the second direction (Y).
  • U, V and W among the figure represent storage array U, storage array V and storage array W respectively);
  • Data signal line YIO (several, as YIO1 and YIO2), for electrically connecting the read-write control circuit 102 and the array unit; wherein, different array units of each storage array 101 are electrically connected to different read-write control circuits 102 through different data signal lines YIO.
  • the first direction X is the direction in which the word lines WL extend
  • the second direction Y is the direction in which the bit lines BL extend.
  • Embodiments of the present disclosure provide a memory block with superior structural performance, including a memory array divided into at least two array units, a read-write control circuit, and data signal lines for electrically connecting the read-write control circuit and the array units.
  • each read-write control circuit only needs to access one array unit in the corresponding storage array, and the read-write control circuit and each array unit in the storage array are connected through different data signal lines
  • each data signal line is only electrically connected to one array unit, that is, it has an electrical contact point. Therefore, the electrical contact points during a single read and write operation are reduced, and the parasitic resistance and parasitic capacitance of this memory block are also reduced. Therefore, it is beneficial to reduce the power consumption of the storage block.
  • the read-write control circuit is arranged between two adjacent memory arrays, the distance from the read-write control circuit to the corresponding array unit can be greatly shortened, thereby reducing the length of the data signal line and improving the efficiency of data transmission.
  • the present embodiment will be described in detail below in conjunction with the accompanying drawings. It should be noted that, for the sake of illustration, the following embodiments take the storage block including three storage arrays 101 and four read-write control circuits 102 as an example for illustration.
  • the number of read and write control circuits 102 can also be other numbers, which can be set according to actual needs.
  • the thick solid line symbols and thick dashed line symbols marked in Fig. 2 and Fig. 5 both indicate electrical connection, that is, have electrical contact points.
  • the difference between the thick solid line and the thick dotted line is only the sorting position of the connected memory array. , wherein, the thick solid line is connected with the memory arrays sorted by odd numbers, and the thick dashed line is connected with the memory arrays sorted by even numbers.
  • the storage block may include three storage arrays U, V and W, and each storage array 101 is divided into two array units (such as array unit 1101 and array unit 1102) along the second direction Y. ); 4 read-write control circuits 102 are located between any two storage arrays 101, and each read-write control circuit 102 can be electrically connected to any one or more array units in the 3 storage arrays 101, but each storage array needs to be satisfied Different array units of the array 101 are electrically connected to different read/write control circuits 102 through different data signal lines YIO.
  • each read-write control circuit 102 in the two read-write control circuits 102 close to the storage array V is connected to one array in the storage array U.
  • the cell is connected to an array cell in the memory array V.
  • a read-write control circuit 102 is connected to the array units 1101 in the storage array V and the storage array U, and the read-write control circuit 102 is connected to the odd-numbered memory arrays in the two array units 1101 through the data signal line YIO1, The even-numbered memory arrays in the two array units 1101 are connected through the data signal line YIO2; similarly, another read-write control circuit 102 is connected with the two array units 1102 in the storage array V and the storage array U, and the read-write The control circuit 102 connects the odd-numbered memory arrays in the two array units 1102 through the data signal line YIO1 , and connects the even-numbered memory arrays in the two array units 1102 through the data signal line YIO2 .
  • Each of the two read-write control circuits 102 close to the storage array W is connected to an array unit in the storage array W.
  • a read-write control circuit 102 is connected to the array unit 1101 in the storage array W; the read-write control circuit 102 is connected to the odd-numbered and even-numbered memory arrays in the array unit 1101 through the data signal line YIO1 and the data signal line YIO2 at the same time.
  • another read-write control circuit 102 is connected to the array unit 1102 in the storage array W; the read-write control circuit 102 is connected to the array unit 1102 through the data signal line YIO1 and the data signal line YIO2 at the same time. memory array.
  • an array unit is connected to more than one YIO, and the data signal line YIO1 and the data signal line YIO2 generally refer to one of the data signal lines connected to a memory array in the array unit.
  • Each memory array 101 includes a memory array (numbered 0, 1, 2, . . . as shown in FIG. 2 ) and a sense amplifier array (Sense Amplifier, SA) (not shown in FIG. 2 , please refer to FIG. 1 ).
  • the memory array includes multiple memory cells (cells) for storing data; the sense amplifier array is used for amplifying the output signal of the memory array.
  • the number of memory arrays and sense amplifier arrays included in each array unit may be the same or different.
  • the data signal line is only connected to one array unit in the memory array 101, that is, the data signal line is only electrically connected to a part of the memory array, so that the number of electrical contacts is reduced.
  • the parasitic in the memory block can be reduced circuit and parasitic capacitance, and the load on the data signal line is significantly reduced, so the power consumption of the memory block can be significantly reduced.
  • the data signal line on the side of the array unit 1101 in the memory array is only electrically connected to the array unit 1101, without extending to the side of the array unit 1102; similarly, the data signal line on the side of the array unit 1102 in the memory array is only electrically connected to the array Unit 1102 without extending to the side of array unit 1101, thereby reducing the length of the data signal line, which is conducive to further reducing the resistance of the data signal line and the power consumption, thereby further reducing the power consumption of the memory block. consumption.
  • the storage block provided by this embodiment consumes less power each time, and the corresponding storage block has the advantage of low power consumption.
  • ECC Error Checking and Correcting, error detection and correction
  • the ECC check technology can not only find but also correct it, and ECC check can also find 2 to 4 bit errors, but it is difficult for ECC check to correct 2 or more errors. That is to say, although the ECC check technology can detect and correct a single bit error at the same time, if two or more bit data errors are detected at the same time, the current ECC check technology is helpless. In addition, further analysis found that the two data currently in adjacent positions have a higher probability of errors at the same time. Further analysis found that the analysis of the main reasons leading to this problem is as follows:
  • FIG. 3 is a schematic top view of a layout of a memory.
  • the memory includes: a plurality of active regions 10 arranged in an array; word lines 12 , bit lines 11 and capacitors 13 electrically connected to the active regions.
  • the capacitor 91 is connected to the bit line BL3 through a transistor
  • the capacitor 92 is connected to the bit line BL2 through a transistor.
  • the occurrence probability of such defects is also increasing.
  • Fig. 4 is a structural diagram of a memory, the memory includes: a memory array, composed of memory cells 14, each memory cell 14 is connected to a bit line BL and a word line WL; a column selection signal unit, marked as CSL ⁇ n in Fig.
  • each column selection signal unit includes a plurality of column selection signal lines, and each column selection signal line is connected to the local data bus by controlling the corresponding bit line BL in the memory array , the control signal of the switch comes from the column decoding circuit (not shown in Figure 4), and is used to determine whether the data on the bit line BL is transmitted to the local data bus, for example, the column selection signal unit CSL ⁇ n> includes 8 Column selection signal line, 8 column selection signal lines are connected to the local data bus through the switch control bit line BL in the storage array; the local data bus is marked as LIO in Figure 4, where LIO: O ⁇ 3:0> is marked The local data bus with an odd number, LIO: E ⁇ 3:0> indicates the local data bus with an even number; the block data bus is marked as YIO in Figure 4, where YIO: O ⁇ 3:0> indicates that the number is odd block data bus, YIO: E ⁇ 3:0> indicates the even-numbered block data bus, and
  • the block data bus YIO:E ⁇ 3:0> and YIO:O ⁇ 3:0> are connected to the same error detection and correction unit 15. If the two bit lines BL corresponding to the two memory cells 14 are just connected to the same column decoding circuit, then two errors occur simultaneously at the same readout time point, such as memory cell 91 and memory cell 92 in FIG.
  • Another embodiment of the present disclosure also provides a storage block, which is roughly the same as the storage block provided in the previous embodiment, the difference is that several storage arrays 101 are used to store data and check codes; the storage block also includes : a number of error detection and correction units, arranged between two adjacent storage arrays 101, electrically connected to a number of read-write control circuits 102, used for error detection and/or error correction of data according to the check code; wherein, During the read operation, the data and check code read by the read-write control circuit 102 are divided into at least two parts, and the read-write control circuit 102 is configured to transmit each part to a different error detection and correction unit.
  • the read-write control circuit 102 Since the read-write control circuit 102 divides the output data of the array unit into at least two parts during each read operation, and the read-write control circuit 102 transmits each part to a different error detection and correction unit, so that the output data of the array unit When more than one error occurs at the same time, different errors can be corrected by different error detection and error correction units, so that the storage block can correct more than one error and improve the error detection and error correction capability of the storage block.
  • the storage block provided by this embodiment will be described below in conjunction with the accompanying drawings. It should be noted that for parts that are the same as or corresponding to the previous embodiment, please refer to the detailed description of the previous embodiment, and will not be described in detail below.
  • the number of several error detection and error correction units 103 in the storage block can be two, and it is arranged close to the read-write control circuit 102, and is electrically connected with the above-mentioned 4 read-write control circuits 102, for
  • the check code read from the array unit performs error detection and/or error correction on the read data.
  • the data and the check code read from the array unit by the read/write control circuit 102 are divided into at least two parts (such as random distribution, or distribution according to the serial number parity of the memory array where the data is located), and the read The write control circuit 102 is configured to transmit a part of them to one error detection and correction unit, and transmit the remaining part to another error detection and correction unit.
  • each read-write control circuit 102 divides all check codes and data read from the array unit into two parts, and in these two parts, a part is transmitted by the read-write control circuit 102 to the adjacent array unit.
  • the error detection and correction unit 103 of 1101 the remaining part is transmitted by the read/write control circuit 102 to the error detection and correction unit 1032 close to the array unit 1102 .
  • the write control circuit 102 divides the output data of the array unit into at least two parts during each read operation, and the read-write control circuit 102 transmits each part to a different error detection and correction unit, so that the output data of the array unit
  • different errors can be corrected by different error detection and error correction units, so that the storage block can correct more than one error, improve the error detection and correction ability of the storage block, and improve the read and write of the memory performance.
  • the memory block in this embodiment further includes: a row decoding circuit (not shown in the figure), which is used to send out row decoding signals to locate and select word lines in different array units.
  • a row decoding circuit (not shown in the figure), which is used to send out row decoding signals to locate and select word lines in different array units.
  • the data signal line YIO1 or YIO2 on the side of the array unit 1101 in the storage array U and the storage array V will read the corresponding array unit 1101 data in .
  • Fig. 6 is a memory block provided by another embodiment of the present disclosure.
  • error detection and error correction units 103 which can be respectively:
  • the first error detection and correction unit 1031 is connected to each array unit through the read-write control circuit 102, and is used to perform error detection and correction on a part of the output data of the array unit; the second error detection and correction unit 1032, through the read-write The control circuit 102 is connected to each array unit, and is used for error detection and error correction on the remaining output data of the array unit.
  • the arrangement of the storage array may refer to FIG. 3 and FIG. 4 .
  • the output data of the storage array U is 136 bits as an example, wherein the 128 bits data is valid data (data that the memory needs to interact with the external controller through the memory interface), and the 8 bits data is the first error detection and error correction unit 1031 and the check code generated after processing by the second error detection and correction unit 1032.
  • the memory includes a data write operation and a data read operation. When a data write operation is performed to the storage array in the memory, the data received by the memory interface passes through the ECC module (for example, the first error detection and correction unit 1031 in FIG.
  • 128bits data this 128bits data is also called valid data
  • the data output by the ECC module is 136bits (128bits valid data+8bits check code)
  • 128bits data is valid data
  • 8bits is the check code generated by the ECC module.
  • These 136bits will be stored in the storage array of the storage array U, which can be called an encoding process when the ECC module operates for writing data; When the array reads data, it also outputs 136bits (128bits valid data + 8bits check code) data from the storage array U, and these 136bits enter the ECC module at the same time.
  • the ECC module is a decoding process for the read data operation.
  • the ECC module decodes the 128bits valid data and compares the result of the decoding operation with the 8bits check code to judge whether there is an error in the output 128bits valid data. There is only 1 bit error in 64bits (one bit error), and the ECC module can also correct the one bit error.
  • 136bits ( The output data of 128bits storage data+8bits check code) is output to the first error detection and correction unit 1031 and the second error detection and correction unit 1032 respectively, and the 136bits (128bits storage data+8bits checksum) read from the storage array V code) output data to the first error detection and correction unit 1031 and the second error detection and correction unit 1032 respectively.
  • the storage array U outputs the output data of 138bits (128bits storage data+8bits check code) to the first error detection and correction unit 1031, and the storage array V outputs 136bits (128 storage data+8bits check code)
  • the output data of is output to the second error detection and correction unit 1032.
  • part of the output data of the storage array U (or storage array V) is input to the first error detection and correction unit 1031 for error detection and correction, and the rest of the output data is input to the second error detection and correction unit 1032 for detection.
  • Error correction so that when more than one error (for example, two-bit error) occurs simultaneously in the output data of the storage array U (or storage array V), different errors can be detected and corrected by the first error detection and error correction unit 1031 or the second error detection and correction unit 1031.
  • the error unit 1032 corrects, so that the memory can correct more than one error and improve the error detection and correction capability of the memory.
  • the number of data bits received by the first error detection and correction unit 1031 is the same as the number of data bits received by the second error detection and correction unit 1032 .
  • the number of data bits received by the first error detection and correction unit 1031 and the number of data bits received by the second error detection and correction unit 1032 are both 128bits+8bits, wherein 128bits is the storage array U and the storage array V write 8 bits is the check code generated by the first error detection and error correction unit 1031 or the second error detection and error correction unit 1032.
  • the internal error detection algorithm of the first error detection and correction unit 1031 is the same as the internal error detection algorithm of the second error detection and correction unit 1032, which is beneficial to reduce the design difficulty of the memory.
  • the first error detection and correction unit 1031 uses an internal error detection algorithm to calculate the valid data (128 bits), and calculates the parity bit (8 bits), Record it as the first parity bit, then write the valid data (128bits) and the parity bit (8bits) into the memory array 101 simultaneously; ) Calculate the check digit (8bits), record it as the second check digit, compare the second check digit with the directly read first check digit, if the results are the same, it means that the data is correct, otherwise it means If there is an error, the first error detection and correction unit 1031 can logically detect the error; when only one bit error occurs, the first error detection and correction unit 1031 can correct the error without affecting the memory read operation. For example, when the "0" in the third bit of 128 bits is an error bit, the first error detection and correction unit 1031 corrects the "0" in the third bit to "1".
  • Part of the output data in the storage array U is input to the first error detection and correction unit 1031 for error detection and error correction, and the rest of the output data is input to the second error detection and error correction unit 1032 for error detection and error correction.
  • the adjacent two-bit errors that may occur in U are respectively placed in different ECC units, because the two erroneous data are processed by the first error detection and error correction unit 1031 and the second error detection and error correction unit 1032 respectively, that is, the first error detection and error correction unit 1032
  • Both the first error detection and correction unit 1031 and the second error detection and correction unit 1032 process only one error, so at the memory level, the memory can correct the two errors at the same time.
  • the storage capacity of the storage arrays U and V and the storage capacity of W are the same. In other embodiments, the storage capacities of the storage arrays U, V, and W may not be exactly the same.
  • FIG. 7 is a schematic diagram of the connection of signal lines in a local area represented by a thick line in a long square of the storage array 101 in FIG.
  • the thick dotted line is only connected with the even grid, and the storage array V, W are the same as the storage array U)
  • the local data bus LIO is connected with a plurality of sense amplifiers (not shown) through the column selection signal unit 109, and the sense amplifier There is a one-to-one correspondence with the bit line BL of the memory cell 105 .
  • the column selection signal unit 109 includes a selection switch, and the column selection signal (columnselect signal) controls the conduction or shutdown of the selection switch.
  • the sense amplifier When the selection switch is turned on, the sense amplifier exchanges data with the local data bus LIO, and when the selection switch is turned off , the sense amplifier and the local data bus LIO no longer exchange data.
  • the output data on the adjacent bit line BL enters the local data bus O and the local data bus E respectively through the sense amplifier and the column selection signal unit 109 .
  • LIO:E in FIG. 7 shows the local data bus E
  • LIO:O shows the local data bus O, shown by CSL ⁇ n-1>, CSL ⁇ n> and CSL ⁇ n+1>
  • the column selection signal unit is provided, the gate switch is located in the column selection signal unit (not shown), and the sensitive amplifier is located on both sides of the bit line BL (not shown).
  • the local data bus E exchanges data with the block data bus E through a local conversion circuit (not shown), and the local data bus O exchanges data with the block data bus O through a local conversion circuit (not shown).
  • the block data bus E is indicated by a solid line YIO:E with an arrow
  • the block data bus O is indicated by a dotted line YIO:O with an arrow.
  • YIO1_O one of the block data bus O is illustrated with YIO1_O
  • one of the block data bus E is illustrated with YIO1_E.
  • YIO:E in Fig. 7 can be understood as one of the YIO1_E in Fig. 7
  • YIO:O can be understood as one of YIO1_O.
  • YIO1_O passes through the block amplifier (not shown) and the read-write control circuit 102 to the first error detection and correction unit 1031
  • YIO1_E passes through the block amplifier (not shown) and the read-write control circuit 102 to the second error detection and correction unit 1032.
  • YIO2_O indicates one block data bus O
  • YIO2_E indicates one block data bus E.
  • YIO:E in FIG. 7 can be understood as one of YIO2_E
  • YIO:O in FIG. 7 can be It is understood as one of YIO2_O.
  • YIO2_O passes through the block amplifier (not shown) and the read-write control circuit 102 to the first error detection and correction unit 1031
  • YIO2_E passes through the block amplifier (not shown) and the read-write control circuit 102 to the second error detection and correction unit 1032.
  • the data of YIO_O enters the first error detection and correction unit 1031
  • the data of YIO_E enters the second error detection and correction unit 1032
  • the storage arrays U, V, and W all include a local switching circuit (LocalSA, not shown) and an even number of local data buses.
  • the local data buses are divided into local data buses O and local data buses E.
  • the local data buses O The block data bus O is connected through a local switching circuit, and the local data bus E is connected to the block data bus E through a local switching circuit.
  • the local data buses are numbered sequentially from zero according to natural numbers, the local data bus with an odd number is defined as a local data bus O, and the local data bus with an even number is defined as a local data bus E;
  • the local data bus at an odd position is defined as a local data bus O, and the local data bus at an even position is defined as a local data bus E.
  • the arrangement of the storage arrays in the storage array U is numbered from 0 according to natural numbers, and the block data bus is electrically connected to the even-numbered storage array.
  • the storage array includes a storage unit, a local data bus E, a local data bus The bus O and the local conversion circuit, the block data bus is connected to the local data bus E through the local conversion circuit; the block data bus is connected to the local data bus O through the local conversion circuit, and the block data bus and the storage array are marked with thick line symbols in Fig. 6 connection relationship.
  • connection relationship of the block data buses of the storage arrays V and W reference may be made to the corresponding description of the storage array U, which will not be described in detail below.
  • the block data bus is 2*4*(16*N), the local data bus is 2*4*M*(16*N); the block data bus 0 is 4*( 16*N), block data bus E is 4*(16*N); local data bus O is 4*M*(16*N), local data bus E is 4*M*(16*N) 1 block data bus O corresponds to M local data buses O, and 1 block data bus E corresponds to M local data buses E; local data buses are divided into M in groups of 4 adjacent ones *(16*N) groups of local data buses O and M*(16*N) groups of local data buses E.
  • M and N are natural numbers greater than or equal to 1.
  • the block data bus is 2*4*16
  • the local data bus is 2*4*16
  • the block data bus O is 4*16
  • the block data bus E is 4*16
  • the local data bus O is 4*16
  • the local data bus E is 4*16
  • the data signal lines corresponding to each array unit include an even number of block data buses, and the block data buses are numbered sequentially from zero according to natural numbers, and the block data buses O (denoted as YIO_O , such as YIO1_O or YIO2_O) is connected to the first error detection and error correction unit 1031 through the read-write control circuit 102, and the even-numbered block data bus E (marked as YIO_E, such as YIO1_E or YIO2_E) is connected to the second detection error correction unit through the read-write control circuit 102.
  • YIO_O such as YIO1_O or YIO2_O
  • each array unit in the storage array U comprises an even block data bus, and the block data bus is numbered sequentially from zero according to a natural number, and the block data bus O (marked as YIO_O) of an odd number is controlled by reading and writing
  • the circuit 102 is connected to the first error detection and correction unit 1031, and the even-numbered block data bus E (denoted as YIO_E) is connected to the second error detection and correction unit 1032 through the read and write control circuit 102;
  • each array unit in the storage array V Including an even number of block data buses, the block data buses are numbered sequentially from zero according to natural numbers, and the numbered block data buses O (denoted as YIO_O) are connected to the first error detection and error correction unit 1031 through the read-write control circuit 102, and the numbers are even numbers
  • the block data bus E (denoted as YIO_E) is connected to the second error detection and error correction unit 1032 through the read-write control circuit 102; Numbered sequentially, the Y
  • the data of the block data bus O (YIO_O) of the storage arrays U, V, W enters the first error detection and correction unit 1031 through the read-write control circuit 102 to perform error detection and correction; the block data of the storage arrays U, V, W
  • the data on the bus E (YIO_E) enters the second error detection and correction unit 1032 through the read/write control circuit 102 for error detection and correction.
  • the data signal line corresponding to each array unit includes an even number of block data buses, and the block data buses are numbered sequentially from zero according to natural numbers, and the odd numbered block data bus O (denoted as YIO_O) is connected to the second detector
  • the error correction unit 1032 is connected to the first error detection and error correction unit 1031 with an even-numbered block data bus E (denoted as YIO_E).
  • Each array unit in the storage array U includes an even number of block data buses, and the block data buses are numbered sequentially from zero according to natural numbers, and the odd numbered block data bus O (denoted as YIO_O) is connected to the second error detection and correction unit 1032,
  • the even-numbered block data bus E (denoted as YIO_E) is connected to the first error detection and error correction unit 1031;
  • each array unit in the storage array V includes an even number of block data buses, and the block data buses are numbered sequentially from zero according to natural numbers,
  • the block data bus O (denoted as YIO_O) with an odd number is connected to the second error detection and error correction unit 1032, and the block data bus E (denoted as YIO_E) with an even number is connected to the first error detection and error correction unit 1031;
  • Each array unit of the array unit includes an even block data bus, and the block data bus is numbered sequentially from zero according to a natural number, and the odd block data bus O (deno
  • the data of the block data bus O (YIO_O) of the storage arrays U, V, W enters the second error detection and correction unit 1032 for error detection and error correction; the data of the block data bus E (YIO_E) of the storage arrays U, V, W The data enters the first error detection and correction unit 1031 for error detection and correction.
  • the output data of the same array unit are respectively input into different error detection and correction units, that is, part of the output data is input to the first error detection and correction unit 1031 for error detection and correction, and the remaining part is output
  • the data is input to the second error detection and correction unit 1032 for error detection and correction, so that if there are two bits of data error at the same time, the first error detection and correction unit 1031 and the second error detection and correction unit 1032 can respectively detect and correct errors in the two bits. One bit of data is corrected, thereby improving the error detection and correction capabilities of the memory.
  • FIG. 6 in this embodiment, there are multiple read-write control circuits 102, and they are divided into a first type of read-write control circuit 102 and a second type of read-write control circuit 102;
  • Each first type of read-write control circuit 102 corresponds to two array units, and the first type of read-write control circuit 102 includes: a first read-write control unit 1021 and a second read-write control unit 1022; the first read-write control unit 1021 Connected between the odd-numbered block data bus O of the corresponding array unit and the first error detection and correction unit 1031, the second read-write control unit 1022 is connected to the even-numbered block data bus E of the corresponding array unit and the second error detection and correction unit 1031. Between the error correction unit 1032;
  • Each second type of read-write control circuit 102 is corresponding to an array unit, and the second type of read-write control circuit 102 is used to be connected to all block data buses of the corresponding array unit as a whole (odd-numbered block data bus 0+even-numbered block data Between the bus E) and the first error detection and correction unit 1031 and the second error detection and correction unit 1032 .
  • the read-write control circuit 102 integrally receives the data transmitted by the odd-numbered block data bus O and the even-numbered block data bus E of the array unit (the two reads near the array unit W in Fig. 6
  • a read-write control circuit 102 is also designed to be split into two read-write control units, wherein one read-write control unit 1021 is responsible for receiving the data transmitted by the odd-numbered block data bus O of the array unit, and the other A read-write control unit 1022 is responsible for exclusively receiving the data transmitted by the even-numbered block data bus E of the same array unit.
  • FIG. 8 is a schematic structural diagram of a storage block provided by another embodiment of the present disclosure.
  • the output data of the two array units of the storage array U, the storage array V, and the storage array W correspond to high-order data and low-order data respectively, for example, the array unit 1101 in the storage array U stores high-order data, and the array Unit 1102 stores low-order data; the array unit 1101 on the side with the smaller memory array sorting number in storage array V stores low-order data, and array unit 1102 stores high-order data; array unit 1101 stores high-order data in storage array W, and array unit 1102 stores low-order data .
  • the above-mentioned several storage arrays 101 include a storage array U, a storage array V, and a storage array arranged in sequence along the first direction.
  • Storage array W each storage array is divided into two array units along the second direction; two array units located on the same side in the second direction in the storage array U and storage array V share the same word line address; storage array U
  • the read-write control circuit corresponding to the storage array V is associated and configured to simultaneously access the storage units of the same word line address in the two array units on the same side of the storage array U and the storage array V.
  • the two array cells located on the first side in the storage array U and the storage array V share the same word line address; the read and write control circuits corresponding to the storage array U and the storage array V are associated and configured to access the storage array U at the same time , memory cells with the same word line address in the two array cells on the first side in the storage array V; or, the two array cells located on the second side in the memory array U and the memory array V share the same word line address, and the first The side and the second side are opposite sides on the second direction; the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the two sides of the second side in the storage array U and the storage array V. Memory cells with the same word line address in the array cells.
  • the side where the array unit 1101 is located in the storage array U and the storage array V is set as the first side
  • the side where the array unit 1102 is located is set as the second side
  • the storage array U and the storage array V The two array units located on the first side share the same word line address as an example.
  • the two array units 1101 in memory arrays U and V can share the same word line address, that is, the same word line address can access the same word line address.
  • storage array For example, accessing the word line address corresponding to 1 can simultaneously access the data in memory array number 3 in memory arrays U and V.
  • the two array units located on the first side in the storage array U and the storage array V share the same word line
  • the two array units located on the second side in the storage array U and the storage array V share the same word line.
  • Word line address; the read-write control circuit 102 corresponding to the storage array U and the storage array V is associated and configured to simultaneously access two array units on the second side of the storage array U and the storage array V; when the storage array U and the storage array V When the two array units located on the second side share the same word line address, the two array units located on the first side in the storage array U and the storage array V share the same word line address;
  • the read-write control circuit 102 is associated and configured to simultaneously access the two array units on the first side of the storage array U and the storage array V.
  • the side where the array unit 1101 is located in the storage array U and the storage array V is set as the first side
  • the side where the array unit 1102 is located is set as the second side
  • the storage array U and the storage array V are located at the second side.
  • Two array units on one side share the same word line address as an example.
  • the two array units in memory array U and memory array V 1102 can also share the same word line address, that is, the same word line can access memory arrays with the same word line address. For example, accessing the word line address corresponding to 2 may simultaneously access the data in the memory arrays numbered 20 in the memory arrays U and V.
  • the storage The two array cells located on the first side and the second side in the array W share the same word line address; the read-write control circuit corresponding to the storage array W is associated and configured to simultaneously access the first side and the second side of the storage array W array unit.
  • the side where the array unit 1101 is located in the storage array U and the storage array V is set as the first side
  • the side where the array unit 1102 is located is set as the second side
  • the storage array U and the storage array V are located at the second side.
  • Two array units on one side share the same word line address as an example, when two array units 1101 in memory array U and memory array V share the same word line address, the two array units (array unit 1101) in memory array W 1101 and array unit 1102) can also share the same word line address, that is, the same word line can access memory arrays with the same word line address. For example, accessing the word line address corresponding to 3 may simultaneously access the data in the array unit 1101 in the storage array W and the memory array number 38 in the array unit 1102 .
  • the memory block provided by this embodiment can access two memory array units at the same time according to the same word line address by configuring the access state of the read-write control circuit corresponding to each memory array.
  • the data in the array unit, the real line can access the data combination flexibly.
  • this embodiment also provides a memory, which includes the storage blocks in any one or at least two combined embodiments above.
  • a memory block and a memory provided by an embodiment of the present disclosure include a memory array divided into at least two array units, a read/write control circuit, and data signal lines for electrically connecting the read/write control circuit and the array units.
  • each read-write control circuit only needs to access one array unit in the corresponding storage array, and the read-write control circuit and each array unit in the storage array are connected through different data signal lines
  • each data signal line is only electrically connected to one array unit, that is, it has an electrical contact point. Therefore, the electrical contact points during a single read and write operation are reduced, and the parasitic resistance and parasitic capacitance of this memory block are also reduced. Therefore, it is beneficial to reduce the power consumption of the storage block.
  • the storage array is used to store data and a check code; the storage block also includes an error detection and correction unit for performing error detection and/or error correction on the data according to the check code.
  • the layout between the read-write control circuit and the error detection and correction unit can be compacted, reducing the layout area; Write the distance between the control circuit and the error detection and correction unit, thereby reducing the length of the data signal line between the two and improving the efficiency of data transmission.
  • the output data on two adjacent bit lines respectively enter the local data bus O and the local data bus E through the sense amplifier and the strobe switch, so that the data corresponding to the physically adjacent local data buses respectively enter the first error detection and correction An error unit and a second error detection and correction unit, so when the data corresponding to adjacent bit lines is processed to make an error at the same time, the error can also be corrected, further improving the error detection and error correction capability of the memory.
  • several storage arrays include storage array U, storage array V and storage array W, and each storage array is divided into two array units;
  • the same word line address is shared, and the read-write control circuits corresponding to the storage array U and the storage array V are associated and configured to simultaneously access the two array units on the same side in the storage array U and the storage array V, so that the two array units on the same side of the storage array U and the storage array V can be accessed through the shared word line
  • the address simultaneously accesses two memory arrays, reducing word line overhead and energy consumption.

Abstract

本公开提供一种存储块以及存储器，存储块包括沿第一方向设置的若干个存储阵列，每一存储阵列沿第二方向被划分为至少两个阵列单元，第一方向与第二方向互相垂直；若干个读写控制电路，读写控制电路设置在相邻的两个存储阵列之间；若干个数据信号线，用于电连接读写控制电路和阵列单元；其中，每一存储阵列的不同阵列单元通过不同的数据信号线电连接至不同的读写控制电路。

Description

一种存储块及存储器
本公开基于申请号为202111590252.0、申请日为2021年12月23日、申请名称为“一种存储块及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种存储块及存储器。
背景技术
动态随机存取存储块(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储块件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM可以分为双倍速率同步(Double Data Rate，DDR)动态随机存储块、GDDR(Graphics Double Data Rate)动态随机存储块、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储块。随着DRAM应用的领域越来越多，如DRAM越来越多的应用于移动领域，用户对于DRAM功耗指标的要求越来越高。
然而，目前的DRAM功耗仍然较高，难以满足低功耗需求。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种存储块及存储器。
本公开的第一方面提供一种存储块，包括：。
沿第一方向设置的若干个存储阵列，每一所述存储阵列沿第二方向被划分为至少两个阵列单元，所述第一方向与所述第二方向互相垂直；
读写控制电路，所述读写控制电路设置在相邻的两个所述存储阵列之间；
数据信号线，用于电连接所述读写控制电路和所述阵列单元；
其中，每一所述存储阵列的不同阵列单元通过不同的所述数据信号线电连接至不同的所述读写控制电路。
根据本公开的一些实施例，所述若干个存储阵列，用于存储数据和校验码；所述存储块还包括：若干检错纠错单元，设置在所述相邻的两个所述存储阵列之间，与所述若干读写控制电路电连接，用于根据所述校验码对所述数据进行检错和/或纠错。
根据本公开的一些实施例，所述若干检错纠错单元至少包括：第一检错纠错单元，通过所述读写控制电路与每个所述阵列单元均连接，用于对所述阵列单元的一部分输出数据进行检错纠错；第二检错纠错单元，通过所述读写控制电路与每个所述阵列单元均连接，用于对所述阵列单元的剩余输出部分数据进行检错纠错。
根据本公开的一些实施例，每个所述阵列单元对应的数据信号线包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O连接所述第一检错纠错单元，编号为偶数的块数据总线E连接所述第二检错纠错单元。
根据本公开的一些实施例，每个所述阵列单元均包括本地转换电路和偶数条本地数据总线，所述本地数据总线分为本地数据总线O和本地数据总线E，所述本地数据总线O通过所述本地转换电路连接所述块数据总线O，所述本地数据总线E通过所述本地转换电路连接所述块数据总线E。
根据本公开的一些实施例，每条所述本地数据总线通过选通开关与多个灵敏放大器连接，所述灵敏放大器与所述存储阵列中的位线一一对应设置。
根据本公开的一些实施例，相邻两条所述位线上的所述输出数据经所述灵敏放大器和所述选通开关分别进入所述本地数据总线O和所述本地数据总线E。
根据本公开的一些实施例，所述块数据总线为2*4*(16*N)条，所述本地数据总线为2*4*M*(16*N)条；所述块数据总线O为4*(16*N)条，所述块数据总线E为4*(16*N)条；所述本地数据总线O为4*M*(16*N)条，所述本地数据总线E为4*M*(16*N)条；1条所述块数据总线O与M条所述本地数据总线O相对应，1条所述块数据总线E与M条所述本地数据总线E相对应；所述本地数据总线以相邻的4条为一组被划分为M*(16*N)组的所述本地数据总线O和M*(16*N)组的所述本地数据总线E。
根据本公开的一些实施例，所述读写控制电路为多个，且分为第一类读写控制电路和第二类读写控制电路；
每个所述第一类读写控制电路与两个所述阵列单元对应，所述第一类读写控制电路包括：第一读写控制单元和第二读写控制单元；所述第一读写控制单元连接于对应的所述阵列单元的所述奇数的块数据总线O与所述第一检错纠错单元之间，所述第二读写控制单元连接于对应的所述阵列单元的所述偶数的块数据总线E与所述第二检错纠错单元之间；
每个所述第二类读写控制电路与一个所述阵列单元对应，所述第二类读写控制电路，用于整体连接于对应的所述阵列单元的所有块数据总线与所述第一检错纠错单元、所述第二检错纠错单元之间。
根据本公开的一些实施例，所述若干个存储阵列包括沿所述第一方向依次设置的存储阵列U、存储阵列V和存储阵列W；每一所述存储阵列沿第二方向划分为两个阵列单元；所述存储阵列U、存储阵列V中位于所述第二方向上一个同侧的两个阵列单元共用相同的字线地址；
所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述该一个同侧的两个阵列单元中相同字线地址的存储单元。
根据本公开的一些实施例，所述存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址；所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第一侧的两个阵列单元中相同字线地址的存储单元；或者，
所述存储阵列U、存储阵列V中位于第二侧的两个阵列单元共用相同的字线地址，所述第一侧和所述第二侧为所述第二方向上的相对两侧；所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第二侧的两个阵列单元中相同字线地址的存储单元。
根据本公开的一些实施例，当所述存储阵列U、存储阵列V中位于所述第一侧的两个阵列单元共用相同的字线地址时，所述存储阵列U、存储阵列V中位于所述第二侧的两个阵列单元共用相同的字线地址；
所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第二侧的两个阵列单元；
当所述存储阵列U、存储阵列V中位于所述第二侧的两个阵列单元共用相同的字线地址时，所述存储阵列U、存储阵列V中位于所述第一侧的两个阵列单元共用相同的字线地址；
所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第一侧的两个阵列单元。
根据本公开的一些实施例，当所述存储阵列U、存储阵列V中位于所述第一侧的两个阵列单元共用相同的字线地址和/或位于所述第二侧的两个阵列单元共用相同的字线地址时，所述存储阵列W中位于所述第一侧和所述第二侧的两个阵列单元共用相同的字线地址；
所述存储阵列W对应的读写控制电路被关联配置为同时访问所述存储阵列W中所述第一侧和所述第二侧的阵列单元。
根据本公开的一些实施例，还包括：行译码电路，用于发出行译码信号，以定位选中不同所述阵列单元中的字线。
本公开的第二方面提供一种存储器，包括上述第一方面所述的存储块。
本公开所提供的一种存储块及存储器中，提供了一种结构性能优越的存储块，包括被划分为至少两个阵列单元的存储阵列，读写控制电路以及用于电连接读写控制电路和阵列单元的数据信号线。在单次读取操作时，每个读写控制电路，仅需要访问对应的存储阵列中的一个阵列单元即可，且读写控制电路与存储阵列中的各阵列单元是通过不同的数据信号线进行连接，由于每条数据信号线仅与一个阵列单元电连接即具有电接触点，因此，在单次读写操作过程中的电接触点减少，此存储块的寄生电阻和寄生电容也减少，从而有利于降低存储块的功耗。同时，由于读写控制电路设置在相邻的两个存储阵列之间，可以大大缩短读写控制电路到对应阵列单元的距离，从而减少了数据信号线的长度，提高了数据传输的效率。
另外，存储阵列用于存储数据和校验码；存储块还包括用于根据校验码对数据进行检错和/或纠错的检错纠错单元。由于检错纠错单元设置在读写控制电路所在的相邻的两个存储阵列之间，可以使读写控制电路与检错纠错单元之间布局紧凑，减少布局面积；同时还能缩短读写控制电路到检错纠错单元的距离，从而减少了二者之间数据信号线的长度，提高了数据传输的效率。
另外，相邻两条位线上的输出数据经灵敏放大器和选通开关分别进入本地数据总线O和本地数据总线E，使得物理上相邻的本地数据总线对应的数据分别进入第一检错纠错单元和第二检错纠错单元，因此处理相邻位置的位线对应的数据同时出错时，该错误也能够被纠正，进一步提高存储器的检错纠错能力。
另外，若干个存储阵列包括存储阵列U、存储阵列V和存储阵列W，每一存储阵列划分为两个阵列单元；通过设置存储阵列U、存储阵列V中位于至少一个同侧的两个阵列单元共用相同的字线地址，并且存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问存储阵列U、存储阵列V中该同侧的两个阵列单元，从而可以通过共用字线地址对两个存储阵列进行同时访问，减少字线开销，降低能耗。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为一种DARM的结构示意图；
图2为本公开一实施例提供的存储块的结构示意图；
图3为一种存储器的版图俯视结构示意图；
图4为一种存储器的结构示意图；
图5为本公开另一实施例提供的存储块的结构示意图；
图6为本公开又一实施例提供的存储块的结构示意图；
图7为图6中存储器的局部区域的信号线连接示意图；
图8为本公开又一实施例提供的存储块的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，目前的DRAM的功耗有待进一步降低。
现结合一种DRAM的结构示意图进行分析，图1为一种DARM的结构示意图。参考图1，DRAM由多个存储块(bank，也称为存储体)构成，每个存储块包括若干存储阵列，每一存储阵列包括存储器阵列(array)以及灵敏放大器阵列。对于DRAM，无论是DDR(2/3/4，等)系列，还是LPDDR(2/3/4/5)系列，均按照输出管脚(DQ)将存储块分为了高位一组和低位一组。也就是说，每个bank也可以对应分为2个half bank，其中一个half bank作为第一模块M1，第一模块M1提供低位输出管脚，另一个half bank作为第二模块M2，第二模块M2提供高位输出管脚。
数据信号线YIO用于在选中的存储器阵列与读写控制电路之间传输数据。无论是低位一组的half bank还是高位一组的half bank，为了顺利的完成读取以及写入操作，数据信号线YIO线与half bank中的每个存储器阵列均具有电接触点，产生寄生电容；数据信号线YIO线很长，导致寄生电阻较大，这将带来每次读写消耗的电量大的问题，导致DRAM功耗大。
进一步分析发现，寄生电阻以及寄生电容也是导致DARM功耗大的主要原因之一。对于数据信号线YIO，在每一次读取操作或者写入操作期间，每一组数据信号线YIO与每一个存储器阵列的电接触点均存在寄生电容以及寄生电阻。由于电接触点多，相应的寄生电阻以及寄生电阻大，导致DRAM功耗大。
本公开实施例提供一种结构性能优越的存储块，通过特殊结构的设计，减小存储块的寄生电阻以及寄生电容，从而降低存储块的功耗。
图2为本公开一实施例提供的存储块的结构示意图。
参考图2，本实施例中，存储块包括沿第一方向(X)设置的若干个存储阵列101，每一存储阵列101沿第二方向(Y)被划分为至少两个阵列单元(如阵列单元1101、阵列单元1102)，第一方向X与第二方向Y互相垂直；读写控制电路102(若干个)，读写控制电路102设置在相邻的两个存储阵列之间101之间(如图2中存储阵列V和存储阵列W，为了便于图示，图中的U、V和W分别代表存储阵列U、存储阵列V和存储阵列W)；数据信号线YIO(若干个，如YIO1和YIO2)，用于电连接读写控制电路102和阵列单元；其中，每一存储阵列101的不同阵列单元通过不同的数据信号线YIO电连接至不同的读写控制电路102。可以知道的是，上述第一方向X为字线WL延伸的方向，第二方向Y为位线BL延伸的方向。
本公开实施例提供一种结构性能优越的存储块，包括被划分为至少两个阵列单元的存储阵列，读写控制电路以及用于电连接读写控制电路和阵列单元的数据信号 线。在单次读取操作时，每个读写控制电路，仅需要访问对应的存储阵列中的一个阵列单元即可，且读写控制电路与存储阵列中的各阵列单元是通过不同的数据信号线进行连接，由于每条数据信号线仅与一个阵列单元电连接即具有电接触点，因此，在单次读写操作过程中的电接触点减少，此存储块的寄生电阻和寄生电容也减少，从而有利于降低存储块的功耗。同时，由于读写控制电路设置在相邻的两个存储阵列之间，可以大大缩短读写控制电路到对应阵列单元的距离，从而减少了数据信号线的长度，提高了数据传输的效率。
以下将结合附图对本实施例进行详细说明。需要说明的是，为了便于说明，以下实施例以存储块包括3个存储阵列101，4个读写控制电路102为例进行说明，可以知道的是，在本公开的实施例中，存储阵列101和读写控制电路102的数量也可以为其他数量，可以根据实际需求进行设置。同时为了便于图示，图2和图5中标示的粗实线符号和粗虚线符号均表示电连接即具有电接触点，粗实线和粗虚线的区别仅是连接的存储器阵列的排序位置不同，其中，粗实线与排序为奇数的存储器阵列连接、粗虚线与排序为偶数的存储器阵列连接。
如图2所示，本实施例中，存储块可包括3个存储阵列U、V和W，每一存储阵列101沿第二方向Y划分为两个阵列单元(如阵列单元1101和阵列单元1102)；4个读写控制电路102位于任意两个存储阵列101之间，每个读写控制电路102可以和3个存储阵列101中任意一个或者多个阵列单元电连接，但需要满足每一存储阵列101的不同阵列单元是通过不同的数据信号线YIO电连接至不同的读写控制电路102。
例如，4个读写控制电路102位于存储阵列V和存储阵列W之间，靠近存储阵列V的2个读写控制电路102中的每个读写控制电路102均与存储阵列U中的一个阵列单元和存储阵列V中的一个阵列单元连接。其中，一个读写控制电路102与存储阵列V和存储阵列U中的阵列单元1101连接，且该读写控制电路102通过数据信号线YIO1连接该两个阵列单元1101中排序为奇数的存储器阵列，通过数据信号线YIO2连接该两个阵列单元1101中排序为偶数的存储器阵列；同理，另一个读写控制电路102与存储阵列V和存储阵列U中两个阵列单元1102连接，且该读写控制电路102通过数据信号线YIO1连接该两个阵列单元1102中排序为奇数的存储器阵列，通过数据信号线YIO2连接该两个阵列单元1102中排序为偶数的存储器阵列。靠近存储阵列W的2个读写控制电路102中的每个读写控制电路102均与存储阵列W中的一个阵列单元连接。其中，一个读写控制电路102与存储阵列W中的阵列单元1101连接；该读写控制电路102同时通过数据信号线YIO1和数据信号线YIO2连接该阵列单元1101中排序为奇数和偶数的存储器阵列；同理，另一个读写控制电路102与存储阵列W中的阵列单元1102连接；该读写控制电路102同时通过数据信号线YIO1和数据信号线YIO2连接该阵列单元1102中排序为奇数和偶数的存储器阵列。
在实际布线设计时，可以设计距离较近的阵列单元和读写控制电路102连接，以降低布线成本。需要说明的是，一个阵列单元不止与一条YIO连接，数据信号线YIO1、数据信号线YIO2仅是泛指与阵列单元中一个存储器阵列连接的其中一条数据信号线。
每一存储阵列101包括存储器阵列(如图2中所示编号0、1、2、……)以及灵敏放大器阵列(Sense Amplifier，SA)(图2中未画出，请参考图1)。存储器阵列中包括多个存储单元(cell)，用于存储数据；灵敏放大器阵列用于放大存储器阵列的输出信号。每个阵列单元内包括的存储器阵列和灵敏放大器阵列的数量可以相同也可以不同。
相较于采用一个存储阵列101中所有的存储器阵列均与数据信号线电连接并通过 数据信号线电连接至读写控制电路的方案而言，本实施例中，在单次读取操作或者写入操作中，数据信号线仅与存储阵列101中的一个阵列单元连接，即数据信号线仅电连接部分的存储器阵列，使得电接触点的数量减少，如此，不仅能够减小存储块中的寄生电路以及寄生电容，且数据信号线上挂的负载都明显减少，因而能够显著的降低存储块的功耗。
此外，由于采用不同的数据信号线与不同的阵列单元连接，因此可以减小数据信号线的长度，例如图2中，各存储阵列101的两个阵列单元中，阵列单元1101与阵列单元1102采用两段相互断开的数据信号线(数据信号线YIO1和数据信号线YIO2也分别被分为两段)。即：存储阵列中阵列单元1101一侧的数据信号线仅电连接阵列单元1101，而无需延伸至阵列单元1102一侧；同理，存储阵列中阵列单元1102一侧的数据信号线仅电连接阵列单元1102，而无需延伸至阵列单元1101一侧，从而减小了数据信号线的长度，从而有利于进一步的减小该数据信号线的电阻以及消耗的功耗，从而进一步的降低存储块的功耗。
综上所述，本实施例提供的存储块每次消耗的电量小，相应的存储块具有低功耗的优势。
在相关技术中，对于DRAM来说，在数据存储的过程中数据常常会出现错误，因此需要ECC(Error Checking and Correcting，错误检测和纠正)技术来保证数据存储的正确性，相关技术通常是利用在一定长度的有效数据位的基础上增加校验位来检测和纠正出错的数据。相关技术的ECC技术仍存在不足。
分析发现，如果数据中有一位错误，ECC校验技术不但能发现而且可以对其更正，ECC校验还可以发现2～4位错误，然而ECC检验难以对2位及以上的错误进行纠正。也就是说，ECC校验技术虽然可以同时检测和纠正单一比特错误，但如果同时检测出两个及以上比特的数据有错误，目前的ECC校验技术则无能为力。此外，进一步分析发现，目前处于相邻位置的两个数据同时出现错误的概率较大。进一步分析发现，导致这一问题的主要原因的分析如下：
图3为一种存储器的版图俯视结构示意图，存储器包括：多个阵列式排布的有源区10；字线12、位线11以及与有源区电连接的电容13。存储器中存在相邻单元桥连(celltocellbridge)的缺陷，或称为相邻两比特错误，例如相邻有源区10对应的电容91和电容92之间发生桥连等，如图3中虚线框所示，电容91通过晶体管与位线BL3连接，电容92通过晶体管与位线BL2连接。随着存储器工艺尺寸越来越小，这种缺陷的发生概率也越来越大。
图4为一种存储器的结构示意图，存储器包括：存储阵列，由存储单元14组成，每一存储单元14连接位线BL以及字线WL；列选择信号单元，在图4中标示为CSL<n-1>、CSL<n>以及CSL<n+1>，每一列选择信号单元包括多条列选择信号线，每一列选择信号线通过开关控制存储阵列中对应的位线BL与本地数据总线连接，开关的控制信号来源于列译码电路(在图4中未示出)，用于决定位线BL上的数据是否被传到本地数据总线，例如列选择信号单元CSL<n>包括8条列选择信号线，8条列选择信号线通过开关控制存储阵列中的位线BL连接与本地数据总线连接；本地数据总线，在图4中标示为LIO，其中LIO：O<3:0>标示编号为奇数的本地数据总线，LIO：E<3:0>标示编号为偶数的本地数据总线；块数据总线，在图4中标示为YIO，其中YIO：O<3:0>标示编号为奇数的块数据总线，YIO：E<3:0>标示编号为偶数的块数据总线，本地数据总线通过本地转换电路(如本地感测放大电路，图4中未示出)连接块数据总线，图4中以弧形曲线示意出YIO：E<3:0>与LIO：E<3:0>之间交互，YIO：O<3:0>与LIO：O<3:0>之间交互。
结合图3及图4，块数据总线YIO：E<3:0>以及YIO：O<3:0>连接至同一检错纠 错单元15。若两个存储单元14对应的两个位线BL正好连接同一列译码电路，则有两个错误同时发生在同一个读出时间点，例如图3中存储单元91和存储单元92(在图3中91和92表示电容，而在图4中91和92表示存储单元，存储单元通常包括电容和晶体管，这里将其标示为相同，是为了结合图3和图4来说明相邻两比特错误)同时出错，对应的位线BL2和BL3都通过列选择信号单元CSL<n>将其数据传输至本地数据线LIO：O<3:0>和本地数据线LIO：E<3:0>，然后经本地转换电路将数据传输至YIO：E<3:0>和YIO：O<3:0>，那么就同时有两比特错误进入检错纠错单元15。目前使用的ECC(例如，对于128bits(数据位)+8bits(校验位)的ECC，只能完成一比特的纠正)，则无法对上述两比特错误进行纠正。
本公开另一实施例还提供一种存储块，该存储块与上一实施例提供的存储块大致相同，区别在于，若干个存储阵列101，用于存储数据和校验码；存储块还包括：若干检错纠错单元，设置在相邻的两个存储阵列101之间，与若干读写控制电路102电连接，用于根据校验码对数据进行检错和/或纠错；其中，在读取操作时，读写控制电路102读出的数据和校验码被分为至少两部分，且读写控制电路102被配置为将每部分传输至不同的检错纠错单元。由于读写控制电路102在每次读取操作时将阵列单元的输出数据分为至少两部分，且读写控制电路102将每部分传输至不同的检错纠错单元，使得阵列单元的输出数据中同时出现一个以上错误时，不同的错误能够被不同的检错纠错单元进行纠正，从而使得存储块能够对一个以上的错误进行纠正，提高存储块的检错纠错能力。以下将结合附图对本实施提供的存储块进行说明，需要说明的是，与前一实施例相同或者相应的部分，请参考前一实施例的详细说明，以下将不做详细赘述。
如图5所示，存储块中若干检错纠错单元103的数量可以为两个，且贴近读写控制电路102布设，分别与上述4个读写控制电路102电连接，用于根据每次从阵列单元中读取的校验码对读取的数据进行检错和/或纠错。其中，在读取操作时，读写控制电路102从阵列单元读出的数据和校验码被分为至少两部分(如随机分配，或者按数据所在存储器阵列的序号奇偶性分配)，且读写控制电路102被配置为将其中一部分传输至一个检错纠错单元，将剩余部分传输至另一个检错纠错单元。
例如图5中，每一个读写控制电路102将从阵列单元中读取的所有校验码和数据都分成两部分，且这两部分中，一部分被该读写控制电路102传输至靠近阵列单元1101的检错纠错单元103，剩余部分被该读写控制电路102传输至靠近阵列单元1102的检错纠错单元1032。
由于写控制电路102在每次读取操作时将阵列单元的输出数据分为至少两部分，且读写控制电路102将每部分传输至不同的检错纠错单元，使得阵列单元的输出数据中同时出现一个以上错误时，不同的错误能够被不同的检错纠错单元进行纠正，从而使得存储块能够对一个以上的错误进行纠正，提高存储块的检错纠错能力，提高存储器的读写性能。
本实施例的存储块还包括：行译码电路(图未示)，用于发出行译码信号，以定位选中不同阵列单元中的字线。
例如，当行译码信号定位选中存储阵列U和存储阵列V中的阵列单元1101时，位于存储阵列U和存储阵列V中阵列单元1101一侧的数据信号线YIO1或YIO2将读取相应阵列单元1101中的数据。
图6为本公开又一实施例提供的一种存储块，在前述任一存储块结构的基础上，若干检错纠错单元103数量为两个，分别可以为：
第一检错纠错单元1031，通过读写控制电路102与每个阵列单元均连接，用于对阵列单元的一部分输出数据进行检错纠错；第二检错纠错单元1032，通过读写控制 电路102与每个阵列单元均连接，用于对阵列单元的剩余输出部分数据进行检错纠错。
本示例中，存储阵列的排布可参考图3和图4。本实施例中，以存储阵列U输出数据为136bits作为示例，其中，128bits数据为有效数据(存储器需要通过存储器接口与外部控制器交互的数据)，8bits数据为经过第一检错纠错单元1031和第二检错纠错单元1032处理后产生的校验码。需要说明的是，存储器包括写数据操作和读数据操作，当向存储器中的存储阵列进行写数据操作时，存储器接口接收的数据经过ECC模块(例如图6中的第一检错纠错单元1031和第二检错纠错单元1032)进行处理，例如进入ECC模块为128bits数据，这128bits数据同样称为有效数据，而ECC模块输出的数据则为136bits(128bits有效数据+8bits校验码)，其中128bits数据为有效数据，8bits则为ECC模块产生的校验码，这136bits都会存储到存储阵列U的存储阵列中，可以称ECC模块针对写数据操作时为编码过程；当从存储器中的存储阵列进行读数据操作时，则从存储阵列U同样输出136bits(128bits有效数据+8bits校验码)数据，这136bits同时进入ECC模块，ECC模块此时执行的是和写入相反的算法，可以称ECC模块针对读数据操作时为解码过程，ECC模块通过对128bits有效数据进行解码运算，将解码运算产生的结果与8bits校验码进行比较，从而判断输出的128bits有效数据是否存在错误，如果存在每64bits中只有1bit出错(一比特错误)，ECC模块还可以将该一比特错误纠正。
继续参考图6，在本实施例中，例如，以从存储阵列U和存储阵列V中读出272bits数据(256bits存储数据+16bits校验码)为例，从存储阵列U中读出的136bits(128bits存储数据+8bits校验码)的输出数据分别输出到第一检错纠错单元1031和第二检错纠错单元1032，从存储阵列V中读出的136bits(128bits存储数据+8bits校验码)的输出数据分别输出到第一检错纠错单元1031和第二检错纠错单元1032。提供一对比实施例，存储阵列U将138bits(128bits存储数据+8bits校验码)的输出数据输出到第一检错纠错单元1031，存储阵列V将136bits(128存储数据+8bits校验码)的输出数据输出到第二检错纠错单元1032。相比较而言，由于存储阵列U(或存储阵列V)的输出数据部分输入至第一检错纠错单元1031进行检错纠错，其余输出数据输入至第二检错纠错单元1032进行检错纠错，使得存储阵列U(或存储阵列V)的输出数据中同时出现一个以上错误时(例如两比特错误)，不同的错误能够被第一检错纠错单元1031或者第二检错纠错单元1032进行纠正，从而使得存储器能够对一个以上的错误进行纠正，提高存储器的检错纠错能力。
本实施例中，第一检错纠错单元1031的接收的数据位数和第二检错纠错单元1032的接收的数据位数相同。在一个例子中，第一检错纠错单元1031接收的数据位数和第二检错纠错单元1032接收的数据位数均为128bits+8bits，其中，128bits为存储阵列U和存储阵列V写入或者读取的有效数据，8bits为第一检错纠错单元1031或第二检错纠错单元1032产生的校验码。。
此外，第一检错纠错单元1031的内部检错算法与第二检错纠错单元1032的内部检错算法相同，这样，有利于降低存储器的设计难度。
以第一检错纠错单元1031作为示例，每次数据写入时，第一检错纠错单元1031使用内部检错算法对有效数据(128bits)进行计算，计算得到校验位(8bits)，记为第一校验位，然后将有效数据(128bits)和校验位(8bits)同时写入存储阵列101；当这些数据从存储阵列101中读出时，采用同一算法再次对有效数据(128bits)计算得到校验位(8bits)，记为第二校验位，用第二校验位和直接读取出来的第一校验位进行比较，如果结果相同，说明数据是正确的，反之说明有错误，第一检错纠错单元1031可以从逻辑上检测出错误；当只出现一比特错误的时候，第一检错纠错单元 1031可以把错误改正过来而不影响存储器读取操作。例如，当128bits的第3位出现的“0”为出错比特时，第一检错纠错单元1031将第3位的“0”纠正为“1”。
关于第二检错纠错单元1032的工作原理可参考第一检错纠错单元1031，以下将不做赘述。
存储阵列U中的部分输出数据输入至第一检错纠错单元1031进行检错纠错，其余部分输出数据输入至第二检错纠错单元1032进行检错纠错，这样，在同一存储阵列U中可能出现的相邻两比特错误分别被放在不同的ECC单元里，由于这两个错误的数据分别被第一检错纠错单元1031和第二检错纠错单元1032处理，即第一检错纠错单元1031和第二检错纠错单元1032处理均只处理一个错误，是因此在存储器的层面看，该存储器能够同时纠正这两个错误。
关于存储阵列V、存储阵列W中出现错误时的检错纠错机理，可参考存储阵列U的相应说明，在此不再赘述。
本实施例中，存储阵列U、V的存储容量以及W的存储容量相同。在其他实施例中，存储阵列U、V、W的存储容量也可以不完全相同。
结合参考图6及图7，图7为图6中存储阵列101的一个长方格内粗线代表的局部区域的信号线连接示意图(以存储阵列U展开示意，粗实线仅与奇数方格有连接，粗虚线仅与偶数方格有连接，且存储阵列V、W同存储阵列U)，本地数据总线LIO通过列选择信号单元109与多个灵敏放大器(未示出)连接，且灵敏放大器与存储单元105的位线BL一一对应设置。列选择信号单元109包括选通开关，列选择信号(columnselectsignal)控制选通开关的导通或关断，当选通开关导通时，灵敏放大器与本地数据总线LIO交互数据，当选通开关关断时，灵敏放大器与本地数据总线LIO不再交互数据。此外，相邻位线BL上的输出数据经灵敏放大器和列选择信号单元109分别进入本地数据总线O和本地数据总线E。为了便于区别，图7中LIO:E示意出了本地数据总线E，LIO:O示意出了本地数据总线O，以CSL<n-1>、CSL<n>以及CSL<n+1>示出了列选择信号单元，选通开关位于列选择信号单元中(未示出)，敏感放大器位于位线BL两侧(未示出)。本地数据总线E又与块数据总线E通过本地转换电路(未示出)交互数据，本地数据总线O又与块数据总线O通过本地转换电路(未示出)交互数据。在图7中，以带箭头的实线YIO:E示意出了块数据总线E，以带箭头的虚线YIO:O示意出了块数据总线O。
继续参考图6，以YIO1_O示意块数据总线O的一条，以YIO1_E示意块数据总线E的一条，在一种实施例中，图7中的YIO:E可理解为其中一条YIO1_E，图7中的YIO:O可理解为其中一条YIO1_O。YIO1_O经过块放大器(未示出)以及读写控制电路102后到第一检错纠错单元1031，YIO1_E经过块放大器(未示出)以及读写控制电路102后到第二检错纠错单元1032。同理，YIO2_O示意块数据总线O的一条，YIO2_E示意块数据总线E的一条，在一种实施例中，图7中的YIO:E可理解为其中一条YIO2_E，图7中的YIO:O可理解为其中一条YIO2_O。YIO2_O经过块放大器(未示出)以及读写控制电路102后到第一检错纠错单元1031，YIO2_E经过块放大器(未示出)以及读写控制电路102后到第二检错纠错单元1032。
继续参考图6，YIO_O的数据进入第一检错纠错单元1031，YIO_E的数据进入第二检错纠错单元1032。本实施例中，存储阵列U、V、W均包括本地转换电路(LocalSA，未示出)和偶数条本地数据总线，本地数据总线分为本地数据总线O和本地数据总线E，本地数据总线O通过本地转换电路连接块数据总线O，本地数据总线E通过本地转换电路连接块数据总线E。
需要说明的是，将本地数据总线按照自然数从零依次编号，编号为奇数的本地数据总线定义为本地数据总线O，编号为偶数的本地数据总线定义为本地数据总线 E；或者说，物理位置相邻的存储阵列对应的本地数据总线中，处于奇数位置的本地数据总线定义为本地数据总线O，处于偶数位置的本地数据总线定义为本地数据总线E。
由于物理上相邻的数据放在不同的检错纠错单元中，即分别进入第一检错纠错单元1031和第二检错纠错单元1032中，当有两比特相邻错误发生的时候，由于这两比特错误分别在不同的检错纠错单元中进行纠错，因此能够同时处理掉这两比特错误。可以理解的是，即使工艺尺寸不断缩小，相邻电容之间发生桥连的风险增加，但是由于相邻电容对应的数据进入到不同的检错纠错单元中进行纠错，因此即使工艺尺寸不断缩小，仍能保证物理上相邻的两比特数据的错误均能被纠正。
继续参考图6，存储阵列U中的存储阵列的排布按照自然数从0开始编号，块数据总线与编号为偶数的存储阵列电连接，例如，存储阵列包括存储单元、本地数据总线E、本地数据总线O和本地转换电路，块数据总线通过本地转换电路与本地数据总线E连接；块数据总线通过本地转换电路与本地数据总线O连接，图6中以粗线符号标示了块数据总线与存储阵列的连接关系。有关存储阵列V、W的块数据总线的连接关系的说明，可参考关于存储阵列U的相应描述，以下将不做赘述。
可以理解的是，在一个例子中，块数据总线为2*4*(16*N)条，本地数据总线为2*4*M*(16*N)条；块数据总线O为4*(16*N)条，块数据总线E为4*(16*N)条；本地数据总线O为4*M*(16*N)条，本地数据总线E为4*M*(16*N)条；1条块数据总线O与M条本地数据总线O相对应，1条块数据总线E与M条本地数据总线E相对应；本地数据总线以相邻的4条为一组被划分为M*(16*N)组的本地数据总线O和M*(16*N)组的本地数据总线E。其中，M和N为大于或等于1的自然数。以M和N均为1为例，块数据总线为2*4*16条，本地数据总线为2*4*16条，块数据总线O为4*16条，块数据总线E为4*16条，本地数据总线O为4*16条，本地数据总线E为4*16条，共16组本地数据总线O和16组本地数据总线E。
在一个例子中，如图6所示，每个阵列单元对应的数据信号线包括偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O，如YIO1_O或YIO2_O)通过读写控制电路102连接第一检错纠错单元1031，编号为偶数的块数据总线E(记为YIO_E，如YIO1_E或YIO2_E)通过读写控制电路102连接第二检错纠错单元1032；存储阵列U中的每一阵列单元包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)通过读写控制电路102连接第一检错纠错单元1031，编号为偶数的块数据总线E(记为YIO_E)通过读写控制电路102连接第二检错纠错单元1032；存储阵列V中的每一阵列单元包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)通过读写控制电路102连接第一检错纠错单元1031，编号为偶数的块数据总线E(记为YIO_E)通过读写控制电路102连接第二检错纠错单元1032；存储阵列W中的每一阵列单元包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)通过读写控制电路102连接第一检错纠错单元1031，编号为偶数的块数据总线E(记为YIO_E)通过读写控制电路102连接第二检错纠错单元1032。
这样，存储阵列U、V、W的块数据总线O(YIO_O)的数据通过读写控制电路102进入第一检错纠错单元1031进行检错纠错；存储阵列U、V、W的块数据总线E(YIO_E)的数据通过读写控制电路102进入第二检错纠错单元1032进行检错纠错。
在另一例子中，每个阵列单元对应的数据信号线包括偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)连接第二检错纠错单元1032，编号为偶数的块数据总线E(记为YIO_E)连接第一检错纠错 单元1031。存储阵列U中的每一阵列单元包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)连接第二检错纠错单元1032，编号为偶数的块数据总线E(记为YIO_E)连接第一检错纠错单元1031；存储阵列V中的每一阵列单元包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)连接第二检错纠错单元1032，编号为偶数的块数据总线E(记为YIO_E)连接第一检错纠错单元1031；存储阵列W中的每一阵列单元包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO_O)连接第二检错纠错单元1032，编号为偶数的块数据总线E(记为YIO_E)连接第一检错纠错单元1031。
这样，存储阵列U、V、W的块数据总线O(YIO_O)的数据进入第二检错纠错单元1032进行检错纠错；存储阵列U、V、W的块数据总线E(YIO_E)的数据进入第一检错纠错单元1031进行检错纠错。
本实施例提供的存储块，由于同一阵列单元的输出数据分别输入至不同的检错纠错单元中，即部分输出数据输入至第一检错纠错单元1031进行检错纠错，其余部分输出数据输入至第二检错纠错单元1032进行检错纠错，这样如果同时存在两比特数据出错，则第一检错纠错单元1031和第二检错纠错单元1032能够分别对两比特中的一比特数据进行纠正，从而提高存储器的检错纠错能力。
继续参考图6，本实施例中，读写控制电路102为多个，且分为第一类读写控制电路102和第二类读写控制电路102；
每个第一类读写控制电路102与两个阵列单元对应，第一类读写控制电路102包括：第一读写控制单元1021和第二读写控制单元1022；第一读写控制单元1021连接于对应的阵列单元的奇数的块数据总线O与第一检错纠错单元1031之间，第二读写控制单元1022连接于对应的阵列单元的偶数的块数据总线E与第二检错纠错单元1032之间；
每个第二类读写控制电路102与一个阵列单元对应，第二类读写控制电路102，用于整体连接于对应的阵列单元的所有块数据总线(奇数的块数据总线O+偶数的块数据总线E)与第一检错纠错单元1031、第二检错纠错单元1032之间。
参考图6，本实施例中，在保留部分读写控制电路102整体接收阵列单元的奇数的块数据总线O和偶数的块数据总线E传输的数据(图6中靠近阵列单元W的两个读写控制电路102)外，还设计将一个读写控制电路102拆分为两个读写控制单元，其中一个读写控制单元1021负责专门接收阵列单元的奇数的块数据总线O传输的数据，另一个读写控制单元1022负责专门接收同一阵列单元的偶数的块数据总线E传输的数据。
通过专门设置分别接收阵列单元奇数的块数据总线O和偶数的块数据总线E传输的数据的两个读写控制单元，可以提高对数据的分化管理，节省设计成本。
图8为本公开另一实施例提供的存储块的一种结构示意图。
在本公开的一些实施例中，存储阵列U、存储阵列V和存储阵列W的两个阵列单元的输出数据分别对应为高位数据和低位数据，例如存储阵列U中阵列单元1101存储高位数据，阵列单元1102存储低位数据；存储阵列V中存储器阵列排序数较小一侧的阵列单元1101存储低位数据，阵列单元1102存储高位数据；存储阵列W中阵列单元1101存储高位数据，阵列单元1102存储低位数据。这样，由于存储阵列U、存储阵列V和存储阵列W的两个阵列单元输出的数据包括低位数据和高位数据，因此单次访问只会访问存储阵列U、存储阵列V或存储阵列W中的一个存储高位数据的阵列单元和另一个位于不同存储阵列101中的一个存储低位数据的阵列单元，从而降低存储器的功耗。
参考图8，上述若干个存储阵列101(除存储阵列101以外的其余结构可参见前述实施例中的记载，在此不做赘述)包括沿第一方向依次设置的存储阵列U、存储阵列V和存储阵列W；每一存储阵列沿第二方向划分为两个阵列单元；存储阵列U、存储阵列V中位于第二方向上一个同侧的两个阵列单元共用相同的字线地址；存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问存储阵列U、存储阵列V中该一个同侧的两个阵列单元中相同字线地址的存储单元。
例如，可以是存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址；存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问存储阵列U、存储阵列V中第一侧的两个阵列单元中相同字线地址的存储单元；或者，存储阵列U、存储阵列V中位于第二侧的两个阵列单元共用相同的字线地址，第一侧和第二侧为第二方向上的相对两侧；存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中第二侧的两个阵列单元中相同字线地址的存储单元。
例如，参考图8，以存储阵列U、存储阵列V中阵列单元1101所在一侧设定为第一侧，阵列单元1102所在一侧设定为第二侧，且存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址为例，此时存储阵列U、V中两个阵列单元1101可共用相同的字线地址，即同一字线地址可以访问字线地址相同的存储阵列。例如访问1对应的字线地址可以同时访问存储阵列U、V中存储器阵列编号为3中的数据。
继续参考图8，当存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线时，存储阵列U、存储阵列V中位于第二侧的两个阵列单元共用相同的字线地址；存储阵列U、存储阵列V对应的读写控制电路102被关联配置为同时访问存储阵列U、存储阵列V中第二侧的两个阵列单元；当存储阵列U、存储阵列V中位于第二侧的两个阵列单元共用相同的字线地址时，存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址；存储阵列U、存储阵列V对应的读写控制电路102被关联配置为同时访问存储阵列U、存储阵列V中第一侧的两个阵列单元。
参考图8，以存储阵列U、存储阵列V中阵列单元1101所在一侧设定为第一侧，阵列单元1102所在一侧设定为第二侧，且存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址为例，当存储阵列U、存储阵列V中两个阵列单元1101共用相同的字线地址时，存储阵列U、存储阵列V中两个阵列单元1102也可共用相同的字线地址，即同一字线可以访问字线地址相同的存储器阵列。例如访问2对应的字线地址可以同时访问存储阵列U、V中存储器阵列编号为20中的数据。
继续参考图8，当存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址和/或位于第二侧的两个阵列单元共用相同的字线地址时，存储阵列W中位于第一侧和第二侧的两个阵列单元共用相同的字线地址；存储阵列W对应的读写控制电路被关联配置为同时访问存储阵列W中第一侧和第二侧的阵列单元。
参考图8，以存储阵列U、存储阵列V中阵列单元1101所在一侧设定为第一侧，阵列单元1102所在一侧设定为第二侧，且存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址为例，当存储阵列U、存储阵列V中两个阵列单元1101共用相同的字线地址时，存储阵列W中的两个阵列单元(阵列单元1101和阵列单元1102)也可共用相同的字线地址，即同一字线可以访问字线地址相同的存储器阵列。例如访问3对应的字线地址可以同时访问存储阵列W中阵列单元1101，以及阵列单元1102中存储器阵列编号为38中的数据。
与前述实施例相比，本实施例提供的存储块通过配置各存储阵列对应的读写控制电路的访问状态，可以实线两个阵列单元中的数据按字线地址相同而能够同时访 问两个阵列单元中的数据，实线灵活的访问数据组合。
基于上述各实施例中的存储块，本实施例还提供了一种存储器，该存储器包括上述任一或者至少两种组合实施例中的存储块。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的一种存储块以及存储器，包括被划分为至少两个阵列单元的存储阵列，读写控制电路以及用于电连接读写控制电路和阵列单元的数据信号线。在单次读取操作时，每个读写控制电路，仅需要访问对应的存储阵列中的一个阵列单元即可，且读写控制电路与存储阵列中的各阵列单元是通过不同的数据信号线进行连接，由于每条数据信号线仅与一个阵列单元电连接即具有电接触点，因此，在单次读写操作过程中的电接触点减少，此存储块的寄生电阻和寄生电容也减少，从而有利于降低存储块的功耗。同时，由于读写控制电路设置在相邻的两个存储阵列之间，可以大大缩短读写控制电路到对应阵列单元的距离，从而减少了数据信号线的长度，提高了数据传输的效率。另外，存储阵列用于存储数据和校验码；存储块还包括用于根据校验码对数据进行检错和/或纠错的检错纠错单元。由于检错纠错单元设置在读写控制电路所在的相邻的两个存储阵列之间，可以使读写控制电路与检错纠错单元之间布局紧凑，减少布局面积；同时还能缩短读写控制电路到检错纠错单元的距离，从而减少了二者之间数据信号线的长度，提高了数据传输的效率。另外，相邻两条位线上的输出数据经灵敏放大器和选通开关分别进入本地数据总线O和本地数据总线E，使得物 理上相邻的本地数据总线对应的数据分别进入第一检错纠错单元和第二检错纠错单元，因此处理相邻位置的位线对应的数据同时出错时，该错误也能够被纠正，进一步提高存储器的检错纠错能力。另外，若干个存储阵列包括存储阵列U、存储阵列V和存储阵列W，每一存储阵列划分为两个阵列单元；通过设置存储阵列U、存储阵列V中位于至少一个同侧的两个阵列单元共用相同的字线地址，并且存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问存储阵列U、存储阵列V中该同侧的两个阵列单元，从而可以通过共用字线地址对两个存储阵列进行同时访问，减少字线开销，降低能耗。

Claims (15)

  1. 一种存储块，包括：
    沿第一方向设置的若干个存储阵列，每一所述存储阵列沿第二方向被划分为至少两个阵列单元，所述第一方向与所述第二方向互相垂直；
    读写控制电路，所述读写控制电路设置在相邻的两个所述存储阵列之间；
    数据信号线，用于电连接所述读写控制电路和所述阵列单元；
    其中，每一所述存储阵列的不同阵列单元通过不同的所述数据信号线电连接至不同的所述读写控制电路。
  2. 如权利要求1所述的存储块，所述若干个存储阵列，用于存储数据和校验码；所述存储块还包括：
    若干检错纠错单元，设置在所述相邻的两个所述存储阵列之间，与所述若干读写控制电路电连接，用于根据所述校验码对所述数据进行检错和/或纠错。
  3. 如权利要求2所述的存储块，其中，所述若干检错纠错单元至少包括：
    第一检错纠错单元，通过所述读写控制电路与每个所述阵列单元均连接，用于对所述阵列单元的一部分输出数据进行检错纠错；第二检错纠错单元，通过所述读写控制电路与每个所述阵列单元均连接，用于对所述阵列单元的剩余输出部分数据进行检错纠错。
  4. 如权利要求3所述的存储块，其中，每个所述阵列单元对应的数据信号线包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O连接所述第一检错纠错单元，编号为偶数的块数据总线E连接所述第二检错纠错单元。
  5. 如权利要求4所述的存储块，其中，每个所述阵列单元均包括本地转换电路和偶数条本地数据总线，所述本地数据总线分为本地数据总线O和本地数据总线E，所述本地数据总线O通过所述本地转换电路连接所述块数据总线O，所述本地数据总线E通过所述本地转换电路连接所述块数据总线E。
  6. 如权利要求5所述的存储块，其中，每条所述本地数据总线通过选通开关与多个灵敏放大器连接，所述灵敏放大器与所述存储阵列中的位线一一对应设置。
  7. 如权利要求6所述的存储块，其中，相邻两条所述位线上的所述输出数据经所述灵敏放大器和所述选通开关分别进入所述本地数据总线O和所述本地数据总线E。
  8. 如权利要求7所述的存储器，其中，所述块数据总线为2*4*(16*N)条，所述本地数据总线为2*4*M*(16*N)条；所述块数据总线O为4*(16*N)条，所述块数据总线E为4*(16*N)条；所述本地数据总线O为4*M*(16*N)条，所述本地数据总线E为4*M*(16*N)条；1条所述块数据总线O与M条所述本地数据总线O相对应，1条所述块数据总线E与M条所述本地数据总线E相对应；所述本地数据总线以相邻的4条为一组被划分为M*(16*N)组的所述本地数据总线O和M*(16*N)组的所述本地数据总线E。
  9. 如权利要求4-8中任一项所述的存储块，其中，所述读写控制电路为多个，且分为第一类读写控制电路和第二类读写控制电路；
    每个所述第一类读写控制电路与两个所述阵列单元对应，所述第一类读写控制电路包括：第一读写控制单元和第二读写控制单元；所述第一读写控制单元连接于对应的所 述阵列单元的所述奇数的块数据总线O与所述第一检错纠错单元之间，所述第二读写控制单元连接于对应的所述阵列单元的所述偶数的块数据总线E与所述第二检错纠错单元之间；
    每个所述第二类读写控制电路与一个所述阵列单元对应，所述第二类读写控制电路，用于整体连接于对应的所述阵列单元的所有块数据总线与所述第一检错纠错单元、所述第二检错纠错单元之间。
  10. 如权利要求1所述的存储块，其中，所述若干个存储阵列包括沿所述第一方向依次设置的存储阵列U、存储阵列V和存储阵列W；每一所述存储阵列沿第二方向划分为两个阵列单元；所述存储阵列U、存储阵列V中位于所述第二方向上一个同侧的两个阵列单元共用相同的字线地址；
    所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述该一个同侧的两个阵列单元中相同字线地址的存储单元。
  11. 如权利要求10所述的存储块，其中，所述存储阵列U、存储阵列V中位于第一侧的两个阵列单元共用相同的字线地址；所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第一侧的两个阵列单元中相同字线地址的存储单元；或者，
    所述存储阵列U、存储阵列V中位于第二侧的两个阵列单元共用相同的字线地址，所述第一侧和所述第二侧为所述第二方向上的相对两侧；所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第二侧的两个阵列单元中相同字线地址的存储单元。
  12. 如权利要求11所述的存储块，其中，当所述存储阵列U、存储阵列V中位于所述第一侧的两个阵列单元共用相同的字线地址时，所述存储阵列U、存储阵列V中位于所述第二侧的两个阵列单元共用相同的字线地址；
    所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第二侧的两个阵列单元；
    当所述存储阵列U、存储阵列V中位于所述第二侧的两个阵列单元共用相同的字线地址时，所述存储阵列U、存储阵列V中位于所述第一侧的两个阵列单元共用相同的字线地址；
    所述存储阵列U、存储阵列V对应的读写控制电路被关联配置为同时访问所述存储阵列U、存储阵列V中所述第一侧的两个阵列单元。
  13. 如权利要求12所述的存储块，其中，当所述存储阵列U、存储阵列V中位于所述第一侧的两个阵列单元共用相同的字线地址和/或位于所述第二侧的两个阵列单元共用相同的字线地址时，所述存储阵列W中位于所述第一侧和所述第二侧的两个阵列单元共用相同的字线地址；
    所述存储阵列W对应的读写控制电路被关联配置为同时访问所述存储阵列W中所述第一侧和所述第二侧的阵列单元。
  14. 如权利要求1所述的存储块，还包括：行译码电路，用于发出行译码信号，以定位选中不同所述阵列单元中的字线。
  15. 一种存储器，其特征在于，包括如权利要求1-14任一项所述的存储块。
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