WO2022057417A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2022057417A1
WO2022057417A1 PCT/CN2021/106114 CN2021106114W WO2022057417A1 WO 2022057417 A1 WO2022057417 A1 WO 2022057417A1 CN 2021106114 W CN2021106114 W CN 2021106114W WO 2022057417 A1 WO2022057417 A1 WO 2022057417A1
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WIPO (PCT)
Prior art keywords
block
data bus
storage sub
error detection
data
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PCT/CN2021/106114
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English (en)
French (fr)
Inventor
尚为兵
李红文
张良
冀康灵
池性洙
吴道训
汪瑛
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21868246.6A priority Critical patent/EP4227944A1/en
Priority to US17/481,413 priority patent/US11894089B2/en
Publication of WO2022057417A1 publication Critical patent/WO2022057417A1/zh
Priority to US18/393,820 priority patent/US20240145022A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line (Word Line, WL), the drain is connected to the bit line (Bit Line, BL), and the source is connected to the capacitor.
  • the voltage signal on the word line The transistor can be controlled to be turned on or off, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage.
  • ECC Error Checking and Correcting
  • An embodiment of the present disclosure provides a memory, including: a storage block, the storage block includes a U storage sub-block and a V storage sub-block, a first error detection and error correction unit, and the U storage sub-block and the V storage sub-block
  • the blocks are all connected to perform error detection and error correction on the output data of the U storage sub-block and the V storage sub-block;
  • the second error detection and error correction unit is connected to the U storage sub-block and the V storage sub-block.
  • the blocks are all connected to perform error detection and correction on the output data of the U storage sub-block and the V storage sub-block.
  • 1 is a schematic top view of a layout of a memory
  • Fig. 2 is the structural representation of a kind of memory
  • FIG. 3 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of signal line connection in a local area of the memory in FIG. 3;
  • FIG. 5 is another schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • FIG. 6 is another schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another memory according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a memory provided by another embodiment of the present disclosure.
  • FIG. 9 is another schematic structural diagram of a memory provided by another embodiment of the present disclosure.
  • FIG. 1 is a schematic top view of a layout of a memory.
  • the memory includes a plurality of active regions 10 arranged in an array, bit lines 11 , word lines 12 , and capacitors 13 electrically connected to the active regions.
  • the capacitor 91 is connected to the bit line BL3 via a transistor
  • the capacitor 92 is connected to the bit line BL2 via a transistor, as shown by the middle dotted line.
  • the probability of such defects is also increasing.
  • FIG. 2 is a schematic structural diagram of a memory, and the memory includes:
  • the memory array is composed of memory cells 14, and each memory cell 14 is connected to a bit line BL and a word line WL.
  • each column selection signal unit includes a plurality of column selection signal lines, and each column selection signal line passes through a switch It is connected to the corresponding bit line BL in the memory array, and the control signal of the switch comes from the column decoding circuit (not shown in FIG. 2, marked as YDEC in FIG. 3), which is used to determine whether the data on the bit line BL is It is transmitted to the local data bus.
  • the column selection signal unit CSL ⁇ n> includes 8 column selection signal lines, and the 8 column selection signal lines are connected to the 8 bit lines BL in the memory array through switches.
  • LIO The local data bus is denoted as LIO in FIG. 2 , wherein LIO:O ⁇ 3:0> denotes an odd-numbered local data bus, and LIO:E ⁇ 3:0> denotes an even-numbered local data bus.
  • the block data bus is marked as YIO in Figure 2, where YIO: O ⁇ 3:0> marks the odd-numbered block data bus, YIO: E ⁇ 3:0> marks the even-numbered block data bus, local data bus
  • the block data bus is connected through a local conversion circuit (such as a local sense amplifying circuit, not shown in Figure 2).
  • YIO:E ⁇ 3:0> and LIO:E ⁇ 3:0> are shown by an arc curve Interaction between YIO:O ⁇ 3:0> and LIO:O ⁇ 3:0>.
  • the block data buses YIO:E ⁇ 3:0> and YIO:O ⁇ 3:0> are connected to the same error detection and correction unit 15 .
  • the memory cell 91 and the memory cell 92 in FIG. 91 and 92 in 1 represent capacitors
  • FIG. 2 91 and 92 represent memory cells, which usually include capacitors and transistors, which are marked the same here to illustrate adjacent two-bit errors in conjunction with FIG. 1 and FIG.
  • the corresponding bit lines BL2 and BL3 both transmit their data to the local data line LIO: O ⁇ 3:0> and the local data line LIO: E ⁇ 3:0> through the column selection signal unit CSL ⁇ n>, Then, the data is transmitted to YIO:E ⁇ 3:0> and YIO:O ⁇ 3:0> through the local conversion circuit, then two-bit errors enter the error detection and correction unit 15 at the same time.
  • the currently used ECC technology (for example, for the ECC technology of 128 bits (data bits) + 8 bits (parity bits), can only complete one-bit correction), the above two-bit errors cannot be corrected.
  • the present disclosure provides a memory including a first error detection and error correction unit and a second error detection and error correction unit.
  • the two error detection and error correction units are arranged so that when the storage sub-block outputs two data at the same time. Errors can be corrected, thereby improving the error detection and correction capability of the memory and improving the read and write performance of the memory.
  • FIG. 3 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • the memory includes:
  • a plurality of storage blocks 100 each storage block 100 includes a U storage sub-block 101 and a V storage sub-block 102;
  • the first error detection and correction unit 103 is connected with both the U storage sub-block 101 and the V storage sub-block 102, and is used to perform error detection and error correction on the output data of the U storage sub-block 101 and the V storage sub-block 102;
  • the second error detection and correction unit 104 is connected to both the U storage sub-block 101 and the V storage sub-block 102, and is configured to perform error detection and error correction on the output data of the U storage sub-block 101 and the V storage sub-block 102.
  • the output data of the U storage sub-block 101 corresponds to high-order (high-order) data
  • the output data of the V storage sub-block 102 corresponds to low-order (low-order) data
  • the storage block may also be configured such that the output data of the U storage sub-block corresponds to the low-order data
  • the output data of the V storage word block corresponds to the high-order data. It can be understood that the high-order data and the low-order data are relative, and the high-order data and the low-order data are clearly defined in comparison.
  • Both the U storage sub-block 101 and the V storage sub-block 102 include several storage arrays arranged in an array (refer to FIG. 1 and FIG. 2 ).
  • the output data of the U storage sub-block 101 is 68 bits as an example, wherein the 64 bits data is valid data (the memory needs to interact with the external controller through the memory interface), and the 4 bits data is the first error detection error correction.
  • the memory includes a write data operation and a read data operation.
  • the data received by the memory interface passes through the ECC module (for example, the first error detection and correction unit 103 in FIG. 3 ). and the second error detection and correction unit 104) for processing.
  • the data entering the ECC module is 64bits data, which is also called valid data
  • the data output by the ECC module is 68bits (64bits+4bits), of which 64bits data is valid data, and 4bits are the check bits generated by the ECC module.
  • the 68 bits are all stored in the storage array of the U storage sub-block 101, and it can be called an encoding process when the ECC module performs data writing operations.
  • 68bits (64bits+4bits) data is also output from the U storage sub-block 101, and these 68bits enter the ECC module at the same time, and the ECC module performs the opposite algorithm to the write at this time. , it can be called the decoding process when the ECC module operates on the read data.
  • the ECC module performs decoding operation on the 64bits valid data, and compares the result of the decoding operation with the 4bits check bit, so as to determine whether the output 64bits valid data has errors. The one-bit error can also be corrected.
  • the U storage sub-block 101 outputs the output data of 68bits (64bits+4bits) to the first error detection and correction unit 103, and the V storage subblock 102 also outputs the 68bits (64bits+4bits) output data to the first error detection and correction unit 103.
  • 4bits) output data is output to the first error detection and correction unit 103;
  • U storage sub-block 101 outputs the output data of 68bits (64bits+4bits) to the second error detection and correction unit 104,
  • V storage sub-block 102 also 68bits
  • the output data of (64bits+4bits) is output to the second error detection and correction unit 104 .
  • the U storage sub-block 101 outputs the output data of 136bits (128bits+8bits) to the first error detection and correction unit 103
  • the V storage subblock 102 outputs the output data of 136bits (128bits+8bits) to the first error detection and correction unit 103.
  • Two error detection and correction unit 104 Two error detection and correction unit 104 .
  • the unit 104 performs error detection and error correction, so that when more than one error (eg, two-bit error) occurs simultaneously in the output data of the U storage sub-block 101 (or the V storage sub-block 102), different errors can be detected and corrected by the first error.
  • the unit 103 or the second error detection and correction unit 104 performs correction, so that the memory can correct more than one error, thereby improving the error detection and correction capability of the memory.
  • the input number of bits of the first error detection and correction unit 103 is the same as that of the second error detection and correction unit 104 .
  • the input number of bits of the first error detection and correction unit 103 and the input number of bits of the second error detection and correction unit 104 are both 64bits+4bits, where 64bits is the U storage sub-block 101 or the V storage word block 102 is the valid data written or read, and 4 bits are the input bits of the first error detection and correction unit 103 or the check bits generated by the second error detection and correction unit 104 .
  • the internal error detection algorithm of the first error detection and correction unit 103 is the same as the internal error detection algorithm of the second error detection and correction unit 104, which is beneficial to reduce the design difficulty of the memory.
  • the first error detection and correction unit 103 uses an internal error detection algorithm to calculate the valid data (64bits), and calculates the check bit (4bits), It is recorded as the first check bit, and then the valid data (64bits) and the check bit (4bits) are written into the storage array 105 at the same time; when these data are read from the storage array 105, the valid data (64bits ) Calculate the check digit (4bits), record it as the second check digit, compare the second check digit with the directly read first check digit, if the result is the same, the data is correct, otherwise If there is an error, the first error detection and correction unit 103 can logically detect the error; when only one bit error occurs, the first error detection and correction unit 103 can correct the error without affecting the memory read operation. For example, when "0" in the third bit of 64 bits is an error bit, the first error detection and correction unit 103 corrects the "0" in the third bit to
  • part of the output data in the U storage sub-block 101 is input to the first error detection and correction unit 103 for error detection and correction, and the rest of the output data is input to the second error detection and correction unit 104 for error detection and correction
  • the adjacent two-bit errors that may occur in the same U storage sub-block 101 are placed in different ECC units respectively, because the two erroneous data are respectively processed by the first error detection and error correction unit 103 and the second
  • the second error detection and correction unit 104 processes, that is, the first error detection and correction unit 103 and the second error detection and correction unit 104 only process one error, but at the memory level, the memory can correct these two errors at the same time .
  • the storage capacity of the U storage sub-block 101 is the same as the storage capacity of the V storage sub-block 102 .
  • the storage capacity of the U storage sub-block may also be larger or smaller than the storage capacity of the V storage sub-block.
  • FIG. 4 is a schematic diagram of the signal line connection of the local area represented by the triangle 106 of the memory in FIG. 3.
  • the local data bus LIO is connected to an even number of sense amplifiers (not shown) through the column selection signal unit 109, And the sense amplifiers are arranged in a one-to-one correspondence with the bit lines BL of the memory array 105 .
  • the column selection signal unit 109 includes a gate switch, and the column selection signal (Column Select Signal, CSS) controls the turn-on or turn-off of the gate switch.
  • the gate switch When the gate switch is turned on, the sense amplifier exchanges data with the local data bus LIO; When the switch is turned off, the sense amplifier and the local data bus no longer exchange data.
  • the output data on the adjacent bit line BL enters the local data bus O and the local data bus E through the sense amplifier and the column selection signal unit 109, respectively.
  • LIO:E in FIG. 4 shows the local data bus E
  • LIO:O shows the local data bus O, which are shown as CSL ⁇ n-1>, CSL ⁇ n> and CSL ⁇ n+1>
  • the gate switches are located in the column selection signal unit (not shown), and the sense amplifiers are located on both sides of the bit line BL (not shown).
  • the local data bus E in turn exchanges data with the block data bus E through a local conversion circuit (not shown), and the local data bus O in turn exchanges data with the block data bus O through a local conversion circuit (not shown).
  • the block data bus E is indicated by the solid line YIO:E with arrows
  • the block data bus O is indicated by the solid line YIO:O with arrows.
  • a block data bus O is indicated with YIO1_O
  • a block data bus E is indicated with YIO1_E.
  • YIO:E in Fig. 4 can be understood as YIO1_E
  • YIO in Fig. 4: E: O can be understood as YIO1_O.
  • one YIO1_O or YIO1_E can be connected to YIO:O or YIO:E of multiple storage arrays 105 .
  • YIO1_O passes through the block amplifier 110 to the first error detection and correction unit 103
  • YIO1_E passes through the block amplifier 110 to the second error detection and correction unit 104 .
  • both the U storage sub-block 101 and the V storage sub-block 102 include a local conversion circuit (Local SA, not shown) and an even number of local data buses, and the local data buses are divided into a local data bus O and a local data bus E , the local data bus O is connected to the block data bus O through the local conversion circuit, and the local data bus E is connected to the block data bus E through the local conversion circuit.
  • a local conversion circuit Local SA, not shown
  • the local data buses are numbered in sequence from zero according to the natural numbers, the local data bus with an odd number is defined as the local data bus O, and the local data bus with an even number is defined as the local data bus E;
  • the local data bus in the odd-numbered position is defined as the local data bus O, and the local data bus in the even-numbered position is defined as the local data bus E.
  • the column decoding circuit YDEC and the column selection signal CSL generated by the column decoding circuit YDEC are electrically connected to the plurality of memory arrays 105 , and the memory array for the memory operation is selected by the column selection signal CSL 105.
  • the column selection signal CSL corresponds to CSL ⁇ n-1>, CSL ⁇ n>, and CSL ⁇ n+1> in FIG. 4 .
  • the arrangement of the storage arrays 105 in the U storage sub-block 101 is numbered from 1 according to natural numbers, and the block data bus is electrically connected to the storage arrays 105 with even numbers.
  • the storage array 105 includes a storage unit, a local data bus E, a local data bus O, and a local conversion circuit, and the block data bus is connected to the local data bus E through the local conversion circuit; the block data bus is connected to the local data bus through the local conversion circuit.
  • the data bus O is connected, and the connection relationship between the block data bus and the storage array 105 is marked with a triangle symbol in FIG. 3 .
  • the connection relationship of the block data bus of the V storage sub-block 102 reference may be made to the corresponding description of the U storage sub-block 101, which will not be repeated below.
  • the parasitic resistance of the column selection signal line CSL1 can be reduced, thereby reducing power consumption.
  • the column decoding circuits YDEC are located on opposite sides of the plurality of memory arrays 105 respectively, and for the V memory sub-block 102 , the column decoding circuits YDEC are respectively located on the opposite sides of the plurality of memory arrays 105 . It should be noted that, in other embodiments, for each U storage sub-block or V storage sub-block, the number of column decoding circuits may also be one.
  • the block data bus is 2*4*(16*N), the local data bus is 2*4*M*(16*N); the block data bus O is 4*( 16*N), block data bus E is 4*(16*N); local data bus O is 4*M*(16*N), local data bus E is 4*M*(16*N) 1 block data bus O corresponds to M local data bus O, and 1 block data bus E corresponds to M local data bus E; the local data bus is divided into M with adjacent 4 as a group *(16*N) group local data bus O and M*(16*N) group local data bus E.
  • M and N are natural numbers greater than or equal to 1.
  • the block data bus is 2*4*16
  • the local data bus is 2*4*16
  • the block data bus O is 4*16
  • the block data bus E is 4*16
  • the U storage sub-block 101 includes even-numbered block data buses, the block data buses are numbered sequentially from zero according to natural numbers, and the odd-numbered block data bus O (denoted as YIO1_O) is connected to the first Error detection and correction unit 103, an even-numbered block data bus E (marked as YIO1_E) is connected to the second error detection and correction unit 104;
  • V storage sub-block 102 includes an even-numbered block data bus, and the block data bus is a natural number from zero Sequentially numbered, the odd-numbered block data bus O (marked as YIO2_O) is connected to the first error detection and correction unit 103 , and the even numbered block data bus E (marked as YIO2_E) is connected to the second error detection and correction unit 104 .
  • the data of the block data bus O (YIO1_O) of the U storage sub-block 101 and the data of the block data bus O (YIO2_O) of the V storage sub-block 102 enter the first error detection and correction unit 103 for error detection and correction;
  • U storage The data on the block data bus E (YIO1_E) of the sub-block 101 and the data on the block data bus E (YIO2_E) of the V storage sub-block 102 enter the second error detection and correction unit 104 for error detection and correction.
  • the U storage sub-block 101 includes even-numbered block data buses, the block data buses are numbered in sequence from zero according to natural numbers, and the odd-numbered block data bus O (YIO1_O) is connected to the first checkpoint.
  • an even-numbered block data bus E (YIO1_E) is connected to the second error detection and correction unit 104;
  • V storage sub-block 102 includes even-numbered block data buses, and the block data buses are sequentially numbered from zero according to natural numbers,
  • the odd-numbered block data bus O (YIO2_O) is connected to the second error detection and correction unit 104 , and the even-numbered block data bus E (YIO2_E) is connected to the first error detection and correction unit 103 .
  • the data of the block data bus O (YIO1_O) of the U storage sub-block 101 and the data of the block data bus E (YIO2_E) of the V storage sub-block 102 enter the first error detection and correction unit 103 for error detection and correction ;
  • the data of the block data bus E (YIO1_E) of the U storage sub-block 101 and the data of the block data bus O (YIO2_O) of the V storage sub-block 102 enter the second error detection and correction unit 104 for error detection and correction.
  • the U storage sub-block 101 includes an even number of block data buses, the block data buses are numbered in sequence from zero according to natural numbers, and the odd-numbered block data bus O (YIO1_O) is connected to the The second error detection and correction unit 104, the block data bus E (YIO1_E) numbered as an even number is connected to the first error detection and correction unit 103; the V storage sub-block 102 includes an even number of block data buses, and the block data bus is converted from Zeros are numbered in sequence, the odd-numbered block data bus O (YIO2_O) is connected to the first error detection and correction unit 103 , and the even-numbered block data bus E (YIO2_E) is connected to the second error detection and correction unit 104 .
  • the data of the block data bus E (YIO1_E) of the U storage sub-block 101 and the data of the block data bus O (YIO2_O) of the V storage sub-block 102 enter the first error detection and correction unit 103 for error detection and correction
  • the data of the block data bus O (YIO1_O) of the U storage sub-block 101 and the data of the block data bus E (YIO2_E) of the V storage sub-block 102 enter the second error detection and correction unit 104 for error detection and correction.
  • the U storage sub-block 101 includes even-numbered block data buses, the block data buses are numbered sequentially from zero according to natural numbers, and the odd-numbered block data bus O (YIO1_O) is connected to the second check Error correction unit 104, an even-numbered block data bus E (YIO1_E) is connected to the first error detection and correction unit 103;
  • the V storage sub-block includes even-numbered block data buses, and the block data buses are sequentially numbered from zero according to natural numbers, and the numbers are
  • the odd-numbered block data bus O (YIO2_O) is connected to the second error detection and correction unit 104
  • the even-numbered block data bus E (YIO2_E) is connected to the first error detection and correction unit 103 .
  • the data of the block data bus E of the U storage sub-block 101 and the data of the block data bus E (YIO1_E and YIO2_E) of the V storage sub-block 102 enter the first error detection and error correction unit 103 to perform error detection and error correction;
  • the data of the block data bus O of the U storage sub-block 101 and the data of the block data bus O (YIO1_O and YIO2_O) of the V storage sub-block 102 enter the second error detection and correction unit 104 for error detection and correction.
  • the output data of the same storage sub-block are respectively input to different error detection and correction units, that is, part of the output data is input to the first error detection and correction unit 103 for error detection and correction, and the rest is output
  • the data is input to the second error detection and correction unit 104 for error detection and correction, so that if there are two data errors at the same time, the first error detection and correction unit 103 and the second error detection and correction unit 104 can respectively The one-bit data is corrected, thereby improving the error detection and correction capability of the memory.
  • Another embodiment of the present disclosure further provides a memory, which is substantially the same as the memory provided in the foregoing embodiment, and the main differences include that in another embodiment, the output data of the U storage sub-block includes high-order data (high-order data) and Lower-bit data (lower-bit data); the output data of the V storage sub-block includes upper-bit data and lower-bit data.
  • the memory provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as in the foregoing embodiment, reference may be made to the detailed description of the foregoing embodiment, which will not be repeated below.
  • FIG. 8 is a schematic structural diagram of a memory provided by another embodiment of the present disclosure
  • FIG. 9 is another structural schematic diagram of a memory provided by another embodiment of the present disclosure.
  • the memory includes: a plurality of storage blocks 200 , and the storage block 200 includes a U storage sub-block and a V storage sub-block; a first error detection and correction unit 203 and a second error detection and correction unit 204 .
  • the memory also includes a column decoding circuit YDEC and a block amplifier 210 .
  • the memory block 200 includes a plurality of memory arrays 205 .
  • part of the output data of the U storage sub-block corresponds to high-order data, and the rest corresponds to low-order data
  • part of the output data of the V storage sub-block corresponds to high-order data, and the rest corresponds to low-order data.
  • half of the output data of the U storage sub-block corresponds to high-order data, and the other half corresponds to low-order data
  • half of the output data of the V storage sub-block corresponds to high-order data, and the other half corresponds to low-order data.
  • the output data of the U storage sub-block includes low-order data and high-order data, a single access will only access part of the storage array in the U storage sub-block, thereby reducing the power consumption of the memory;
  • the output data includes low-order data and high-order data, so a single access will only access a part of the storage array in the V storage sub-block, which is also conducive to reducing the power consumption of the memory.
  • the U storage sub-block includes a first U storage sub-block 211 and a second U storage sub-block 221 , the output data of the first U storage sub-block 211 is high-order data, and the second U storage sub-block 211 Block 221 outputs data as low-order data.
  • the V storage sub-block includes a first V storage sub-block 212 and a second V storage sub-block 222. The output data of the first V storage sub-block 212 is high-order data, and the output data of the second V-storage sub-block 222 is low-order data.
  • the U storage sub-block includes a block data bus, including a block data bus YIO_U1_O (numbered odd) and a block data bus YIO_U1_E (numbered even) corresponding to the first U storage subblock 211 , and corresponding to the second U storage subblock 221
  • the V storage sub-block includes a block data bus, including a block data bus YIO_V1_O (numbered odd) and a block data bus YIO_V1_E (numbered even) corresponding to the first V storage sub-block 212 , and corresponding to the second V storage sub-block 222
  • the block data bus YIO_U1_E, the block data bus YIO_U2_E, the block data bus YIO_V1_E, and the block data bus YIO_V2_E are connected to the first error detection and correction unit 203, and the block data bus YIO_U1_O, the block data bus YIO_U2_O, the block data bus YIO_V1_O, and the block data bus YIO_V2_O are connected with The connection of the second error detection and correction unit 204 , the triangle 206 in FIG. 8 indicates that the block data bus is electrically connected to the corresponding storage array 205 .
  • 34 bits of the first V storage sub-block 212 32 bits of valid data + 2 bits check bit, corresponding to the block data bus YIO_V1_E
  • 34 bits of the second V storage sub-block 222 32bits valid data+2bits check bit, corresponding to block data bus YIO_V2_E), a total of 136bits (128bits valid data+8bits check bit) are input to the first error detection and correction unit 203; 32bits valid data + 2bits check bit, corresponding to the block data bus YIO_U1_O), 34bits of the second U storage sub-block 2
  • the output data of the same storage sub-block (for example, the first U storage sub-block 211) are respectively input to different error detection and correction units, that is, part of the output data is input to the first error detection and correction unit 203 for error detection and correction, The remaining part of the output data is input to the second error detection and error correction unit 204 for error detection and error correction, so that if there is an error in two bits of data at the same time, the first error detection and error correction unit 203 and the second error detection and error correction unit 204 can respectively One bit of data in the two bits is corrected, thereby improving the error detection and correction capability of the memory.
  • the U storage sub-block includes a first U storage sub-block 211 , a second U storage sub-block 221 , a third U storage sub-block 231 and a fourth U storage sub-block arranged in sequence 241, the output data of the first U storage sub-block 211 and the third U storage sub-block 231 are high-order data, and the output data of the second U-storage sub-block 221 and the fourth U-storage sub-block 241 are low-order data.
  • the V storage sub-block includes a first V storage sub-block 212, a second V storage sub-block 222, a third V storage sub-block 232 and a fourth V storage sub-block 242, the first V storage sub-block 212 and the third V storage sub-block 242 arranged in sequence
  • the output data of the V storage sub-block 232 is high-order data
  • the output data of the second V-storage sub-block 222 and the fourth V-storage sub-block 242 are low-order data.
  • Triangles 206 in FIG. 9 indicate that the block data bus is electrically connected to the corresponding memory array 205 .
  • the block data bus corresponding to the U storage sub-block is divided into block data bus YIO_U_O1, block data bus YIO_U_O2, block data bus YIO_U_E1, block data bus YIO_U_E2 according to odd and even positions;
  • the block data bus corresponding to the storage subblock is divided into block data bus YIO_V_O1, block data bus YIO_V_O2, block data bus YIO_V_E1, block data bus YIO_V_E2.
  • the block data bus YIO_U_O1 is connected to the first U storage sub-block 211 and the third U storage sub-block 231, and the block data bus YIO_U_O2 is connected to the second U storage sub-block 221 and the fourth U storage sub-block 241;
  • the bus YIO_V_O1 is connected to the first V storage sub-block 212 and the third V storage sub-block 232
  • the block data bus YIO_V_O2 is connected to the second V storage sub-block 222 and the fourth V storage sub-block 242 .
  • the memory provided in this embodiment can not only correct two bits at the same time, but also because the output data part of the U storage sub-block and the V storage sub-block is high-order data, and the rest are low-order data, so in single When accessing the memory for the second time, only a part of the storage array in the U storage sub-block or the V storage sub-block is accessed, which is beneficial to reduce the power consumption of the memory.

Abstract

一种存储器，包括存储块（100），所述存储块（100）包括U存储子块（101）和V存储子块（102），其中，包括：第一检错纠错单元（103），与所述U存储子块（101）、所述V存储子块（102）均连接，用于对所述U存储子块（101）和所述V存储子块（102）的输出数据进行检错纠错；第二检错纠错单元（104），与所述U存储子块（101）、所述V存储子块（102）均连接，用于对所述U存储子块（101）和所述V存储子块（102）的所述输出数据进行检错纠错。

Description

存储器
相关申请的交叉引用
本公开基于申请号为202010988666.8、申请日为2020年09月18日、申请名称为“存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开实施例涉及但不限于一种存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线(Word Line，WL)相连、漏极与位线(Bit Line，BL)相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
对于DRAM来说，在数据存储的过程中数据常常会出现错误，因此需要错误检测和纠正(Error Checking and Correcting，ECC)技术来保证数据存储的正确性，通常是利用在一定长度的有效数据位的基础上增加校验位来检测和纠正出错的数据。
发明内容
本公开实施例提供一种存储器，包括：存储块，所述存储块包括U存储子块和V存储子块，第一检错纠错单元，与所述U存储子块、所述V存储子块均连接，用于对所述U存储子块和所述V存储子块的输出数据进行检错纠错；第二检错纠错单元，与所述U存储子块、所述V存储子块均连接，用于对所述U存储子块和所述V存储子块的所述输出数据进行检错纠错。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一种存储器的版图俯视结构示意图；
图2为一种存储器的结构示意图；
图3为本公开一实施例提供的存储器的一种结构示意图；
图4为图3中存储器的局部区域的信号线连接示意图；
图5为本公开一实施例提供的存储器的另一种结构示意图；
图6为本公开一实施例提供的存储器的又一种结构示意图；
图7为本公开一实施例提供的存储器的再一种结构示意图；
图8为本公开另一实施例提供的存储器的一种结构示意图；
图9为本公开另一实施例提供的存储器的另一种结构示意图。
具体实施方式
由背景技术可知，相关技术的ECC技术仍存在不足。
分析发现，如果数据中有一位错误，ECC技术不但能发现而且可以对其更正，ECC技术还可以发现2至4位错误，然而ECC技术难以对2位及以上的错误进行纠正。也就是说，ECC技术虽然可以同时检测和纠正单一比特错误，但如果同时检测出两个及以上比特的数据有错误，目前的ECC技术则无能为力。此外，进一步分析发现，目前处于相邻位置的两位同时出现错误的概率较大。进一步分析发现，导致这一问题的主要原因的分析如下：
图1为一种存储器的版图俯视结构示意图，存储器包括：多个阵列式排布的有源区10、位线11、字线12以及与有源区电连接的电容器13。存储器中存在相邻单元桥连(cell to cell bridge)的缺陷，或称为相邻两比特错误，例如相邻有源区10对应的电容器91和电容器92之间发生桥连等，如图1中虚线框所示，电容器91通过晶体管与位线BL3连接，电容器92通过晶体管与位线BL2连接。随着存储器工艺尺寸越来越小，这种缺陷的发生概率也越来越大。
图2为一种存储器的结构示意图，存储器包括：
存储阵列，由存储单元14组成，每一存储单元14连接位线BL以及字线WL。
列选择信号单元，在图2中标示为CSL<n-1>、CSL<n>以及CSL<n+1>，每一列选择信号单元包括多条列选择信号线，每一列选择信号线通过开关与存储阵列中对应的位线BL连接，开关的控制信号来源于列译码电路(在图2中未示出，在图3中标示为YDEC)，用于决定位线BL上的数据是否被传到本地数据总线，例如列选择信号单元CSL<n>包括8条列选择信号线，8条列选择信号线通过开关与存储阵列中的8条位线BL连接。
本地数据总线，在图2中标示为LIO，其中LIO：O<3:0>标示编号为奇数的本地数据总线，LIO：E<3:0>标示编号为偶数的本地数据总线。
块数据总线，在图2中标示为YIO，其中YIO：O<3:0>标示编号为奇数的块数据总 线，YIO：E<3:0>标示编号为偶数的块数据总线，本地数据总线通过本地转换电路(如本地感测放大电路，图2中未示出)连接块数据总线，图2中以弧形曲线示意出YIO：E<3:0>与LIO：E<3:0>之间交互，YIO：O<3:0>与LIO：O<3:0>之间交互。
结合图1及图2，块数据总线YIO：E<3:0>以及YIO：O<3:0>连接至同一检错纠错单元15。若两个存储单元14对应的两个位线BL正好连接同一列译码电路，则有两个错误同时发生在同一个读出时间点，例如图2中存储单元91和存储单元92(在图1中91和92表示电容器，而在图2中91和92表示存储单元，存储单元通常包括电容器和晶体管，这里将其标示为相同，是为了结合图1和图2来说明相邻两比特错误)同时出错，对应的位线BL2和BL3都通过列选择信号单元CSL<n>将其数据传输至本地数据线LIO：O<3:0>和本地数据线LIO：E<3:0>，然后经本地转换电路将数据传输至YIO：E<3:0>和YIO：O<3:0>，那么就同时有两比特错误进入检错纠错单元15。目前使用的ECC技术(例如，对于128bits(数据位)+8bits(校验位)的ECC技术，只能完成一比特的纠正)，则无法对上述两比特错误进行纠正。
为解决上述问题，本公开实施提供一种存储器，包括第一检错纠错单元和第二检错纠错单元，两个检错纠错单元的设置，使得当存储子块同时输出两个数据出错时能够被纠正，从而提高存储器的检错纠错能力，提高存储器的读写性能。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图3为本公开一实施例提供的存储器的结构示意图。
参考图3，本实施例中，存储器包括：
多个存储块100，每一存储块100包括U存储子块101和V存储子块102；
第一检错纠错单元103，与U存储子块101和V存储子块102均连接，用于对U存储子块101和V存储子块102的输出数据进行检错纠错；
第二检错纠错单元104，与U存储子块101和V存储子块102均连接，用于对U存储子块101和V存储子块102的输出数据进行检错纠错。
以下将结合附图对本实施例提供的存储器进行详细说明。
为了便于图示和说明，图3中仅示意出一个存储块100作为示例。本实施例中，U存储子块101的输出数据对应为高位(高比特位)数据，V存储子块102的输出数据对 应为低位(低比特位)数据。在其他实施例中，存储块也可以配置为，U存储子块的输出数据对应为低位数据，V存储字块的输出数据对应为高位数据。可以理解的是，高位数据和低位数据是相对而言的，高比特位数据和低比特位数据相比较而言是清楚的定义。
U存储子块101和V存储子块102均包括若干阵列式排布的存储阵列(参考图1和图2)。本实施例中，以U存储子块101输出数据为68bits作为示例，其中，64bits数据为有效数据(存储器需要通过存储器接口与外部控制器交互的数据)，4bits数据为经过第一检错纠错单元103和/或者第二检错纠错单元104处理后产生的校验位。
需要说明的是，存储器包括写数据操作和读数据操作，当向存储器中的存储阵列进行写数据操作时，存储器接口接收的数据经过ECC模块(例如图3中的第一检错纠错单元103和第二检错纠错单元104)进行处理。
例如进入ECC模块为64bits数据，这64bits数据同样称为有效数据，而ECC模块输出的数据则为68bits(64bits+4bits)，其中64bits数据为有效数据，4bits则为ECC模块产生的校验位，这68bits都会存储到U存储子块101的存储阵列中，可以称ECC模块针对写数据操作时为编码过程。
当从存储器中的存储阵列进行读数据操作时，则从U存储子块101同样输出68bits(64bits+4bits)数据，这68bits同时进入ECC模块，ECC模块此时执行的是和写入相反的算法，可以称ECC模块针对读数据操作时为解码过程。ECC模块通过对64bits有效数据进行解码运算，将解码运算产生的结果与4bits校验位进行比较，从而判断输出的64bits有效数据是否存在错误，如果64bits中只有1bit出错(一比特错误)，ECC模块还可以将该一比特错误纠正。
继续参考图3，在本实施例中，例如，U存储子块101将68bits(64bits+4bits)的输出数据输出到第一检错纠错单元103，V存储子块102也将68bits(64bits+4bits)的输出数据输出到第一检错纠错单元103；U存储子块101将68bits(64bits+4bits)的输出数据输出到第二检错纠错单元104，V存储子块102也将68bits(64bits+4bits)的输出数据输出到第二检错纠错单元104。
提供一对比实施例，U存储子块101将136bits(128bits+8bits)的输出数据输出到第一检错纠错单元103，V存储子块102将136bits(128bits+8bits)的输出数据输出到第二检错纠错单元104。
相比较而言，由于U存储子块101(或V存储子块102)的输出数据部分输入至第一检错纠错单元103进行检错纠错，其余输出数据输入至第二检错纠错单元104进行检 错纠错，使得U存储子块101(或V存储子块102)的输出数据中同时出现一个以上错误时(例如两比特错误)，不同的错误能够被第一检错纠错单元103或者第二检错纠错单元104进行纠正，从而使得存储器能够对一个以上的错误进行纠正，提高存储器的检错纠错能力。
本实施例中，第一检错纠错单元103的输入位数和第二检错纠错单元104的输入位数相同。在一个例子中，第一检错纠错单元103的输入位数和第二检错纠错单元104的输入位数均为64bits+4bits，其中，64bits为U存储子块101或者V存储字块102写入或者读取的有效数据，4bits为第一检错纠错单元103的输入位数或第二检错纠错单元104产生的校验位。
此外，第一检错纠错单元103的内部检错算法与第二检错纠错单元104的内部检错算法相同，这样，有利于降低存储器的设计难度。
以第一检错纠错单元103作为示例，每次数据写入时，第一检错纠错单元103使用内部检错算法对有效数据(64bits)进行计算，计算得到校验位(4bits)，记为第一校验位，然后将有效数据(64bits)和校验位(4bits)同时写入存储阵列105；当这些数据从存储阵列105中读出时，采用同一算法再次对有效数据(64bits)计算得到校验位(4bits)，记为第二校验位，用第二校验位和直接读取出来的第一校验位进行比较，如果结果相同，说明数据是正确的，反之说明有错误，第一检错纠错单元103可以从逻辑上检测出错误；当只出现一比特错误的时候，第一检错纠错单元103可以把错误改正过来而不影响存储器读取操作。例如，当64bits的第3位出现的“0”为出错比特时，第一检错纠错单元103将第3位的“0”纠正为“1”。
关于第二检错纠错单元104的工作原理可参考第一检错纠错单元103，以下将不做赘述。
在一些实施例中，U存储子块101中的部分输出数据输入至第一检错纠错单元103进行检错纠错，其余部分输出数据输入至第二检错纠错单元104进行检错纠错，这样，这样在同一U存储子块101中可能出现的相邻两比特错误分别被放在不同的ECC单元里，由于这两个错误的数据分别被第一检错纠错单元103和第二检错纠错单元104处理，即第一检错纠错单元103和第二检错纠错单元104处理均只处理一个错误，但是在存储器的层面看，该存储器能够同时纠正这两个错误。
关于V存储子块102中出现错误时的检错纠错机理，可参考U存储子块101的相应说明，在此不再赘述。
本实施例中，U存储子块101的存储容量与V存储子块102的存储容量相同。在其他实施例中，U存储子块的存储容量也可以大于或者小于V存储子块的存储容量。例如，对于8Gbit的DRAM芯片，一共16个存储块100(bank)，每一个存储块100包括2个存储子块(half bank)，所以一个U存储子块101和V存储子块102的存储容量可以都是256Mbit。
结合参考图3及图4，图4为图3中存储器的三角形106代表的局部区域的信号线连接示意图，本地数据总线LIO通过列选择信号单元109与偶数个灵敏放大器(未示出)连接，且灵敏放大器与存储阵列105的位线BL一一对应设置。列选择信号单元109包括选通开关，列选择信号(Column Select Signal，CSS)控制选通开关的导通或关断，当选通开关导通时，灵敏放大器与本地数据总线LIO交互数据；当选通开关关断时，灵敏放大器与本地数据总线不再交互数据。
此外，相邻位线BL上的输出数据经灵敏放大器和列选择信号单元109分别进入本地数据总线O和本地数据总线E。为了便于区别，图4中LIO:E示意出了本地数据总线E，LIO:O示意出了本地数据总线O，以CSL<n-1>、CSL<n>以及CSL<n+1>示出了列选择信号单元，选通开关位于列选择信号单元中(未示出)，敏感放大器位于位线BL两侧(未示出)。本地数据总线E又与块数据总线E通过本地转换电路(未示出)交互数据，本地数据总线O又与块数据总线O通过本地转换电路(未示出)交互数据。在图4中，以带箭头的实线YIO:E示意出了块数据总线E，以带箭头的实线YIO:O示意出了块数据总线O。
继续参考图3，以YIO1_O示意块数据总线O的一条，以YIO1_E示意块数据总线E的一条，在一种实施例中，图4中的YIO:E可理解为YIO1_E，图4中的YIO:O可理解为YIO1_O。在一种实施例中，一条YIO1_O或YIO1_E可以连接多个存储阵列105的YIO:O或YIO:E。YIO1_O经过块放大器110到第一检错纠错单元103，YIO1_E经过块放大器110到第二检错纠错单元104。
继续参考图3，YIO_O的数据进入第一检错纠错单元103，YIO_E的数据进入第二检错纠错单元104。本实施例中，U存储子块101和V存储子块102均包括本地转换电路(Local SA，未示出)和偶数条本地数据总线，本地数据总线分为本地数据总线O和本地数据总线E，本地数据总线O通过本地转换电路连接块数据总线O，本地数据总线E通过本地转换电路连接块数据总线E。
需要说明的是，将本地数据总线按照自然数从零依次编号，编号为奇数的本地数据 总线定义为本地数据总线O，编号为偶数的本地数据总线定义为本地数据总线E；或者说，物理位置相邻的存储阵列对应的本地数据总线中，处于奇数位置的本地数据总线定义为本地数据总线O，处于偶数位置的本地数据总线定义为本地数据总线E。
由于物理上相邻的数据放在不同的检错纠错单元中，即分别进入第一检错纠错单元103和第二检错纠错单元104中，当有两比特相邻错误发生的时候，由于这两比特错误分别在不同的检错纠错单元中进行纠错，因此能够同时处理掉这两比特错误。可以理解的是，即使工艺尺寸不断缩小，相邻电容器之间发生桥连的风险增加，但是由于相邻电容器对应的数据进入到不同的检错纠错单元中进行纠错，因此即使工艺尺寸不断缩小，仍能保证物理上相邻的两比特数据的错误均能被纠正。
继续参考图3，列译码电路YDEC以及与列译码电路YDEC产生的列选择信号CSL，该列选择信号CSL与多个存储阵列105电连接，通过列选择信号CSL选择进行存储操作的存储阵列105。继续参考图4，在一种实施例中，列选择信号CSL对应图4中的CSL<n-1>、CSL<n>以及CSL<n+1>。
继续参考图3，U存储子块101中的存储阵列105的排布按照自然数从1开始编号，块数据总线与编号为偶数的存储阵列105电连接。在一些实施例中，存储阵列105包括存储单元、本地数据总线E、本地数据总线O和本地转换电路，块数据总线通过本地转换电路与本地数据总线E连接；块数据总线通过本地转换电路与本地数据总线O连接，图3中以三角形符号标示了块数据总线与存储阵列105的连接关系。有关V存储子块102的块数据总线的连接关系的说明，可参考关于U存储子块101的相应描述，以下将不做赘述。
本实施例中，为了减小列选择信号线CSL1的长度，以便于减小列选择信号线CSL1的寄生电阻，从而降低功耗。对于U存储子块101，列译码电路YDEC分别位于多个存储阵列105的相对两侧，对于V存储子块102，列译码电路YDEC分别位于多个存储阵列105的相对两侧。需要说明的是，在其他实施例中，对于每一U存储子块或者V存储子块而言，列译码电路的数量也可以为一个。
可以理解的是，在一个例子中，块数据总线为2*4*(16*N)条，本地数据总线为2*4*M*(16*N)条；块数据总线O为4*(16*N)条，块数据总线E为4*(16*N)条；本地数据总线O为4*M*(16*N)条，本地数据总线E为4*M*(16*N)条；1条块数据总线O与M条本地数据总线O相对应，1条块数据总线E与M条本地数据总线E相对应；本地数据总线以相邻的4条为一组被划分为M*(16*N)组的本地数据总线O和M*(16*N)组的 本地数据总线E。其中，M和N为大于或等于1的自然数。以M和N均为1为例，块数据总线为2*4*16条，本地数据总线为2*4*16条，块数据总线O为4*16条，块数据总线E为4*16条，本地数据总线O为4*16条，本地数据总线E为4*16条，共16组本地数据总线O和16组本地数据总线E。
在一个例子中，如图3所示，U存储子块101包括偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO1_O)连接第一检错纠错单元103，编号为偶数的块数据总线E(记为YIO1_E)连接第二检错纠错单元104；V存储子块102包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(记为YIO2_O)连接第一检错纠错单元103，编号为偶数的块数据总线E(记为YIO2_E)连接第二检错纠错单元104。
这样，U存储子块101的块数据总线O(YIO1_O)的数据以及V存储子块102的块数据总线O(YIO2_O)的数据进入第一检错纠错单元103进行检错纠错；U存储子块101的块数据总线E(YIO1_E)的数据以及V存储子块102的块数据总线E(YIO2_E)的数据进入第二检错纠错单元104进行检错纠错。
在另一例子中，如图5所示，U存储子块101包括偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(YIO1_O)连接第一检错纠错单元103，编号为偶数的块数据总线E(YIO1_E)连接第二检错纠错单元104；V存储子块102包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(YIO2_O)连接第二检错纠错单元104，编号为偶数的块数据总线E(YIO2_E)连接第一检错纠错单元103。
继续参考图5，U存储子块101的块数据总线O(YIO1_O)的数据以及V存储子块102的块数据总线E(YIO2_E)的数据进入第一检错纠错单元103进行检错纠错；U存储子块101的块数据总线E(YIO1_E)的数据以及V存储子块102的块数据总线O(YIO2_O)的数据进入第二检错纠错单元104进行检错纠错。
在又一例子中，如图6所示，U存储子块101包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(YIO1_O)连接所述第二检错纠错单元104，编号为偶数的块数据总线E(YIO1_E)连接第一检错纠错单元103；V存储子块102包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(YIO2_O)连接第一检错纠错单元103，编号为偶数的块数据总线E(YIO2_E)连接第二检错纠错单元104。
继续参考图6，U存储子块101的块数据总线E(YIO1_E)的数据以及V存储子块102的块数据总线O(YIO2_O)的数据进入第一检错纠错单元103进行检错纠错；U存储子块101的块数据总线O(YIO1_O)的数据以及V存储子块102的块数据总线E(YIO2_E)的数据进入第二检错纠错单元104进行检错纠错。
在再一例子中，如图7所示，U存储子块101包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(YIO1_O)连接第二检错纠错单元104，编号为偶数的块数据总线E(YIO1_E)连接第一检错纠错单元103；V存储子块包含偶数条块数据总线，将块数据总线按自然数从零依次编号，编号为奇数的块数据总线O(YIO2_O)连接第二检错纠错单元104，编号为偶数的块数据总线E(YIO2_E)连接第一检错纠错单元103。
继续参考图7，U存储子块101的块数据总线E的数据以及V存储子块102的块数据总线E(YIO1_E和YIO2_E)的数据进入第一检错纠错单元103进行检错纠错；U存储子块101的块数据总线O的数据以及V存储子块102的块数据总线O(YIO1_O和YIO2_O)的数据进入第二检错纠错单元104进行检错纠错。
本实施例提供的存储器，由于同一存储子块的输出数据分别输入至不同的检错纠错单元中，即部分输出数据输入至第一检错纠错单元103进行检错纠错，其余部分输出数据输入至第二检错纠错单元104进行检错纠错，这样如果同时存在两比特数据出错，则第一检错纠错单元103和第二检错纠错单元104能够分别对两比特中的一比特数据进行纠正，从而提高存储器的检错纠错能力。
本公开另一实施例还提供一种存储器，该存储器与前述实施例提供的存储器大致相同，主要区别包括另一实施例中，U存储子块的输出数据包括高比特位数据(高位数据)和低比特位数据(低位数据)；V存储子块的输出数据包括高比特位数据和低比特位数据。以下将结合附图对本公开另一实施例提供的存储器进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细说明，以下将不做赘述。
图8为本公开另一实施例提供的存储器的一种结构示意图，图9为本公开另一实施例提供的存储器的另一种结构示意图。
参考图8，本实施例中，存储器包括：多个存储块200，存储块200包括U存储子块和V存储子块；第一检错纠错单元203以及第二检错纠错单元204。
存储器还包括列译码电路YDEC以及块放大器210。存储块200包括多个存储阵列205。在一个例子中，U存储子块的输出数据中部分对应为高位数据，其余部分对应为 低位数据；V存储子块的输出数据中部分对应为高位数据，其余部分对应为低位数据。在一个例子中，U存储子块的输出数据中一半对应为高位数据，另一半对应为低位数据；V存储子块的输出数据中一半对应为高位数据，另一半对应为低位数据。
这样，由于U存储子块的输出数据包括低位数据和高位数据，因此单次访问只会访问U存储子块中的部分存储阵列，从而降低存储器的功耗；同样的，由于V存储子块的输出数据包括低位数据和高位数据，因此单次访问只会访问V存储子块中的部分存储阵列，也有利于降低存储器的功耗。
在一个例子中，如图8所示，U存储子块包括第一U存储子块211以及第二U存储子块221，第一U存储子块211输出数据为高位数据，第二U存储子块221输出数据为低位数据。V存储子块包括第一V存储子块212以及第二V存储子块222，第一V存储子块212输出数据为高位数据，第二V存储子块222输出数据为低位数据。
U存储子块包括块数据总线，包括与第一U存储子块211对应的块数据总线YIO_U1_O(编号为奇数)和块数据总线YIO_U1_E(编号为偶数)，以及与第二U存储子块221对应的块数据总线YIO_U2_O(编号为奇数)和块数据总线YIO_U2_E(编号为偶数)。V存储子块包括块数据总线，包括与第一V存储子块212对应的块数据总线YIO_V1_O(编号为奇数)和块数据总线YIO_V1_E(编号为偶数)，以及与第二V存储子块222对应的块数据总线YIO_V2_O(编号为奇数)和块数据总线YIO_V2_E(编号为偶数)。块数据总线YIO_U1_E、块数据总线YIO_U2_E、块数据总线YIO_V1_E、块数据总线YIO_V2_E与第一检错纠错单元203连接，块数据总线YIO_U1_O、块数据总线YIO_U2_O、块数据总线YIO_V1_O、块数据总线YIO_V2_O与第二检错纠错单元204的连接，图8中三角形206表示块数据总线与相应的存储阵列205电连接。
继续参考图8，提供一实施例，例如，将第一U存储子块211的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_U1_E)、第二U存储子块221的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_U2_E)、第一V存储子块212的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_V1_E)、第二V存储子块222的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_V2_E)，总共136bits(128bits有效数据+8bits校验位)输入第一检错纠错单元203；将第一U存储子块211的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_U1_O)、第二U存储子块221的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_U2_O)、第一V存储子块212的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_V1_O)、第二V存 储子块222的34bits(32bits有效数据+2bits校验位，对应块数据总线YIO_V2_O)，总共136bits(128bits有效数据+8bits校验位)输入第二检错纠错单元204。由于同一存储子块(例如第一U存储子块211)的输出数据分别输入至不同的检错纠错单元中，即部分输出数据输入至第一检错纠错单元203进行检错纠错，其余部分输出数据输入至第二检错纠错单元204进行检错纠错，这样如果同时存在两比特数据出错，则第一检错纠错单元203和第二检错纠错单元204能够分别对两比特中的一比特数据进行纠正，从而提高存储器的检错纠错能力。
在另一例子中，如图9所示，U存储子块包括依次排列的第一U存储子块211、第二U存储子块221、第三U存储子块231以及第四U存储子块241，第一U存储子块211以及第三U存储子块231的输出数据为高位数据，第二U存储子块221以及第四U存储子块241的输出数据为低位数据。V存储子块包括依次排列的第一V存储子块212、第二V存储子块222、第三V存储子块232以及第四V存储子块242，第一V存储子块212以及第三V存储子块232的输出数据为高位数据，第二V存储子块222以及第四V存储子块242的输出数据为低位数据。图9中三角形206表示块数据总线与相应的存储阵列205电连接。
如前一实施例所述，按照奇数偶数位置将U存储子块对应的块数据总线划分为块数据总线YIO_U_O1、块数据总线YIO_U_O2、块数据总线YIO_U_E1、块数据总线YIO_U_E2；按照奇数偶数位置将V存储子块对应的块数据总线划分为块数据总线YIO_V_O1、块数据总线YIO_V_O2、块数据总线YIO_V_E1、块数据总线YIO_V_E2。其中，块数据总线YIO_U_O1与第一U存储子块211、和第三U存储子块231连接，块数据总线YIO_U_O2与第二U存储子块221、和第四U存储子块241连接；块数据总线YIO_V_O1与第一V存储子块212、和第三V存储子块232连接，块数据总线YIO_V_O2与第二V存储子块222、和第四V存储子块242连接。
有关U存储子块和V存储子块对应的块数据总线与第一纠错单元203和第二纠错单元204的连接关系，可参考前述实施例的说明在此不再赘述。
与前述实施例相比，本实施例提供的存储器不仅能同时对两位进行纠错，且由于U存储子块和V存储子块中输出数据部分为高位数据，其余为低位数据，因此在单次访问存储器时仅访问U存储子块或者V存储子块中的部分存储阵列，有利于降低存储器的功耗。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的示例性的实施例， 而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (13)

  1. 一种存储器，包括存储块，所述存储块包括U存储子块和V存储子块，包括：
    第一检错纠错单元，与所述U存储子块、所述V存储子块均连接，用于对所述U存储子块和所述V存储子块的输出数据进行检错纠错；
    第二检错纠错单元，与所述U存储子块、所述V存储子块均连接，用于对所述U存储子块和所述V存储子块的所述输出数据进行检错纠错。
  2. 如权利要求1所述的存储器，其中，所述第一检错纠错单元的输入位数与所述第二检错纠错单元的输入位数相同。
  3. 如权利要求1所述的存储器，其中，所述第一检错纠错单元的内部检错算法与所述第二检错纠错单元的内部检错算法相同。
  4. 如权利要求1所述的存储器，其中，所述U存储子块的存储容量与所述V存储子块的存储容量相同。
  5. 如权利要求1所述的存储器，其中，所述U存储子块包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O连接所述第一检错纠错单元，编号为偶数的块数据总线E连接所述第二检错纠错单元。
  6. 如权利要求1所述的存储器，其中，所述U存储子块包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O连接所述第二检错纠错单元，编号为偶数的块数据总线E连接所述第一检错纠错单元。
  7. 如权利要求1所述的存储器，其中，所述V存储子块包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O连接所述第一检错纠错单元，编号为偶数的块数据总线E连接所述第二检错纠错单元。
  8. 如权利要求1所述的存储器，其中，所述V存储子块包含偶数条块数据总线，将所述块数据总线按自然数从零依次编号，编号为奇数的块数据总线O连接所述第二检错纠错单元，编号为偶数的块数据总线E连接所述第一检错纠错单元。
  9. 如权利要求5或6或7或8所述的存储器，其中，所述V存储子块和所述U存储子块均包括本地转换电路和偶数条本地数据总线，所述本地数据总线分为本地数据总线O和本地数据总线E，所述本地数据总线O通过所述本地转换电路连接所述块数据总线O，所述本地数据总线E通过所述本地转换电路连接所述块数据总线E。
  10. 如权利要求9所述的存储器，其中，每条所述本地数据总线通过选通开关与偶 数个灵敏放大器连接，所述灵敏放大器与所述存储器中的位线一一对应设置。
  11. 如权利要求10所述的存储器，其中，相邻两条所述位线上的所述输出数据经所述灵敏放大器和所述选通开关分别进入所述本地数据总线O和所述本地数据总线E。
  12. 如权利要求11所述的存储器，其中，所述块数据总线为2*4*(16*N)条，所述本地数据总线为2*4*M*(16*N)条；所述块数据总线O为4*(16*N)条，所述块数据总线E为4*(16*N)条；所述本地数据总线O为4*M*(16*N)条，所述本地数据总线E为4*M*(16*N)条；1条所述块数据总线O与M条所述本地数据总线O相对应，1条所述块数据总线E与M条所述本地数据总线E相对应；所述本地数据总线以相邻的4条为一组被划分为M*(16*N)组的所述本地数据总线O和M*(16*N)组的所述本地数据总线E。
  13. 如权利要求1所述的存储器，其中，所述U存储子块的所述输出数据包括高比特位数据和低比特位数据；所述V存储子块的所述输出数据包括高比特位数据和低比特位数据。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11869610B2 (en) 2021-06-01 2024-01-09 Changxin Memory Technologies, Inc. Storage device
US11935612B2 (en) 2021-06-01 2024-03-19 Changxin Memory Technologies, Inc. Memory using dual sense amplifiers for error detection and correction

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1771565A (zh) * 2003-08-18 2006-05-10 富士通株式会社 半导体存储器以及半导体存储器的操作方法
US20070214403A1 (en) * 1999-06-16 2007-09-13 Madrone Solutions, Inc. Method and apparatus for error detection and correction
CN101622603A (zh) * 2007-08-31 2010-01-06 株式会社东芝 半导体存储器件及其控制方法
CN101946239A (zh) * 2008-02-29 2011-01-12 株式会社东芝 半导体存储装置及其控制方法和错误纠正系统
CN102436406A (zh) * 2010-09-15 2012-05-02 株式会社东芝 半导体装置及其数据存取方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4509172A (en) * 1982-09-28 1985-04-02 International Business Machines Corporation Double error correction - triple error detection code
ATE216096T1 (de) * 1994-02-22 2002-04-15 Siemens Ag Flexible fehlerkorrekturcode/paritätsbit- architektur
JP3944380B2 (ja) * 2001-11-08 2007-07-11 日本テキサス・インスツルメンツ株式会社 誤り訂正回路を備えた半導体記憶装置
CA2447204C (en) * 2002-11-29 2010-03-23 Memory Management Services Ltd. Error correction scheme for memory
JP4703220B2 (ja) * 2005-03-04 2011-06-15 株式会社東芝 半導体記憶装置
JP4791831B2 (ja) * 2006-01-20 2011-10-12 株式会社東芝 半導体記憶装置
KR100856129B1 (ko) * 2006-12-29 2008-09-03 삼성전자주식회사 오정정 확률을 줄이는 에러 정정 회로, 그 방법 및 상기회로를 구비하는 반도체 메모리 장치
TWI381392B (zh) * 2010-02-04 2013-01-01 Transcend Information Inc 雙層面記憶體錯誤修正方法以及相關的記憶體裝置
CN102339641B (zh) * 2010-07-23 2014-12-17 北京兆易创新科技股份有限公司 检错/纠错校验模块及该模块读写数据的方法
JP2014096021A (ja) * 2012-11-09 2014-05-22 Nec Corp ブロックメモリ装置、データ補正方法およびプログラム
KR20200028255A (ko) * 2018-09-06 2020-03-16 에스케이하이닉스 주식회사 컨트롤러 및 그 동작 방법
CN111078459B (zh) * 2018-10-22 2022-11-29 长鑫存储技术有限公司 半导体芯片的测试方法、装置及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070214403A1 (en) * 1999-06-16 2007-09-13 Madrone Solutions, Inc. Method and apparatus for error detection and correction
CN1771565A (zh) * 2003-08-18 2006-05-10 富士通株式会社 半导体存储器以及半导体存储器的操作方法
CN101622603A (zh) * 2007-08-31 2010-01-06 株式会社东芝 半导体存储器件及其控制方法
CN101946239A (zh) * 2008-02-29 2011-01-12 株式会社东芝 半导体存储装置及其控制方法和错误纠正系统
CN102436406A (zh) * 2010-09-15 2012-05-02 株式会社东芝 半导体装置及其数据存取方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11869610B2 (en) 2021-06-01 2024-01-09 Changxin Memory Technologies, Inc. Storage device
US11935612B2 (en) 2021-06-01 2024-03-19 Changxin Memory Technologies, Inc. Memory using dual sense amplifiers for error detection and correction

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