WO2022033100A1 - 半导体结构及半导体结构的制造方法 - Google Patents

半导体结构及半导体结构的制造方法 Download PDF

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Publication number
WO2022033100A1
WO2022033100A1 PCT/CN2021/094441 CN2021094441W WO2022033100A1 WO 2022033100 A1 WO2022033100 A1 WO 2022033100A1 CN 2021094441 W CN2021094441 W CN 2021094441W WO 2022033100 A1 WO2022033100 A1 WO 2022033100A1
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Prior art keywords
diffusion barrier
hole
substrate
layer
barrier material
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French (fr)
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汪雷
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/409,876 priority Critical patent/US20220051974A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
  • the present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure to improve the performance of the semiconductor structure.
  • a semiconductor structure comprising:
  • a semiconductor base a plug contact hole is arranged on the semiconductor base, and a groove is arranged on the side wall of the bottom of the plug contact hole;
  • a diffusion barrier layer which is arranged on the hole wall of the plug contact hole and fills the groove
  • the conductive plug is disposed in the diffusion barrier layer.
  • the semiconductor body includes:
  • the dielectric layer is arranged on the substrate, and the dielectric layer has a first through hole;
  • a protective layer the protective layer is arranged above the dielectric layer, the protective layer has a second through hole, the first through hole and the second through hole are connected, and the vertical projection of the second through hole facing the substrate is located at the position where the first through hole faces the substrate. In vertical projection;
  • a groove is formed between the substrate and the protective layer.
  • the depth of the groove in the first direction is 5 nm ⁇ 20 nm, and the first direction is perpendicular to the extending direction of the first through hole.
  • the thickness of the dielectric layer in the second direction is 20 nm to 200 nm
  • the thickness of the protective layer in the second direction is 50 nm to 500 nm
  • the second direction is perpendicular to the substrate.
  • a diffusion barrier layer is disposed between the semiconductor substrate and the conductive plug.
  • the diffusion barrier layer includes a first main body portion and a first protruding portion, the first protruding portion is provided on the hole wall of the plug contact hole and fills the groove, and the first main body portion is provided on the hole wall of the plug contact hole. on the semiconductor substrate and outside the plug contact hole;
  • the conductive plug includes a second main body part and a second protruding part, the second protruding part is arranged in the first main body part and the first protruding part, and the second main body part is arranged on the first main body part.
  • the thickness of the first main body portion in the second direction is 10 nm ⁇ 50 nm
  • the thickness of the second main body portion in the second direction is 100 nm ⁇ 800 nm
  • the second direction is perpendicular to the substrate.
  • the diffusion barrier layer includes a first diffusion barrier material and a second diffusion barrier material, the first diffusion barrier material is filled in the groove, and the second diffusion barrier material covers the inner wall of the first diffusion barrier material and the second diffusion barrier material.
  • the inner wall of the protective layer includes a first diffusion barrier material and a second diffusion barrier material, the first diffusion barrier material is filled in the groove, and the second diffusion barrier material covers the inner wall of the first diffusion barrier material and the second diffusion barrier material. The inner wall of the protective layer.
  • a method for fabricating a semiconductor structure comprising:
  • the second diffusion barrier material covers the inner wall of the first diffusion barrier material and the hole wall of the plug contact hole, and the first diffusion barrier material and the second diffusion barrier material form a diffusion barrier layer;
  • a conductive plug is formed by filling the diffusion barrier layer.
  • forming a semiconductor substrate with plug contact holes includes:
  • a protective layer with a second through hole is formed on the dielectric layer, the second through hole is communicated with the opening, and the opening of the second through hole coincides with the opening of the opening.
  • forming the protective layer includes:
  • the protective material is etched to form a protective layer with a second through hole on the protective material, and an opening is etched.
  • the method for manufacturing the semiconductor structure further includes:
  • the second diffusion barrier material covers the hole wall of the opening, the hole wall of the second through hole and the protective layer.
  • a method for fabricating a semiconductor structure comprising:
  • the diffusion barrier layer is arranged on the hole wall of the plug contact hole, and fills the groove;
  • a conductive plug is formed by filling the diffusion barrier layer.
  • forming a semiconductor body includes:
  • a protective layer with a second through hole is formed on the dielectric layer, the first through hole is connected with the second through hole, and the vertical projection of the second through hole toward the substrate is located within the vertical projection of the first through hole toward the substrate;
  • a groove is formed between the substrate and the protective layer.
  • the diffusion barrier layer is embedded in the semiconductor substrate, thereby increasing the contact area between the diffusion barrier layer and the semiconductor substrate, thereby improving leakage current and improving the stability of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment
  • FIG. 2 is a schematic flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 3 is a schematic structural diagram of forming a dielectric material on a substrate according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 4 is a schematic structural diagram of forming a dielectric layer on a substrate according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 5 is a schematic structural diagram of forming a first diffusion barrier material according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 6 is a schematic structural diagram of removing part of the first diffusion barrier material in a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 7 is a schematic structural diagram of forming an opening according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 8 is a schematic structural diagram of forming a protective material according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 9 is a schematic structural diagram of forming a protective layer according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 10 is a schematic structural diagram of forming a diffusion barrier layer according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 11 is a schematic flowchart of a method for manufacturing a semiconductor structure according to another exemplary embodiment.
  • the semiconductor structure includes: a semiconductor base 10 , a plug contact hole 14 is formed on the semiconductor base 10 , and a groove is formed on the sidewall of the bottom of the plug contact hole 14 15.
  • the diffusion barrier layer 20 is arranged on the hole wall of the plug contact hole 14 and fills the groove 15; the conductive plug 30 is arranged in the diffusion barrier layer 20.
  • the diffusion barrier layer 20 is embedded in the semiconductor substrate 10 , thereby increasing the contact area between the diffusion barrier layer 20 and the semiconductor substrate 10 , thereby improving leakage current and improving the stability of the semiconductor structure.
  • the semiconductor base 10 is provided with a plug contact hole 14 .
  • the semiconductor base 10 has a receiving slot
  • the plug contact hole 14 has an opening
  • the groove 15 surrounds the plug contact hole in the circumferential direction of the plug contact hole 14
  • the hole wall of the plug contact hole 14 is arranged, that is, an annular groove is formed on the hole wall of the plug contact hole 14 , which is an embedded groove relative to the plug contact hole 14 .
  • the diffusion barrier layer 20 is provided on the hole wall of the plug contact hole 14 , that is, the diffusion barrier layer 20 is also provided on the outer side opposite to the opening of the groove 15 , rather than only the diffusion barrier layer 20 is provided in the groove 15 , namely The diffusion barrier layer 20 between the bottom end sidewall of the conductive plug 30 and the semiconductor body 10 is relatively thick.
  • the conductive plug 30 may be a metallic material, eg, Cu, Al, W, or alloys thereof.
  • the diffusion barrier layer 20 may include Ta, Ti, Ru, TaN, TiN, RuTa, RuTaN, W, Ir, or the like.
  • the diffusion barrier layer 20 may be any other material that prevents the conductive material from diffusing therethrough.
  • the semiconductor base 10 includes: a substrate 11; a dielectric layer 12, the dielectric layer 12 is disposed on the substrate 11, and the dielectric layer 12 has a first through hole 121; a protective layer 13, the protective layer 13 is disposed on the dielectric layer Above 12 , the protective layer 13 has a second through hole 131 , the first through hole 121 and the second through hole 131 are connected, and the vertical projection of the second through hole 131 toward the substrate 11 is located where the first through hole 121 faces the substrate 11 . In the vertical projection; wherein, a groove 15 is formed between the substrate 11 and the protective layer 13 .
  • a dielectric layer 12 is provided on the substrate 11 , and a first through hole 121 is opened in the middle of the dielectric layer 12 , that is, the upper surface of the substrate 11 is exposed, and the upper surface of the dielectric layer 12 is opened.
  • a protective layer 13 is provided, and a second through hole 131 is opened in the middle of the protective layer 13, that is, part of the hole section of the first through hole 121 can be exposed.
  • the protective layer 13 covers a part of the first through hole 121 , and the covering part is the space sandwiched between the substrate 11 and the protective layer 13 , that is, the groove 15 is formed (combined with FIG. 9 , the groove 15 is filled with There is a first diffusion barrier material 40).
  • the substrate 11 may comprise a semiconductor substrate.
  • the semiconductor substrate may be formed of a silicon-containing material.
  • the semiconductor substrate may be formed of any suitable material, including, for example, at least one of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.
  • the dielectric layer 12 may include materials such as SiN, SiCN, and the like.
  • the protective layer 13 may include SiO2, SiOC and other materials.
  • the depth of the groove 15 in the first direction is 5 nm ⁇ 20 nm, and the first direction is perpendicular to the extending direction of the first through hole 121 .
  • a diffusion barrier layer 20 with a thickness of 5 nm to 20 nm is added to increase the thickness of the diffusion barrier layer 20 on the bottom sidewall of the conductive plug 30, thereby avoiding the formation of Diffusion of the metallic material of the conductive plug 30 .
  • the extending direction of the first through hole 121 is the direction perpendicular to the substrate 11 , so the first direction can be understood as being parallel to the substrate 11 . Accordingly, the second direction is perpendicular to the substrate 11, and thus, the first direction is perpendicular to the second direction. Perpendicular to the substrate 11 can be understood as being perpendicular to the upper surface of the substrate 11 .
  • grooves 15 may be filled with the diffusion barrier layer 20 .
  • the thickness of the dielectric layer 12 in the second direction is 20 nm ⁇ 200 nm.
  • the thickness of the protective layer 13 in the second direction is 50 nm ⁇ 500 nm.
  • a diffusion barrier layer 20 is disposed between the semiconductor substrate 10 and the conductive plug 30 , that is, the semiconductor substrate 10 and the conductive plug 30 are completely isolated by the diffusion barrier layer 20 .
  • the diffusion barrier layer 20 includes a first main body part 21 and a first protruding part 22 .
  • the first protruding part 22 is disposed on the hole wall of the plug contact hole 14 and fills the groove 15 .
  • the conductive plug 30 includes a second body portion 31 and a second protruding portion 32, and the second protruding portion 32 is provided on the first body portion 21 and the second protruding portion 32.
  • the second main body portion 31 is disposed on the first main body portion 21 .
  • the first protrusion 22 of the diffusion barrier layer 20 is disposed inside the semiconductor substrate 10 , that is, on the hole wall of the plug contact hole 14 and in the groove 15 , and the diffusion barrier layer 20 is
  • the first main body portion 21 covers the upper surface of the semiconductor base 10 .
  • the second protruding portion 32 of the conductive plug 30 is filled in the accommodating space formed by the first main body portion 21 and the first protruding portion 22 , and the conductive plug 30
  • the second main body portion 31 covers the upper surface of the diffusion barrier layer 20 , that is, the semiconductor substrate 10 and the conductive plug 30 are completely separated by the diffusion barrier layer 20 .
  • the thickness of the first body portion 21 in the second direction is 10 nm ⁇ 50 nm.
  • the thickness of the second body portion 31 in the second direction is 100 nm ⁇ 800 nm.
  • the diffusion barrier layer 20 includes a first diffusion barrier material 40 and a second diffusion barrier material 44 , the first diffusion barrier material 40 is filled in the groove 15 , and the second diffusion barrier material 44 The inner wall of the first diffusion barrier material 40 and the inner wall of the protective layer 13 are covered.
  • first diffusion barrier material 40 and the second diffusion barrier material 44 may be integrally formed, that is, formed in the groove 15 and the plug contact hole 14 at one time.
  • first diffusion barrier material 40 and the second diffusion barrier material 44 are formed independently, that is, after the first diffusion barrier material 40 is filled in the groove 15, after other steps, the second diffusion barrier material 44 is Formed in the plug contact hole 14 .
  • the diffusion barrier layer 20 includes a first diffusion barrier material 40 and a second diffusion barrier material 44
  • the first body portion 21 of the diffusion barrier layer 20 includes a portion of the second diffusion barrier material 44 , that is, covering the semiconductor substrate 10
  • the first protrusion 22 of the diffusion barrier layer 20 includes other second diffusion barrier materials 44 and all of the first diffusion barrier materials 40 .
  • the semiconductor structure of the present disclosure improves the stability of the semiconductor structure by embedding a portion of the diffusion barrier layer 20 in the semiconductor substrate 10 to balance the metal stress formed by the conductive plug 30 to cope with high-density current flushing.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, please refer to FIG. 2 , including:
  • the second diffusion barrier material 44 covers the inner wall of the first diffusion barrier material 40 and the hole wall of the plug contact hole 14, the first diffusion barrier material 40 and the second diffusion barrier material material 44 forms diffusion barrier 20;
  • the diffusion barrier layer 20 is filled in the groove 15 of the semiconductor substrate 10 , that is, the in-cell diffusion barrier layer 20 is formed, so that the connection between the diffusion barrier layer 20 and the semiconductor substrate 10 can be increased. contact area, thereby improving leakage current and improving the stability of the semiconductor structure.
  • the groove 15 is filled with the first diffusion barrier material 40, and the plug contact hole 14 is filled with the second diffusion barrier material 44, that is, the first diffusion barrier material 40 and the second diffusion barrier material 44 form a diffusion barrier layer 20.
  • forming the semiconductor base 10 having the plug contact holes 14 includes: providing a substrate 11 ; forming the dielectric layer 12 having the first through holes 121 on the substrate 11 ; filling the first diffusion barrier material 40 The first through hole 121 covers the dielectric layer 12; the first diffusion barrier material 40 on the dielectric layer 12 is removed to expose the dielectric layer 12, and the upper surface of the first diffusion barrier material 40 and the upper surface of the dielectric layer 12 remain Flush; partially etch the first diffusion barrier material 40 in the first through hole 121 to form an opening 41 in the first diffusion barrier material 40 and expose the substrate 11 ; form a second through hole 131 on the dielectric layer 12 In the protective layer 13 , the second through hole 131 communicates with the opening 41 , and the aperture of the second through hole 131 coincides with the aperture of the opening 41 .
  • forming the semiconductor base 10 includes: providing a substrate 11 ; forming a dielectric layer 12 with first through holes 121 on the substrate 11 ; forming a protective layer with second through holes 131 on the dielectric layer 12 13.
  • the first through hole 121 and the second through hole 131 communicate with each other; wherein, a groove 15 is formed between the substrate 11 and the protective layer 13 .
  • the semiconductor base 10 may include a substrate 11 , a dielectric layer 12 and a protective layer 13 , and the dielectric layer 12 and the protective layer 13 are sequentially formed on the substrate 11 , that is, after the dielectric layer 12 is formed on the substrate 11 , on the dielectric layer 12
  • the protective layer 13 is formed.
  • the substrate 11 may be a semiconductor substrate containing silicon material.
  • the semiconductor substrate may be formed of any suitable material, including, for example, at least one of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.
  • the dielectric material 42 is etched, so that the first through holes 121 are etched on the dielectric material 42 and the upper surface of the substrate 11 is exposed, As shown in FIG. 4 , the dielectric layer 12 having the first through holes 121 is formed on the substrate 11 at this time.
  • the dielectric material 42 may include materials such as SiN, SiCN, and the like.
  • the dielectric material 42 may be formed on the substrate 11 by a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process or an atomic layer deposition (Atomic Layer Deposition, ALD) process. Then, dry etching or wet etching of the dielectric material 42 may be used to form the first through holes 121 .
  • the thickness of the dielectric layer 12 is 20 nm ⁇ 200 nm.
  • the first diffusion barrier material 40 is made to fill the first through holes 121 and cover the dielectric layer 12 . After the first through hole 121 is formed, the first diffusion barrier material 40 is used for filling, and then most of the first diffusion barrier material 40 is removed, but a small amount of the first diffusion barrier material 40 is retained to fill the first through hole 121, that is, filling In the groove 15 , a portion of the diffusion barrier layer 20 embedded in the semiconductor substrate 10 is formed.
  • the first diffusion barrier material 40 may include Ta, Ti, Ru, TaN, TiN, RuTa, RuTaN, W, Ir, or the like.
  • the first diffusion barrier material 40 may be any other material that prevents the conductive material from diffusing therethrough.
  • the first diffusion barrier material 40 may be formed on the dielectric layer 12 by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process, and the first diffusion barrier material 40 fills the first through holes 121 . And cover the dielectric layer 12 , as shown in FIG. 5 .
  • Dry etching or chemical mechanical polishing is used to remove the first diffusion barrier material 40 covering the dielectric layer 12, thereby exposing the dielectric layer 12, and the dielectric layer 12 and the first through holes 121.
  • the first diffusion barrier material 40 is flush, as shown in FIG. 6 .
  • the first diffusion barrier material 40 in the first through hole 121 is etched by dry method, an opening 41 is formed in the first diffusion barrier material 40, and the substrate 11 is exposed, as shown in FIG. 7 .
  • the thickness of the final remaining first diffusion barrier material 40 is 5 nm ⁇ 20 nm, that is, the depth of the groove 15 in the first direction is 5 nm ⁇ 20 nm.
  • forming the protective layer 13 includes: filling the opening 41 with the protective material 43 and covering the dielectric layer 12 and the first diffusion barrier material 40 ; and etching the protective material 43 to form a second diffusion barrier material on the protective material 43 .
  • the protective layer 13 of the through hole 131 is etched and the opening 41 is etched.
  • the protective material 43 may include SiO2, SiOC and other materials.
  • the protective material 43 may be formed on the dielectric layer 12 and the first diffusion barrier material 40 by a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process, and the protective material 43 fills the opening 41 , such as shown in Figure 8.
  • the protective material 43 is etched by dry method, and the etching direction is the direction of the opening 41, so that the protective material 43 in the direction of the opening 41 is completely removed, that is, the complete opening 41 is exposed. At this time, a protective layer with the second through hole 131 is formed 13.
  • the diameters of the second through holes 131 and the openings 41 are equal, that is, the cross-sectional areas of the second through holes 131 and the openings 41 are equal, as shown in FIG. 9 .
  • the thickness of the protective material 43 on the dielectric layer 12 and the first diffusion barrier material 40 is 50 nm to 500 nm, that is, the thickness of the protective layer 13 is 50 nm to 500 nm.
  • the ratio of the thickness of the dielectric layer 12 in the second direction to the thickness of the protective layer 13 in the second direction may be 5% to 30%, such as 8%, 10%, 15%, 20%, and the like.
  • the ratio of the height of the groove 15 in the second direction to the height of the plug contact hole in the second direction may be 5% ⁇ 30%.
  • the manufacturing method of the semiconductor structure further includes: making the second diffusion barrier material 44 cover the hole wall of the opening 41 , the hole wall of the second through hole 131 and the protective layer 13 , the first The diffusion barrier material 40 and the second diffusion barrier material 44 form the diffusion barrier layer 20 .
  • the second diffusion barrier material 44 may include Ta, Ti, Ru, TaN, TiN, RuTa, RuTaN, W, Ir, or the like.
  • the second diffusion barrier material 44 may be any other material that prevents the conductive material from diffusing therethrough.
  • the first diffusion barrier material 40 and the second diffusion barrier material 44 may be selected from the same material, and of course, the selection of different materials is not excluded.
  • the second diffusion barrier material 44 may be formed on the hole wall of the opening 41 , the hole wall of the second through hole 131 and the protective layer 13 by using a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. upper surface, as shown in Figure 10.
  • the thickness of the second diffusion barrier material 44 covering the protective layer 13 is 10 nm ⁇ 50 nm.
  • the first diffusion barrier material 40 and the second diffusion barrier material 44 located in the groove 15 constitute the diffusion barrier layer 20 , that is, the diffusion barrier Layer 20 is prepared in two steps.
  • Cu, Al, W or their alloys can be filled in the second diffusion barrier material 44 by physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process, and cover the upper surface of the second diffusion barrier material 44 to form conductive 30 is plugged, thereby completing the fabrication of the semiconductor structure shown in FIG. 1 .
  • the thickness of the conductive plug 30 covering the upper surface of the second diffusion barrier material 44 is 100 nm ⁇ 800 nm.
  • a method of fabricating a semiconductor structure is used to fabricate the semiconductor structure described above.
  • the first diffusion barrier material 40 and the second diffusion barrier material 44 are used to fill the semiconductor substrate 10 successively, and the first diffusion barrier material 40 is embedded in the semiconductor substrate 10 to balance the conductive plug.
  • the metal stress formed by 30 can cope with high-density current flushing, thereby improving the stability of the semiconductor structure.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, please refer to FIG. 11 , including:
  • the diffusion barrier layer 20 is disposed on the hole wall of the plug contact hole 14, and fills the groove 15;
  • the diffusion barrier layer 20 is filled in the groove 15 of the semiconductor substrate 10 , that is, the in-cell diffusion barrier layer 20 is formed, so that the connection between the diffusion barrier layer 20 and the semiconductor substrate 10 can be increased. contact area, thereby improving leakage current and improving the stability of the semiconductor structure.
  • the diffusion barrier layer 20 in this embodiment is filled into the groove 15 and the plug contact hole 14 at one time.
  • forming the semiconductor base 10 includes: providing a substrate 11 ; forming a dielectric layer 12 with first through holes 121 on the substrate 11 ; forming a protective layer with second through holes 131 on the dielectric layer 12 13.
  • the first through hole 121 and the second through hole 131 are connected, and the vertical projection of the second through hole 131 toward the substrate 11 is located in the vertical projection of the first through hole 121 toward the substrate 11; wherein the substrate 11 and the protection Grooves 15 are formed between the layers 13 .
  • the groove 15 and the plug contact hole 14 are obtained through two processes, that is, the first through hole 121 and the second through hole 131 are formed in sequence, and after the first through hole 121 and the second through hole 131 are formed, The diffusion barrier layer 20 is filled at one time.
  • the grooves 15 and the plug contact holes 14 are etched in the semiconductor substrate 10 by means of side etching or adjusting the etching selectivity ratio, and then the diffusion barrier layer 20 is formed in the grooves 15 and the plug contact holes 14 .
  • the dielectric layer 12 and the protective layer 13 are sequentially formed on the substrate 11 , and then the protective layer 13 and the dielectric layer 12 are etched, and a wider channel is etched in the dielectric layer 12 by side etching or adjusting the etching selection ratio. holes, so that grooves 15 and plug contact holes 14 are formed in the dielectric layer 12 and the protective layer 13 .
  • a method of fabricating a semiconductor structure is used to fabricate the semiconductor structure described above.
  • the diffusion barrier layer 20 fills the semiconductor substrate 10 at one time, and the diffusion barrier layer 20 is embedded in the semiconductor substrate 10, so as to balance the metal stress formed by the conductive plug 30 to cope with high-density current Erosion, thereby improving the stability of the semiconductor structure.

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Abstract

一种半导体结构及半导体结构的制造方法，所述半导体结构包括半导体基体（10）、扩散阻挡层（20）以及导电栓塞（30），半导体基体（10）上设置有栓塞接触孔（14），栓塞接触孔（14）底部的侧壁上设置有凹槽（15）；扩散阻挡层（20）设置在栓塞接触孔（14）的孔壁上，且填充凹槽（15）；导电栓塞（30）设置在扩散阻挡层（20）内。通过在半导体基体内镶嵌扩散阻挡层，从而增加了扩散阻挡层与半导体基体的接触面积，以此改善漏电流，提升半导体结构的稳定性。

Description

半导体结构及半导体结构的制造方法
交叉引用
本公开要求于2020年08月13日提交的申请号为202010811914.1、名称为“半导体结构及半导体结构的制造方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制造方法。
背景技术
随着半导体的集成度越来越高，电路尺寸逐渐变小，导电栓塞接触结构达到的深度增加且电流密度增大，导电栓塞接触结构在经受高密度电流之后容易产生严重的漏电流问题，影响器件性能。
发明内容
本公开提供一种半导体结构及半导体结构的制造方法，以改善半导体结构的性能。
根据本公开的第一个方面，提供了一种半导体结构，包括：
半导体基体，半导体基体上设置有栓塞接触孔，栓塞接触孔底部的侧壁上设置有凹槽；
扩散阻挡层，扩散阻挡层设置在栓塞接触孔的孔壁上，且填充凹槽；
导电栓塞，导电栓塞设置在扩散阻挡层内。
在本公开的一个实施例中，半导体基体包括：
衬底；
介质层，介质层设置在衬底上，介质层具有第一通孔；
保护层，保护层设置在介质层上方，保护层具有第二通孔，第一通孔和第二通孔相连通，第二通孔朝向衬底的垂直投影位于第一通孔朝向衬底的垂直投影内；
其中，衬底与保护层之间形成凹槽。
在本公开的一个实施例中，凹槽在第一方向上的深度为5nm～20nm，第一方向垂直第一通孔的延伸方向。
在本公开的一个实施例中，介质层在第二方向上的厚度为20nm～200nm，保护层在第 二方向上的厚度为50nm～500nm，第二方向垂直衬底。
在本公开的一个实施例中，半导体基体与导电栓塞之间均设置扩散阻挡层。
在本公开的一个实施例中，扩散阻挡层包括第一主体部和第一凸起部，第一凸起部设置在栓塞接触孔的孔壁上，且填充凹槽，第一主体部设置在半导体基体上，且位于栓塞接触孔的外侧；
导电栓塞包括第二主体部和第二凸起部，第二凸起部设置在第一主体部和第一凸起部内，第二主体部设置在第一主体部上。
在本公开的一个实施例中，第一主体部在第二方向上的厚度为10nm～50nm，第二主体部在第二方向上的厚度为100nm～800nm，第二方向垂直衬底。
在本公开的一个实施例中，扩散阻挡层包括第一扩散阻挡材料和第二扩散阻挡材料，第一扩散阻挡材料填充于凹槽内，第二扩散阻挡材料覆盖第一扩散阻挡材料的内壁和保护层的内壁。
根据本公开的第二个方面，提供了一种半导体结构的制造方法，包括：
形成具有栓塞接触孔的半导体基体，在栓塞接触孔底部的侧壁上设置有填充了第一扩散阻挡材料的凹槽；
在半导体基体上形成第二扩散阻挡材料，第二扩散阻挡材料覆盖第一扩散阻挡材料的内壁和覆盖栓塞接触孔的孔壁，第一扩散阻挡材料和第二扩散阻挡材料形成扩散阻挡层；
在扩散阻挡层内填充形成导电栓塞。
在本公开的一个实施例中，形成具有栓塞接触孔的半导体基体，包括：
提供衬底；
在衬底上形成具有第一通孔的介质层；
使第一扩散阻挡材料填满第一通孔，并覆盖介质层；
去除介质层上的第一扩散阻挡材料，以露出介质层，且保留的第一扩散阻挡材料的上表面与介质层的上表面齐平；
部分蚀刻第一通孔内的第一扩散阻挡材料，以在第一扩散阻挡材料内形成开口，并露出衬底；
在介质层上形成具有第二通孔的保护层，第二通孔与开口相连通，且第二通孔的孔口与开口的孔口相重合。
在本公开的一个实施例中，形成保护层，包括：
使保护材料填满开口，并覆盖介质层和第一扩散阻挡材料；
蚀刻保护材料，以在保护材料上形成具有第二通孔的保护层，并蚀刻出开口。
在本公开的一个实施例中，在形成保护层后，半导体结构的制造方法还包括：
使第二扩散阻挡材料覆盖开口的孔壁、第二通孔的孔壁以及保护层。
根据本公开的第三个方面，提供了一种半导体结构的制造方法，包括：
形成具有栓塞接触孔的半导体基体，在栓塞接触孔底部的侧壁上设置有凹槽；
在半导体基体上形成扩散阻挡层，扩散阻挡层设置在栓塞接触孔的孔壁上，且填充凹槽；
在扩散阻挡层内填充形成导电栓塞。
在本公开的一个实施例中，形成半导体基体，包括：
提供衬底；
在衬底上形成具有第一通孔的介质层；
在介质层上形成具有第二通孔的保护层，第一通孔和第二通孔相连通，第二通孔朝向衬底的垂直投影位于第一通孔朝向衬底的垂直投影内；
其中，衬底与保护层之间形成凹槽。
本公开的半导体结构通过在半导体基体内镶嵌扩散阻挡层，从而增加了扩散阻挡层与半导体基体的接触面积，以此改善漏电流，提升半导体结构的稳定性。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的结构示意图；
图2是根据一示例性实施方式示出的一种半导体结构的制造方法的流程示意图；
图3是根据一示例性实施方式示出的一种半导体结构的制造方法在衬底上形成介质材料的结构示意图；
图4是根据一示例性实施方式示出的一种半导体结构的制造方法在衬底上形成介质层的结构示意图；
图5是根据一示例性实施方式示出的一种半导体结构的制造方法形成第一扩散阻挡材料的结构示意图；
图6是根据一示例性实施方式示出的一种半导体结构的制造方法去除部分第一扩散 阻挡材料的结构示意图；
图7是根据一示例性实施方式示出的一种半导体结构的制造方法形成开口的结构示意图；
图8是根据一示例性实施方式示出的一种半导体结构的制造方法形成保护材料的结构示意图；
图9是根据一示例性实施方式示出的一种半导体结构的制造方法形成保护层的结构示意图；
图10是根据一示例性实施方式示出的一种半导体结构的制造方法形成扩散阻挡层的结构示意图；
图11是根据另一示例性实施方式示出的一种半导体结构的制造方法的流程示意图。
附图标记说明如下：
10、半导体基体；11、衬底；12、介质层；121、第一通孔；13、保护层；131、第二通孔；14、栓塞接触孔；15、凹槽；20、扩散阻挡层；21、第一主体部；22、第一凸起部；30、导电栓塞；31、第二主体部；32、第二凸起部；40、第一扩散阻挡材料；41、开口；42、介质材料；43、保护材料；44、第二扩散阻挡材料。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构，请参考图1，半导体结构包括：半导体基体10，半导体基体10上设置有栓塞接触孔14，栓塞接触孔14底部的侧壁上设置有凹槽15，扩散阻挡层20设置在栓塞接触孔14的孔壁上，且填充凹槽15；导电栓塞30，导 电栓塞30设置在扩散阻挡层20内。
本公开一个实施例的半导体结构通过在半导体基体10内镶嵌扩散阻挡层20，从而增加了扩散阻挡层20与半导体基体10的接触面积，以此改善漏电流，提升半导体结构的稳定性。
具体的，半导体基体10上设置有栓塞接触孔14，可以理解为半导体基体10具有容纳槽孔，栓塞接触孔14具有一个开口，而凹槽15沿栓塞接触孔14的周向方向环绕栓塞接触孔14的孔壁设置，即在栓塞接触孔14的孔壁形成了一个环形凹槽，相对于栓塞接触孔14为内嵌凹槽。
扩散阻挡层20设置在栓塞接触孔14的孔壁上，即与凹槽15的开口相对的外侧也设置有扩散阻挡层20，而不是单纯的仅凹槽15内设置有扩散阻挡层20，即导电栓塞30的底端侧壁与半导体基体10之间的扩散阻挡层20相对较厚。
在一个实施例中，导电栓塞30可以是金属材料，例如，Cu、Al、W或其合金。
在一个实施例中，扩散阻挡层20可以包括Ta、Ti、Ru、TaN、TiN、RuTa、RuTaN、W或Ir等。扩散阻挡层20可以是防止导电材料扩散通过的任何其它材料。
在一个实施例中，半导体基体10包括：衬底11；介质层12，介质层12设置在衬底11上，介质层12具有第一通孔121；保护层13，保护层13设置在介质层12上方，保护层13具有第二通孔131，第一通孔121和第二通孔131相连通，第二通孔131朝向衬底11的垂直投影位于第一通孔121朝向衬底11的垂直投影内；其中，衬底11与保护层13之间形成凹槽15。
具体的，结合图4和图9进行说明，衬底11上设置有介质层12，介质层12的中部开设有第一通孔121，即露出衬底11的上表面，而介质层12的上方设置有保护层13，保护层13的中部开设有第二通孔131，即可以露出第一通孔121的部分孔段，由于第二通孔131的孔径小于第一通孔121的孔径，故保护层13会覆盖一部分的第一通孔121，而此覆盖部分正是夹设于衬底11与保护层13之间的空间，即形成了凹槽15(结合图9，凹槽15内填充有第一扩散阻挡材料40)。
在一个实施例中，衬底11可以包括半导体衬底。半导体衬底可以由含硅材料形成。半导体衬底可以由任何合适的材料形成，例如，包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗以及碳掺杂硅中的至少一种。
在一个实施例中，介质层12可以包括SiN、SiCN等材料。
在一个实施例中，保护层13可以包括SiO2、SiOC等材料。
在一个实施例中，凹槽15在第一方向上的深度为5nm～20nm，第一方向垂直第一通孔121的延伸方向。在覆盖于栓塞接触孔14孔壁上的扩散阻挡层20的厚度基础上，增加5nm～20nm厚度的扩散阻挡层20，以此提高导电栓塞30底部侧壁扩散阻挡层20的厚度，从而避免形成导电栓塞30的金属材料的扩散。
需要说明的是，第一通孔121的延伸方向即为垂直于衬底11的方向，故，第一方向可以理解为平行衬底11。相应地，第二方向垂直衬底11，因此，第一方向垂直于第二方向。垂直于衬底11可以理解为是垂直于衬底11的上表面。
需要注意的是，凹槽15内可均填充有扩散阻挡层20。
在一个实施例中，介质层12在第二方向上的厚度为20nm～200nm。
在一个实施例中，保护层13在第二方向上的厚度为50nm～500nm。
在一个实施例中，如图1所示，半导体基体10与导电栓塞30之间均设置扩散阻挡层20，即半导体基体10与导电栓塞30之间完全通过扩散阻挡层20进行隔离。
在一个实施例中，扩散阻挡层20包括第一主体部21和第一凸起部22，第一凸起部22设置在栓塞接触孔14的孔壁上，且填充凹槽15，第一主体部21设置在半导体基体10上，且位于栓塞接触孔14的外侧；导电栓塞30包括第二主体部31和第二凸起部32，第二凸起部32设置在第一主体部21和第一凸起部22内，第二主体部31设置在第一主体部21上。
具体的，结合图1进行说明，扩散阻挡层20的第一凸起部22设置在半导体基体10的内部，即位于栓塞接触孔14的孔壁上以及凹槽15内，而扩散阻挡层20的第一主体部21覆盖半导体基体10的上表面，相应地，导电栓塞30的第二凸起部32填充在第一主体部21和第一凸起部22形成的容纳空间内，而导电栓塞30的第二主体部31覆盖在扩散阻挡层20的上表面，即半导体基体10与导电栓塞30之间完全通过扩散阻挡层20进行分隔。
在一个实施例中，第一主体部21在第二方向上的厚度为10nm～50nm。
在一个实施例中，第二主体部31在第二方向上的厚度为100nm～800nm。
在一个实施例中，如图1所示，扩散阻挡层20包括第一扩散阻挡材料40和第二扩散阻挡材料44，第一扩散阻挡材料40填充于凹槽15内，第二扩散阻挡材料44覆盖第一扩散阻挡材料40的内壁和保护层13的内壁。
具体的，第一扩散阻挡材料40和第二扩散阻挡材料44可以是一体成型的，即一次成型于凹槽15和栓塞接触孔14内。或者，第一扩散阻挡材料40和第二扩散阻挡材料44是独立成型的，即在将第一扩散阻挡材料40填充于凹槽15后，在经过其他步骤之后，在将 第二扩散阻挡材料44成型于栓塞接触孔14内。
结合图1进行说明，扩散阻挡层20包括第一扩散阻挡材料40和第二扩散阻挡材料44，扩散阻挡层20的第一主体部21包括部分的第二扩散阻挡材料44，即覆盖半导体基体10上表面的部分，而扩散阻挡层20的第一凸起部22包括其他的第二扩散阻挡材料44和全部的第一扩散阻挡材料40。
本公开的半导体结构通过将扩散阻挡层20的部分内嵌入半导体基体10中，以此平衡导电栓塞30形成的金属应力以应对高密度的电流冲刷，从而提升半导体结构的稳定性。
本公开的一个实施例还提供了一种半导体结构的制造方法，请参考图2，包括：
S101，形成具有栓塞接触孔14的半导体基体10，在栓塞接触孔14底部的侧壁上设置有填充了第一扩散阻挡材料40的凹槽15；
S103，在半导体基体10上形成第二扩散阻挡材料44，第二扩散阻挡材料44覆盖第一扩散阻挡材料40的内壁和栓塞接触孔14的孔壁，第一扩散阻挡材料40和第二扩散阻挡材料44形成扩散阻挡层20；
S105，在扩散阻挡层20内填充形成导电栓塞30。
本公开一个实施例的半导体结构的制造方法通过在半导体基体10的凹槽15内填充扩散阻挡层20，即形成了内嵌式扩散阻挡层20，从而可以增加扩散阻挡层20与半导体基体10的接触面积，以此改善漏电流，提升半导体结构的稳定性。
需要说明的是，凹槽15内填充第一扩散阻挡材料40，而栓塞接触孔14内填充第二扩散阻挡材料44，即第一扩散阻挡材料40和第二扩散阻挡材料44形成了扩散阻挡层20。
在一个实施例中，形成具有栓塞接触孔14的半导体基体10，包括：提供衬底11；在衬底11上形成具有第一通孔121的介质层12；使第一扩散阻挡材料40填满第一通孔121，并覆盖介质层12；去除介质层12上的第一扩散阻挡材料40，以露出介质层12，且保留的第一扩散阻挡材料40的上表面与介质层12的上表面齐平；部分蚀刻第一通孔121内的第一扩散阻挡材料40，以在第一扩散阻挡材料40内形成开口41，并露出衬底11；在介质层12上形成具有第二通孔131的保护层13，第二通孔131与开口41相连通，且第二通孔131的孔口与开口41的孔口相重合。
在一个实施例中，形成半导体基体10，包括：提供衬底11；在衬底11上形成具有第一通孔121的介质层12；在介质层12上形成具有第二通孔131的保护层13，第一通孔121和第二通孔131相连通；其中，衬底11与保护层13之间形成凹槽15。
半导体基体10可包括衬底11、介质层12以及保护层13，且介质层12以及保护层 13依次形成于衬底11上，即在衬底11上形成介质层12后，在于介质层12上形成保护层13。
需要说明的是，衬底11可以选择含硅材料的半导体衬底。半导体衬底可以由任何合适的材料形成，例如，包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗以及碳掺杂硅中的至少一种。
在一个实施例中，如图3所示，使介质材料42覆盖衬底11后，蚀刻介质材料42，从而在介质材料42上蚀刻出第一通孔121，并露出衬底11的上表面，如图4所示，此时在衬底11上形成具有第一通孔121的介质层12。
具体的，介质材料42可以包括SiN、SiCN等材料。介质材料42可以采用物理气相沉积(Physical Vapor Deposition，PVD)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺或原子层沉积(Atomic Layer Deposition，ALD)工艺形成于衬底11上。然后可以采用干法蚀刻或者湿法蚀刻介质材料42，以此形成第一通孔121。其中，介质层12的厚度为20nm～200nm。
在一个实施例中，在形成保护层13之前，使第一扩散阻挡材料40填满第一通孔121，并覆盖介质层12。在形成第一通孔121后先采用第一扩散阻挡材料40进行填充，然后去除大部分的第一扩散阻挡材料40，但保留少量的第一扩散阻挡材料40填充第一通孔121，即填充于凹槽15内，以此形成扩散阻挡层20内嵌于半导体基体10内的部分。
具体的，第一扩散阻挡材料40可以包括Ta、Ti、Ru、TaN、TiN、RuTa、RuTaN、W或Ir等。第一扩散阻挡材料40可以是防止导电材料扩散通过的任何其它材料。
在图4的基础上，第一扩散阻挡材料40可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成于介质层12上，第一扩散阻挡材料40填满第一通孔121，并覆盖介质层12，如图5所示。
采用干法蚀刻或者化学机械研磨(Chemical Mechanical Polishing，CMP)去除覆盖在介质层12上的第一扩散阻挡材料40，以此露出介质层12，且介质层12与位于第一通孔121内的第一扩散阻挡材料40平齐，如图6所示。
然后采用干法蚀刻第一通孔121内的第一扩散阻挡材料40，在第一扩散阻挡材料40内形成开口41，并露出衬底11，如图7所示。其中，最终剩余的第一扩散阻挡材料40的厚度为5nm～20nm，即凹槽15在第一方向上的深度为5nm～20nm。
在一个实施例中，形成保护层13，包括：使保护材料43填满开口41，并覆盖介质层12和第一扩散阻挡材料40；蚀刻保护材料43，以在保护材料43上形成具有第二通孔131 的保护层13，并蚀刻出开口41。
具体的，保护材料43可以包括SiO2、SiOC等材料。
在图7的基础上，保护材料43可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成于介质层12以及第一扩散阻挡材料40上，且保护材料43填满开口41，如图8所示。
采用干法蚀刻保护材料43，且蚀刻方向为开口41所在方向，从而将开口41所在方向的保护材料43完全除去，即露出完整的开口41，此时，形成具有第二通孔131的保护层13，第二通孔131与开口41的孔径相等，即第二通孔131与开口41的横截面积相等，如图9所示。其中，位于介质层12以及第一扩散阻挡材料40上的保护材料43的厚度为50nm～500nm，即保护层13的厚度为50nm～500nm。
具体的，介质层12在第二方向上的厚度与保护层13在第二方向上的厚度的比例可以为5％～30％，比如8％，10％，15％，20％等。相应的，在最终形成的半导体结构中，凹槽15在第二方向上的高度与栓塞接触孔在第二方向上的高度的比例可以为5％～30％。
在一个实施例中，在形成保护层13后，半导体结构的制造方法还包括：使第二扩散阻挡材料44覆盖开口41的孔壁、第二通孔131的孔壁以及保护层13，第一扩散阻挡材料40和第二扩散阻挡材料44形成扩散阻挡层20。
具体的，第二扩散阻挡材料44可以包括Ta、Ti、Ru、TaN、TiN、RuTa、RuTaN、W或Ir等。第二扩散阻挡材料44可以是防止导电材料扩散通过的任何其它材料。其中，第一扩散阻挡材料40和第二扩散阻挡材料44可以选择相同的材料，当然也不排除选择不同的材料。
在图9的基础上，第二扩散阻挡材料44可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺形成于开口41的孔壁、第二通孔131的孔壁以及保护层13的上表面，如图10所示。其中，第二扩散阻挡材料44覆盖保护层13的厚度为10nm～50nm，此时位于凹槽15内的第一扩散阻挡材料40和第二扩散阻挡材料44组成了扩散阻挡层20，即扩散阻挡层20由两个步骤制备而成。
最后将Cu、Al、W或其合金可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺填充于第二扩散阻挡材料44内，以及覆盖第二扩散阻挡材料44的上表面以形成导电栓塞30，从而完成图1所示的半导体结构的制造。其中，导电栓塞30覆盖第二扩散阻挡材料44的上表面的厚度为100nm～800nm。
在一个实施例中，半导体结构的制造方法用于制造上述的半导体结构。
本公开的半导体结构的制造方法，先后采用第一扩散阻挡材料40和第二扩散阻挡材料44填充半导体基体10，并使得第一扩散阻挡材料40内嵌于半导体基体10内，以此平衡导电栓塞30形成的金属应力以应对高密度的电流冲刷，从而提升半导体结构的稳定性。
本公开的一个实施例还提供了一种半导体结构的制造方法，请参考图11，包括：
S201，形成具有栓塞接触孔14的半导体基体10，在栓塞接触孔14底部的侧壁上设置有凹槽15；
S203，在半导体基体10上形成扩散阻挡层20，扩散阻挡层20设置在栓塞接触孔14的孔壁上，且填充凹槽15；
S205，在扩散阻挡层20内填充形成导电栓塞30。
本公开一个实施例的半导体结构的制造方法通过在半导体基体10的凹槽15内填充扩散阻挡层20，即形成了内嵌式扩散阻挡层20，从而可以增加扩散阻挡层20与半导体基体10的接触面积，以此改善漏电流，提升半导体结构的稳定性。
需要说明的是，本实施例中的扩散阻挡层20一次性填充入凹槽15以及栓塞接触孔14内。
在一个实施例中，形成半导体基体10，包括：提供衬底11；在衬底11上形成具有第一通孔121的介质层12；在介质层12上形成具有第二通孔131的保护层13，第一通孔121和第二通孔131相连通，第二通孔131朝向衬底11的垂直投影位于第一通孔121朝向衬底11的垂直投影内；其中，衬底11与保护层13之间形成凹槽15。
具体的，凹槽15以及栓塞接触孔14是通过两个过程获得，即依次形成了第一通孔121和第二通孔131，并在形成第一通孔121和第二通孔131后，一次性填充扩散阻挡层20。
在一个实施例中，采用侧蚀刻或者调整蚀刻选择比的方式，在半导体基体10内蚀刻出凹槽15以及栓塞接触孔14，然后在凹槽15和栓塞接触孔14内形成扩散阻挡层20。
具体的，在衬底11上依次形成介质层12和保护层13，然后蚀刻保护层13和介质层12，通过侧蚀刻或者调整蚀刻选择比的方式，在介质层12内蚀刻出更宽的通孔，从而在介质层12和保护层13内形成了凹槽15和栓塞接触孔14。
在一个实施例中，半导体结构的制造方法用于制造上述的半导体结构。
本公开的半导体结构的制造方法，扩散阻挡层20一次性填充半导体基体10，并使得扩散阻挡层20内嵌于半导体基体10内，以此平衡导电栓塞30形成的金属应力以应对高密度的电流冲刷，从而提升半导体结构的稳定性。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由前面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (14)

  1. 一种半导体结构，其特征在于，包括：
    半导体基体(10)，所述半导体基体(10)上设置有栓塞接触孔(14)，所述栓塞接触孔(14)底部的侧壁上设置有凹槽(15)；
    扩散阻挡层(20)，所述扩散阻挡层(20)设置在所述栓塞接触孔(14)的孔壁上，且填充所述凹槽(15)；
    导电栓塞(30)，所述导电栓塞(30)设置在所述扩散阻挡层(20)内。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述半导体基体(10)包括：
    衬底(11)；
    介质层(12)，所述介质层(12)设置在所述衬底(11)上，所述介质层(12)具有第一通孔(121)；
    保护层(13)，所述保护层(13)设置在所述介质层(12)上方，所述保护层(13)具有第二通孔(131)，所述第一通孔(121)和所述第二通孔(131)相连通，所述第二通孔(131)朝向所述衬底(11)的垂直投影位于所述第一通孔(121)朝向所述衬底(11)的垂直投影内；
    其中，所述衬底(11)与所述保护层(13)之间形成所述凹槽(15)。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述凹槽(15)在第一方向上的深度为5nm～20nm，所述第一方向垂直所述第一通孔(121)的延伸方向。
  4. 根据权利要求3所述的半导体结构，其特征在于，所述介质层(12)在第二方向上的厚度为20nm～200nm，所述保护层(13)在所述第二方向上的厚度为50nm～500nm，所述第二方向垂直所述衬底(11)。
  5. 根据权利要求2所述的半导体结构，其特征在于，所述半导体基体(10)与所述导电栓塞(30)之间均设置所述扩散阻挡层(20)。
  6. 根据权利要求5所述的半导体结构，其特征在于，所述扩散阻挡层(20)包括第一主体部(21)和第一凸起部(22)，所述第一凸起部(22)设置在所述栓塞接触孔(14)的孔壁上，且填充所述凹槽(15)，所述第一主体部(21)设置在所述半导体基体(10)上，且位于所述栓塞接触孔(14)的外侧；
    所述导电栓塞(30)包括第二主体部(31)和第二凸起部(32)，所述第二凸起部(32)设置在所述第一主体部(21)和所述第一凸起部(22)内，所述第二主体部(31)设置在 所述第一主体部(21)上。
  7. 根据权利要求6所述的半导体结构，其特征在于，所述第一主体部(21)在第二方向上的厚度为10nm～50nm，所述第二主体部(31)在所述第二方向上的厚度为100nm～800nm，所述第二方向垂直所述衬底(11)。
  8. 根据权利要求2所述的半导体结构，其特征在于，所述扩散阻挡层(20)包括第一扩散阻挡材料(40)和第二扩散阻挡材料(44)，所述第一扩散阻挡材料(40)填充于所述凹槽(15)内，所述第二扩散阻挡材料(44)覆盖所述第一扩散阻挡材料(40)的内壁和所述保护层(13)的内壁。
  9. 一种半导体结构的制造方法，其特征在于，包括：
    形成具有栓塞接触孔(14)的半导体基体(10)，在所述栓塞接触孔(14)底部的侧壁上设置有填充了第一扩散阻挡材料(40)的凹槽(15)；
    在所述半导体基体(10)上形成第二扩散阻挡材料(44)，所述第二扩散阻挡材料(44)覆盖所述第一扩散阻挡材料(40)的内壁和覆盖所述栓塞接触孔(14)的孔壁，所述第一扩散阻挡材料(40)和所述第二扩散阻挡材料(44)形成扩散阻挡层(20)；
    在所述扩散阻挡层(20)内填充形成导电栓塞(30)。
  10. 根据权利要求9所述的半导体结构的制造方法，其特征在于，形成具有栓塞接触孔(14)的半导体基体(10)，包括：
    提供衬底(11)；
    在所述衬底(11)上形成具有第一通孔(121)的介质层(12)；
    使所述第一扩散阻挡材料(40)填满所述第一通孔(121)，并覆盖所述介质层(12)；
    去除所述介质层(12)上的第一扩散阻挡材料(40)，以露出所述介质层(12)，且保留的第一扩散阻挡材料(40)的上表面与所述介质层(12)的上表面齐平；
    部分蚀刻所述第一通孔(121)内的所述第一扩散阻挡材料(40)，以在所述第一扩散阻挡材料(40)内形成开口(41)，并露出所述衬底(11)；
    在所述介质层(12)上形成具有第二通孔(131)的保护层(13)，所述第二通孔(131)与所述开口(41)相连通，且所述第二通孔(131)的孔口与所述开口(41)的孔口相重合。
  11. 根据权利要求10所述的半导体结构的制造方法，其特征在于，形成所述保护层(13)，包括：
    使保护材料(43)填满所述开口(41)，并覆盖所述介质层(12)和所述第一扩散阻 挡材料(40)；
    蚀刻所述保护材料(43)，以在所述保护材料(43)上形成具有所述第二通孔(131)的所述保护层(13)，并蚀刻出所述开口(41)。
  12. 根据权利要求10所述的半导体结构的制造方法，其特征在于，在形成所述保护层(13)后，所述半导体结构的制造方法还包括：
    使所述第二扩散阻挡材料(44)覆盖所述开口(41)的孔壁、所述第二通孔(131)的孔壁以及所述保护层(13)。
  13. 一种半导体结构的制造方法，其特征在于，包括：
    形成具有栓塞接触孔(14)的半导体基体(10)，在所述栓塞接触孔(14)底部的侧壁上设置有凹槽(15)；
    在所述半导体基体(10)上形成扩散阻挡层(20)，所述扩散阻挡层(20)设置在所述栓塞接触孔(14)的孔壁上，且填充所述凹槽(15)；
    在所述扩散阻挡层(20)内填充形成导电栓塞(30)。
  14. 根据权利要求13所述的半导体结构的制造方法，其特征在于，形成所述半导体基体(10)，包括：
    提供衬底(11)；
    在所述衬底(11)上形成具有第一通孔(121)的介质层(12)；
    在所述介质层(12)上形成具有第二通孔(131)的保护层(13)，所述第一通孔(121)和所述第二通孔(131)相连通，所述第二通孔(131)朝向所述衬底(11)的垂直投影位于所述第一通孔(121)朝向所述衬底(11)的垂直投影内；
    其中，所述衬底(11)与所述保护层(13)之间形成所述凹槽(15)。
PCT/CN2021/094441 2020-08-13 2021-05-18 半导体结构及半导体结构的制造方法 Ceased WO2022033100A1 (zh)

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