WO2022029534A1 - 半導体装置の駆動方法 - Google Patents

半導体装置の駆動方法 Download PDF

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Publication number
WO2022029534A1
WO2022029534A1 PCT/IB2021/056525 IB2021056525W WO2022029534A1 WO 2022029534 A1 WO2022029534 A1 WO 2022029534A1 IB 2021056525 W IB2021056525 W IB 2021056525W WO 2022029534 A1 WO2022029534 A1 WO 2022029534A1
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Prior art keywords
transistor
wiring
circuit
insulator
potential
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Ceased
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PCT/IB2021/056525
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
木村肇
國武寛司
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202180047447.2A priority Critical patent/CN115867968A/zh
Priority to US18/006,323 priority patent/US12266392B2/en
Priority to DE112021004116.9T priority patent/DE112021004116T5/de
Priority to KR1020237006224A priority patent/KR20230043924A/ko
Priority to JP2022541319A priority patent/JP7702411B2/ja
Publication of WO2022029534A1 publication Critical patent/WO2022029534A1/ja
Anticipated expiration legal-status Critical
Priority to US19/019,968 priority patent/US20250157519A1/en
Priority to JP2025105432A priority patent/JP2025139598A/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access

Definitions

  • One aspect of the present invention relates to a method for driving a semiconductor device and the like.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical fields of one aspect of the present invention disclosed in the present specification and the like include semiconductor devices, image pickup devices, display devices, light emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, and input / output devices.
  • Devices, their driving methods, or their manufacturing methods can be mentioned as an example.
  • IGZO In-Ga-Zn oxides
  • Exo In-Ga-Zn oxides
  • CAAC c-axis aligned crystalline
  • nc nanocrystalline structure
  • Oxide semiconductor transistors having metal oxide semiconductors in the channel formation region
  • OS transistors have been reported to have a minimum off-current (for example, non-patented).
  • Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • 2T 2-transistor type
  • 3T 3-transistor type
  • the OS transistor has an extremely small leakage current, that is, a current flowing between the source and the drain in the off state.
  • the NOSRAM can be used as a non-volatile memory by holding a charge corresponding to the data in the cell using the characteristic that the leakage current is extremely small.
  • the electric charge corresponding to the data is held in the capacity of the cell. Therefore, if the amount of charge that can be held in the capacitance is small, the accuracy of reading data is significantly reduced due to the leakage of charge from the capacitance. Therefore, it may not be possible to retain data in the cell for a long period of time.
  • One aspect of the present invention is to provide a semiconductor device capable of holding data for a long period of time and a method for driving the same.
  • one aspect of the present invention is to provide a semiconductor device having low power consumption and a method for driving the same.
  • one aspect of the present invention is to provide a semiconductor device capable of applying a high voltage and a method for driving the same.
  • one aspect of the present invention is to provide a highly reliable semiconductor device and a driving method thereof.
  • one aspect of the present invention is to provide a novel semiconductor device and a method for driving the same.
  • one aspect of the present invention does not necessarily have to solve all of the above problems, but may solve at least one problem. Moreover, the description of the above-mentioned problem does not prevent the existence of other problems. Issues other than these are self-evident from the description of the description, claims, drawings, etc., and the issues other than these should be extracted from the description of the specification, claims, drawings, etc. Is possible.
  • One aspect of the present invention comprises a cell in which a capacitance, a first transistor, and a second transistor are provided, and the capacitance includes a first electrode, a second electrode, and a strong dielectric layer.
  • the strong dielectric layer is provided between the first electrode and the second electrode, and the strong dielectric layer has a first saturated polarization voltage or a first saturated polarization voltage.
  • the potential of the first electrode in the first period and the potential of the first electrode in the second period are different from the potential of the second electrode in the first period and the second. It may be different from the potential of the second electrode in the period of.
  • the first transistor may be turned on in the first period and the second period, and the first transistor may be turned off in the third period.
  • the cell has a third transistor, one of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor, and the first to first.
  • the third transistor may be turned off, and in the fourth period, the third transistor may be turned on.
  • the potential of the second electrode does not have to fluctuate during the second to fourth periods.
  • a constant potential may be supplied to the other of the source or drain of the second transistor in the first to fourth periods.
  • the polarity of the polarization amount of the ferroelectric layer in the first period and the polarity of the polarization amount of the ferroelectric layer in the second period may be the same.
  • the data voltage may represent analog data.
  • the first transistor may have a metal oxide in the channel forming region.
  • a semiconductor device capable of holding data for a long period of time and a method for driving the same.
  • a semiconductor device having low power consumption and a driving method thereof can be provided.
  • a highly reliable semiconductor device and a driving method thereof can be provided.
  • a novel semiconductor device and a driving method thereof can be provided.
  • FIG. 1A is a circuit diagram showing a configuration example of a cell.
  • 1B1 to 1B4 are diagrams showing a configuration example of a capacitance.
  • FIG. 2 is a diagram showing the hysteresis characteristics of the ferroelectric substance.
  • FIG. 3 is a timing chart showing an example of a cell driving method.
  • 4A and 4B are circuit diagrams showing an example of a cell driving method.
  • 5A and 5B are circuit diagrams showing an example of a cell driving method.
  • FIG. 6 is a timing chart showing an example of a cell driving method.
  • 7A and 7B are circuit diagrams showing an example of a cell driving method.
  • 8A and 8B are circuit diagrams showing an example of a cell driving method.
  • FIG. 1A is a circuit diagram showing a configuration example of a cell.
  • 1B1 to 1B4 are diagrams showing a configuration example of a capacitance.
  • FIG. 2 is a diagram showing the hystere
  • FIG. 9 is a timing chart showing an example of a cell driving method.
  • 10A and 10B are circuit diagrams showing a configuration example of a cell.
  • 11A and 11B are circuit diagrams showing a configuration example of a cell.
  • 12A and 12B are circuit diagrams showing a configuration example of a cell.
  • FIG. 13 is a block diagram showing a configuration example of a semiconductor device.
  • 14A and 14B are diagrams illustrating a hierarchical neural network.
  • FIG. 15A is a block diagram showing a configuration example of a semiconductor device.
  • FIG. 15B is a circuit diagram showing a configuration example of a circuit included in the semiconductor device.
  • 16A to 16C are timing charts illustrating an operation example of the semiconductor device.
  • 17A to 17C are timing charts illustrating an operation example of the semiconductor device.
  • FIG. 18A to 18C are timing charts illustrating an operation example of the semiconductor device.
  • FIG. 19 is a diagram showing a structural example of a semiconductor device.
  • 20A to 20C are diagrams showing a configuration example of a transistor.
  • FIG. 21A is a diagram illustrating the classification of the crystal structure of IGZO.
  • FIG. 21B is a diagram illustrating an XRD spectrum of crystalline IGZO.
  • FIG. 21C is a diagram illustrating a microelectron diffraction pattern of crystalline IGZO.
  • FIG. 22A is a perspective view showing an example of a semiconductor wafer.
  • FIG. 22B is a perspective view showing an example of the chip.
  • 22C and 22D are perspective views showing an example of an electronic component.
  • FIG. 23A to 23J are diagrams illustrating an example of an electronic device.
  • 24A to 24E are diagrams illustrating an example of an electronic device.
  • 25A to 25C are diagrams illustrating an example of an electronic device.
  • FIG. 26 is a circuit diagram illustrating an outline of the off-current measurement TEG of the embodiment.
  • FIG. 27A is a cross-sectional view illustrating the configuration of the capacitance of the embodiment.
  • FIG. 27B is a circuit diagram illustrating an outline of the capacitance leakage current measurement TEG of the embodiment.
  • FIG. 28 is a graph showing the temperature dependence of the leakage current of the embodiment.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like is regarded as another embodiment or the component referred to in “second” in the scope of claims. It is possible. Further, for example, the component referred to in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the scope of claims.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. can. Further, in the case of describing as an OS FET or an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, the metal oxide having nitrogen may be referred to as metal oxynitride.
  • the cell has a function of holding data. Specifically, the cell has a capacity, and by holding a charge in the capacity, the data written in the cell can be held. Therefore, the cell can be called a memory cell, and the semiconductor device can be called a storage device.
  • the capacitance is configured to include a first electrode, a second electrode, and a ferroelectric layer.
  • the ferroelectric layer is provided between the first electrode and the second electrode.
  • a ferroelectric substance means a substance that maintains a polarized state even when the application of a voltage is stopped after the polarization is applied by applying a voltage.
  • the normal dielectric means a substance that disappears because the state of polarization is not maintained when the application of the voltage is stopped after the polarization is applied by applying the voltage.
  • FIG. 1A is a circuit diagram showing a configuration example of a cell 10 included in the semiconductor device of one aspect of the present invention.
  • the cell 10 has a capacitance 11, a transistor 21, a transistor 22, and a transistor 23.
  • the capacitance 11 has a ferroelectric layer 12, an electrode 13a, and an electrode 13b, and the ferroelectric layer 12 is provided between the electrodes 13a and 13b.
  • the electrode 13a is electrically connected to either the source or the drain of the transistor 21.
  • One of the source or drain of the transistor 21 is electrically connected to the gate of the transistor 22.
  • One of the source or drain of the transistor 22 is electrically connected to one of the source or drain of the transistor 23.
  • the node to which the electrode 13a, one of the source or drain of the transistor 21, and the gate of the transistor 22 are electrically connected is referred to as a node ND1.
  • the gate of the transistor 21 is electrically connected to the wiring 31.
  • the electrode 13b is electrically connected to the wiring 32.
  • the gate of the transistor 23 is electrically connected to the wiring 33.
  • the other of the source or drain of the transistor 21 is electrically connected to the wiring 41.
  • the other of the source or drain of the transistor 22 is electrically connected to the wiring 42.
  • the other of the source or drain of the transistor 23 is electrically connected to the wiring 43.
  • a constant potential can be supplied to the wiring 42.
  • a back gate may be provided.
  • a back gate may be provided in a part of the transistor 21 to the transistor 23, or a back gate may be provided in all of them.
  • the potential of the wiring 31 can be the potential of the gate of the transistor 21.
  • the potential of the wiring 32 can be the potential of the electrode 13b.
  • the potential of the wiring 33 can be the potential of the gate of the transistor 23.
  • the transistor 21 is an n-channel type transistor, if the wiring 31 has a high potential, the transistor 21 can be turned on, and if the wiring 31 has a low potential, the transistor 21 can be turned off. .. The same applies to the relationship between the transistor 23 and the wiring 33.
  • the wiring 41 can be called a writing line.
  • the charge of the node ND1 is retained by turning off the transistor 21. Therefore, the data can be held in the cell 10.
  • the potential of the gate of the transistor 22 is the potential of the node ND1. Therefore, when the transistor 23 is turned on while the data is held in the cell 10, a current having a magnitude corresponding to the data flows to the wiring 43 via the transistor 22 and the transistor 23. As a result, the data held in the cell 10 can be read out. Therefore, the wiring 43 can be said to be a read line.
  • the capacitance 11 is provided with the ferroelectric layer 12 between the electrodes 13a and 13b.
  • the ferroelectric layer 12 and the dielectric layer are compared with the case where the ferroelectric layer 12 is not provided between the electrodes 13a and 13b and the dielectric layer is provided.
  • the capacitance value of the capacitance 11 becomes large.
  • the amount of charge that can be stored in the capacity 11 increases. Therefore, the fluctuation of the potential of the node ND1 due to the leakage of the electric charge from the capacitance 11 becomes small. Therefore, the data can be retained in the cell 10 for a long period of time.
  • the frequency of refreshing (rewriting data to the cell 10) can be reduced, so that the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.
  • the data held by the cell 10 can be analog data because the fluctuation of the potential of the node ND1 due to the leakage of the electric charge from the capacity 11 becomes small. Further, the data held by the cell 10 can be multi-valued digital data, specifically digital data having three or more values. Of course, cell 10 can also hold binary digital data.
  • ferroelectric layer 12 for example, barium titanate, lead zirconate titanate, strontium bismuthate tantalate, or the like can be used.
  • the transistor 21 is preferably an OS transistor.
  • the OS transistor has a characteristic that the off-current is extremely small. Therefore, by using the OS transistor as the transistor 21, it is possible to prevent the electric charge accumulated in the node ND1 from leaking through the transistor 21. As a result, the electric charge can be retained in the node ND1 for a long period of time, so that the data in the cell 10 can be retained for a long period of time. As a result, the frequency of refreshing can be reduced, so that the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.
  • the transistor 22 and the transistor 23 can be a transistor (hereinafter referred to as a Si transistor) containing silicon in the channel forming region.
  • a Si transistor a transistor containing silicon in the channel forming region.
  • the silicon for example, amorphous silicon (sometimes referred to as hydrided amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon and the like can be used.
  • the on-current of the transistor 22 and the transistor 23 can be increased.
  • the data held in the cell 10 can be read out by the current having a magnitude corresponding to the potential of the node ND1 flowing through the wiring 43 via the transistor 22 and the transistor 23. From the above, by using a Si transistor as the transistor 22 and the transistor 23, data can be read out at high speed.
  • a Si transistor can be used as the transistor 21.
  • an OS transistor can be used as the transistor 22 and the transistor 23.
  • the OS transistor has a characteristic of having a high withstand voltage. Therefore, by using the transistor 21 to the transistor 23 as an OS transistor, a high voltage can be supplied to the node ND1. As a result, the difference between the minimum value and the maximum value of the potential of the signal that can be supplied to the wiring 41 can be increased.
  • FIGS. 1B1 to 1B4 are diagrams showing a configuration example of the capacity 11.
  • the layer provided between the electrodes 13a and 13b is different from the capacity 11 shown in FIG. 1A.
  • FIG. 1B1 shows a configuration in which the ferroelectric layer 12 has a region in contact with the electrode 13a and the dielectric layer 14 has a region in contact with the electrode 13b.
  • FIG. 1B2 shows a configuration in which the dielectric layer 14 has a region in contact with the electrode 13a and the ferroelectric layer 12 has a region in contact with the electrode 13b.
  • the capacitance 11 shown in FIG. 1B3 is provided with a ferroelectric layer 12a, a ferroelectric layer 12b, and a dielectric layer 14.
  • the ferroelectric layer 12a has a region in contact with the electrode 13a
  • the ferroelectric layer 12b has a region in contact with the electrode 13b.
  • the dielectric layer 14 is provided between the ferroelectric layer 12a and the ferroelectric layer 12b.
  • the same material as the ferroelectric layer 12 can be used for the ferroelectric layer 12a and the ferroelectric layer 12b.
  • the capacitive layer 11 shown in FIG. 1B4 is provided with a ferroelectric layer 12, an ordinary dielectric layer 14a, and an ordinary dielectric layer 14b.
  • the dielectric layer 14a has a region in contact with the electrode 13a
  • the dielectric layer 14b has a region in contact with the electrode 13b.
  • the ferroelectric layer 12 is provided between the normal dielectric layer 14a and the normal dielectric layer 14b.
  • high dielectric constant (high-k) materials such as aluminum oxide, hafnium oxide, tantalum pentoxide, and zirconium oxide can be used. .. As a result, the capacity value of the capacity 11 can be increased.
  • FIG. 2 is a graph showing the hysteresis characteristics of the ferroelectric layer 12.
  • the horizontal axis shows the voltage applied to the ferroelectric layer 12, specifically, the value obtained by subtracting the potential of the electrode 13b from the potential of the electrode 13a.
  • the vertical axis indicates the amount of polarization of the ferroelectric layer 12, and when it is a positive value, it indicates that the positive charge is biased toward the electrode 13b and the negative charge is biased toward the electrode 13a.
  • the amount of polarization when the amount of polarization is a negative value, it indicates that the positive charge is biased toward the electrode 13a and the negative charge is biased toward the electrode 13b.
  • the voltage shown on the horizontal axis of the graph of FIG. 2 may be a value obtained by subtracting the potential of the electrode 13a from the potential of the electrode 13b.
  • the amount of polarization shown on the vertical axis of the graph of FIG. 2 is set to a positive value when the positive charge is biased toward the electrode 13a and the negative charge is biased toward the electrode 13b, and the positive charge is biased toward the electrode 13b.
  • the negative charge when the negative charge is biased toward the electrode 13a, it may be a negative value.
  • the hysteresis characteristic of the ferroelectric layer 12 can be represented by the curve 51 and the curve 52.
  • the voltage at the intersection of the curve 51 and the curve 52 is defined as the voltage VSP1 and the voltage VSP2.
  • VSP1 and the voltage VSP2 the voltage at the intersection of the curve 51 and the curve 52.
  • the voltage applied to the ferroelectric layer 12 is increased after the voltage VSP1 is applied to the ferroelectric layer 12, the amount of polarization of the ferroelectric layer 12 increases according to the curve 51.
  • the voltage VSP2 is applied to the ferroelectric layer 12 and then the voltage applied to the ferroelectric layer 12 is lowered, the amount of polarization of the ferroelectric layer 12 decreases according to the curve 52. Therefore, the voltage VSP1 and the voltage VSP2 can be said to be saturated polarization voltages.
  • the voltage applied to the ferroelectric layer 12 when the polarization amount of the ferroelectric layer 12 changes according to the curve 51 and the polarization amount of the ferroelectric layer 12 is 0 is defined as the voltage V1. .. Further, the voltage applied to the ferroelectric layer 12 when the polarization amount of the ferroelectric layer 12 changes according to the curve 52 and the polarization amount of the ferroelectric layer 12 is 0 is defined as the voltage V2. As shown in FIG. 2, the voltage V1 can be a positive value and the voltage V2 can be a negative value. The value of the voltage V1 and the value of the voltage V2 can be a value between the voltage VSP1 and the voltage VSP2.
  • FIG. 3 is a timing chart showing an example of the driving method of the cell 10.
  • "H” represents a high potential
  • "L” represents a low potential.
  • the wiring resistance, the potential change due to the resistance between the drain and the source of the transistor, the signal delay, and the like are not taken into consideration. The above applies to other timing charts as well.
  • the potential of the wiring 31 is set to a high potential
  • the potential of the wiring 32 is set to the potential PCH
  • the potential of the wiring 33 is set to a low potential.
  • the potential of the wiring 41 is defined as the potential PRESS. Since the transistor 21 is in the ON state, the potential of the node ND1 becomes the potential PRESS.
  • the voltage applied to the ferroelectric layer 12 specifically, the difference between the potential of the electrode 13a and the potential of the electrode 13b becomes the voltage “PRES-PCH”. Also in the following description, the voltage applied to the ferroelectric layer 12 indicates the difference between the potential of the electrode 13a and the potential of the electrode 13b.
  • FIG. 4A is a circuit diagram showing the state of the cell 10 in the period T1.
  • the transistors in the off state are marked with a cross. The same description may be made in other figures.
  • the voltage VSS1 is applied to the ferroelectric layer 12 during the period T1.
  • the values of the potential PRES and the potential PCH are set so that the value of the voltage "PRES-PCH" becomes equal to the value of the voltage VSS1.
  • the potential PRESS is 0V and the potential PCH is 3.3V.
  • FIG. 4A the voltage applied to the ferroelectric layer 12 is shown by being surrounded by a alternate long and short dash line. Similar descriptions may be made in other drawings.
  • the polarization state of the ferroelectric layer 12 can be reset by applying a voltage VSP1 which is a saturated polarization voltage to the ferroelectric layer 12. Therefore, the potential PRES supplied to the node ND1 during the period T1 can be said to be a reset potential. Further, the operation performed during the period T1 can be said to be a reset operation.
  • the potential of the wiring 32 is defined as the potential PCL.
  • the data signal is supplied to the wiring 41.
  • the potential of the wiring 41 is defined as the potential PSIG. Since the transistor 21 is in the ON state, the potential of the node ND1 becomes the potential PSIG. As a result, the voltage applied to the ferroelectric layer 12 becomes the voltage "PSIG-PCL".
  • the potential PCL can be a potential lower than the potential PCH.
  • FIG. 4B is a circuit diagram showing the state of the cell 10 in the period T2.
  • the potential and the voltage changed from the period T1 are shown by being surrounded by a two-dot chain line. Similar descriptions may be made in other drawings.
  • the voltage applied to the ferroelectric layer 12 during the period T2 is defined as the voltage VSIG. Since the potential PSIG supplied to the node ND1 in the period T2 is the potential corresponding to the data signal, the voltage VSIG can be said to be the data voltage. Since the voltage VSS1 is applied to the ferroelectric layer 12 in the period T1, the amount of polarization of the ferroelectric layer 12 in the period T2 is as shown in the curve 51 shown in FIG.
  • the values of the potential PSIG and the potential PCL are set so that the value of the voltage VSIG is higher than the voltage VSP1 and lower than the voltage VSP2.
  • the capacity value of the capacity 11 corresponds to the slope of the curve 51, specifically, for example, the slope of the tangent line of the curve 51
  • the value of the voltage VSIG is such that the slope of the curve 51 has a certain magnitude or more. It is preferable to set so as to be. Thereby, the capacity value of the capacity 11 can be increased.
  • the ferroelectric layer 12 and the dielectric layer 12 are compared with the case where the ferroelectric layer 12 is not provided between the electrodes 13a and 13b and the dielectric layer is provided. Assuming that the dielectric constants of the body layers are equal, the capacitance value of the capacitance 11 becomes large.
  • the value of the voltage VSIG is preferably not more than the voltage at which the slope of the curve 51 is equal to or more than a certain value and not more than the voltage at the inflection point of the curve 51. Further, the value of the voltage VSIG is preferably set so that the polarity of the polarization amount of the ferroelectric layer 12 in the period T1 and the polarity of the polarization amount of the ferroelectric layer 12 in the period T2 are the same. .. That is, when the polarity of the ferroelectric layer 12 in the period T1 is negative, specifically, when the positive charge is biased toward the electrode 13a and the negative charge is biased toward the electrode 13b, the ferroelectric layer in the period T2. It is preferable that the polarity of 12 is also negative. Therefore, the voltage VSIG is preferably set to the voltage V1 or less shown in FIG. In FIG. 4B and the like, the voltage VSIG is assumed to be the voltage V1 or less.
  • the value of the voltage VSIG is, for example, a voltage or more at which the slope of the curve 51 becomes a constant value or more and a voltage V1 or less.
  • the potential PSIG is preferably 0V or more and 1.2V or less. In this case, the voltage VSIG is 0 V or more and 1.2 V or less.
  • data can be written in the cell 10 in the period T2.
  • the potential of the wiring 31 is set to a low potential.
  • the transistor 21 is turned off, so that the electric charge accumulated in the node ND1 is retained. Therefore, the potential of the node ND1 is held in the potential PSIG.
  • FIG. 5A is a circuit diagram showing the state of the cell 10 in the period T3. As shown in FIG. 5A, during the period T3, the voltage applied to the ferroelectric layer 12 is held by the voltage VSIG.
  • the capacity value of the capacity 11 can be increased as described above.
  • the amount of charge that can be stored in the capacity 11 can be increased. Therefore, in the period T3, the fluctuation of the potential of the node ND1 due to the leakage of the electric charge from the capacitance 11 can be reduced. Therefore, the data can be retained in the cell 10 for a long period of time. As a result, the frequency of refreshing can be reduced, so that the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.
  • the data held by the cell 10 can be analog data.
  • the data held by the cell 10 can be multi-valued digital data, specifically digital data having three or more values. Of course, cell 10 can also hold binary digital data.
  • the potential of the wiring 33 is set to a high potential.
  • the transistor 23 is turned on, so that a current having a magnitude corresponding to the potential PSIG of the node ND1 flows to the wiring 43 via the transistor 22 and the transistor 23.
  • the data held in the cell 10 can be read out.
  • FIG. 5B is a circuit diagram showing the state of the cell 10 in the period T4.
  • the transistor 23 is turned on, and the data held in the cell 10 is read out from the wiring 43.
  • the potential of the wiring 33 is set to a low potential.
  • the transistor 23 is turned off, and the reading of the data held in the cell 10 is completed. Since the potential of the node ND1 does not change due to the reading of data, the reading is a non-destructive reading.
  • FIG. 6 is a timing chart showing an example of a method of driving the cell 10 when the voltage VSS2 is applied to the ferroelectric layer 12 in the period T1.
  • 7A, 7B, 8A, and 8B are circuit diagrams showing the states of the cells 10 in the periods T1 to T4 shown in FIG. 6, respectively.
  • the potential of the wiring 32 can be the potential PCL in the period T1 and the potential PCH in the period T2 to T5. Further, in the driving method shown in FIG. 3, for example, the potential PRES is lower than the potential PSIG, but in the driving method shown in FIG. 6, the potential PRES can be higher than the potential PSIG.
  • the values of the potential PRES and the potential PCL are set so that the value of the voltage “PRES-PCL” becomes equal to the value of the voltage VSS2.
  • the voltage VSP2 is 3.3V
  • the potential PRES is 3.3V
  • the potential PCL is 0V.
  • the voltage applied to the ferroelectric layer 12 during the period T2 becomes the voltage “PSIG-PCH”. Since the voltage VSP2 is applied to the ferroelectric layer 12 in the period T1, the amount of polarization of the ferroelectric layer 12 in the period T2 is as shown in the curve 52 shown in FIG.
  • the value of the voltage VSIG is, for example, the voltage V2 or more shown in FIG. 2 and the slope of the curve 52, specifically, for example, the slope of the tangent line of the curve 52 is a constant value or more. It is preferable that the voltage is equal to or lower than the above voltage.
  • the potential PSIG is preferably 2.1V or more and 3.3V or less. In this case, the voltage VSIG is ⁇ 1.2V or higher and 0V or lower.
  • the voltage VSIG is assumed to be a voltage V2 or higher.
  • FIG. 9 is a timing chart showing an example of a method of driving the cell 10 in the case where the potential PCL is supplied as a constant potential to the wiring 32 in the period T1 to the period T5.
  • the potential of the node ND1 in the period T1 is defined as the potential PRESSa.
  • the potential PRESS can be lower than the potential PRESS shown in FIG. 3 and the like.
  • the potential PRESS can be -3.3V.
  • the potential PRESS can be 0V. Therefore, assuming that the voltages VSS1 are equal, the potential PRESS can be lower than the potential PRESS.
  • the OS transistor 21 When the cell 10 is driven by the method shown in FIG. 9, it is preferable to use an OS transistor as the transistor 21.
  • the OS transistor has a characteristic of having a high withstand voltage. Therefore, if an OS transistor is used as the transistor 21, the potential PRESS can be lowered. Similarly, it is preferable to use an OS transistor for the transistor 22. Further, an OS transistor may be used for the transistor 23 as well.
  • FIG. 10A is a circuit diagram showing a configuration example of the cell 10 when the transistor 22 and the transistor 23 are p-channel transistors.
  • the transistor 21 can be, for example, an OS transistor or a Si transistor.
  • the transistor 22 and the transistor 23 can be Si transistors.
  • FIG. 10B is a circuit diagram showing a configuration example of the cell 10 when all the transistors 21 to 23 are p-channel type transistors.
  • the transistor 21 to the transistor 23 can be, for example, a Si transistor.
  • the driving method shown in FIGS. 3 to 9 can be applied even if the cell 10 has the configuration shown in FIG. 10A or FIG. 10B by appropriately exchanging the magnitude relation of the potentials.
  • FIG. 11A is a circuit diagram showing a configuration example of the cell 10 in which the transistor 23 is omitted.
  • one of the source and the drain of the transistor 22 is electrically connected to the wiring 43.
  • the data held in the cell 10 can be read out from the wiring 43 without performing the operation in the period T4 shown in FIG. 3 or the like.
  • the wiring having a function as a write line is a wiring 41
  • the wiring having a function as a read line is a wiring 43.
  • the write line and the read line may be shared.
  • the cell 10 shown in FIG. 11B is different from the cell 10 shown in FIG. 11A in that the wiring having a function as a write line and the wiring having a function as a read line are shared as the wiring 44.
  • the other of the source or drain of the transistor 21 and one of the source or drain of the transistor 22 are electrically connected to the wiring 44.
  • the number of wires provided in the semiconductor device having the cell 10 can be reduced.
  • the semiconductor device can be miniaturized.
  • FIG. 12A is a modification of the cell 10 shown in FIG. 1A, and the point that the wiring having a function as a write line and the wiring having a function as a read line are shared as the wiring 44 is shown in FIG. 1A. It is different from the cell 10 shown.
  • the other of the source or drain of the transistor 21 and the other of the source or drain of the transistor 23 are electrically connected to the wiring 44.
  • FIG. 12B is a modification of the cell 10 shown in FIG. 12A, in which the other of the source or drain of the transistor 21 is electrically connected to one of the source or drain of the transistor 22 and one of the source or drain of the transistor 23. This point is different from the cell 10 shown in FIG. 12A.
  • FIG. 13 is a block diagram showing a configuration example of the semiconductor device 60 having the cell 10.
  • a cell array 61 is composed of cells 10 having m rows and n columns (m and n are integers of 2 or more).
  • the semiconductor device 60 includes a circuit 62 and a circuit 63.
  • [1,1], [i, 1], [m, 1], [1, j], [i, j], [m, j], [1, n], [i, n] and [m, n] are the addresses of cell 10.
  • the cell 10 described as [i, j] is the cell 10 in the i-row and j-th column.
  • the cell 10 having the address [i, j] is described as the cell 10 [i, j].
  • the cell 10 is electrically connected to the circuit 62 via the wiring 31, the wiring 32, and the wiring 33, and is electrically connected to the circuit 63 via the wiring 41 and the wiring 43.
  • the cell 10 [i, j] is electrically connected to the circuit 62 via the wiring 31 (i), the wiring 32 (i), and the wiring 33 (i), and the wiring 41 (j) and the wiring 43 ( It is electrically connected to the circuit 63 via j).
  • the circuit 62 has a function of generating an electric potential necessary for driving the cell 10 and supplying the electric potential to the wiring 31, the wiring 32, or the wiring 33.
  • the circuit 62 can sequentially write data to cell 10 and read data held in cell 10 from cell 10 in the first row to cell 10 in the mth row. As shown in FIG. 9, when the constant potential is supplied to the wiring 32, the wiring 32 does not have to be electrically connected to the circuit 62.
  • the reset operation which is an operation performed during the period T1
  • the reset operation can be performed for all cells 10 at the same time, for example.
  • the potential PRESSa which is the potential of the wiring 41 in the period T1
  • the potential PRESSa has a negative value. Therefore, when the transistor 21 is turned off, the difference between the potential of the gate of the transistor 21 and the potential PRESS of the source is equal to or larger than the threshold voltage of the transistor 21 unless the potential of the gate of the transistor 21 is lowered. It may not be possible to turn it off.
  • the transistor when the potential PRESS is -3.3V, the transistor may not be turned off even if a potential of 0V is supplied as a low potential to the gate of the transistor 21.
  • the reset operation which is the operation performed in the period T1
  • the cell 10 in which the reset operation is not performed may perform the data read operation. If the transistor 21 included in the cell 10 performing the data reading operation is not in the off state, the potential of the node ND1 becomes the potential PRESSa, and the data reading may not be performed correctly. From the above, when the cell 10 is driven by the method shown in FIG. 9, it is preferable that the reset operation, which is the operation performed during the period T1, is performed for all the cells 10 at the same time, for example.
  • the circuit 63 has a function of writing data to the cell 10 and a function of reading data from the cell 10.
  • the circuit 63 has a function of generating a potential PRES, a potential PSIG, and the like and supplying them to the cell 10 via the wiring 41. Further, the circuit 63 has a function of reading data from the cell 10 based on the potential of the wiring 43.
  • the circuit 63 is electrically connected to the cell 10 via the wiring 44.
  • the cell 10 [i, j] can be electrically connected to the circuit 63 via the wiring 44 (j).
  • the potential supplied to the wiring 31, the potential supplied to the wiring 32, and the potential supplied to the wiring 33 are all generated by the circuit 62, but the respective potentials are different.
  • the circuit may be generated.
  • the circuit that generates the potential supplied to the wiring 32 may be different from the circuit that generates the potential supplied to the wiring 31 and the potential supplied to the wiring 33.
  • the circuit 63 has both a function of writing data to the cell 10 and a function of reading data from the cell 10, but a circuit having a function of writing data to the cell 10 and data from the cell 10 are read from the cell 10. It may be different from the circuit having a read function.
  • a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers.
  • the hierarchical neural network 100 shown in FIG. 14A shows an example thereof, and the neural network 100 has a first layer to an R layer (R here can be an integer of 4 or more). ing.
  • R can be an integer of 4 or more
  • the first layer corresponds to the input layer
  • the R layer corresponds to the output layer
  • the other layers correspond to the intermediate layer.
  • FIG. 14A illustrates the (k-1) th layer and the kth layer (here, k is an integer of 3 or more and R-1 or less) as the intermediate layer, and the other intermediate layers. Is not shown.
  • Each layer of the neural network 100 has one or more neurons.
  • the first layer has neurons N 1 (1) to neurons N p (1) (where p is an integer of 1 or more), and the layer (k-1) has neurons N 1 .
  • the kth layer is neuron N 1 (k) to neuron N n (k) (
  • n is an integer of 1 or more
  • the layer R has neurons N 1 (R) to neurons N q (R) (where q is an integer of 1 or more).
  • FIG. 14B shows the neuron N j (k) in the k-th layer, the signal input to the neuron N j ( k) , and the signal output from the neuron N j (k).
  • the degree of signal transmission is determined by the strength of synaptic connections (hereinafter referred to as weighting factors) that connect these neurons.
  • weighting factors the strength of synaptic connections that connect these neurons.
  • the signal output from the neurons in the previous layer is multiplied by the corresponding weighting factor and input to the neurons in the next layer.
  • i be an integer of 1 or more and m or less, and set the weight coefficient of the synapse between the neuron N i (k-1) in the (k-1) layer and the neuron N j (k) in the kth layer as wi ( k ).
  • j (k) When j (k) is set, the signal input to the neuron Nj (k) in the kth layer can be expressed by the equation (1).
  • the neuron N j (k) produces an output signal z j (k ) in response to u j (k) .
  • the output signal z j ( k) from the neuron N j (k) is defined by the following equation.
  • the function f (u j (k) ) is an activation function in a hierarchical neural network, and a step function, a linear ramp function, a sigmoid function, or the like can be used.
  • the activation function may be the same or different in all neurons.
  • the activation function of neurons may be the same or different in each layer.
  • the signal output by the neurons in each layer, the weighting factor w, or the bias b may be an analog value or a digital value.
  • the digital value may be, for example, a binary value or a ternary value. A value with a larger number of bits may be used.
  • an analog value for example, a linear ramp function, a sigmoid function, or the like may be used as the activation function.
  • binary digital values for example, a step function with an output of -1 or 1 or 0 or 1 may be used.
  • the signal output by the neurons in each layer may have three or more values.
  • the neural network 100 By inputting an input signal to the first layer (input layer), the neural network 100 is sequentially input from the front layer in each layer from the first layer (input layer) to the last layer (output layer). Based on the signal, an output signal is generated using the equation (1), the equation (2) (or the equation (3)), and the equation (4), and the output signal is output to the next layer.
  • the signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.
  • the weight coefficient of the synapse circuit of the neural network 100 is binary (a combination of “-1” and “+1”, a combination of “0”, “+1”, etc.), and 3 A value (a combination of "-1", “0”, “1”, etc.) or a multi-value of 4 or more values (in the case of 5 values, "-2", “-1", “0”, “1” , “2” combination, etc.), and the activation function of the neuron is binary ("-1", "+1” combination, or "0", "+1” combination, etc.), trivalent (“-1").
  • the weighting coefficient is referred to as the first data, and the value of the signal input from the neuron in the previous layer to the neuron in the next layer (sometimes referred to as an calculated value) may be referred to as the second data.
  • the weighting coefficient and the calculated value of the synaptic circuit of the neural network 100 are not limited to digital values, and analog values can be used for at least one of them.
  • the arithmetic circuit 110 shown in FIG. 15A is, for example, a semiconductor device including an array unit ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP.
  • the arithmetic circuit 110 transmits signals z 1 (k-1) to z m (k-1) input to neurons N 1 (k) to neurons N n (k) in the kth layer in FIGS. 14A and 14B. It is a circuit which processes and generates the signal z 1 (k) to z n (k) output from each of the neuron N 1 (k) to the neuron N n (k) .
  • the whole or a part of the arithmetic circuit 110 may be used for purposes other than the neural network or AI.
  • the processing may be performed using the whole or a part of the calculation circuit 110. .. That is, not only the calculation for AI but also the whole or a part of the arithmetic circuit 110 may be used for general calculation.
  • the circuit ILD is electrically connected to the wiring IL [1] to the wiring IL [n] and the wiring ILB [1] to the wiring ILB [n].
  • the circuit WLD is electrically connected to the wiring WLS [1] to the wiring WLS [m].
  • the circuit XLD is electrically connected to the wiring XLS [1] to the wiring XLS [m].
  • the circuit AFP is electrically connected to the wiring OL [1] to the wiring OL [n] and the wiring OLB [1] to the wiring OLB [n].
  • the array unit ALP has m ⁇ n circuits MP as an example.
  • the circuit MP is arranged in a matrix of m rows and n columns in the array unit ALP.
  • the circuit MP located in the i-row j column (where i is an integer of 1 or more and m or less and j is an integer of 1 or more and n or less) is referred to as a circuit MP [i, It is written as j].
  • FIG. 15A only the circuit MP [1,1], the circuit MP [m, 1], the circuit MP [i, j], the circuit MP [1, n], and the circuit MP [m, n] are shown.
  • Other circuit MPs are not shown.
  • the circuit MP [i, j] includes wiring IL [j], wiring ILB [j], wiring WLS [i], wiring XLS [i], wiring OL [j], and wiring OLB [ j] and are electrically connected to.
  • the circuit MP [i, j] has, for example, a function of holding a weighting coefficient (first data) between the neuron N i (k-1) and the neuron N j (k) .
  • the circuit MP [i, j] has information (for example, potential, resistance value, etc.) according to the first data (weight coefficient) input from the wiring IL [j] and the wiring ILB [j]. (Current value, etc.) is maintained.
  • the circuit MP [i, j] has a function of outputting the product of the signal zi (k-1) (second data) output from the neuron N i (k-1 ) and the first data. Have.
  • the circuit MP [i, j] obtains information (for example, potential, resistance value, current value, etc.) corresponding to the second data zi (k-1) from the wiring XLS [i].
  • information corresponding to the product of the first data and the second data (for example, potential, resistance value, current value, etc.) is output to the wiring OL [j] and the wiring OLB [j].
  • the wiring IL [j] and the wiring ILB [j] are arranged, one aspect of the present invention is not limited to this. Only one of the wiring IL [j] and the wiring ILB [j] may be arranged.
  • the circuit XLD connects the information (for example, potential, current value, etc.) corresponding to the second data zi (k- 1) output from the neuron Ni (k-1) to the wiring XLS [ It is supplied to each of the circuit MP [i, 1] to the circuit MP [i, n] via i].
  • the circuit WLD has a function of selecting a circuit MP to which information (for example, potential, resistance value, current value, etc.) corresponding to the first data input from the circuit ILD is written. For example, when information (for example, potential, resistance value, current value, etc.) is written to the circuit MP [i, 1] to the circuit MP [i, n] located in the i-th row of the array unit ALP, the circuit WLD is used. For example, a signal for turning the write switching element included in the circuit MP [i, 1] to the circuit MP [i, n] into an on state or an off state is supplied to the wiring WLS [i], except for the i-th line.
  • information for example, potential, resistance value, current value, etc.
  • the potential for turning off the writing switching element included in the circuit MP of the above circuit MP may be supplied to the wiring WLS.
  • a wiring for transmitting an inverted signal of the signal input to the wiring WLS [i] may be separately arranged.
  • the signal corresponds to the signal z j (k) output from the neuron N j (k) .
  • the circuit ACTF [1] to the circuit ACTF [n] functions, for example, as a circuit for performing the calculation of the activation function of the neural network described above.
  • the circuit ACTF [1] to the circuit ACTF [n] may have a function of converting an analog signal into a digital signal.
  • the circuit ACTF [1] to the circuit ACTF [n] may have a function of amplifying and outputting an analog signal, that is, a function of converting an output impedance.
  • FIG. 15B is an example of the configuration of the circuit MP.
  • the circuit MP includes a circuit MC and a circuit MCr.
  • the circuit MC has, for example, transistors M1 to M4 and a capacitance C1.
  • the circuit MCr has, for example, transistors M1r to M4r and a capacitance C1r.
  • the capacity C1 and the capacity C1r can have the same configuration as the capacity 11 shown in the first embodiment.
  • the holding portion HC is composed of, for example, the transistor M2 and the capacitance C1. Further, for example, the holding portion HCr is composed of, for example, the transistor M2r and the capacitance C1r.
  • the transistors M1 to M4 and the transistors M1r to M4r shown in FIG. 15B are, for example, n-channel transistors having a multi-gate structure having gates above and below the channel.
  • Each of the transistors M1 to M4 and the transistors M1r to M4r has a first gate and a second gate.
  • the size of the transistor M3 is preferably equal to the size of the transistor M4, and the size of the transistor M3r is preferably equal to the size of the transistor M4r.
  • one of the source and drain of the transistor M1 is electrically connected to the wiring VE.
  • the other of the source or drain of the transistor M1 is electrically connected to one of the source or drain of the transistor M3 and one of the source or drain of the transistor M4.
  • the gate of the transistor M1 is electrically connected to the first electrode of the capacitance C1 and one of the source or drain of the transistor M2.
  • the second electrode of the capacitance C1 is electrically connected to the wiring VE.
  • the other of the source or drain of the transistor M2 is electrically connected to the wiring OL.
  • the gate of the transistor M2 is electrically connected to the wiring WL.
  • a connection configuration different from that of the circuit MC will be described in the circuit MCr.
  • the other of the source or drain of the transistor M3r is electrically connected to the wiring OL, not the wiring OL, and the other of the source or drain of the transistor M4r is electrically connected to the wiring OL, not the wiring OLB.
  • One of the source or drain of the transistor M1r and the second electrode of the capacitance C1r are electrically connected to the wiring VEr.
  • the electrical connection point between the gate of the transistor M1, the first electrode of the capacitance C1, and either the source or the drain of the transistor M2 is designated as a node n1.
  • the electrical connection point between the gate of the transistor M1r, the first electrode of the capacitance C1r, and one of the source or drain of the transistor M2r is a node n1r.
  • the holding unit HC has a function of holding a potential according to the first data.
  • the potential in the holding portion HC included in the circuit MC of FIG. 15B when the transistors M2 and M3 are turned on, the potential is input from the wiring OL and the potential is written in the capacitance C1. After that, the transistor M2 is turned off. Thereby, the potential of the node n1 can be held as the potential corresponding to the first data. At this time, a current can be input from the wiring OL, and a potential having a magnitude corresponding to the magnitude of the current can be held in the capacitance C1. Therefore, it is possible to reduce the influence of variations in the current characteristics of the transistor M1.
  • both ends of the wiring OL shown in FIG. 15B are referred to as nodes ina and outa, and both ends of the wiring OL are referred to as nodes inb and outb.
  • the wiring VE and the wiring VEr function as wiring for supplying a constant potential, for example.
  • the constant potential is, for example, a low potential VSS, a ground potential, or a low potential other than these. Can be done.
  • FIGS. 17A to 17C, and FIGS. 18A to 18C are timing charts showing operation examples of the circuit MP, and fluctuations in the potentials of the wiring WL, WX1L, X2L, nodes n1, and n1r, respectively. Is shown.
  • "H” shown in FIGS. 16A to 18C indicates a high potential
  • "L” indicates a low potential.
  • IOL the amount of current output from the wiring OL to the node outa (or from the node outa to the wiring OL) is defined as IOL.
  • the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is defined as IOLB .
  • IOLB the amount of current output from the wiring OLB to the node outb (or from the node outb to the wiring OLB)
  • VSS low potential
  • the transistor M1 when the transistors M2 and M3 are in the ON state, the transistor M1 has a diode connection configuration. Therefore, when a current flows from the wiring OL to the circuit MC, the potentials of the other of the source or drain of the transistor M1 and the gate of the transistor M1 become substantially equal. The potential is determined by the amount of current flowing from the wiring OL to the circuit MC, the potential of one of the source or drain of the transistor M1 (here, VSS), and the like.
  • the transistor M1 functions as a current source through which a current corresponding to the potential of the gate of the transistor M1 flows. Therefore, it is possible to reduce the influence of variations in the current characteristics of the transistor M1.
  • the amount of current flowing from the wiring OL to the circuit MC is 0, I 1 , and I 2 . Therefore, the amount of current programmed in the transistor M1 is 0, I 1 , and I 2 .
  • the potential of the gate of the transistor M1 held in the holding portion HC is VSS
  • the potential of one of the source or drain of the transistor M1 and the potential of the other of the source or drain are also VSS, so that the potential of the transistor M1 is If the threshold voltage is higher than 0, the transistor M1 is turned off. Therefore, no current flows between the source and drain of the transistor M1. Therefore, it can be said that the amount of current flowing between the source and drain of the transistor M1 is programmed to be zero.
  • the amount of current flowing through the transistor M1 is I 2 . Therefore, when the potential of the gate of the transistor M1 is V 2 , it can be said that the amount of current flowing between the source and drain of the transistor M1 is programmed in I 2 .
  • the amount of current of I 1 is larger than 0 and smaller than I 2 .
  • the potential V 1 is higher than VSS and lower than V 2 .
  • the threshold voltage of the transistor M1 is higher than 0 and lower than V1 - VSS.
  • each combination of the first data for example, hereinafter referred to as a weighting coefficient
  • the second data for example, in the following, a neuron signal value (calculated value), etc.
  • a low potential is applied to the wiring WL, WX1L, and X2L.
  • a low potential is input to the respective gates of the transistors M2, M2r, M3, M3r, M4, and M4r, so that each of the transistors M2, M2r, M3, M3r, M4, and M4r is turned off.
  • a high potential is applied to the wiring WL and the wiring WX1L.
  • a high potential is input to each of the gates of the transistors M2, M2r, M3, and M3r, so that each of the transistors M2, M2r, M3, and M3r is turned on.
  • Vini is applied as an initialization potential to each of the wiring OL and OLB. Since each of the transistors M2, M2r, M3, and M3r is in the ON state, the potentials of the node n1 of the holding portion HC and the potentials of the node n1r of the holding portion HCr are V ini . That is, in the period T12, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr are initialized.
  • the transistors M1 and M1r are turned off, so that the wiring OL and the wiring VE are in a non-conducting state, and the wiring OLB and the wiring VEr are in a non-conducting state.
  • a low potential is applied to the wiring WL and the wiring WX1L.
  • a low potential is input to each of the gates of the transistors M2, M2r, M3, and M3r, so that each of the transistors M2, M2r, M3, and M3r is turned off.
  • the transistors M2 and M2r are turned off, the potential VSS of the node n1 of the holding portion HC is held, and the potential VSS of the node n1r of the holding portion HCr is held.
  • the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE via the circuit MC.
  • the transistor M3r is turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr.
  • the first data (weight coefficient) is "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is "+1".
  • the product of the first data (weight coefficient) and the second data (neuron signal value) is "0".
  • the result that the product of the first data (weighting factor) and the second data (neuron signal value) is "0" is that in the operation of the circuit MP, the current IOL and the current IOLB are each in the period T15. Corresponds to the case where it does not change.
  • the first data for example, weighting coefficient, etc.
  • the second data neuro signal value, calculated value, etc.
  • I 1 is input from the wiring OL to the circuit MC as a current amount
  • the potential VSS is input from the wiring OLB to the circuit MCr.
  • the potential of the node n1 of the holding portion HC becomes V1
  • the potential of the node n1r of the holding portion HCr becomes VSS.
  • the transistor M1 is programmed to pass I 1 as a current amount, so that I 1 flows from the wiring OL to the wiring VE via the circuit MC.
  • the transistor M1r since the transistor M1r is programmed to pass 0 as the amount of current, no current flows from the wiring OLB to the wiring VEr via the circuit MCr.
  • a low potential is applied to the wiring WL and the wiring WX1L.
  • a low potential is input to each of the gates of the transistors M2, M2r, M3, and M3r, so that each of the transistors M2, M2r, M3, and M3r is turned off.
  • the transistors M2 and M2r are turned off, the potential V1 of the node n1 of the holding portion HC is held, and the potential VSS of the node n1r of the holding portion HCr is held.
  • the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE via the circuit MC.
  • the transistor M3r is turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr.
  • a high potential is input to the wiring WX1L and a low potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “+1” to the circuit MP.
  • a high potential is input to each gate of the transistors M3 and M3r, and a low potential is input to each gate of the transistors M4 and M4r. Therefore, each of the transistors M3 and M3r is turned on, and each of the transistors M4 and M4r is turned off.
  • the wiring VE from the wiring OL. Current flows in the meantime. Further, in the circuit MC, since the transistor M4 is in the off state, no current flows between the wiring OLB and the wiring VE. On the other hand, in the circuit MCr, the transistor M3r is in the on state, but the transistor M1 is in the off state (because it is programmed to pass 0 as the amount of current), so that the wiring from the wiring OLB to the wiring VEr No current flows between them.
  • the first data (weight coefficient) is set to "+1” and the second data (value of the neuron signal) input to the circuit MP is set to "+1", so that the equation (1) is used.
  • the product of the first data (weighting factor) and the second data (neuron signal value) is "+1".
  • the result that the product of the first data (weight coefficient) and the second data (neuron signal value) is "+1" is that in the operation of the circuit MP, the current IOL increases by I 1 in the period T15, and the current Corresponds to the case where the IOLB does not change.
  • the potential VSS is input from the wiring OL to the circuit MC
  • I 1 is input from the wiring OLB to the circuit MCr as the amount of current.
  • the potential of the node n1 of the holding portion HC becomes VSS
  • the potential of the node n1r of the holding portion HCr becomes V1.
  • the transistor M1 is programmed to pass 0 as the amount of current
  • no current flows from the wiring OL to the wiring VE via the circuit MC.
  • the transistor M1r is programmed to flow I 1 as a current amount, I 1 flows from the wiring OLB to the wiring VEr via the circuit MCr.
  • a low potential is applied to the wiring WL and the wiring WX1L.
  • a low potential is input to each of the gates of the transistors M2, M2r, M3, and M3r, so that each of the transistors M2, M2r, M3, and M3r is turned off.
  • the transistors M2 and M2r are turned off, the potential VSS of the node n1 of the holding portion HC is held, and the potential V1 of the node n1r of the holding portion HCr is held.
  • the transistor M3 is turned off, no current flows from the wiring OL to the wiring VE via the circuit MC.
  • the transistor M3r is turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr.
  • a high potential is input to the wiring WX1L and a low potential is input to the wiring X2L as the input of the second data (neuron signal (calculated value)) “+1” to the circuit MP.
  • a high potential is input to each gate of the transistors M3 and M3r, and a low potential is input to each gate of the transistors M4 and M4r. Therefore, each of the transistors M3 and M3r is turned on, and each of the transistors M4 and M4r is turned off.
  • the transistor M3 is in the on state, but the transistor M1 is in the off state (because it is programmed to pass 0 as the amount of current), so from the wiring OL to the wiring VE. No current flows between them.
  • the transistor M4 since the transistor M4 is in the off state, no current flows between the wiring OLB and the wiring VE.
  • the transistor M3r since the transistor M3r is in the ON state and the transistor M1r is in the ON state (because it is programmed to pass I1 as the amount of current), from the wiring OLB to the wiring VEr. Current flows between them.
  • the transistor M4r since the transistor M4r is in the off state, no current flows from the wiring OL to the wiring VEr. From the above, the current IOL output from the node outa of the wiring OL does not change between the period T14 and the period T15, and the current IOLB output from the node outb of the wiring OL increases by I1 in the period T15.
  • the first data (weight coefficient) is "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is "+1".
  • the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1".
  • the result that the product of the first data (weight coefficient) and the second data (neuron signal value) is "-1" is that in the operation of the circuit MP, the current IOL does not change in the period T15, and the current I OLB corresponds to the case where I increases by 1 .
  • V 2 can be held in the holding portion HCr by programming the current flowing from the wiring OLB to the circuit MCr to I 2 instead of I 1 .
  • "-2" is set as the first data (weighting factor) of the circuit MP.
  • the first data from the equation (1) can be obtained.
  • the product of the data (weight coefficient) and the second data (value of the signal of the neuron) is "-2".
  • a low potential is input to the wiring WX1L and a high potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “-1” to the circuit MP.
  • a low potential is input to each gate of the transistors M3 and M3r, and a high potential is input to each gate of the transistors M4 and M4r. Therefore, each of the transistors M3 and M3r is turned off, and each of the transistors M4 and M4r is turned on.
  • the circuit MC and the wiring OL and the circuit MCr and the wiring OLB become non-conducting, and the circuit MC and the wiring OLB and the circuit MCr and the wiring OL become non-conducting.
  • the interval becomes conductive.
  • the first data (weight coefficient) is set to “0” and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1".
  • the product of the first data (weight coefficient) and the second data (neuron signal value) is “0”.
  • the result that the product of the first data (weight coefficient) and the second data (neuron signal value) is "0" is that in the operation of the circuit MP, the current I OL and the current I in the period T14 and the period T15.
  • each of the OLBs does not change, which is consistent with the result of the circuit operation of condition 1.
  • a low potential is input to the wiring WX1L and a high potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “-1” to the circuit MP.
  • a low potential is input to each gate of the transistors M3 and M3r, and a high potential is input to each gate of the transistors M4 and M4r. Therefore, each of the transistors M3 and M3r is turned off, and each of the transistors M4 and M4r is turned on.
  • the circuit MC and the wiring OL and the circuit MCr and the wiring OLB become non-conducting, and the circuit MC and the wiring OLB and the circuit MCr and the wiring OL become non-conducting.
  • the interval becomes conductive.
  • the transistor M4r since the transistor M4r is in the ON state and the transistor M1 is in the OFF state (because it is programmed to pass 0 as the current amount), from the wiring OL to the wiring VEr. No current flows between them. From the above, the current IOL output from the node outa of the wiring OL does not change between the period T14 and the period T15, and the current IOLB output from the node outb of the wiring OL increases by I1 in the period T15.
  • the first data (weight coefficient) is "+1" and the second data (neuron signal value (calculated value)) input to the circuit MP is "-1".
  • the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1".
  • the result that the product of the first data (weight coefficient) and the second data (neuron signal value) is "-1" is that in the operation of the circuit MP, the current IOL does not change in the period T15, and the current The I OLB corresponds to the case of increasing I 1 , which is consistent with the result of the circuit operation of condition 3.
  • the current flowing from the wiring OL to the circuit MC may be programmed to I 2 instead of I 1 to hold V 2 in the holding unit HC. ..
  • "+2" is set as the first data (weighting factor) of the circuit MP.
  • the first data (weighting factor) and the second data (weighting factor) can be obtained from the equation (1).
  • the product of the data (value of the signal of the neuron) is "-2".
  • the first data is set to "-1”
  • the second data neuroon signal value (calculated value)
  • FIG. 17C is a timing chart of the circuit MP in that case.
  • a low potential is input to the wiring WX1L and a high potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “-1” to the circuit MP.
  • a low potential is input to each gate of the transistors M3 and M3r, and a high potential is input to each gate of the transistors M4 and M4r. Therefore, each of the transistors M3 and M3r is turned off, and each of the transistors M4 and M4r is turned on.
  • the circuit MC and the wiring OL and the circuit MCr and the wiring OLB become non-conducting, and the circuit MC and the wiring OLB and the circuit MCr and the wiring OL become non-conducting.
  • the interval becomes conductive.
  • the transistor M4r since the transistor M4r is in the ON state and the transistor M1 is in the ON state (because it is programmed to pass I1 as the amount of current), from the wiring OL to the wiring VEr. Current flows between them. From the above, the current IOL output from the node outa of the wiring OL increases by I1 in the period T15, and the current IOLB output from the node outb of the wiring OL does not change between the period T14 and the period T15.
  • this condition is because the first data (weight coefficient) is set to “-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1".
  • the product of the first data (weight coefficient) and the second data becomes “+1”.
  • the result that the product of the first data (weight coefficient) and the second data (neuron signal value) is "+1” is that the current IOL changes between the period T14 and the period T15 in the operation of the circuit MP.
  • a low potential is input to the wiring WX1L and a low potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “0” to the circuit MP.
  • a low potential is input to each gate of the transistors M3, M3r, M4, and M4r. Therefore, each of the transistors M3, M3r, M4, and M4r is turned off. That is, by this operation, the circuit MC and the wiring OL, the circuit MCr and the wiring OLB, the circuit MC and the wiring OLB, and the circuit MCr and the wiring OL are in a non-conducting state.
  • the first data (weight coefficient) is set to “0” and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "0".
  • the product of the first data (weight coefficient) and the second data (neuron signal value) is "0".
  • the result that the product of the first data (weighting factor) and the second data (neuron signal value) is "0" is that in the operation of the circuit MP, the current IOL and the current IOLB are each in the period T15. Corresponds to the case where it does not change, which is consistent with the result of the circuit operation of conditions 1 and 4.
  • a low potential is input to the wiring WX1L and a low potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “0” to the circuit MP.
  • a low potential is input to each gate of the transistors M3, M3r, M4, and M4r. Therefore, each of the transistors M3, M3r, M4, and M4r is turned off. That is, as in condition 7, this operation causes the circuit between the circuit MC and the wiring OL, between the circuit MCr and the wiring OLB, regardless of the amount of programmed current flowing through each of the transistors M1 and M1r.
  • a non-conducting state is established between the MC and the wiring OLB, and between the circuit MCr and the wiring OL. Therefore, no current flows from the wiring OL to one of the wiring VE or the wiring VEr, and no current flows from the wiring OLB to the other of the wiring VE or the wiring VEr. From the above, the current I OL output from the node outa of the wiring OL and the current I OLB output from the node outb of the wiring OL do not change between the period T14 and the period T15, respectively.
  • the first data (weight coefficient) is set to "+1" and the second data (neuron signal (calculated value)) input to the circuit MP is set to "0", so that the equation (1).
  • the product of the first data (weight coefficient) and the second data (neuron signal value) is "0".
  • the result that the product of the first data (weighting factor) and the second data (neuron signal value) is "0" is that in the operation of the circuit MP, the current IOL and the current IOLB are each in the period T15. Corresponds to the case where it does not change, which is consistent with the result of the circuit operation of conditions 1, 4, and 7.
  • a low potential is input to the wiring WX1L and a low potential is input to the wiring X2L as the input of the second data (value of the signal of the neuron (calculated value)) “0” to the circuit MP.
  • a low potential is input to each gate of the transistors M3, M3r, M4, and M4r. Therefore, each of the transistors M3, M3r, M4, and M4r is turned off. That is, as in condition 7, this operation causes the circuit between the circuit MC and the wiring OL, between the circuit MCr and the wiring OLB, regardless of the amount of programmed current flowing through each of the transistors M1 and M1r.
  • a non-conducting state is established between the MC and the wiring OLB, and between the circuit MCr and the wiring OL. Therefore, no current flows from the wiring OL to one of the wiring VE or the wiring VEr, and no current flows from the wiring OLB to the other of the wiring VE or the wiring VEr. From the above, the current I OL output from the node outa of the wiring OL and the current I OLB output from the node outb of the wiring OL do not change between the period T14 and the period T15, respectively.
  • the first data (weight coefficient) is set to "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "0".
  • the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0".
  • the result that the product of the first data (weight coefficient) and the second data (neuron signal value) is "0" is that in the operation of the circuit MP, the current I OL and the current I in the period T14 and the period T15.
  • each of the OLBs does not change, which is consistent with the result of the circuit operation of conditions 1, 4, 7, and 8.
  • the first data is set to only two values of "+1” and "-1
  • the second data value of the signal of the neuron
  • the circuit MP can perform the same operation as the circuit (matching circuit) in which the exclusive OR is negated.
  • the first data is set to only two values of "+1” and "0"
  • the second data value of the signal of the neuron
  • the potentials held in the holding portions HC and HCr of the circuit MC and MCr of the circuit MP are set to multiple values such as VSS, V1 and V2, but the holding portions HC and HCr . May hold a potential indicating a binary value or an analog value.
  • the first data (weight coefficient) is a “positive analog value”
  • a high level analog potential is held in the node n1 of the holding unit HC
  • a low potential is held in the node n1r of the holding unit HCr.
  • the first data (weight coefficient) is a "negative analog value"
  • a low potential is held in the node n1 of the holding unit HC
  • a high level analog potential is held in the node n1r of the holding unit HCr. Ru.
  • the magnitudes of the currents of the current IOL and the currents IOLB are the magnitudes corresponding to the analog potentials.
  • FIG. 19 shows a part of the cross-sectional structure of the semiconductor device.
  • the semiconductor device shown in FIG. 19 has a transistor 550, a transistor 500, and a capacity of 600.
  • FIG. 20A is a top view of the transistor 500.
  • FIG. 20B is a cross-sectional view of the portion L1-L2 shown by the alternate long and short dash line in FIG. 20A, and is a cross-sectional view of the transistor 500 in the channel length direction.
  • FIG. 20C is a cross-sectional view of the portion W1-W2 shown by the alternate long and short dash line in FIG. 20A, and is a cross-sectional view of the transistor 500 in the channel width direction.
  • the transistor 500 corresponds to an OS transistor, for example, a transistor 21 included in the semiconductor device shown in the above embodiment.
  • the transistor 550 corresponds to a Si transistor, for example, a transistor 22 included in the semiconductor device shown in the above embodiment.
  • the transistor 500 is an OS transistor.
  • the OS transistor has an extremely small off current. Therefore, it is possible to hold the data potential or electric charge written in the storage node via the transistor 500 for a long period of time. That is, the frequency of refreshing operations of the storage node is reduced, or the refreshing operation is not required, so that the power consumption of the semiconductor device can be reduced.
  • the transistor 500 is provided above the transistor 550, and the capacitance 600 is provided above the transistor 550 and the transistor 500.
  • the transistor 550 is provided on the substrate 371.
  • the substrate 371 is, for example, a p-type silicon substrate.
  • the substrate 371 may be an n-type silicon substrate.
  • the oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed in a substrate 371 by embedded oxidation (Blured oxide), for example, silicon oxide.
  • the transistor 550 is provided on a single crystal silicon, so-called SOI (Silicon On Insulator) substrate, which is provided on the substrate 371 via the oxide layer 374.
  • SOI Silicon On Insulator
  • the substrate 371 in the SOI substrate is provided with an insulator 373 that functions as an element separation layer.
  • the substrate 371 also has a well region 372.
  • the well region 372 is a region to which n-type or p-type conductivity is imparted depending on the conductive type of the transistor 550.
  • the single crystal silicon in the SOI substrate is provided with a semiconductor region 375, a low resistance region 376a that functions as a source region or a drain region, and a low resistance region 376b. Further, a low resistance region 376c is provided on the well region 372.
  • the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.
  • the conductor 378 may function as a first gate (also referred to as a top gate) electrode. Further, the well region 372 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the potential applied to the well region 372 can be controlled via the low resistance region 376c.
  • the low resistance region 376a which is the region where the channel of the semiconductor region 375 is formed, the region in the vicinity thereof, the source region, or the drain region, and the low resistance region 376b and the well region 372 connected to the electrodes that control the potential.
  • the region 376c or the like preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 550 may be a HEMT by using GaAs and GaAlAs or the like.
  • the conductor 378 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • a silicide such as nickel silicide may be used as the conductor 378.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the low resistance region 376a, the low resistance region 376b, and the low resistance region 376c may be configured to be provided by laminating another conductor, for example, a silicide such as nickel silicide. With this configuration, the conductivity of the region that functions as an electrode can be enhanced. At this time, an insulator that functions as a side wall spacer (also referred to as a side wall insulating layer) may be provided on the side surface of the conductor 378 that functions as the gate electrode and the side surface of the insulator that functions as the gate insulating film. .. With this configuration, it is possible to prevent the conductor 378 and the low resistance region 376a and the low resistance region 376b from being in a conductive state.
  • a silicide such as nickel silicide
  • An insulator 379, an insulator 381, an insulator 383, and an insulator 385 are laminated in this order so as to cover the transistor 550.
  • the insulator 379, the insulator 381, the insulator 383, and the insulator 385 for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, etc. are used. Just do it.
  • silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition refers to a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material having a composition higher in oxygen content than nitrogen
  • aluminum nitride means a material having a composition higher in nitrogen content than oxygen. Is shown.
  • the insulator 381 may have a function as a flattening film for flattening a step generated by a transistor 550 or the like provided below the insulator 381.
  • the upper surface of the insulator 381 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 383 it is preferable to use a film having a barrier property so that hydrogen or impurities do not diffuse in the region where the transistor 500 is provided from the substrate 371 or the transistor 550 or the like.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS) or the like.
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 383 is the amount desorbed in terms of hydrogen atoms in the range of 50 ° C. to 500 ° C. in the surface temperature of the film in TDS analysis, which is converted per area of the insulator 383. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 385 preferably has a lower dielectric constant than the insulator 383.
  • the relative permittivity of the insulator 385 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 385 is preferably 0.7 times or less, more preferably 0.6 times or less the relative permittivity of the insulator 383.
  • the insulator 379, the insulator 381, the insulator 383, and the insulator 385 are embedded with a capacity 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • the conductor having a function as a plug or wiring may collectively give the same reference numeral to a plurality of configurations.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten.
  • a wiring layer may be provided on the insulator 385 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 550.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 550 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 354 and the conductor 356.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order.
  • a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 has a function as a plug or wiring.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 360 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 383.
  • the conductor 366 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 364 and the conductor 366.
  • the insulator 370, the insulator 369, and the insulator 368 are laminated in this order.
  • a conductor 376 is formed on the insulator 370, the insulator 369, and the insulator 368.
  • the conductor 376 has a function as a plug or wiring.
  • the conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 370 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 383.
  • the conductor 376 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen.
  • the insulator 380 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 383.
  • the conductor 386 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen.
  • the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment has been described. It is not limited to this.
  • the number of wiring layers similar to the wiring layer including the conductor 356 may be 3 or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be 5 or more.
  • An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are laminated on the insulator 384 in this order.
  • any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen and hydrogen.
  • the insulator 510 and the insulator 514 it is preferable to use a film having a barrier property against hydrogen or impurities in the region where the transistor 500 is provided, for example, from the region where the substrate 371 or the transistor 550 is provided. Therefore, the same material as the insulator 383 can be used.
  • silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, which may deteriorate the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.
  • the film having a barrier property against hydrogen for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • the same material as the insulator 379 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • a conductor 518, a conductor constituting the transistor 500 (for example, a conductor 503) and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516.
  • the conductor 518 has a capacity of 600, or a function as a plug or wiring for connecting to the transistor 550.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water.
  • the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable to have.
  • the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 545.
  • oxide 530a and the oxide 530b may be collectively referred to as an oxide 530.
  • the transistor 500 shows a configuration in which two layers of oxide 530a and oxide 530b are laminated in a region where a channel is formed and in the vicinity thereof, but the present invention is not limited to this.
  • a single layer of the oxide 530b or a laminated structure of three or more layers may be provided.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved and high frequency characteristics can be provided.
  • the conductor 560 may function as a first gate (also referred to as a gate or top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, it is possible to increase the threshold voltage of the transistor 500 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
  • the configuration of a transistor that electrically surrounds a channel forming region by an electric field of a pair of gate electrodes is referred to as a curved channel (S-channel) configuration.
  • S-channel configuration disclosed in the present specification and the like is different from the Fin type configuration and the planar type configuration.
  • the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • the conductor 503a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, etc.
  • the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductor 503 also has a wiring function
  • the conductor 503 is shown by laminating the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer structure.
  • the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition.
  • the oxygen is easily released from the membrane by heating.
  • oxygen released by heating may be referred to as "excess oxygen”. That is, it is preferable that the insulator 524 is formed with a region containing excess oxygen (also referred to as “excess oxygen region”).
  • the defect (hereinafter, may be referred to as VOH) functions as a donor and may generate electrons as carriers.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in an oxide semiconductor is easily moved by stress such as heat and electric field, if a large amount of hydrogen is contained in the oxide semiconductor, the reliability of the transistor may be deteriorated. In one aspect of the invention, it is preferred to reduce VOH in the oxide 530 as much as possible to achieve high purity or substantially high purity.
  • an oxide material in which a part of oxygen is desorbed by heating is those whose oxygen desorption amount in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed.
  • a reaction in which the bond of VoH is cleaved occurs, in other words, a reaction of “VOH ⁇ Vo + H ” occurs, and dehydrogenation can be performed.
  • a part of the hydrogen generated at this time may be combined with oxygen to form H2O , which may be removed from the oxide 530 or the insulator in the vicinity of the oxide 530. Further, a part of hydrogen may be gettered to the conductor 542a and the conductor 542b.
  • the microwave processing for example, it is preferable to use a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side.
  • a device having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
  • the heat treatment in a state where the surface of the oxide 530 is exposed.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas, 1% or more, or 10% or more, and then continuously heat-treated in an atmosphere of nitrogen gas or an inert gas.
  • the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo + O ⁇ null" can be promoted. Further, the oxygen supplied to the hydrogen remaining in the oxide 530 reacts with the hydrogen, so that the hydrogen can be removed (dehydrated) as H2O . As a result, it is possible to suppress the hydrogen remaining in the oxide 530 from recombination with the oxygen deficiency to form VOH.
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • oxygen for example, oxygen atom, oxygen molecule, etc.
  • the insulator 522 has a function of suppressing the diffusion of oxygen or impurities, the oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 or the oxide 530.
  • the insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or in a laminated manner. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for an insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (which oxygen is difficult to permeate).
  • an insulator containing an oxide of one or both of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 is formed using such a material, the insulator 522 suppresses the release of oxygen from the oxide 530 or the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon nitride nitride, or silicon nitride may be laminated on the above insulator.
  • the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer laminated structure, but the second gate is shown.
  • the insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • the transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium).
  • One or more selected from hafnium, tantalum, tungsten, gallium and the like may be used.
  • the metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method.
  • ALD Atomic Layer Deposition
  • the metal oxide that functions as a channel forming region in the oxide 530 it is preferable to use a metal oxide having a band gap of preferably 2 eV or more, more preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • the oxide 530 can suppress the diffusion of impurities from the composition formed below the oxide 530a to the oxide 530b.
  • the oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic number ratios of each metal atom.
  • the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b. Is preferable.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the energy at the lower end of the conduction band of the oxide 530a is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxides 530a and 530b is continuously changed or continuously bonded. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.
  • the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer having a low defect level density can be formed.
  • the oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 530a.
  • the main path of the carrier is the oxide 530b.
  • the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
  • a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
  • the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
  • Iridium, strontium, a metal element selected from lanthanum, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like is preferably used.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film may be laminated.
  • the titanium film and the aluminum film may be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may be a two-layer structure in which copper films are laminated.
  • a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and the molybdenum film or the molybdenum nitride film is further formed on the aluminum film or the copper film.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a region 543a and a region 543b may be formed as a low resistance region at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity thereof.
  • the region 543a functions as one of the source region or the drain region
  • the region 543b functions as the other of the source region or the drain region.
  • a channel forming region is formed in a region sandwiched between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and come into contact with the insulator 524.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium and the like. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
  • the insulator 544 it is preferable to use aluminum oxide, or an oxide containing hafnium oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate), which is an insulator containing an oxide of one or both of aluminum and hafnium. ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
  • the conductors 542a and 542b are materials having oxidation resistance or materials whose conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an essential configuration. It may be appropriately designed according to the desired transistor characteristics.
  • the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 542a and the conductor 542b due to the excess oxygen contained in the insulator 580.
  • the insulator 545 functions as a first gate insulating film. Like the above-mentioned insulator 524, the insulator 545 is preferably formed by using an insulator that contains excessive oxygen and releases oxygen by heating.
  • silicon oxide having excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, silicon oxide to which nitrogen is added, and vacancies are used.
  • Silicon oxide having can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • the insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel forming region of the oxide 530b. Further, as with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 545 is reduced.
  • the film thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. Further, the above-mentioned microwave treatment may be performed before and / or after the formation of the insulator 545.
  • a metal oxide may be provided between the insulator 545 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 545 may have a laminated structure as in the case of the second gate insulating film.
  • an insulator that functions as a gate insulating film is heat-k material and heat.
  • the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 20B and 20C, it may have a single-layer structure or a laminated structure of three or more layers.
  • the conductor 560a has a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom and an oxygen molecule). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 545 to reduce the conductivity.
  • impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule ( N2O, NO, NO2 , etc.) and copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be called an OC (Oxide Controller) electrode.
  • OC Oxide Controller
  • the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon, resin, or the like silicon oxide and silicon nitride nitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 in which oxygen is released by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.
  • the opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the conductor 560 may have a shape having a high aspect ratio.
  • the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545.
  • an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like is used. Can be done.
  • aluminum oxide has a high barrier property, and even a thin film of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
  • an insulator 581 that functions as an interlayer film on the insulator 574. It is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the membrane, similarly to the insulator 524 and the like.
  • the conductor 540a and the conductor 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
  • the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween.
  • the conductor 540a and the conductor 540b have the same configuration as the conductor 546 and the conductor 548 described later.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen or hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582.
  • a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the same material as the insulator 379 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546 and the conductor 548. Is embedded.
  • the conductor 546 and the conductor 548 have a capacity of 600, a transistor 500, or a function as a plug or wiring for connecting to the transistor 550.
  • the conductor 546 and the conductor 548 can be provided by using the same materials as the conductor 328 and the conductor 330.
  • an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening.
  • an insulator having a high barrier property against hydrogen or water By wrapping the transistor 500 with the above-mentioned insulator having a high barrier property, it is possible to prevent moisture and hydrogen from invading from the outside.
  • a plurality of transistors 500 may be collectively wrapped with an insulator having a high barrier property against hydrogen or water.
  • an opening is formed so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the above-mentioned insulator having a high barrier property is provided so as to be in contact with the insulator 522 or the insulator 514.
  • the insulator having a high barrier property to hydrogen or water for example, the same material as the insulator 522 or the insulator 514 may be used.
  • the capacity 600 has a conductor 610, a conductor 620, and an insulator 630.
  • the conductor 612 may be provided on the conductor 546 and the conductor 548.
  • the conductor 612 has a function as a plug or wiring for connecting to the transistor 500.
  • the conductor 610 has a function as an electrode having a capacity of 600. The conductor 612 and the conductor 610 can be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film and the like can be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the configuration is not limited to this, and a laminated configuration of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.
  • a ferroelectric substance can be used for the insulator 630.
  • the insulator 630 for example, a material similar to the material that can be used for the ferroelectric layer 12 shown in the above embodiment can be used. Further, the insulator 630 may have a laminated structure of a ferroelectric layer and a normal dielectric layer as shown in FIGS. 1B1 to 1B4.
  • the conductor 620 is provided so as to be superimposed on the conductor 610 via the insulator 630.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is particularly preferable to use tungsten.
  • tungsten or molybdenum which has both heat resistance and conductivity
  • it is particularly preferable to use tungsten When it is formed at the same time as other configurations such as a conductor, Cu (copper) or Al (aluminum), which is a low resistance metal material, may be used.
  • An insulator 640 is provided on the conductor 620 and the insulator 630.
  • the insulator 640 can be provided by using the same material as the insulator 379. Further, the insulator 640 may function as a flattening film that covers the uneven shape below the insulator 640.
  • the metal oxide preferably contains at least one of indium and zinc. In particular, it is preferable to contain indium and zinc. Moreover, in addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like may be contained. ..
  • FIG. 21A is a diagram illustrating the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).
  • IGZO a metal oxide containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes “completable amorphous”.
  • Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Complex).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 21A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 21B is simply referred to as an XRD spectrum.
  • the vertical axis of FIG. 21B is Intensity, and the horizontal axis is 2 ⁇ .
  • the thickness of the CAAC-IGZO film shown in FIG. 21B is 500 nm.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or the substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 21C.
  • FIG. 21C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 21A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystal oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: atomous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a grid image, for example, in a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type, composition, and the like of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction, or the bond distance between the atoms changes due to the replacement of metal atoms. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor having high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, the generation of defects, etc., CAAC-OS can be said to be an oxide semiconductor having few impurities or defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductor depending on the analysis method.
  • a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan.
  • electron beam diffraction also referred to as selected area electron diffraction
  • a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic shape or a patch shape.
  • the CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic, and the first region is distributed in the film (hereinafter, also referred to as a cloud shape). It is said.). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn with respect to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region containing indium oxide, indium zinc oxide, or the like as a main component.
  • the second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) are unevenly distributed and have a mixed structure.
  • the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function).
  • the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on -current (Ion), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor having high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more preferably 1 ⁇ 10 -9 cm -3 or more.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are determined. , 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor wafer 4800 shown in FIG. 22A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by the previous step. Further, after that, the surface on the opposite side on which the plurality of circuit portions 4802 of the wafer 4801 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 and the like can be reduced, and the size of the wafer can be reduced.
  • a dicing step is performed. Dicing is performed along the scrib line SCL1 and the scrib line SCL2 (which may be referred to as a dicing line or a cutting line) indicated by a alternate long and short dash line.
  • the spacing 4803 is provided so that the plurality of scribe lines SCL1 are parallel to each other and the plurality of scribe lines SCL2 are parallel to each other in order to facilitate the dicing process. It is preferable to provide it so that it is vertical.
  • the chip 4800a as shown in FIG. 22B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit portions 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 22A.
  • it may be a semiconductor wafer having a rectangular shape.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 22C shows a perspective view of a board (mounting board 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 22C has a chip 4800a in the mold 4711.
  • As the chip 4800a a storage device or the like according to one aspect of the present invention can be used.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711.
  • the land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by the wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 22D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • the electronic component 4730 is provided with an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, and storage device can be used.
  • a semiconductor device such as a CPU, GPU, FPGA, and storage device.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as an interposer for mounting HBM.
  • the reliability is unlikely to be lowered due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 4730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 22D shows an example in which the electrode 4733 is formed of a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 4730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Base-Chip
  • PGA Stepgered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFNeg
  • the semiconductor device is, for example, a storage of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital still camera, a video camera, a recording / playback device, a navigation system, a game machine, etc.). Applicable to devices. It can also be used for image sensors, IoT (Internet of Things), healthcare and the like.
  • the computer includes a tablet-type computer, a notebook-type computer, a desktop-type computer, and a large-scale computer such as a server system.
  • FIGS. 23A to 23J and FIGS. 24A to 24E illustrate how the electronic component 4700 or the electronic component 4730 having the semiconductor device is included in each electronic device.
  • the information terminal 5500 shown in FIG. 23A is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and a button is provided in the housing 5510.
  • the information terminal 5500 can hold a temporary file (for example, a cache when using a web browser) generated when an application is executed.
  • a temporary file for example, a cache when using a web browser
  • FIG. 23B illustrates an information terminal 5900, which is an example of a wearable terminal.
  • the information terminal 5900 has a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.
  • the wearable terminal can hold a temporary file generated when the application is executed by applying the semiconductor device according to one aspect of the present invention.
  • FIG. 23C shows a desktop type information terminal 5300.
  • the desktop type information terminal 5300 has a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can hold a temporary file generated when the application is executed by applying the semiconductor device according to one aspect of the present invention.
  • smartphones, wearable terminals, and desktop information terminals are taken as examples as electronic devices and are shown in FIGS. 23A to 23C, respectively, but information terminals other than smartphones, wearable terminals, and desktop information terminals can be applied. can. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.
  • PDAs Personal Digital Assistants
  • FIG. 23D shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 is an electric freezer / refrigerator compatible with IoT (Internet of Things).
  • the semiconductor device can be applied to the electric freezer / refrigerator 5800.
  • the electric refrigerator-freezer 5800 can send and receive information such as foodstuffs stored in the electric refrigerator-freezer 5800 and the expiration date of the foodstuffs to an information terminal or the like via the Internet or the like.
  • the electric refrigerator / freezer 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Examples include appliances, washing machines, dryers, audiovisual equipment, and the like.
  • FIG. 23E illustrates a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 23F illustrates a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a display unit for displaying a game image, a touch panel as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 23F, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller having a shape imitating a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be provided with a camera, a depth sensor, a microphone and the like instead of using a controller, and may be operated by a game player's gesture and / or voice.
  • the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the semiconductor device described in the above embodiment By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, it is possible to realize the low power consumption portable game machine 5200 or the low power consumption stationary game machine 7500. .. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • FIG. 23E shows a portable game machine.
  • FIG. 23F shows a stationary game machine for home use.
  • the electronic device of one aspect of the present invention is not limited to this. Examples of the electronic device of one aspect of the present invention include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like.
  • the semiconductor device described in the above embodiment can be applied to an automobile which is a mobile body and around the driver's seat of the automobile.
  • FIG. 23G shows an automobile 5700, which is an example of a moving body.
  • a speedometer or tachometer Around the driver's seat of the automobile 5700, a speedometer or tachometer, and an instrument panel that provides various information by displaying mileage, fuel gauge, gear status, air conditioner settings, etc. are provided. .. Further, a display device showing such information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment can temporarily hold information. Therefore, the semiconductor device can be used for holding necessary temporary information in an automatic driving system of an automobile 5700, a system for performing road guidance, danger prediction, and the like.
  • the display device may be configured to display temporary information such as road guidance and danger prediction. Further, the image of the driving recorder installed in the automobile 5700 may be retained.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets) and the like.
  • FIG. 23H illustrates a digital camera 6240, which is an example of an image pickup apparatus.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, or the like can be separately attached.
  • a low power consumption digital camera 6240 can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 23I illustrates a video camera 6300, which is an example of an image pickup apparatus.
  • the video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by the connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 is determined by the connecting portion 6306. It can be changed.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connection unit 6306.
  • the video camera 6300 When recording a video image taken by a video camera 6300, it is necessary to perform encoding according to the data recording format. By utilizing the above-mentioned semiconductor device, the video camera 6300 can hold a temporary file generated during encoding.
  • ICD implantable cardioverter-defibrillator
  • FIG. 23J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is surgically placed in the body, and two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body, and one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. To be done.
  • the ICD main body 5400 has a function as a pacemaker and paces the heart when the heart rate deviates from a specified range. If the heart rate does not improve due to pacing and rapid ventricular tachycardia, ventricular fibrillation, or the like remains, treatment with electric shock is performed.
  • the ICD body 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shock. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Further, the ICD main body 5400 can store the heart rate data acquired by the sensor or the like, the number of times of treatment by pacing, the time, etc. in the electronic component 4700.
  • the ICD main body 5400 has a plurality of batteries, so that the safety can be enhanced. Specifically, even if a part of the battery of the ICD main body 5400 becomes unusable, the remaining battery can function, so that it also functions as an auxiliary power source.
  • the antenna 5404 that can receive power it may have an antenna that can transmit physiological signals.
  • physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.
  • a system for monitoring various cardiac activities may be configured.
  • the semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • a computer such as a PC (Personal Computer) and an expansion device for an information terminal.
  • FIG. 24A shows, as an example of the expansion device, an expansion device 6100 externally attached to a PC, which is equipped with a portable chip capable of storing information.
  • the expansion device 6100 can store information by the chip by connecting to a PC by, for example, USB (Universal Serial Bus) or the like.
  • USB Universal Serial Bus
  • FIG. 24A illustrates a portable expansion device 6100, but the expansion device according to one aspect of the present invention is not limited to this, and is relatively equipped with, for example, a cooling fan or the like. It may be a large form of expansion device.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104.
  • the substrate 6104 is housed in the housing 6101.
  • the substrate 6104 is provided with a circuit for driving the semiconductor device or the like described in the above embodiment.
  • an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The semiconductor device described in the above embodiment can be applied to an information terminal or an SD card that can be attached to an electronic device such as a digital camera.
  • FIG. 24B is a schematic diagram of the appearance of the SD card
  • FIG. 24C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113.
  • the connector 5112 functions as an interface for connecting to an external device.
  • the substrate 5113 is housed in the housing 5111.
  • the substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113.
  • the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the write circuit, low driver, read circuit, etc. provided in the electronic component may be configured to be incorporated in the controller chip 5115 instead of the electronic component 4700.
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 5113. As a result, wireless communication can be performed between the external device and the SD card 5110, and the data of the electronic component 4700 can be read and written.
  • SSD Solid State Drive
  • electronic device such as an information terminal.
  • FIG. 24D is a schematic diagram of the appearance of the SSD
  • FIG. 24E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153.
  • the connector 5152 functions as an interface for connecting to an external device.
  • the board 5153 is housed in the housing 5151.
  • the substrate 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153.
  • a work memory is built in the memory chip 5155.
  • a DRAM chip may be used for the memory chip 5155.
  • a processor, an ECC circuit, and the like are incorporated in the controller chip 5156.
  • the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configurations may be appropriately changed depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • the computer 5600 shown in FIG. 25A is an example of a large-scale computer.
  • a plurality of rack-mounted computers 5620 are stored in the rack 5610.
  • the computer 5620 may have, for example, the configuration of the perspective view shown in FIG. 25B.
  • the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted in the slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 25C is an example of a processing board including a CPU, GPU, semiconductor device, and the like.
  • the PC card 5621 has a board 5622. Further, the board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 25C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628. Regarding these semiconductor devices, the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5627 described below are shown. The description of the semiconductor device 5628 may be taken into consideration.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe and the like.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be, for example, an interface for supplying power to the PC card 5621, inputting a signal, or the like. Further, for example, it can be an interface for outputting a signal calculated by the PC card 5621.
  • Examples of the standards of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and the like.
  • HDMI registered trademark
  • the connection terminal 5625 HDMI (registered trademark) and the like can be mentioned as the respective standards.
  • the semiconductor device 5626 has a terminal (not shown) for inputting / outputting signals, and the semiconductor device 5626 and the board 5622 can be inserted by inserting the terminal into a socket (not shown) included in the board 5622. Can be electrically connected.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering to the wiring provided with the terminals 5622. be able to.
  • Examples of the semiconductor device 5627 include FPGA (Field Programmable Gate Array), GPU, CPU and the like.
  • an electronic component 4730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering to the wiring provided with the terminals 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device and the like.
  • an electronic component 4700 can be used as the semiconductor device 5628.
  • the computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations necessary for learning artificial intelligence and inference can be performed.
  • the power consumption of the electronic devices can be reduced.
  • an off-current measurement TEG (Test Element Group) sample and a capacitance leak current measurement TEG sample having the transistor 500 shown in FIGS. 20A to 20C were prepared and evaluated for temperature dependence.
  • the sample is an insulator placed on a substrate (not shown), an insulator 514 on the insulator 512, and an insulator placed on the insulator 514.
  • the insulator 524 arranged on the insulator 522, the oxide 530a arranged on the insulator 524, the oxide 530b arranged on the oxide 530a, and the oxide 530b separated from each other.
  • the insulator 544 placed above, the insulator 580 placed on the insulator 544, the insulator 545 placed on the oxide 530b, and the conductor 560 placed on the insulator 545. It has an insulator 574 arranged on the insulator 580 and the conductor 560, and an insulator 581 arranged on the insulator 574.
  • a target of In: Ga: Zn 1: 3: 4 [atomic number ratio] was used for the film formation of the oxide 530a.
  • a target of In: Ga: Zn 1: 1: 2 [atomic number ratio] was used.
  • the insulator 545 has a four-layer laminated structure.
  • the first layer of the insulator 545 was aluminum oxide having a film thickness of 1 nm, which was formed by the ALD method.
  • the second layer of the insulator 545 was silicon oxide having a film thickness of 5 nm, which was formed by a CVD method.
  • the third layer of the insulator 545 was hafnium oxide having a film thickness of 1.5 nm, which was formed by the ALD method.
  • the fourth layer of the insulator 545 was silicon nitride having a film thickness of 1 nm, which was formed by the ALD method.
  • microwave treatment was performed, respectively.
  • argon gas and oxygen gas were used as the treatment gas
  • the treatment temperature was 400 ° C.
  • the treatment time was 600 seconds.
  • the sample further has a conductor 540.
  • heat treatment was performed in a nitrogen atmosphere at a temperature of 400 ° C. for 8 hours. From the above, an off-current measurement TEG sample having a transistor 500 was prepared.
  • FIG. 26 shows a circuit diagram illustrating an outline of the off-current measurement TEG.
  • the off-current TEG has terminals A to E, a transistor 901, a transistor 902, a read circuit 903, and a node ND2.
  • the transistor 901 is a write transistor for supplying a potential to the node ND2.
  • the transistor 902 is a target transistor for off-current measurement.
  • One of the source or drain of the transistor 901 is electrically connected to the terminal A. Further, the other of the source or drain of the transistor 901 is electrically connected to the node ND2. Further, the gate of the transistor 901 is electrically connected to the terminal B. Further, one of the source and drain of the transistor 902 is electrically connected to the node ND2. Further, the other of the source or drain of the transistor 902 is electrically connected to the terminal D. Further, the gate of the transistor 902 is electrically connected to the terminal C. Further, the bottom gate of the transistor 902 is electrically connected to the terminal E. Further, the reading circuit 903 is electrically connected to the node ND2. The reading circuit 903 can always read the potential of the node ND2.
  • the potential V11 that turns on the transistor 901 is supplied to the terminal B to turn on the transistor 901.
  • the potential V12 is supplied to the terminal A until the potential of the node ND2 becomes V12.
  • V12 was set to 1.2V.
  • the potential V13 that turns off the transistor 901 is supplied to the terminal B to turn off the transistor 901.
  • the transistor 902 is always turned off by supplying the potential -2V to the terminal C, the potential -3V to the terminal E, and the potential 0V to the terminal D.
  • the potential change ⁇ V ND of the node ND2 with an elapsed time of 1 hour is read, and in the measurement environment with an elapsed time of 125 ° C., the potential change ⁇ V ND of the node ND2 with an elapsed time of 1 hour is read, and the temperature is 100 ° C.
  • the potential change ⁇ V ND of the node ND2 having an elapsed time of 2 hours was read, and in the measurement environment at a temperature of 85 ° C., the potential change ⁇ V ND of the node ND2 having an elapsed time of 4 hours was read.
  • FIG. 28 shows a graph of the temperature dependence of the off-current of the transistor 902.
  • the horizontal axis of FIG. 28 shows 1000 times the reciprocal of the absolute temperature T [K], and the vertical axis shows the leak current (off current).
  • the off-current of the transistor 902 at each temperature is shown in a diamond plot in FIG. At a temperature of 150 ° C, an off current of 1.4 ⁇ 10-20 (A), at a temperature of 125 ° C, an off current of 2.9 ⁇ 10-21 (A), and at a temperature of 100 ° C, 6.9 ⁇ 10-22 . At the off-current of (A) and the temperature of 85 ° C., the off-current of 2.9 ⁇ 10-22 (A) was obtained, respectively.
  • the approximate straight line is shown by a solid line. Extrapolating the approximate straight line to room temperature (RT) yielded a very small off-current of about 2 ⁇ 10-24 (A) at room temperature. From the above, the temperature dependence of the off-current was confirmed.
  • the capacitance leak current measurement TEG sample has a capacitance configuration in addition to the configuration of the off-current measurement TEG sample described in [Off-current measurement] above.
  • FIG. 27A shows a cross-sectional view of the capacity configuration.
  • the capacitance includes the conductor 910a on the transistor 500 (not shown), the conductor 910b on the conductor 910a, the conductor 910a, and the dielectric 930a covering the conductor 910b, and the dielectric on the dielectric 930a. It has a 930b, a conductor 920a on a dielectric 930b, a conductor 920b on a conductor 920a, an insulator 983a covering the conductor 920a and the conductor 920b, and an insulator 983b on the insulator 983a.
  • the conductor 910a tungsten having a film thickness of 30 nm, which was formed by a sputtering method, was used. Further, as the conductor 910b, titanium nitride having a film thickness of 5 nm, which was formed by a CVD method, was used. The conductors 910a and 910b function as lower electrodes of the capacitance.
  • dielectric 930a aluminum oxide having a film thickness of 14 nm formed by the ALD method was used.
  • dielectric 930b silicon oxide having a film thickness of 7 nm formed by the CVD method was used.
  • the dielectric 930a and the dielectric 930b function as a capacitive dielectric.
  • the conductor 920a titanium nitride having a film thickness of 10 nm formed by the CVD method was used.
  • the conductor 920b tungsten having a film thickness of 20 nm formed by a sputtering method was used.
  • the conductor 920a and the conductor 920b function as an upper electrode of the capacitance.
  • the insulator 983a aluminum oxide having a film thickness of 5 nm formed by the ALD method was used.
  • As the insulator 983b aluminum oxide having a film thickness of 35 nm formed by a sputtering method was used.
  • the insulator 983a and the insulator 983b function as a passivation film. After the capacity was formed, heat treatment was performed in a nitrogen atmosphere at a temperature of 400 ° C. for 8 hours. Based on the above, a TEG sample for measuring capacitance leakage current was prepared.
  • FIG. 27B a circuit diagram showing an outline of the capacitance leakage current measurement TEG is shown in FIG. 27B.
  • the capacitance leak current measurement TEG has a terminal A, a terminal B, a terminal D, a transistor 901, a capacitance 904, a read circuit 903, and a node ND2.
  • the transistor 901 is a write transistor for supplying a potential to the node ND2.
  • the capacity 904 is the capacity to be measured for the capacity leak current.
  • As the capacitance 904, 60,000 capacitances having a capacitance of 4.26 fF and a configuration shown in FIG. 27A are connected in parallel.
  • One of the source or drain of the transistor 901 is electrically connected to the terminal A. Further, the other of the source or drain of the transistor 901 is electrically connected to the node ND2. Further, the gate of the transistor 901 is electrically connected to the terminal B. Further, one electrode of the capacitance 904 is electrically connected to the node ND2. Further, the other electrode having the capacitance 904 is electrically connected to the terminal D. Further, the reading circuit 903 is electrically connected to the node ND2. The reading circuit 903 can always read the potential of the node ND2.
  • the potential V11 that turns on the transistor 901 is supplied to the terminal B to turn on the transistor 901.
  • the potential V12 is supplied to the terminal A until the potential of the node ND2 becomes V12.
  • V12 was set to 1.2V. Further, 0V was supplied to the terminal D.
  • the potential change ⁇ V ND of the node ND2 with an elapsed time of 1 hour is read, and in the measurement environment with an elapsed time of 125 ° C., the potential change ⁇ V ND of the node ND2 with an elapsed time of 4 hours is read, and the temperature is 100 ° C.
  • the potential change ⁇ V ND of the node ND2 with an elapsed time of 8 hours was read.
  • FIG. 28 shows a graph of the temperature dependence of the leakage current of the capacitance 904.
  • the horizontal axis of FIG. 28 indicates 1000 times the reciprocal of the absolute temperature T [K], and the vertical axis indicates the leakage current.
  • the leakage current of the capacitance 904 at each temperature is shown as a white circle plot in FIG. 28.
  • a leak current of 2.2 ⁇ 10-20 (A) at a temperature of 150 ° C. a leak current of 1.2 ⁇ 10-21 (A) at a temperature of 125 ° C.
  • a leakage current of 3.3 ⁇ 10-22 at a temperature of 100 ° C.
  • the leak currents of (A) were obtained respectively.
  • the approximate straight line is shown by a broken line. According to the approximate straight line, it was confirmed that the capacitance leakage current decreased as the temperature decreased. At room temperature, a very small capacitance leakage current was estimated. From the above, the temperature dependence of the capacitance leakage current was confirmed.

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
PCT/IB2021/056525 2020-08-03 2021-07-20 半導体装置の駆動方法 Ceased WO2022029534A1 (ja)

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CN202180047447.2A CN115867968A (zh) 2020-08-03 2021-07-20 半导体装置的驱动方法
US18/006,323 US12266392B2 (en) 2020-08-03 2021-07-20 Driving method of semiconductor device
DE112021004116.9T DE112021004116T5 (de) 2020-08-03 2021-07-20 Betriebsverfahren einer Halbleitervorrichtung
KR1020237006224A KR20230043924A (ko) 2020-08-03 2021-07-20 반도체 장치의 구동 방법
JP2022541319A JP7702411B2 (ja) 2020-08-03 2021-07-20 半導体装置の駆動方法
US19/019,968 US20250157519A1 (en) 2020-08-03 2025-01-14 Driving method of semiconductor device
JP2025105432A JP2025139598A (ja) 2020-08-03 2025-06-23 半導体装置の駆動方法

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WO2024243833A1 (zh) * 2023-05-30 2024-12-05 长江存储科技有限责任公司 半导体器件及其制备方法、存储器系统
KR20250053567A (ko) * 2023-10-13 2025-04-22 삼성전자주식회사 반도체 소자와, 이를 포함하는 메모리 소자 및 전자 장치
KR20250054578A (ko) * 2023-10-16 2025-04-23 삼성전자주식회사 강유전체 전계 효과 트랜지스터, 메모리 장치, 및 뉴럴 네트워크 장치

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