WO2022007160A1 - 一种显示面板及其制作方法 - Google Patents

一种显示面板及其制作方法 Download PDF

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Publication number
WO2022007160A1
WO2022007160A1 PCT/CN2020/113277 CN2020113277W WO2022007160A1 WO 2022007160 A1 WO2022007160 A1 WO 2022007160A1 CN 2020113277 W CN2020113277 W CN 2020113277W WO 2022007160 A1 WO2022007160 A1 WO 2022007160A1
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WO
WIPO (PCT)
Prior art keywords
groove
display panel
layer
pixel definition
opening
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Application number
PCT/CN2020/113277
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English (en)
French (fr)
Inventor
黄茜
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/263,886 priority Critical patent/US20220415978A1/en
Publication of WO2022007160A1 publication Critical patent/WO2022007160A1/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/805Electrodes
    • H10K50/82Cathodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/122Pixel-defining structures or layers, e.g. banks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/236Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers using printing techniques, e.g. applying the etch liquid using an ink jet printer

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof.
  • OLED Organic Light Emitting Diode
  • the light emitting functional layer In the organic light emitting diode display panel, the light emitting functional layer often adopts the low temperature evaporation technology. However, the adhesion between the organic film layers of the light emitting device produced by this technology is poor, which causes the light emitting functional layer structure to easily fall off during the bending process of the display panel. , thus affecting the stability of the display panel.
  • Embodiments of the present invention provide a display panel and a manufacturing method thereof, which are used to improve the stability of the display panel.
  • An embodiment of the present invention provides a display panel, including:
  • an anode the anode is disposed on the thin film transistor array substrate;
  • the pixel definition layer is disposed on the anode and the thin film transistor array substrate, the pixel definition layer includes a first area and a second area, wherein the first area is provided with an opening, the The bottom of the opening is connected to the anode, and the second area is provided with a plurality of grooves;
  • the light-emitting layer is disposed in the opening
  • a cathode which covers the light-emitting layer and the pixel definition layer
  • the groove is formed by a pad printing process.
  • the groove includes a first groove and at least one second groove, wherein the opening of the second groove is located on the side wall and/or the side wall of the first groove. or bottom.
  • the opening of the first groove is larger than the opening of the second groove.
  • the second grooves located at the bottom are vertically embedded on the pixel definition layer, and the embedding angles of the second grooves located on both sides are the same as the pixel definition layer.
  • the included angle of the horizontal direction of the layers is greater than or equal to 0 degrees and less than 90 degrees.
  • the depth of the groove is smaller than the thickness of the pixel definition layer.
  • the depth of the groove is between 0.2 ⁇ m and 1.2 ⁇ m.
  • the display panel further includes a filling layer, and the filling layer covers at least a part of the groove.
  • the material of the filling layer includes an inorganic material.
  • the inorganic material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or inorganic oxide.
  • Embodiments of the present invention also provide a method for manufacturing a display panel, comprising:
  • Step A forming a thin film transistor array substrate
  • Step B forming an anode, the anode is arranged on the thin film transistor array substrate;
  • Step C forming a pixel definition layer, the pixel definition layer includes a first area and a second area, wherein the first area is provided with an opening, and the second area is provided with a plurality of grooves;
  • Step D forming a light-emitting layer, and the light-emitting layer is disposed in the opening;
  • Step E forming a cathode, the cathode covering the light-emitting layer and the pixel definition layer;
  • Step F forming an encapsulation layer, the encapsulation layer covering the cathode.
  • the step C includes:
  • Step c1 forming a pixel definition material layer
  • Step c2 patterning the first region to form the opening
  • Step c3 using a pad printing process to process the second area to form the groove, wherein the groove includes a first groove and at least one second groove, and the opening of the second groove is on the side wall and/or bottom of the first groove.
  • the opening of the first groove is larger than the opening of the second groove.
  • the second groove at the bottom is vertically embedded on the pixel definition layer, and the embedding angle of the second groove at both sides is the same as that of all the second grooves.
  • the included angle in the horizontal direction of the pixel definition layer is greater than or equal to 0 degrees and less than 90 degrees.
  • the depth of the groove is smaller than the thickness of the pixel definition layer.
  • the depth of the groove is between 0.2 micrometers and 1.2 micrometers.
  • step C also comprises step G:
  • a filling layer is formed covering at least a portion of the groove.
  • the material of the filling layer includes an inorganic material.
  • the inorganic material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or inorganic oxide.
  • the material of the filling layer includes an inorganic material.
  • a groove is formed on the pixel definition layer, and a cathode material is filled in the groove to increase the contact between the cathode and the pixel definition layer. area, the adhesion between the cathode and the pixel definition layer is increased, so that the light-emitting layer is not easy to fall off, thereby improving the stability of the display panel.
  • the filling layer in the groove, since the material of the filling layer and the cathode material have the same polarity, the adhesion between the cathode and the pixel definition layer is further increased.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 2 is another schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 3 is another schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a groove in a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the arrangement of sub-pixels inside a display panel according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of step S3 in the method for fabricating a display panel provided by an embodiment of the present invention.
  • the component can be directly on the other component; an intervening component may also be present and the component is placed on the intervening component , and the intermediate component is placed on another component.
  • an intervening component may also be present and the component is placed on the intervening component
  • the intermediate component is placed on another component.
  • an embodiment of the present invention provides a display panel.
  • the display panel 10 includes a thin film transistor array substrate 100 , an anode 110 , a pixel definition layer 120 , a light emitting layer 130 , a cathode 140 and an encapsulation layer 150 .
  • the thin film transistor array substrate 100 includes: a substrate, a substrate layer, an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, a second gate, an interlayer insulating layer, a source and drain , a planarization layer (not shown in the figure).
  • the substrate layer includes a double-layer polyimide film layer and a buffer layer disposed between the polyimide film layer.
  • the structure of the thin film crystal array substrate 100 in the embodiment of the present invention belongs to common knowledge in the art, and the thin film transistor in the embodiment of the present invention may also include other structures, which will not be repeated here.
  • the first surface of the anode 110 is attached to the first surface of the thin film transistor array substrate 100 , and the via hole of the anode 110 is connected to the source or drain on the thin film transistor array substrate 100 .
  • the material of the anode 110 includes indium tin oxide (Indium Tin Oxide, ITO).
  • the pixel definition layer 120 is disposed on the anode 110 and the thin film transistor array substrate 100.
  • the pixel definition layer 120 includes a first region 120a and a second region 120b, and the first region 120a is located on both sides of the second region 120b.
  • the first region 120 a is provided with an opening 1201 , the bottom of the opening 1201 is connected to the first surface of the anode 110 , and the second region 120 b includes a plurality of grooves 1202 .
  • the pixel definition layer 120 is an organic material layer, for example, the pixel definition layer 120 includes polyimide, polyamide, styrene cyclobutene, acrylic resin, silicone, polymethyl methacrylate (PMMA) or At least one of organic materials such as phenolic resins.
  • the pixel definition layer 120 includes polyimide, polyamide, styrene cyclobutene, acrylic resin, silicone, polymethyl methacrylate (PMMA) or At least one of organic materials such as phenolic resins.
  • the light emitting layer 130 is disposed in the opening 1201 of the first region 120a.
  • the materials of the light-emitting layer 130 include fluorescent light-emitting materials, quantum dot light-emitting materials, and the like.
  • the cathode 140 covers the light-emitting layer 130 and the pixel definition layer 120, and the material of the cathode 140 fills the groove 1202; wherein, the cathode material includes metals with lower power functions such as silver, lithium, magnesium, calcium, strontium, aluminum, indium, etc., or Made of metal compounds or alloys.
  • the encapsulation layer 150 covers the cathode 140 .
  • the encapsulation layer 150 is used to prevent the display panel from being invaded by water and oxygen.
  • the grooves 1202 in the embodiment of the present invention are formed by surface embossing technology.
  • the grooves 1202 in this embodiment of the present invention may also be formed by pad printing technology, where the pad printing technology includes PI pad printing technology.
  • FIG. 2 is another schematic structural diagram of the display panel 100 in the embodiment of the present invention.
  • the groove 1202 includes a first groove 12021 and at least one second groove 12022, wherein the opening of the second groove 12022 is located on the side wall and/or the bottom of the first groove 12021.
  • the grooves 1202 are formed by a surface pad printing process. For example, a semi-circular print head is imprinted on the second area 120b, and then the first groove 12021 is formed by rolling the print head. Next, a second imprint is performed on the first groove 12021 to form The second groove 12022 .
  • a print head with a specific shape can also be provided as the main body of the print head, a plurality of coupling parts are arranged on the side and bottom of the main body, and the first groove 12021 and the second groove 12022 are directly formed by embossing. It should be noted that, in the embodiment of the present invention, the shape of the print head can be adjusted according to actual requirements, which is not limited herein.
  • FIG. 4 is another schematic structural diagram of the groove 1202 in the embodiment of the present invention.
  • the number of the second grooves 12022 of the groove 1202 is more than one.
  • the opening of the second groove 12022 is located on the side wall and the bottom of the first groove 12021, and the first groove The opening of the groove 12021 is larger than the opening of the second groove 12022 .
  • the second grooves 12022 are embedded in the pixel definition layer 120, and the embedded angle of the second grooves 12022 ranges from 90 degrees to 180 degrees.
  • the second grooves 12021 at the bottom are vertically embedded on the pixel definition layer 120, and the angle between the embedding angle of the second grooves 12022 at the two sides and the horizontal direction of the pixel definition layer 120 is greater than or equal to 0 degrees , and less than 90 degrees.
  • This arrangement can further increase the contact area between the cathode and the pixel definition layer, and prevent the light-emitting layer from detaching.
  • the depth of the groove 1202 is smaller than the thickness of the pixel definition layer, and optionally, the depth of the groove 1202 is between 0.2 ⁇ m and 1.2 ⁇ m.
  • the depth of the grooves 1202 is any one of 0.2 microns, 0.2 microns, 0.3 microns, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1.0 microns, 1.1 microns, 1.2 microns.
  • a groove is provided in the second region 120b of the pixel definition layer 120 to increase the contact area between the cathode 140 and the pixel definition layer 120, and the adhesion between the cathode 140 and the pixel definition layer 120 is increased. , so that the organic light-emitting layer is not easy to fall off, thereby improving the stability of the display panel.
  • FIG. 3 is another schematic structural diagram of the display panel 10 according to an embodiment of the present invention.
  • the display panel 10 further includes a filling layer 160 , and the filling layer 160 covers at least a part of the groove 1202 .
  • the material of the filling layer 160 includes inorganic materials.
  • the inorganic material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or inorganic oxides. It is easy to understand that the bonding force between the inorganic material and the metal or metal compound is better.
  • the cathode 140 Compared with the existing design, the cathode 140 relies on the van der Waals force between the cathode 140 and the pixel definition layer 120 to adhere, which improves the adhesion of the cathode 140. Therefore, the separation of the cathode 140 and the light emitting layer 130 is effectively avoided when the display panel is impacted or impacted, and the bending resistance strength and the drop impact strength of the display panel are improved.
  • the red sub-pixels R, the blue sub-pixels B and the green sub-pixels G are arranged in the manner of RGBBR, that is, the red sub-pixels R and the blue sub-pixels B share one green sub-pixel G, To achieve the effect of high resolution, this arrangement is called diamond arrangement.
  • the sub-pixels are not closely arranged, but there is a certain gap between each sub-pixel, that is, the red sub-pixel R and the blue sub-pixel B in FIG. 5 and the gap between the green sub-pixel G.
  • a plurality of grooves 1202 are arranged at the gaps to increase the contact area between the cathode and the pixel definition layer, thereby increasing the adhesion between the cathode and the pixel definition layer and preventing the light emitting layer from falling off.
  • an embodiment of the present invention further provides a method for manufacturing a display panel, including the following steps:
  • Step S1 forming a thin film transistor array substrate 100
  • Step S2 forming an anode 110, and the first surface of the anode 110 is arranged to be attached to the first surface of the thin film transistor array substrate 100;
  • Step S3 forming a pixel definition layer 120, the pixel definition layer includes a first area 120a and a second area 120b, wherein the first area 120a includes an opening 1201, and the second area includes a plurality of grooves 1202;
  • Step S4 forming a light-emitting layer 130, and the light-emitting layer 130 is disposed in the opening 1201 of the first region 120a;
  • Step S5 forming a cathode 140 covering the light emitting layer 130 and the pixel definition layer 120;
  • Step S6 forming an encapsulation layer 150 , the encapsulation layer 150 covering the cathode 140 .
  • the thin film transistor array substrate 100 includes: a substrate, a substrate layer, an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, a second gate, an interlayer Insulation layer, source and drain, planarization layer.
  • the substrate layer includes a double-layer polyimide film layer and a buffer layer disposed between the polyimide film layer.
  • the manufacturing method of the thin film crystal array substrate 100 in the embodiment of the present invention belongs to the common knowledge in the art, and the thin film transistor array substrate in the embodiment of the present invention may also include other structures, which will not be repeated here.
  • step S2 first, an anode material layer is formed on the thin film transistor array substrate, a photoresist film layer is formed on the anode material layer, the photoresist film layer and the anode material layer are patterned to form the anode 110, wherein the anode
  • the material of 110 includes indium tin oxide (Indium tin oxide, ITO).
  • ITO indium tin oxide
  • step S3 includes:
  • Step S31 forming a pixel definition material layer
  • Step 32 Pattern the first region 120a through a patterning process to form the opening 1201;
  • Step 33 Process the second region 120b by using a pad printing process to form the groove 1202, wherein the groove 1202 includes a first groove 12021 and at least one second groove 12022, the first groove 12022.
  • the openings of the second grooves 12022 are located on the side walls and/or the bottom of the first groove 12021 .
  • a pixel definition material layer is formed on the anode 110 and the thin film transistor array substrate 100, wherein the material of the pixel definition material layer includes polyimide, polyamide, styrene cyclobutene, acrylic resin, silicone, polymethyl methacrylate At least one of organic materials such as methyl methacrylate or phenolic resin.
  • the first region 120 a is processed through a patterning process to form an opening 1201 , and the bottom of the opening 1201 is connected to the first surface of the anode 120 .
  • the second area 120b is processed by a surface pad printing process.
  • a print head with a specific shape for example, a semi-circular print head is placed on the second area 120b to be imprinted on the second area 120b.
  • the first grooves 12021 are formed in the same manner, and then, a second imprint is performed on the first grooves 12021 to form the second grooves 12022 .
  • a print head with a specific shape can also be provided as the main body of the print head, and a plurality of coupling parts are arranged on the side and bottom of the main body, and the first groove 12021 and the second groove 12022 are formed by direct imprinting.
  • the second grooves 12022 are embedded in the pixel definition layer 120, and the embedded angle of the second grooves 12022 ranges from 90 degrees to 180 degrees. It should be noted that, in the embodiment of the present invention, the shape of the print head can be adjusted according to actual requirements, which is not limited here.
  • step S32 and step S33 is not limited, the opening 1201 can be formed first, and then the groove 1202 can be formed, or the groove 1202 can be formed first, and then the opening can be formed 1201, or the opening 1201 and the groove 1202 are formed simultaneously.
  • the depth of the groove 1202 is smaller than the thickness of the pixel definition layer, and optionally, the depth of the groove 1202 is between 0.2 ⁇ m and 1.2 ⁇ m.
  • the method further includes forming a filling layer 160 , and the filling layer 160 covers at least a part of the groove 1202 .
  • the material of the filling layer 160 includes inorganic materials.
  • the inorganic material includes at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or inorganic oxides. It is easy to understand that the bonding force between the inorganic material and the metal or metal compound is better.
  • the cathode 140 Compared with the existing design, the cathode 140 relies on the van der Waals force between the cathode 140 and the pixel definition layer 120 to adhere, which improves the adhesion of the cathode 140. Therefore, the separation of the cathode 140 and the light emitting layer 130 is effectively avoided when the display panel is impacted or impacted, and the bending resistance strength and the drop impact strength of the display panel are improved.
  • a light-emitting layer is formed in the opening 1201, wherein the material of the light-emitting layer includes a fluorescent light-emitting material, a quantum dot light-emitting material, and the like.
  • a cathode 140 is formed on the pixel definition layer 120 and the light-emitting layer 130 , and the material of the cathode 140 is filled in the groove 1202 .
  • the cathode material includes metals with lower power functions such as silver, lithium, magnesium, calcium, strontium, aluminum, and indium, or is made of metal compounds or alloy materials.
  • step S6 an encapsulation layer 150 is formed on the cathode 140, and the encapsulation layer 150 is used to prevent the display panel from being invaded by water and oxygen, thereby affecting the stability of the display panel.
  • a groove is formed on the pixel definition layer, and a cathode material is filled in the groove to increase the contact between the cathode and the pixel definition layer. area, the adhesion between the cathode and the pixel definition layer is increased, so that the light-emitting layer is not easy to fall off, thereby improving the stability of the display panel.
  • the filling layer in the groove, since the material of the filling layer and the cathode material have the same polarity, the adhesion between the cathode and the pixel definition layer is further increased.

Abstract

本发明提供一种显示面板及其制作方法,包括:薄膜晶体管阵列基板;阳极,阳极设置在薄膜晶体管阵列基板上;像素定义层,像素定义层设置在阳极上,像素定义层包括第一区域和第二区域,其中,第一区域设置有开口,第二区域设置有多个凹槽;发光层,发光层设置于开口内;阴极,阴极覆盖发光层和像素定义层;封装层,封装层覆盖阴极。

Description

一种显示面板及其制作方法 技术领域
本发明涉及显示技术领域,尤其涉及一种显示面板及其制作方法。
背景技术
有机发光二极管(Organic Light Emitting Diode,OLED)作为一种电流型发光器件,因其具有自发光、色彩丰富、响应速度快、视角广、重量轻以及可做成柔性显示屏等优点而受到广泛关注。
在有机发光二极管显示面板中,发光功能层常采用低温蒸镀技术,然而,该技术制作的发光器件有机膜层间的粘附力差,导致显示面板在弯折过程中发光功能层结构容易脱落,从而影响显示面板的稳定性。
故,有必要提出一种新的技术方案,以解决上述技术问题。
技术问题
本发明实施例提供一种显示面板及其制作方法,用于提高显示面板的稳定性。
技术解决方案
本发明实施例提供一种显示面板,包括:
薄膜晶体管阵列基板;
阳极,所述阳极设置在所述薄膜晶体管阵列基板上;
像素定义层,所述像素定义层设置在所述阳极和所述薄膜晶体管阵列基板上,所述像素定义层包括第一区域和第二区域,其中,所述第一区域设置有开口,所述开口的底部与所述阳极相连,所述第二区域设置有多个凹槽;
发光层,所述发光层设置于所述开口内;
阴极,所述阴极覆盖所述发光层和所述像素定义层;
封装层,所述封装层覆盖所述阴极。
在本发明实施例提供的显示面板中,所述凹槽是通过移印工艺形成的。
在本发明实施例提供的显示面板中,所述凹槽包括第一凹槽和至少一个第二凹槽,其中,所述第二凹槽的开口位于所述第一凹槽的侧壁和/或底部。
在本发明实施例提供的显示面板中,所述第一凹槽的开口大于所述第二凹槽的开口。
在本发明实施例提供的显示面板中,位于底部的所述第二凹槽垂直嵌设在所述像素定义层上,位于两侧的所述第二凹槽的嵌设角度与所述像素定义层的水平方向的夹角大于或等于0度,且小于90度。
在本发明实施例提供的显示面板中,所述凹槽的深度小于所述像素定义层的厚度。
在本发明实施例提供的显示面板中,所述凹槽的深度介于0.2微米至1.2微米之间。
在本发明实施例提供的显示面板中,所述显示面板还包括填充层,所述填充层覆盖所述凹槽的至少一部分。
在本发明实施例提供的显示面板中,所述填充层的材料包括无机材料。
在本发明实施例提供的显示面板中,所述无机材料包括氧化硅、氮化硅、碳化硅、氮氧化硅中或无机氧化物中的至少一种。
本发明实施例还提供一种显示面板的制作方法,包括:
步骤A:形成薄膜晶体管阵列基板;
步骤B:形成阳极,所述阳极设置在所述薄膜晶体管阵列基板上;
步骤C:形成像素定义层,所述像素定义层包括第一区域和第二区域,其中,所述第一区域设置有开口,所述第二区域设置有多个凹槽;
步骤D:形成发光层,所述发光层设置于所述开口内;
步骤E:形成阴极,所述阴极覆盖所述发光层和所述像素定义层;
步骤F:形成封装层,所述封装层覆盖所述阴极。
在本发明实施例提供的显示面板的制作方法中,所述步骤C包括:
步骤c1:形成像素定义材料层;
步骤c2:图案化所述第一区域,以形成所述开口;
步骤c3:利用移印工艺对所述第二区域进行处理,以形成所述凹槽,其中,所述凹槽包括第一凹槽和至少一个第二凹槽,所述第二凹槽的开口位于所述第一凹槽的侧壁和/或底部。
在本发明实施例提供的显示面板的制作方法中,所述第一凹槽的开口大于所述第二凹槽的开口。
在本发明实施例提供的显示面板的制作方法中,位于底部的所述第二凹槽垂直嵌设在所述像素定义层上,位于两侧的所述第二凹槽的嵌设角度与所述像素定义层的水平方向的夹角大于或等于0度,且小于90度。
在本发明实施例提供的显示面板的制作方法中,所述凹槽的深度小于所述像素定义层的厚度。
在本发明实施例提供的显示面板的制作方法中,所述凹槽的深度介于0.2微米至1.2微米之间。
在本发明实施例提供的显示面板的制作方法中,所述步骤C之后,还包括步骤G:
形成填充层,所述填充层覆盖所述凹槽的至少一部分。
在本发明实施例提供的显示面板的制作方法中,所述填充层的材料包括无机材料。
在本发明实施例提供的显示面板的制作方法中,所述无机材料包括氧化硅、氮化硅、碳化硅、氮氧化硅中或无机氧化物中的至少一种。
有益效果
在本发明实施例提供显示面板的制作方法中,所述填充层的材料包括无机材料。
相较于现有技术,在本发明实施例提供的显示面板及其制作方法中,在像素定义层上形成凹槽,在凹槽内填充阴极材料,加大阴极与像素定义层之间的接触面积,阴极与像素定义层之间的粘附力增加,使得发光层不易脱落,从而提高显示面板的稳定性。
另外,通过在凹槽内设置填充层,由于填充层的材料与阴极材料的极性相同,进一步增加了阴极与像素定义层的粘附力。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的显示面板的结构示意图;
图2为本发明实施例提供的显示面板的另一结构示意图;
图3为本发明实施例提供的显示面板的又一结构示意图;
图4为本发明实施例提供的显示面板中凹槽的结构示意图;
图5为本发明实施例提供的显示面板内部子像素的排布示意图;
图6为本发明实施例提供的显示面板的制作方法的流程图;
图7为本发明实施例提供的显示面板的制作方法中步骤S3的流程图。
本发明的实施方式
为了使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明作进一步地详细描述,请参照附图中的图式,其中相同的组件符号代表相同的组件,以下的说明是基于所示的本发明具体实施例,其不应被视为限制本发明未在此详述的其他具体实施例。本说明书所使用的词语“实施例”意指实例、示例或例证。此外,本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”,除非另外指定或从上下文可以清楚确定单数形式。
当某些组件,被描述为“在”另一组件“上”时,所述组件可以直接置于所述另一组件上;也可以存在一中间组件,所述组件置于所述中间组件上,且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时,二者可以理解为直接“安装”或“连接”,或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
请参考图1,本发明实施例提供一种显示面板,显示面板10包括薄膜晶体管阵列基板100、阳极110、像素定义层120、发光层130、阴极140和封装层150。其中,薄膜晶体管阵列基板100包括:基板、衬底层、有源层、第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极、层间绝缘层、源漏极、平坦化层(图中未示出)。
其中,衬底层包括双层聚酰亚胺膜层以及设置与聚酰亚胺膜层之间的缓冲层。需要说明的是,本发明实施例中的薄膜晶体阵列基板100的结构属于本领域的公知常识,本发明实施例中的薄膜晶体管还可以包括其他结构,在此不再赘述。
其中,阳极110的第一面与薄膜晶体管阵列基板100的第一面贴合设置,并且,阳极110的通过过孔与薄膜晶体管阵列基板100上的源极或漏极连接。阳极110的材料包括氧化铟锡材料(Indium Tin Oxide,ITO)。
像素定义层120设置在阳极110和薄膜晶体管阵列基板100上,像素定义层120包括第一区域120a和第二区域120b,第一区域120a位于第二区域120b的两侧。其中,第一区域120a设置有开口1201,开口1201的底部与阳极110的第一面相连,第二区域120b包括多个凹槽1202。一般的地,像素定义层120为有机材料层,例如,像素定义层120包括聚酰亚胺、聚酰胺、苯丙环丁烯、亚克力树脂、有机硅、聚甲基丙烯酸甲酯(PMMA)或酚醛树脂等有机材料中的至少一种。
发光层130设置于第一区域120a的开口1201内。其中,发光层130的材料包括荧光发光材料、量子点发光材料等。
阴极140覆盖发光层130和像素定义层120,其阴极140的材料填充凹槽1202;其中,阴极材料包括银、锂、镁、钙、锶、铝、铟等功率函数较低的金属,亦或为金属化合物或合金材料制成。
封装层150覆盖阴极140。封装层150用于防止显示面板受到水氧的侵入。
具体的,本发明实施例中的凹槽1202通过表面印压技术形成的。可选的,本发明实施例中的凹槽1202还可以通过移印技术形成,其中,移印技术包括PI移印技术。
可选的,请参考图2,图2为本发明实施例中显示面板100的另一结构示意图。其中,凹槽1202包括第一凹槽12021和至少一个第二凹槽12022,其中,第二凹槽12022的开口位于第一凹槽12021的侧壁和/或底部。具体的,在本发明提供的显示面板中,凹槽1202的通过表面移印工艺形成的。例如,设置有半圆形的印头压印至第二区域120b上,然后通过滚动印头的方式形成第一凹槽12021,接下来,在第一凹槽12021上进行二次压印,形成第二凹槽12022。也可以设置具有一特定形状的印头作为印头的主体部,主体部的侧面和底部设置多个耦合部,通过压印直接形成第一凹槽12021和第二凹槽12022。需要说明的是,在本发明实施例中,印头的形状可以通过实际需求进行调整,在此不做限定。
可选的,请参考图4,图4为本发明实施例中凹槽1202的又一结构示意图。凹槽1202的第二凹槽12022的数量不止一个,当第二凹槽12022的数量大于1时,第二凹槽12022的开口位于第一凹槽12021的侧壁及底部,且,第一凹槽12021的开口大于第二凹槽12022的开口。具体地,当第二凹槽12022的数量大于1时,第二凹槽12022嵌入像素定义层120中,第二凹槽12022的嵌入角度范围介于90度至180度之间。具体的,位于底部的第二凹槽12021垂直嵌设在像素定义层120上,位于两侧的第二凹槽12022的嵌设角度与像素定义层120的水平方向的夹角大于或等于0度,且小于90度。该设置方式可以进一步的增大阴极与像素定义层的接触面积,防止发光层脱离。
需要说明的是,在本发明实施例中,图中凹槽1202的个数以及形状仅为一种示例,并非对本发明的限定。
进一步的,凹槽1202的深度小于像素定义层的厚度,可选的,凹槽1202的深度介于0.2微米至1.2微米之间。例如,凹槽1202的深度为0.2微米、0.2微米、0.3微米、0.4微米、0.5微米、0.6微米、0.7微米、0.8微米、0.9微米、1.0微米、1.1微米、1.2微米中的任意一者。
在本发明实施例中,在像素定义层120的第二区域120b设置凹槽,加大阴极140与像素定义层120之间的接触面积,阴极140与像素定义层120之间的粘附力增加,使得有机发光层不易脱落,从而提高显示面板的稳定性。
可选的,请参考图3,图3为本发明实施例中显示面板10的又一结构示意图,显示面板10还包括填充层160,填充层160覆盖凹槽1202的至少一部分。其中,填充层160的材料包括无机材料。例如,在一些实施例中,所述无机材料包括氧化硅、氮化硅、碳化硅、氮氧化硅中或无机氧化物中的至少一种。容易理解的是,无机材料与金属或金属化合物的结合力更佳,相比现有设计中阴极140依靠其与像素定义层120之间的范德华力粘附,提高了阴极140的粘附性,从而有效避免在显示面板受到撞击或冲击时阴极140与发光层130发生分离,提高了显示面板的抗弯曲强度和承受跌落撞击强度。
请参考图5,在显示面板中,红色子像素R、蓝色子像素B和绿色子像素G采用RBGBR的方式排布,即红色子像素R和蓝色子像素B共用一个绿色子像素G,来达到高分别率的效果,这个排布方式被称之为diamond排布。在本发明实施例提供的显示面板中,由于底部电路大小的限制,子像素并非紧密排列,而是每个子像素之间存在一定的间隙,即图5中红色子像素R、蓝色子像素B和绿色子像素G之间的间隙。本发明实施例在间隙处设置多个凹槽1202,用于增大阴极和像素定义层之间的接触面积,从而增加阴极和像素定义层之间的黏附力,防止发光层脱落。
请结合图1和图6,本发明实施例还提供一种显示面板的制作方法,包括以下步骤:
步骤S1:形成薄膜晶体管阵列基板100;
步骤S2:形成阳极110,所述阳极110的第一面与所述薄膜晶体管阵列基板100的第一面贴合设置;
步骤S3:形成像素定义层120,所述像素定义层包括第一区域120a和第二区域120b,其中,所述第一区域120a包括开口1201,所述第二区域包括多个凹槽1202;
步骤S4:形成发光层130,所述发光层130设置于所述第一区域120a的所述开口1201内;
步骤S5:形成阴极140,所述阴极140覆盖所述发光层130和所述像素定义层120;
步骤S6:形成封装层150,所述封装层150覆盖所述阴极140。
具体的,在步骤S1中,薄膜晶体管阵列基板100包括:基板、衬底层、有源层、第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极、层间绝缘层、源漏极、平坦化层。
其中,衬底层包括双层聚酰亚胺膜层以及设置与聚酰亚胺膜层之间的缓冲层。需要说明的是,本发明实施例中的薄膜晶体阵列基板100的制作方法属于本领域的公知常识,本发明实施例中的薄膜晶体管阵列基板还可以包括其他结构,在此不再赘述。
在步骤S2中,首先,在薄膜晶体管阵列基板上形成阳极材料层,在阳极材料层上形成光刻胶膜层,图案化光刻胶膜层以及阳极材料层,以形成阳极110,其中,阳极110的材料包括氧化铟锡材料(Indium tin oxide,ITO)。阳极110的第一面与所述薄膜晶体管阵列基板100的第一面贴合设置,并且,阳极110通过过孔与薄膜晶体管阵列基板100上的源极或漏极连接。
请结合图2和图7,可选的,步骤S3包括:
步骤S31:形成像素定义材料层;
步骤32:通过构图工艺图案化所述第一区域120a,以形成所述开口1201;
步骤33:利用移印工艺对所述第二区域120b进行处理,以形成所述凹槽1202,其中,所述凹槽1202包括第一凹槽12021和至少一个第二凹槽12022,所述第二凹槽12022的开口位于所述第一凹槽12021的侧壁和/或底部。
具体的,在阳极110和薄膜晶体管阵列基板100上形成像素定义材料层,其中,像素定义材料层的材料包括聚酰亚胺、聚酰胺、苯丙环丁烯、亚克力树脂、有机硅、聚甲基丙烯酸甲酯或酚醛树脂等有机材料中的至少一种。然后,通过构图工艺对第一区域120a进行处理,形成开口1201,开口1201的底部连接阳极120的第一面。接下来,利用表面移印工艺对第二区域120b进行处理,具体的,设置特定形状的印头,例如,设置有半圆形的印头压印至第二区域120b上,通过滚动印头的方式形成第一凹槽12021,然后,在第一凹槽12021上进行二次压印,形成第二凹槽12022。也可以设置具有一特定形状的印头作为印头的主体部,主体部的侧面和底部设置多个耦合部,通过直接压印,形成第一凹槽12021和第二凹槽12022。当第二凹槽12022的数量大于1时,第二凹槽12022嵌入像素定义层120中,第二凹槽12022的嵌入角度范围介于90度至180度之间。需要说明的是,在本发明实施例中,印头的形状可以通过实际需求进行调整,在此不做限定。
需要说明的是,在本发明的显示面板的制作方法中,对步骤S32和步骤S33的顺序不做限定,可以先形成开口1201,再形成凹槽1202,或者先形成凹槽1202,再形成开口1201,或是同时形成开口1201和凹槽1202。
进一步的,凹槽1202的深度小于像素定义层的厚度,可选的,凹槽1202的深度介于0.2微米至1.2微米之间。
可选的,如图3所示,在本发明提供的显示面板的制作方法中,在形成凹槽1202之后,还包括,形成填充层160,填充层160覆盖凹槽1202的至少一部分。其中,填充层160的材料包括无机材料。所述无机材料包括氧化硅、氮化硅、碳化硅、氮氧化硅中或无机氧化物中的至少一种。容易理解的是,无机材料与金属或金属化合物的结合力更佳,相比现有设计中阴极140依靠其与像素定义层120之间的范德华力粘附,提高了阴极140的粘附性,从而有效避免在显示面板受到撞击或冲击时阴极140与发光层130发生分离,提高了显示面板的抗弯曲强度和承受跌落撞击强度。
在步骤S4中,在开口1201内形成发光层,其中,发光层的材料包括荧光发光材料、量子点发光材料等。
在步骤S5中,在像素定义层120和发光层130上形成阴极140,阴极140的材料填充在凹槽1202内。其中,阴极的材料包括银、锂、镁、钙、锶、铝、铟等功率函数较低的金属,亦或为金属化合物或合金材料制成。
在步骤S6中,在阴极140上形成封装层150,封装层150用于防止显示面板受到水氧的侵入,从而影响显示面板的稳定性。
相较于现有技术,在本发明实施例提供的显示面板及其制作方法中,在像素定义层上形成凹槽,在凹槽内填充阴极材料,加大阴极与像素定义层之间的接触面积,阴极与像素定义层之间的粘附力增加,使得发光层不易脱落,从而提高显示面板的稳定性。
另外,通过在凹槽内设置填充层,由于填充层的材料与阴极材料的极性相同,进一步增加了阴极与像素定义层的粘附力。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种显示面板,其中,包括:
    薄膜晶体管阵列基板;
    阳极,所述阳极设置在所述薄膜晶体管阵列基板上;
    像素定义层,所述像素定义层设置在所述阳极和所述薄膜晶体管阵列基板上,所述像素定义层包括第一区域和第二区域,其中,所述第一区域设置有开口,所述开口的底部与所述阳极相连,所述第二区域设置有多个凹槽;
    发光层,所述发光层设置于所述开口内;
    阴极,所述阴极覆盖所述发光层和所述像素定义层;
    封装层,所述封装层覆盖所述阴极。
  2. 根据权利要求1所述的显示面板,其中,所述凹槽是通过移印工艺形成的。
  3. 根据权利要求1所述的显示面板,其中,所述凹槽包括第一凹槽和至少一个第二凹槽,其中,所述第二凹槽的开口位于所述第一凹槽的侧壁和/或底部。
  4. 根据权利要求3所述的显示面板,其中,所述第一凹槽的开口大于所述第二凹槽的开口。
  5. 根据权利要求3所述的显示面板,其中,位于底部的所述第二凹槽垂直嵌设在所述像素定义层上,位于两侧的所述第二凹槽的嵌设角度与所述像素定义层的水平方向的夹角大于或等于0度,且小于90度。
  6. 根据权利要求1所述的显示面板,其中,所述凹槽的深度小于所述像素定义层的厚度。
  7. 根据权利要求6所述的显示面板,其中,所述凹槽的深度介于0.2微米至1.2微米之间。
  8. 根据权利要求1所述的显示面板,其中,所述显示面板还包括填充层,所述填充层覆盖所述凹槽的至少一部分。
  9. 根据权利要求8所述的显示面板,其中,所述填充层的材料包括无机材料。
  10. 根据权利要求9所述的显示面板,其中,所述无机材料包括氧化硅、氮化硅、碳化硅、氮氧化硅中或无机氧化物中的至少一种。
  11. 一种显示面板的制作方法,其中,包括:
    步骤A:形成薄膜晶体管阵列基板;
    步骤B:形成阳极,所述阳极设置在所述薄膜晶体管阵列基板上;
    步骤C:形成像素定义层,所述像素定义层包括第一区域和第二区域,其中,所述第一区域设置有开口,所述第二区域设置有多个凹槽;
    步骤D:形成发光层,所述发光层设置于所述开口内;
    步骤E:形成阴极,所述阴极覆盖所述发光层和所述像素定义层;
    步骤F:形成封装层,所述封装层覆盖所述阴极。
  12. 根据权利要求11所述的显示面板的制作方法,其中,所述步骤C包括:
    步骤c1:形成像素定义材料层;
    步骤c2:图案化所述第一区域,以形成所述开口;
    步骤c3:利用移印工艺对所述第二区域进行处理,以形成所述凹槽,其中,所述凹槽包括第一凹槽和至少一个第二凹槽,所述第二凹槽的开口位于所述第一凹槽的侧壁和/或底部。
  13. 根据权利要求12所述的显示面板的制作方法,其中,所述第一凹槽的开口大于所述第二凹槽的开口。
  14. 根据权利要求12所述的显示面板的制作方法,其中,位于底部的所述第二凹槽垂直嵌设在所述像素定义层上,位于两侧的所述第二凹槽的嵌设角度与所述像素定义层的水平方向的夹角大于或等于0度,且小于90度。
  15. 根据权利要求11所述的显示面板的制作方法,其中,所述凹槽的深度小于所述像素定义层的厚度。
  16. 根据权利要求15所述的显示面板的制作方法,其中,所述凹槽的深度介于0.2微米至1.2微米之间。
  17. 根据权利要求11所述的显示面板的制作方法,其中,所述步骤C之后,还包括步骤G:
    形成填充层,所述填充层覆盖所述凹槽的至少一部分。
  18. 根据权利要求17所述的显示面板的制作方法,其中,所述填充层的材料包括无机材料。
  19. 根据权利要求18所述的显示面板的制作方法,其中,所述无机材料包括氧化硅、氮化硅、碳化硅、氮氧化硅中或无机氧化物中的至少一种。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220088541A (ko) * 2020-12-18 2022-06-28 삼성디스플레이 주식회사 표시 장치

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160155784A1 (en) * 2014-12-02 2016-06-02 Samsung Display Co., Ltd. Method for fabricating display device and display device
CN108231856A (zh) * 2018-01-12 2018-06-29 京东方科技集团股份有限公司 像素界定层、显示面板及显示装置
CN108807496A (zh) * 2018-08-02 2018-11-13 云谷(固安)科技有限公司 有机电致发光显示面板及显示装置
CN109037287A (zh) * 2018-07-27 2018-12-18 京东方科技集团股份有限公司 子像素排列结构、掩膜装置、显示面板及显示装置
CN109103218A (zh) * 2018-08-03 2018-12-28 昆山国显光电有限公司 显示面板及其制作方法、显示装置
CN208622775U (zh) * 2018-08-03 2019-03-19 云谷(固安)科技有限公司 显示面板及显示装置
CN110416281A (zh) * 2019-08-26 2019-11-05 上海天马微电子有限公司 一种显示面板及显示装置
US20190348483A1 (en) * 2018-05-11 2019-11-14 Samsung Display Co., Ltd. Display device
CN111063715A (zh) * 2019-12-19 2020-04-24 武汉华星光电半导体显示技术有限公司 柔性显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102052432B1 (ko) * 2012-11-13 2019-12-05 엘지디스플레이 주식회사 유기전계발광소자 및 그 제조방법
KR102431626B1 (ko) * 2015-10-06 2022-08-11 삼성디스플레이 주식회사 발광 표시 장치 및 그 제조 방법
CN109065574B (zh) * 2018-07-24 2021-01-26 昆山国显光电有限公司 显示面板及显示装置
CN208622783U (zh) * 2018-08-10 2019-03-19 云谷(固安)科技有限公司 显示模组及显示屏
CN109148538A (zh) * 2018-08-27 2019-01-04 京东方科技集团股份有限公司 显示基板、显示装置及显示基板的制造方法
CN208753325U (zh) * 2018-09-28 2019-04-16 云谷(固安)科技有限公司 Oled显示面板及oled显示装置
CN109585673B (zh) * 2018-10-17 2021-05-18 云谷(固安)科技有限公司 显示面板及其制作方法、电子设备
CN110112195A (zh) * 2019-04-30 2019-08-09 武汉华星光电半导体显示技术有限公司 显示面板
KR20210028789A (ko) * 2019-09-04 2021-03-15 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160155784A1 (en) * 2014-12-02 2016-06-02 Samsung Display Co., Ltd. Method for fabricating display device and display device
CN108231856A (zh) * 2018-01-12 2018-06-29 京东方科技集团股份有限公司 像素界定层、显示面板及显示装置
US20190348483A1 (en) * 2018-05-11 2019-11-14 Samsung Display Co., Ltd. Display device
CN109037287A (zh) * 2018-07-27 2018-12-18 京东方科技集团股份有限公司 子像素排列结构、掩膜装置、显示面板及显示装置
CN108807496A (zh) * 2018-08-02 2018-11-13 云谷(固安)科技有限公司 有机电致发光显示面板及显示装置
CN109103218A (zh) * 2018-08-03 2018-12-28 昆山国显光电有限公司 显示面板及其制作方法、显示装置
CN208622775U (zh) * 2018-08-03 2019-03-19 云谷(固安)科技有限公司 显示面板及显示装置
CN110416281A (zh) * 2019-08-26 2019-11-05 上海天马微电子有限公司 一种显示面板及显示装置
CN111063715A (zh) * 2019-12-19 2020-04-24 武汉华星光电半导体显示技术有限公司 柔性显示面板

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