WO2022001425A1 - 发光基板及其制备方法、显示装置 - Google Patents

发光基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022001425A1
WO2022001425A1 PCT/CN2021/094144 CN2021094144W WO2022001425A1 WO 2022001425 A1 WO2022001425 A1 WO 2022001425A1 CN 2021094144 W CN2021094144 W CN 2021094144W WO 2022001425 A1 WO2022001425 A1 WO 2022001425A1
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Prior art keywords
pattern
conductive pattern
mask
light
conductive
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PCT/CN2021/094144
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English (en)
French (fr)
Inventor
谢晓冬
何敏
王静
张天宇
赵雪
钟腾飞
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2022001425A1 publication Critical patent/WO2022001425A1/zh
Priority to US17/793,975 priority Critical patent/US20230061318A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133612—Electrical details
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • Embodiments of the present disclosure relate to a light-emitting substrate, a method for manufacturing the same, and a display device.
  • At least one embodiment of the present disclosure provides a method for preparing a light-emitting substrate, the preparation method comprising: providing a base substrate; forming a first conductive pattern on the base substrate by using a first mask including a first mask pattern; A first insulating layer is formed on the first conductive pattern using a second mask including a second mask pattern to form a first via hole and a second via hole exposing a partial region of the first conductive pattern, wherein , the second mask pattern is different from the first mask pattern; a second conductive pattern is formed on the first insulating layer by using the first mask, wherein the second conductive pattern is perpendicular to the The direction of the base substrate at least partially overlaps with the first via hole and the second via hole, respectively, and is electrically connected to the first conductive pattern through the first via hole and the second via hole.
  • a third mask with three mask patterns forms a third conductive pattern on the second insulating layer, wherein the third conductive pattern is at least in contact with the third via in a direction perpendicular to the base substrate. A portion overlaps and is electrically connected to the second conductive pattern through the third via hole, the third mask pattern being different from the first mask pattern and the second mask pattern.
  • the orthographic projection of the first via on the base substrate and the orthographic projection of the third via on the base substrate The projections at least partially overlap, and the orthographic projection of the second via hole on the base substrate at least partially overlaps the orthographic projection of the fourth via hole on the base substrate.
  • the first mask pattern includes a first preparation pattern for forming a conductive pattern and a first positioning pattern for positioning
  • the second mask pattern includes a first preparation pattern for forming a conductive pattern and a first positioning pattern for positioning.
  • the mask pattern includes a second preparation pattern for forming an insulating pattern and a second positioning pattern for positioning; the preparation method further includes: forming the first mask on the base substrate by using the first mask At the same time as the conductive pattern, use the first positioning pattern of the first mask to form a first positioning structure; in the process of forming the first insulating layer on the first conductive pattern by using the second mask, use The first positioning structure cooperates with the second positioning pattern of the second mask to position the second mask, and at the same time of forming the first via hole and the second via hole, using the The second positioning pattern of the second mask forms a second positioning structure; in the process of using the first mask to form the second conductive pattern on the first insulating layer, the second positioning structure and the The first positioning pattern of the first mask is matched to position the first mask, and while the second conductive pattern is formed, a third positioning structure is formed by using the first positioning pattern of the first mask; and in the process of forming the second insulating layer on the second conductive pattern by using the second mask, using
  • the first positioning pattern includes a first sub-pattern and a second sub-pattern
  • the second positioning pattern includes a third sub-pattern and a fourth sub-pattern pattern
  • the first sub-pattern of the first positioning pattern is used to form the first positioning structure and the third positioning structure
  • the fourth sub-pattern of the second positioning pattern is used to form the second positioning structure
  • the second sub-pattern of the first positioning pattern corresponds to the fourth sub-pattern of the second positioning pattern for positioning the first mask plate
  • the third sub-pattern of the second positioning pattern corresponds to the The first sub-pattern of the first positioning pattern corresponds to the second mask plate.
  • forming the first conductive pattern on the base substrate by using the first mask includes: passing through the first mask forming the first conductive pattern on the base substrate with a first preparation pattern; using the first mask to form the second conductive pattern on the first insulating layer, including: passing through the first mask
  • the first preparation pattern of the template forms the second conductive pattern on the first insulating layer, wherein the first conductive pattern and the second conductive pattern include the same conductive pattern portion, and the same conductive pattern
  • the pattern portions at least partially overlap in a direction perpendicular to the base substrate.
  • forming the first insulating layer on the first conductive pattern by using the second mask includes: passing through the second mask forming the first insulating layer on the first conductive pattern by the second preparation pattern; forming the second insulating layer on the second conductive pattern by using the second mask, including: The second preparation pattern of the two masks forms a second insulating layer on the second conductive pattern, wherein the first insulating layer and the second insulating layer include the same via pattern portion, and the same The via pattern portions at least partially overlap in a direction perpendicular to the base substrate.
  • the method for preparing a light-emitting substrate further includes: forming a fourth conductive pattern on the third conductive pattern by using the third mask, wherein the fourth conductive pattern is formed on the third conductive pattern.
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the third conductive pattern on the base substrate.
  • the material of the third conductive pattern includes a first metal material
  • the material of the fourth conductive pattern includes a second metal material
  • the first The metallic material and the second metallic material are different.
  • the method for manufacturing a light-emitting substrate further includes: while using the third mask to form the third conductive pattern on the second insulating layer, using the third mask
  • the template forms a fifth conductive pattern different from the third conductive pattern on the second insulating layer, wherein the fifth conductive pattern, the first conductive pattern and the second conductive pattern are insulated from each other to emit light
  • the element is electrically connected to the output terminal of the driving circuit through the fifth conductive pattern.
  • the method for preparing a light-emitting substrate further includes: forming a fourth mask on the third conductive pattern and the fifth conductive pattern to at least partially cover the third conductive pattern and the third conductive pattern.
  • the third insulating layer of the fifth conductive pattern wherein the third insulating layer includes a first connection via for electrically connecting the fifth conductive pattern and the light-emitting element, the second insulating layer and /or the third insulating layer includes a second connection via hole for electrically connecting the light emitting element and the second conductive pattern.
  • the method for preparing a light-emitting substrate further includes: providing the light-emitting element on the third insulating layer, wherein the light-emitting element is connected to the first connection via the first connection via hole.
  • the five conductive patterns are electrically connected, and are electrically connected to the second conductive patterns through the second connection via holes.
  • the method before using the first mask to form the first conductive pattern on the base substrate, the method further includes: A buffer layer is formed on the base substrate, wherein the first conductive pattern is formed on the buffer layer.
  • At least one embodiment of the present disclosure further provides a light-emitting substrate, the light-emitting substrate includes: a base substrate and a first conductive pattern, a first insulating pattern and a first conductive pattern, a first insulating pattern, and a first conductive pattern, which are sequentially arranged on the base substrate in a direction away from the base substrate.
  • the insulating layer includes the same part of the via hole pattern; the via hole pattern of the first insulating layer includes a first via hole and a second via hole, and the second conductive pattern passes through the first via hole and the second via hole.
  • the hole is electrically connected to the first conductive pattern; the via pattern of the second insulating layer includes a third via hole and a fourth via hole, and the third conductive pattern is connected to the second via hole through the third via hole
  • the conductive patterns are electrically connected; the orthographic projection of the first via hole on the base substrate at least partially overlaps the orthographic projection of the third via hole on the base substrate, and the second via hole is in the The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the fourth via hole on the base substrate.
  • the first conductive pattern includes a plurality of first conductive blocks extending along a first direction
  • the second conductive pattern includes a plurality of first conductive blocks extending along the first direction
  • the third conductive pattern includes a plurality of third conductive blocks extending in a second direction different from the first direction; at least one of the plurality of second conductive blocks is perpendicular to the
  • the base substrate at least partially overlaps with at least one of the plurality of third conductive blocks in a direction, and is electrically connected to each other through the third via holes.
  • the orthographic projection of at least one of the plurality of first conductive blocks on the base substrate is the same as the orthographic projection of at least one of the plurality of second conductive blocks
  • the orthographic projections on the base substrate at least partially overlap, and at least one of the plurality of first conductive blocks passes through the first via hole and the second via hole with the plurality of second conductive blocks of at least one electrical connection.
  • At least one of the plurality of first conductive blocks and at least one of the plurality of second conductive blocks have the same direction in the second direction width.
  • the light-emitting substrate provided by at least one embodiment of the present disclosure further includes a fifth conductive pattern and a light-emitting element, the fifth conductive pattern and the third conductive pattern are disposed in the same layer, and the light-emitting element is located between the third conductive pattern and the third conductive pattern.
  • Five conductive patterns are on one side away from the base substrate, wherein the fifth conductive pattern, the first conductive pattern and the second conductive pattern are insulated from each other, and the light-emitting element is connected to the light-emitting element through the fifth conductive pattern.
  • the output end of the driving circuit is electrically connected, the fifth conductive pattern includes at least one fifth conductive block extending along the first direction, the first end of the light-emitting element is electrically connected to one fifth conductive block, and the light-emitting element is electrically connected to the one fifth conductive block.
  • the second end of the element is electrically connected to a second conductive block or another fifth conductive block.
  • the light-emitting substrate provided by at least one embodiment of the present disclosure further includes a third insulating layer, wherein the third insulating layer is located between the third and fifth conductive patterns and the light-emitting element, so
  • the third insulating layer includes a first connection via hole so that the at least one fifth conductive block is electrically connected to the first end and/or the second end of the light emitting element through the first connection via hole, and the first
  • the second insulating layer and the third insulating layer include second connection vias so that the one second conductive block is electrically connected to the second end of the light emitting element through the second connection vias.
  • At least one embodiment of the present disclosure further provides a display device including the light-emitting substrate described in any embodiment of the present disclosure.
  • the display device provided by at least one embodiment of the present disclosure further includes a display panel, wherein the display panel has a display side and a non-display side opposite to the display side, and the light-emitting substrate is disposed on a non-display side of the display panel.
  • the display side is used as a backlight unit.
  • FIG. 1 is a flowchart of a method for preparing a light-emitting substrate provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of a light-emitting substrate provided by some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of the arrangement of light-emitting units of the light-emitting substrate shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a light-emitting unit in the light-emitting substrate shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the pins of the driving circuit in the light-emitting unit of the light-emitting substrate shown in FIG. 2;
  • FIG. 6 is a schematic diagram of the arrangement of light-emitting elements and driving circuits in the light-emitting unit of the light-emitting substrate shown in FIG. 2;
  • FIG. 7 is a schematic plan view of a partial structure of a light-emitting substrate according to some embodiments of the present disclosure.
  • Fig. 8 is a schematic diagram of a partial cross-sectional structure of the light-emitting substrate along the line A-A' shown in Fig. 7;
  • Fig. 9 is a schematic diagram of a partial cross-sectional structure of the light-emitting substrate along the line B-B' shown in Fig. 7;
  • FIG. 10A is a schematic diagram of an example of a first positioning pattern of a first mask provided by some embodiments of the present disclosure
  • 10B is a schematic diagram of an example of a second positioning pattern of a second mask according to some embodiments of the present disclosure
  • 10C is a schematic diagram of an example in which positioning structures are nested with each other for positioning in some embodiments of the disclosure.
  • Figure 10D is a schematic diagram of a specific example of Figure 10C.
  • FIG. 11 is a schematic cross-sectional view of a display device according to some embodiments of the disclosure.
  • Mini Light Emitting Diode (Mini-LED) or Micro Light Emitting Diode (Micro-LED) are small in size and high in brightness, and can be widely used in display devices.
  • the backlight module the backlight is finely adjusted to realize the display of high dynamic range images (High-Dynamic Range, HDR).
  • a typical size (eg length) of a Micro-LED is less than 50 microns, eg, 10 to 50 microns; a typical size (eg, length) of a Mini-LED is 50 to 150 microns, eg, 80 to 120 microns.
  • the metal trace patterns used to transmit power signals for example, often need to have a relatively large thickness.
  • the film thickness of the metal trace pattern needs to be greater than 1.8 microns. Therefore, in order to avoid the risk of peeling off of the metal trace pattern with a large thickness, the metal trace pattern usually needs to be divided into multiple film layers to be prepared separately during the preparation process.
  • the inventors found that since multiple layers of the metal trace pattern need to be stacked and contacted with each other, for example, the upper layer pattern needs to cover the lower layer pattern, so the size of the upper layer pattern (for example, Line width) often needs to be larger (wider) than the size of the film layer pattern located below to ensure the contact effect between adjacent film layers, and at the same time to avoid the deposition and diffusion of the film layer material to the edge when preparing the film layer pattern above. It causes unevenness or excessive deposition of the prepared film layer, so as to ensure the precision and accuracy of the prepared film layer pattern.
  • the size of the upper layer pattern for example, Line width
  • the size of the film layer pattern located below to ensure the contact effect between adjacent film layers, and at the same time to avoid the deposition and diffusion of the film layer material to the edge when preparing the film layer pattern above. It causes unevenness or excessive deposition of the prepared film layer, so as to ensure the precision and accuracy of the prepared film layer pattern.
  • the above-mentioned multiple film layer patterns need to be formed by using different masks to perform patterning processes respectively, resulting in an increase in the number of masks required in the preparation process. , which in turn leads to an increase in the preparation cost of the product, and also increases the difficulty of product design and processing.
  • At least one embodiment of the present disclosure provides a method for preparing a light-emitting substrate, the preparation method comprising: providing a base substrate; forming a first conductive pattern on the base substrate by using a first mask including a first mask pattern; A second mask of the second mask pattern forms a first insulating layer on the first conductive pattern to form a first via hole and a second via hole exposing a partial area of the first conductive pattern, and the second mask pattern is different from a first mask pattern; using a first mask to form a second conductive pattern on the first insulating layer, the second conductive pattern respectively at least partially intersecting the first via hole and the second via hole in a direction perpendicular to the base substrate stacked and electrically connected to the first conductive pattern through the first via hole and the second via hole; a second insulating layer is formed on the second conductive pattern by using a second mask to form a third conductive pattern exposing a partial area of the second conductive pattern a via hole and a fourth via hole; and forming
  • the method for preparing a light-emitting substrate provided by at least one embodiment of the present disclosure can reduce the number of masks required in the preparation process, thereby optimizing the preparation process of the light-emitting substrate, reducing the preparation cost of the light-emitting substrate, and reducing the cost of preparing the light-emitting substrate.
  • the difficulty of design and processing in the process is conducive to mass production and application.
  • At least one embodiment of the present disclosure further provides a light-emitting substrate and a display device.
  • FIG. 1 is a flowchart of a method for fabricating a light-emitting substrate according to some embodiments of the present disclosure.
  • the preparation method of the light-emitting substrate includes the following steps.
  • Step S101 Provide a base substrate.
  • Step S102 forming a first conductive pattern on the base substrate by using a first mask including a first mask pattern.
  • Step S103 Using a second mask including a second mask pattern to form a first insulating layer on the first conductive pattern to form a first via hole and a second via hole exposing a partial region of the first conductive pattern, and the second The mask pattern is different from the first mask pattern.
  • Step S104 using a first mask to form a second conductive pattern on the first insulating layer, where the second conductive pattern at least partially overlaps the first via hole and the second via hole in a direction perpendicular to the base substrate and passes through the The first via hole and the second via hole are electrically connected with the first conductive pattern.
  • Step S105 using a second mask to form a second insulating layer on the second conductive pattern to form a third via hole and a fourth via hole exposing a partial region of the second conductive pattern.
  • Step S106 Using a third mask including a third mask pattern to form a third conductive pattern on the second insulating layer, the third conductive pattern at least partially overlaps the third via in a direction perpendicular to the base substrate and The second conductive pattern is electrically connected through the third via hole, and the third mask pattern is different from the first mask pattern and the second mask pattern.
  • the first conductive pattern and the second conductive pattern are formed using the same first mask, and the first insulating layer and the second insulating layer are formed by using the same second mask Therefore, the electrical connection between the first conductive pattern, the second conductive pattern and the third conductive pattern in the light-emitting substrate can be realized, and the number of masks required in the preparation process can be reduced, and the preparation of the light-emitting substrate can be optimized.
  • the process reduces the design and processing difficulty of the light-emitting substrate, thereby reducing the preparation cost of the light-emitting substrate.
  • the above-mentioned first conductive pattern and second conductive pattern may be different film layer patterns constituting the same trace in the light-emitting substrate, that is, the first conductive pattern and the second conductive pattern are sequentially arranged on the base substrate to form this line.
  • the same first mask to separately prepare different film layer patterns of the same trace
  • the layered preparation of the trace can be realized, so that the trace resistance can be reduced or avoided without substantially increasing the resistance of the trace.
  • the overall thickness of the line is large and the possible peeling phenomenon can reduce the number of masks required in the preparation process, which can not only improve the stability of the prepared light-emitting substrate, but also simplify the preparation process and reduce the cost of the light-emitting substrate. Design and processing difficulty, thereby reducing manufacturing costs.
  • the above-mentioned third conductive pattern can be used to form another trace that overlaps with the above-mentioned traces formed by the first conductive pattern and the second conductive pattern in a plane parallel to the base substrate, so as to form a grid-like trace Line pattern, thereby reducing the voltage drop when the signal is transmitted through the trace, and improving the consistency of the signal transmission effect.
  • the second mask pattern of the second mask plate include both a pattern for forming a first via hole and a second via hole for electrically connecting between the first conductive pattern and the second conductive pattern, and a pattern for forming an electrical connection between the first conductive pattern and the second conductive pattern
  • the patterns of the third via hole and the fourth via hole electrically connected between the second conductive pattern and the third conductive pattern can not only reduce the number of masks required in the preparation process, but also reduce the design and processing of the light-emitting substrate It is difficult to optimize the preparation process, thereby reducing the preparation cost of the light-emitting substrate.
  • the embodiments of the present disclosure do not limit the specific process methods for forming the first insulating layer and the second insulating layer.
  • the first insulating layer and the second insulating layer may adopt conventional methods such as coating, exposure, and development, respectively
  • the process formation reference may be made to conventional process methods for forming insulating layers in the art, and details are not described herein again.
  • the embodiments of the present disclosure do not limit the specific process methods for forming the first conductive pattern, the second conductive pattern, and the third conductive pattern.
  • the first conductive pattern, the second conductive pattern, and the third conductive pattern may be respectively forming a metal film layer, coating a photoresist layer on the metal film layer, exposing the photoresist layer with a mask, developing the exposed photoresist layer to obtain a photoresist pattern, using the photoresist pattern to The metal film layer is formed by etching, stripping the photoresist pattern and other process steps.
  • forming the via holes in the insulating layer can be performed by forming an insulating layer, coating a photoresist layer on the insulating layer, exposing the photoresist layer by using a mask, The exposed photoresist layer is developed to obtain a photoresist pattern, the insulating layer is etched by using the photoresist pattern, and the photoresist pattern is stripped.
  • the method of forming a metal film layer or forming an insulating layer, a method of coating a photoresist, an etching method (wet etching or dry etching), and a method of stripping the photoresist pattern can be specifically adopted.
  • the conventional process methods in the field will not be repeated here.
  • the metal film layer can be formed by a process method such as sputtering, electroplating or electroforming
  • the insulating layer can be formed by a method such as coating.
  • the embodiments of the present disclosure do not limit the material of the photoresist used, the type of the exposure light source, the material for preparing the mask, and the like.
  • the following describes the preparation method of the light-emitting substrate provided by the embodiment of the present disclosure by taking the preparation method provided by the embodiment of the present disclosure for preparing the light-emitting substrate 10 shown in FIG. 2 as an example. It should be noted that the embodiments of the present disclosure include but are not limited thereto.
  • FIG. 2 is a schematic diagram of a light-emitting substrate according to some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of an arrangement of light-emitting units of the light-emitting substrate shown in FIG. 2
  • the light-emitting substrate 10 includes a base substrate 11 and a plurality of light-emitting units 100 arranged in an array on the base substrate 11 .
  • the plurality of light-emitting units 100 are arranged in N rows and M columns, where N is an integer greater than 0, and M is an integer greater than 0.
  • the number of the light-emitting units 100 can be determined according to actual requirements, for example, according to the size of the light-emitting substrate 10 and the required brightness.
  • FIG. 2 only shows the light-emitting units 100 in 3 rows and 5 columns, it should be understood that the The number of units 100 is not limited to this.
  • the base substrate 11 may be a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, etc.
  • the base substrate 11 includes a single-layer or multi-layer circuit, which is not limited by the embodiments of the present disclosure.
  • each column of light-emitting units 100 is arranged along the first direction R1, and each row of the light-emitting units 100 is arranged along the second direction R2.
  • the first direction R1 is the column direction and the second direction R2 is the row direction.
  • the embodiments of the present disclosure are not limited thereto, and the first direction R1 and the second direction R2 may be any direction, as long as the first direction R1 and the second direction R2 intersect.
  • the plurality of light emitting units 100 are not limited to being arranged in a straight line, and may also be arranged in a curved line, a circular arrangement or an arbitrary manner, which may be determined according to actual needs, which is not limited by the embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of a light-emitting unit in the light-emitting substrate shown in FIG. 2
  • FIG. 5 is a schematic diagram of pins of a driving circuit in the light-emitting unit of the light-emitting substrate shown in FIG. 2
  • each light emitting unit 100 includes a driving circuit 160 , a plurality of light emitting elements 140 and a driving voltage terminal Vled.
  • the driving circuit 160 includes a first input terminal Di, a second input terminal Pwr, an output terminal OT and a common voltage terminal GND.
  • the first input terminal Di receives a first input signal, such as an address signal, for gating the drive circuit 160 of the corresponding address.
  • addresses of different driving circuits 160 may be the same or different.
  • the first input signal may be an 8-bit address signal, and the address to be transmitted may be obtained by parsing the address signal.
  • the second input terminal Pwr receives a second input signal, and the second input signal is, for example, a power line carrier communication signal.
  • the second input signal not only provides power to the driving circuit 160, but also transmits communication data to the driving circuit 160, and the communication data can be used to control the lighting duration of the corresponding lighting unit 100, thereby controlling its visual lighting brightness.
  • the output terminal OT can output different signals in different time periods, for example, output the relay signal and the driving signal respectively.
  • the relay signal is an address signal provided to other driving circuits 160 , that is, the first input terminal Di of the other driving circuits 160 receives the relay signal as the first input signal, so as to obtain the address signal.
  • the driving signal may be a driving current for driving the light-emitting element 140 to emit light.
  • the common voltage terminal GND receives a common voltage signal, such as a ground signal.
  • the driving circuit 160 is configured to output the relay signal through the output terminal OT within the first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr, and to output the relay signal within the second period through the output terminal OT.
  • the output terminal OT provides a driving signal to the plurality of light-emitting elements 140 connected in series.
  • the output terminal OT outputs a relay signal, and the relay signal is provided to the other driving circuits 160 so that the other driving circuits 160 obtain the address signal.
  • the output terminal OT outputs a driving signal, and the driving signal is provided to the plurality of light emitting elements 140 connected in series in sequence, so that the light emitting elements 140 emit light during the second period.
  • the first time period and the second time period are different time periods, and the first time period may be earlier than the second time period, for example.
  • the first time period can be continuously connected with the second time period, and the end time of the first time period is the start time of the second time period;
  • the other period can also be used only to separate the first period and the second period, so as to prevent the signals of the output terminal OT from interfering with each other in the first period and the second period.
  • the specific working principle of the driving circuit 160 reference may be made to conventional design solutions in the art, and details are not repeated here.
  • the driving signal when the driving signal is a driving current, the driving current can flow from the output terminal OT to the light-emitting element 140, or flow from the light-emitting element 140 to the output terminal OT, and the flow direction of the driving current can be determined according to the actual needs.
  • the embodiments of this are not limited.
  • "the output terminal OT outputs a driving signal” means that the output terminal OT provides a driving signal, and the direction of the driving signal can either flow out from the output terminal OT or flow into the output terminal OT.
  • a plurality of light emitting elements 140 are connected in series in sequence, and are connected in series between the driving voltage terminal Vled and the output terminal OT.
  • the light emitting element 140 may be a micro light emitting diode (Micro-LED) or a mini light emitting diode (Mini-LED).
  • each light-emitting element 140 includes a positive electrode (+) and a negative electrode (-) (or can also be referred to as an anode and a cathode), and the positive electrodes and negative electrodes of the plurality of light-emitting elements 140 are connected in series in sequence, so that the driving voltage terminals Vled and A current path is formed between the output terminals OT.
  • the driving voltage terminal Vled provides a driving signal to the light-emitting element 140 , for example, a high voltage in a period (second period) that needs to make the light-emitting element 140 emit light, and a low voltage in other periods. Therefore, in the second period, the driving signal (eg, driving current) flows from the driving voltage terminal Vled through the plurality of light emitting elements 140 in sequence, and then flows into the output terminal OT of the driving circuit 160 .
  • the plurality of light-emitting elements 140 emit light when the driving current flows. By controlling the duration of the driving current, the light-emitting duration of the light-emitting elements 140 can be controlled, thereby controlling the visual light-emitting brightness.
  • one light-emitting unit 100 includes 6 light-emitting elements 140 , and the 6 light-emitting elements 140 are arranged in 2 rows and 3 columns.
  • the six light-emitting elements 140 are sequentially numbered as (1,1), (1,2), (1,3), (2,1), and (2) in a manner from left to right and top to bottom. , 2) and (2, 3), the numbers are shown in Figure 4.
  • the light-emitting element 140 at the position (2, 1) is used as the starting point of the series, and (1, 1), (2, 2), (1, 2), (2) are sequentially connected.
  • the positive electrode of the light emitting element 140 at the position (2, 1) is connected to the driving voltage terminal Vled, and the negative electrode of the light emitting element 140 at the position (1, 3) is connected to the output terminal OT of the driving circuit 160 .
  • FIG. 6 is a schematic diagram of the arrangement of light-emitting elements and driving circuits in the light-emitting unit of the light-emitting substrate shown in FIG. 2 .
  • a plurality of (for example, six) light-emitting elements 140 are arranged in an array, for example, arranged in multiple rows and multiple columns, which can make the light emission more uniform.
  • the driving circuit 160 is located in the gap of the array formed by the plurality of light emitting elements 140 .
  • the number of light-emitting elements 140 in each light-emitting unit 100 is not limited, and may be any number such as 4, 5, 7, and 8, but not limited to 6. .
  • the plurality of light-emitting elements 140 can be arranged in any manner, for example, arranged in a desired pattern, and is not limited to a matrix arrangement.
  • the arrangement position of the driving circuit 160 is not limited, and can be arranged in any gap between the light-emitting elements 140, which can be determined according to actual requirements, which is not limited by the embodiments of the present disclosure.
  • the following embodiments of the present disclosure take the wiring layout in the partial region REG1 of the light emitting substrate 10 shown in FIG. 2 as an example to describe the wiring layout in the light emitting substrate.
  • FIG. 7 is a schematic plan view of a partial structure of a light-emitting substrate provided by some embodiments of the present disclosure.
  • FIG. 7 corresponds to the structure in the partial region REG1 of the light-emitting substrate 10 shown in FIG. 2 .
  • the light-emitting substrate 10 further includes a plurality of first driving voltage lines 301 and a plurality of first common voltage lines 401 extending along the first direction R1 , And also includes a plurality of second driving voltage lines 302 and a plurality of second common voltage lines 402 extending along the second direction R2.
  • the first driving voltage line 301 is electrically connected to the driving voltage terminal Vled of each light-emitting unit 100 , such as the positive electrode of the light-emitting element 140 at the position (2, 1), and is configured to transmit to each light-emitting unit 100 drive voltage.
  • the second driving voltage line 302 is electrically connected to the first driving voltage line 301 and forms a grid-like wiring, so as to reduce the transmission resistance as a whole, thereby improving the voltage consistency of each position in the light emitting substrate 10 .
  • the first common voltage line 401 is electrically connected to the common voltage terminal GND of the driving circuit 160 of each light emitting unit 100 , and is configured to transmit a common voltage (eg, ground voltage) to each light emitting unit 100 .
  • the first common voltage line 401 may pass through a structure located between the first common voltage line 401 and the driving circuit 160 in a direction perpendicular to the base substrate 11 (eg, a direction R3 shown in FIG. 8 later) or The via hole H5 of the film layer and the like is electrically connected to the common voltage terminal GND of the driving circuit 160 to provide a common voltage.
  • the second common voltage line 402 is electrically connected to the first common voltage line 401 and forms a grid-like wiring, so as to reduce the transmission resistance as a whole, thereby improving the voltage consistency of each position in the light emitting substrate 10 .
  • first driving voltage line 301 and the first common voltage line 401 are located in the same layer
  • second driving voltage line 302 and the second common voltage line 402 are located in the same layer.
  • the film layer where the first driving voltage line 301 in FIG. 7 is located is located under the light emitting element 140 , therefore, the first driving voltage line 301 can extend to the bottom of the positive electrode of the light emitting element 140 at the position (2, 1). , and is electrically connected to the positive electrode of the light-emitting element 140 at the position (2, 1) through the via hole, that is, the first driving voltage line 301 transmits the driving voltage to the light-emitting element 140 at the position (2, 1). Anode (ie, transmitted to the driving voltage terminal Vled). Although the negative electrode of the light emitting element 140 at the position (2, 1) in FIG.
  • the film layer where the first common voltage line 401 is located is located under the driving circuit 160 . Therefore, the first common voltage line 401 is located under the driving circuit 160 and is electrically connected to the common voltage terminal GND of the driving circuit 160 through a via hole.
  • the length and width of the first driving voltage line 301 , the second driving voltage line 302 , the first common voltage line 401 and the second common voltage line 402 can be set to any applicable values , the lengths may be the same or different, and the widths may also be the same or different, which may be determined according to actual requirements, which are not limited by the embodiments of the present disclosure.
  • the first conductive pattern and the second conductive pattern are used to form the first driving voltage line 301 and the first common voltage line 401, and the third conductive pattern is used to form the second driving voltage line 302 and the second common voltage line 402 as an example.
  • the preparation methods provided in the embodiments of the present disclosure will be described.
  • FIG. 8 is a schematic diagram of a partial cross-sectional structure of the light-emitting substrate 10 along the line AA' shown in FIG. 7
  • FIG. 9 is a partial cross-sectional structure of the light-emitting substrate 10 along the line BB' shown in FIG. 7 .
  • the manufacturing method of the light-emitting substrate 10 shown in FIG. 2 may include the following steps.
  • Step S201 providing the base substrate 11 .
  • Step S202 forming the first conductive pattern 110 on the base substrate 11 by using the first mask including the first mask pattern.
  • a whole layer of conductive material may be formed on the base substrate 11 by, for example, a sputtering process or an electroplating process, and then the conductive material layer may be patterned by a photolithography process using a first mask. to form the first conductive pattern 110; alternatively, in step S202, the first mask can also be directly attached to the base substrate 11, so as to form the first mask directly on the base substrate 11 by, for example, a sputtering process or an electroplating process.
  • a conductive pattern 110 is not limit the specific process method in step 202, and for details, reference may be made to conventional process design in the art, and details are not described herein. The following other steps in the preparation method provided by the embodiment of the present disclosure are basically the same or similar to this, and will not be repeated.
  • Step S203 using the second mask including the second mask pattern to form the first insulating layer 151 on the first conductive pattern 110 , so as to form the first via hole H1 and the second via hole exposing the partial region of the first conductive pattern 110 .
  • the hole H2, the second mask pattern is different from the first mask pattern.
  • Step S204 using the first mask to form the second conductive pattern 120 on the first insulating layer 151 .
  • the second conductive pattern 120 at least partially overlaps the first via hole H1 and the second via hole H2 in the direction R3 perpendicular to the base substrate 11 , respectively, and is connected to the first conductive pattern through the first via hole H1 and the second via hole H2 , respectively.
  • the patterns 110 are electrically connected.
  • the first conductive pattern 110 and the second conductive pattern 120 form a power supply wiring pattern including the first driving voltage line 301 and the first common voltage line 401, so that the same first mask can be used to achieve a double-film layer
  • the structure of the first driving voltage line 301 and the first common voltage line 401 is prepared, thereby increasing the thickness of the first driving voltage line 301 and the first common voltage line 401 to meet the resistance requirements.
  • the thicknesses of the first driving voltage lines 301 and the first common voltage lines 401 in the direction perpendicular to the base substrate 11 may be 1.2 to 2.4 microns, for example, 1.8 to 2 microns.
  • Step 205 using a second mask to form a second insulating layer 152 on the second conductive pattern 120 to form a third via hole H3 and a fourth via hole H4 exposing a partial region of the second conductive pattern 120 .
  • Step S206 forming a third conductive pattern 130 on the second insulating layer 152 by using a third mask including a third mask pattern.
  • the third conductive pattern 130 at least partially overlaps the third via hole H3 in the direction R3 perpendicular to the base substrate 11 and is electrically connected to the second conductive pattern 120 through the third via hole H3, and the third mask pattern is different from the first a mask pattern and a second mask pattern.
  • the third conductive pattern 130 constitutes a power supply wiring pattern including the second driving voltage line 302 and the second common voltage line 402 .
  • the thicknesses of the second driving voltage line 302 and the second common voltage line 402 in the direction perpendicular to the base substrate 11 may be 0.3 to 0.9 microns, for example, 0.6 to 0.8 microns.
  • the mold pattern includes not only a pattern for forming a first via hole H1 and a second via hole H2 for electrical connection between the first conductive pattern 110 and the second conductive pattern 120, but also a pattern for forming a connection between the second conductive pattern 120 and the second via hole H2.
  • the same first mask can be used to realize the preparation of multiple conductive film layer patterns in the first driving voltage line 301 and the first common voltage line 401 with a multi-film structure, and the same second mask can be used.
  • the electrical connection between the first driving voltage line 301 and the second driving voltage line 302 and the electrical connection between the first common voltage line 401 and the second common voltage line 402 are achieved, so that the above-described embodiments of the present disclosure reduce light emission
  • the number of masks required in the preparation process of the substrate reduces the difficulty of designing and processing the light-emitting substrate 10 , thereby reducing the manufacturing cost of the light-emitting substrate 10 .
  • the material of the first conductive pattern 110 may include molybdenum metal and its alloys, copper metal and its alloys, etc., or may also include other suitable metal conductive materials.
  • the first conductive pattern 110 may include copper metal and molybdenum metal.
  • the metal stack structure such as molybdenum-copper-molybdenum (Mo-Cu-Mo) three-layer structure.
  • the thickness of the first conductive pattern 110 in the direction perpendicular to the base substrate 11 may be 0.6 micrometers to 1.2 micrometers, for example, 0.9 micrometers to 1 micrometer.
  • the material of the second conductive pattern 120 may include molybdenum metal and its alloy, copper metal and its alloy, etc., or may also include other suitable metal conductive materials, for example, the second conductive pattern 120 may include copper metal and molybdenum metal.
  • the metal stack structure such as molybdenum-copper-molybdenum (Mo-Cu-Mo) three-layer structure.
  • the thickness of the second conductive pattern 120 in the direction perpendicular to the base substrate 11 may be 0.6 micrometers to 1.2 micrometers, for example, 0.9 micrometers to 1 micrometer.
  • the material of the third conductive pattern 130 may include molybdenum metal and its alloy, copper metal and its alloy, etc., or may also include other suitable metal conductive materials, for example, the third conductive pattern 130 may include copper metal and molybdenum metal.
  • metal stacks such as molybdenum-copper (Mo-Cu) double stacks.
  • the thickness of the third conductive pattern 130 in the direction perpendicular to the base substrate 11 may be 0.3 micrometers to 0.9 micrometers, for example, 0.6 micrometers to 0.8 micrometers.
  • the material of one or more of the first insulating layer 151 and the second insulating layer 152 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. Materials of the first insulating layer 151 and the second insulating layer 152 may be the same or different from each other, which is not limited by the embodiment of the present disclosure.
  • the orthographic projection of the first via hole H1 on the base substrate 11 and the orthographic projection of the third via hole H3 on the base substrate 11 at least partially overlap, for example, completely overlap ;
  • the orthographic projection of the second via hole H2 on the base substrate 11 and the orthographic projection of the fourth via hole H4 on the base substrate at least partially overlap, eg completely overlap. Therefore, the positioning between the first conductive layer 110 , the second conductive layer 120 and the third conductive layer 130 can be achieved, and the distance between the third conductive layer 130 and the first conductive layer 110 and the second conductive layer 120 can be improved.
  • the electrical connection effect is improved, thereby improving the stability of the light-emitting substrate 10 .
  • the first mask pattern of the first mask plate includes a first preparation pattern for forming conductive patterns (eg, the first conductive pattern 110 and the second conductive pattern 120 ) and a first preparation pattern for positioning a positioning pattern;
  • the second mask pattern of the second mask plate includes an insulating pattern for forming an insulating pattern (for example, the insulating pattern of the first insulating layer 151 including the first via hole H1 and the second via hole H2 and the insulating pattern of the second insulating layer 152 A second preparation pattern including an insulating pattern of the third via hole H3 and the fourth via hole H4) and a second positioning pattern for positioning.
  • the first preparation pattern can be used to form the first conductive pattern 110 and the second conductive pattern 120, that is, to form the first driving voltage line 301 and the first common voltage line 401;
  • the second preparation pattern can be used to form the first insulating layer 151 including the first via hole H1 and the second via hole H2, and to form the second insulating layer 152 including the third via hole H3 and the fourth via hole H4, so as to realize the first
  • the electrical connection between a conductive pattern 110 and the second conductive pattern 120 is realized, and the electrical connection between the third conductive pattern 130 and the second conductive pattern 120 is realized.
  • the preparation method of the light-emitting substrate 10 further includes: using the first mask to form the first conductive pattern 110 on the base substrate 11, and simultaneously using the first positioning pattern of the first mask to form the first positioning structure; using the second mask to form the first positioning structure; In the process of forming the first insulating layer 151 on the first conductive pattern 110 by the mask, the first positioning structure is used to cooperate with the second positioning pattern of the second mask to position the second mask, and the first via hole H1 is formed. At the same time as the second via hole H2, the second positioning structure is formed by using the second positioning pattern of the second mask; in the process of forming the second conductive pattern 120 on the first insulating layer 151 by using the first mask, the second positioning structure is formed using the second mask.
  • the positioning structure cooperates with the first positioning pattern of the first mask to position the first mask, and when the second conductive pattern 120 is formed, a third positioning structure is formed by using the first positioning pattern of the first mask; In the process of forming the second insulating layer 152 on the second conductive pattern 120 by the two masks, the third positioning structure is used to coordinate with the second positioning pattern of the second mask to position the second mask.
  • the first positioning structure, the second positioning structure and the third positioning structure can respectively realize the positioning of the first mask plate and the second mask plate in the above steps S201 to S206, so as to improve the prepared conductive pattern or insulating pattern.
  • the accuracy and precision on the base substrate 11 further improves the yield and stability of the prepared light-emitting substrate 10 .
  • the first positioning structure, the second positioning structure and the third positioning structure may be formed on the base substrate 11 without disposing, for example, the light emitting element 140, the driving circuit 160, the first driving voltage line 301, the second driving voltage line 302, the Areas of devices or structures such as a common voltage line 401 and a second common voltage line 402 , such as the peripheral region of the light-emitting substrate 10 , to avoid adverse effects on the preparation of devices or structures in the light-emitting substrate 10 .
  • the embodiments of the present disclosure do not limit the number of the first positioning structure, the second positioning structure and the third positioning structure.
  • the light-emitting substrate 10 is square, it can be The four corners respectively form one or more first positioning structures, one or more second positioning structures and one or more third positioning structures, thereby better realizing positioning.
  • the first positioning structure, the second positioning structure and the third positioning structure can be formed in the corner area of the polygonal (eg rectangular) light-emitting substrate 10 In REG2 and REG3, or can also be formed in other suitable regions that will not adversely affect the preparation of devices or structures in the light-emitting substrate 10, the embodiments of the present disclosure have an impact on the first positioning structure, the second positioning structure and the The specific position where the third positioning structure is formed is not limited.
  • FIG. 10A is a schematic diagram of an example of a first positioning pattern of a first mask provided by some embodiments of the present disclosure
  • FIG. 10B is an example of a second positioning pattern of a second mask provided by some embodiments of the present disclosure.
  • a schematic diagram, FIG. 10C is a schematic diagram of an example in which positioning structures are nested with each other for positioning in some embodiments of the disclosure
  • FIG. 10D is a schematic diagram of a specific example of FIG. 10C .
  • the first positioning pattern includes a first sub-pattern 191 and a second sub-pattern 192
  • the second positioning pattern includes a third sub-pattern 193 and a fourth sub-pattern 194
  • the first sub-pattern 191 of the first positioning pattern is used to form the first positioning structure and the third positioning structure
  • the fourth sub-pattern 194 of the second positioning pattern is used to form the second positioning structure.
  • the second sub-pattern 192 of the first positioning pattern corresponds to the fourth sub-pattern 194 of the second positioning pattern for positioning the first mask. For example, as shown in FIG.
  • the second positioning structure P2 formed by the fourth sub-pattern 194 can be nested in the second sub-pattern 192 to achieve positioning; similarly, the third sub-pattern 193 of the second positioning pattern is the same as the first sub-pattern 193
  • the first sub-pattern 191 of the positioning pattern corresponds to the second mask plate.
  • the first positioning structure and the third positioning structure formed by the first sub-pattern 191 can be nested in the third sub-pattern 193 to realize positioning.
  • the first sub-pattern 191 and the fourth sub-pattern 194 may be a "well" pattern, and the second sub-pattern 192 and the third sub-pattern 193 may be the same as the The diamond pattern matched with the "well" pattern.
  • the size of the first sub-pattern 191 and the fourth sub-pattern 194 may be the same.
  • the length L2 of a line segment in the “well”-shaped pattern may be 1000 microns to 1400 microns, further for example 1100 microns to 1200 microns, width L1 can be 30 microns to 60 microns, further for example 40 microns to 50 microns, width L5 can be 150 microns to 250 microns, further for example 180 microns to 200 microns;
  • the size of the second sub-pattern 192 and the third sub-pattern 193 may be the same. Taking the second sub-pattern 192 as an example, as shown in FIG. 10D , the length L4 of one side of the diamond pattern may be 400 ⁇ m ⁇ 700 ⁇ m, for example 500 to 600 microns, the width L3 may be 30 to 60 microns, for example, 40 to 50 microns.
  • first positioning pattern and the second positioning pattern shown in FIG. 10A and FIG. 10B above are only exemplary descriptions, and the embodiments of the present disclosure have no effect on the first sub-pattern and the second sub-pattern included in the first positioning pattern.
  • the specific structures of the pattern and the third sub-pattern and the fourth sub-pattern included in the second positioning pattern are not limited, as long as the first sub-pattern and the third sub-pattern can be used together to achieve positioning, and the second sub-pattern and the fourth sub-pattern can be used together to achieve positioning. Patterns can be used together to achieve positioning.
  • the embodiments of the present disclosure do not limit the specific sizes of the first positioning structure, the second positioning structure, and the third positioning structure formed, as long as the first mask plate and the second mask plate are formed on the base substrate 11
  • the positioning on the light emitting substrate 10 is sufficient without adversely affecting the preparation of devices or structures in the light emitting substrate 10 .
  • step S202 of the above-mentioned method for preparing the light-emitting substrate 10 specifically includes: forming the first conductive pattern 110 on the base substrate 11 by using the first preparation pattern of the first mask.
  • the step S204 of the method for preparing the light-emitting substrate 10 specifically includes: forming the second conductive pattern 120 on the first insulating layer 151 through the first preparation pattern of the first mask.
  • the first conductive pattern 110 and the second conductive pattern 120 include the same conductive pattern portion, and the same conductive pattern portion at least partially overlaps, eg completely overlaps, in the direction R3 perpendicular to the base substrate 11 .
  • the first conductive pattern 110 and the second conductive pattern 120 can jointly form the first driving voltage line 301 or the first common voltage line 401 having a multi-layer structure.
  • the step S203 of the above-mentioned method for preparing the light-emitting substrate 10 specifically includes: forming the first insulating layer 151 on the first conductive pattern 110 through the second preparation pattern of the second mask.
  • the step S205 of the method for preparing the light-emitting substrate 10 specifically includes: forming a second insulating layer 152 on the second conductive pattern 120 through the second preparation pattern of the second mask.
  • the first insulating layer 151 and the second insulating layer 152 include the same via pattern portions, and the same via pattern portions at least partially overlap, eg, completely overlap, in the direction R3 perpendicular to the base substrate 11 .
  • the third conductive pattern can also be improved 130 and the electrical connection effect between the first conductive pattern 110 and the second conductive pattern 120, thereby improving the stability of the electrical connection between the first driving voltage line 301 and the second driving voltage line 302, and the first common voltage line.
  • the manufacturing method of the light-emitting substrate 10 further includes: forming a fourth conductive pattern 170 on the third conductive pattern 130 by using a third mask plate , the orthographic projection of the fourth conductive pattern on the base substrate 11 and the orthographic projection of the third conductive pattern 130 on the base substrate 11 at least partially overlap, eg completely overlap.
  • the fourth conductive pattern 170 is formed to cover and protect the second driving voltage line 302 and the second common voltage
  • the protective layer on the surface of the line 402 away from the base substrate 11 can further reduce the interference of other devices or structures in the light-emitting substrate 10 to the signals on the second driving voltage line 302 and the second common voltage line 402,
  • the stability of signal transmission is improved, and at the same time, since the third conductive pattern 130 and the fourth conductive pattern 170 can be prepared by using the same third mask, the number of masks required in the preparation process can also be reduced, thereby further simplifying the light-emitting substrate
  • the design and processing difficulty of the light-emitting substrate 10 reduces the manufacturing cost of the light-emitting substrate 10 .
  • the material of the third conductive pattern 130 includes a first metal material
  • the material of the fourth conductive pattern 170 includes a second metal material
  • the first metal material and the second metal material are different.
  • the second metal material different from the first metal material can further improve the protection effect of the fourth conductive pattern 170 on the third conductive pattern 130 , thereby further improving the stability of the light emitting substrate 10 .
  • the first metal material may include molybdenum metal and its alloys, copper metal and its alloys, etc., or may also include other suitable metal conductive materials.
  • the third conductive pattern 130 may include a double stack formed of copper metal and molybdenum metal. layered metal structure.
  • the second metal material may include molybdenum metal and its alloys, copper metal and its alloys, nickel metal and its alloys, etc., or may also include other suitable metal conductive materials
  • the fourth conductive pattern 170 may include A single-layer metal structure formed of copper (CuNi).
  • the manufacturing method of the light-emitting substrate 10 further includes: forming a third conductive layer on the second insulating layer 152 by using a third mask.
  • a fifth conductive pattern 150 different from the third conductive pattern 130 is formed on the second insulating layer 152 by using a third mask.
  • the fifth conductive pattern 150 is insulated from the first conductive pattern 110 and the second conductive pattern 120 from each other, and the light emitting element 140 is electrically connected to the output terminal OT of the driving circuit 160 through the fifth conductive pattern 150 .
  • the fifth conductive pattern 150 can be used to form a plurality of connection traces 501 for realizing electrical connection between the plurality of light-emitting elements 140 and the output terminal OT of the driving circuit 160 .
  • the connection traces between the light-emitting units 100 are connected in series with each other and are electrically connected between the driving voltage terminal Vled and the output terminal OT.
  • the third conductive pattern 130 and the fifth conductive pattern 150 are formed on the second insulating layer 152 by using the third mask
  • the third mask may also be used on the second insulating layer 152
  • Other conductive patterns different from the third conductive pattern 130 and the fifth conductive pattern 150 are formed thereon, so as to form a light-emitting substrate located on the same layer as, for example, the second driving voltage line 302, the second common voltage line 402, and the connecting line 501.
  • Other connection traces in, for example, the connection traces shown in FIG. 4 and FIG. etc., the embodiments of the present disclosure are not limited thereto.
  • the manufacturing method of the light-emitting substrate 10 further includes: forming at least partially covering (eg, completely covering) the third conductive pattern 130 on the third conductive pattern 130 and the fifth conductive pattern 150 by using a fourth mask. and the third insulating layer 153 of the fifth conductive pattern 150 .
  • the third insulating layer 153 includes a first connection via hole H101 for electrically connecting the fifth conductive pattern 150 with the light emitting element 140 .
  • the first connection via hole H101 can be used to connect the light emitting element 140 at the position (2, 1).
  • the negative electrode of the light emitting element 140 is electrically connected to the connection wire 501, and further electrically connected to the positive electrode of the light-emitting element 140 at the position (1, 1) through the connection wire 501.
  • the second insulating layer 152 and/or the third insulating layer 153 includes a second connection via hole H102 for electrically connecting the light emitting element 140 and the second conductive pattern 120, for example, the second connection via hole H102 can be used to make the position (2 , 1)
  • the anode of the light-emitting element 140 is electrically connected to the first driving voltage line 301 to receive the driving voltage, so that the plurality of light-emitting elements 140 in the light-emitting unit 100 are connected in series with each other between the driving voltage terminal Vled and the output terminal OT between.
  • the material of the third insulating layer 153 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the first insulating layer 151 , the second insulating layer 152 and the third insulating layer 153 may be the same or different from each other, which is not limited by the embodiment of the present disclosure.
  • the preparation method of the light-emitting substrate 10 further includes: providing the light-emitting element 140 on the third insulating layer 153, the light-emitting element 140 being electrically connected to the fifth conductive pattern 150 through the first connection via hole H101, and The second conductive pattern 120 is electrically connected through the second connection via hole H102.
  • the negative electrode of the light emitting element 140 at the position (2, 1) is electrically connected to the connection trace 501 through the first connection via H101
  • the positive electrode of the light emitting element 140 at the position (2, 1) is electrically connected through the second connection via H102 It is electrically connected to the first driving voltage line 301 .
  • the preparation method of the light-emitting substrate 10 before using the first mask to form the first conductive pattern 110 on the base substrate 11 , the preparation method of the light-emitting substrate 10 further includes: The buffer layer 12 is formed on the base substrate 11 , and the first conductive pattern 110 is formed on the buffer layer 12 .
  • the buffer layer 12 can not only weaken or prevent harmful substances in the base substrate 11 from intruding into the interior of the light-emitting substrate 10 , but also increase the adhesion of the film layers in the light-emitting substrate 10 on the base substrate 11 .
  • the material of the buffer layer 12 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, which are not limited in the embodiments of the present disclosure.
  • the preparation method of the light-emitting substrate 10 may further include other conventional processes or steps such as cutting, die bonding, gluing, bonding, etc.
  • other conventional processes or steps such as cutting, die bonding, gluing, bonding, etc.
  • At least one embodiment of the present disclosure further provides a light-emitting substrate, the light-emitting substrate includes a base substrate and a first conductive pattern, a first insulating layer, and a second conductive pattern that are sequentially arranged on the base substrate in a direction away from the base substrate pattern, a second insulating layer and a third conductive pattern.
  • the first conductive pattern and the second conductive pattern include the same conductive pattern portion, the first insulating layer and the second insulating layer include the same via pattern portion; the via pattern of the first insulating layer includes the first via hole and the second via hole pattern.
  • the second conductive pattern is electrically connected to the first conductive pattern through the first via hole and the second via hole;
  • the via hole pattern of the second insulating layer includes a third via hole and a fourth via hole, and the third conductive pattern passes through the third via hole
  • the via hole is electrically connected to the second conductive pattern.
  • the first conductive pattern and the second conductive pattern include the same conductive pattern portion, and the first insulating layer and the second insulating layer include the same via pattern portion, the During the preparation process, the first conductive pattern and the second conductive pattern can be formed using the same mask, and the first insulating layer and the second insulating layer can be formed using the same mask, thereby reducing the number of masks required in the preparation process. It can optimize the preparation process of the light-emitting substrate, thereby reducing the preparation cost of the light-emitting substrate, and can also reduce the design and processing difficulty of the light-emitting substrate, which is conducive to mass production and application.
  • the light-emitting substrate provided by at least one embodiment of the present disclosure may be the light-emitting substrate 10 provided in the above-mentioned embodiment of the method for preparing a light-emitting substrate.
  • the light-emitting substrate 10 provided in the above-mentioned embodiment of the method for preparing a light-emitting substrate.
  • the first conductive pattern 110 includes a plurality of first conductive blocks extending along the first direction R1
  • the second conductive pattern 120 includes a plurality of first conductive blocks extending along the first direction R1
  • a plurality of second conductive blocks such as a plurality of first conductive blocks and a plurality of second conductive blocks, may be used to form a plurality of first driving voltage lines 301 and first common voltage lines 401 extending along the first direction R1.
  • the third conductive pattern 130 includes a plurality of third conductive blocks extending in a second direction R2 different from the first direction R1, for example, the plurality of third conductive blocks may be respectively used to form a plurality of second conductive blocks extending in the second direction R2
  • the driving voltage line 302 and the second common voltage line 402 are driven. At least one of the plurality of second conductive blocks at least partially overlaps with at least one of the plurality of third conductive blocks in a direction R3 perpendicular to the base substrate 11 , and is electrically connected to each other through third via holes H3 .
  • a plurality of first driving voltage lines 301 and a plurality of second driving voltage lines 302 overlap each other in a direction R3 perpendicular to the base substrate 11 to form a mesh structure
  • a plurality of first common voltage lines 401 and a plurality of The second common voltage lines 402 overlap each other in the direction R3 perpendicular to the base substrate 11 to form a mesh structure, thereby reducing the transfer resistance as a whole and improving the voltage consistency at various positions in the light emitting substrate 10 .
  • the orthographic projection of at least one of the plurality of first conductive blocks on the base substrate 11 and the orthographic projection of at least one of the plurality of second conductive blocks on the base substrate at least partially overlap, for example, completely overlap, and at least one of the plurality of first conductive blocks is electrically connected to at least one of the plurality of second conductive blocks through the first via hole H1 and the second via hole H2, thereby A plurality of first driving voltage lines 301 and a plurality of first common voltage lines 401 having a double-film structure are formed.
  • At least one of the plurality of first conductive blocks and at least one of the plurality of second conductive blocks have the same width in the second direction R2, thereby
  • the layout design of the wiring in the light emitting substrate 10 is optimized.
  • the light-emitting substrate 10 further includes a fifth conductive pattern 150 and a light-emitting element 140 .
  • the fifth conductive pattern 150 and the third conductive pattern 130 are disposed in the same layer, and the light emitting element 140 is located on the side of the third conductive pattern 130 and the fifth conductive pattern 150 away from the base substrate 11.
  • the fifth conductive pattern 150 is insulated from the first conductive pattern 110 and the second conductive pattern 120.
  • the light emitting element 140 is electrically connected to the output terminal OT of the driving circuit 160 through the fifth conductive pattern 150.
  • At least one fifth conductive block extending from R1 the first end of the light-emitting element 140 (eg, the positive or negative electrode of the light-emitting element) is electrically connected to a fifth conductive block, and the second end of the light-emitting element 140 (for example, the negative electrode or the positive electrode of the light-emitting element) ) is electrically connected to one second conductive block or another fifth conductive block.
  • the first end of the light-emitting element 140 eg, the positive or negative electrode of the light-emitting element
  • the second end of the light-emitting element 140 for example, the negative electrode or the positive electrode of the light-emitting element
  • the fifth conductive pattern 150 may include a plurality of fifth conductive blocks, and the plurality of fifth conductive blocks are used to form a plurality of connection wires 501 .
  • the plurality of connection wires 501 may include a connection wire connecting the negative electrode of the light-emitting element 140 at the position (1, 3) in the light-emitting unit 100 and the output terminal OT of the driving circuit 160, and connecting one of the light-emitting units 100 to emit light A connection trace between the negative electrode or positive electrode of the element 140 and the positive electrode or negative electrode of another light-emitting element 140, so that the plurality of light-emitting elements 140 in the light-emitting unit 100 are connected in series with each other and are electrically connected to the driving voltage terminal Vled and the output between terminals OT.
  • the light emitting substrate 10 further includes a third insulating layer 153 located between the third conductive patterns 130 and the fifth conductive patterns 150 and the light emitting element 140 , the third insulating layer 153 includes a first connection via hole H101 so that at least one fifth conductive block is electrically connected to the first end and/or the second end of the light emitting element 140 through the first connection via hole H101, and the second insulating layer 152 And the third insulating layer 153 includes a second connection via hole H102 so that a second conductive block is electrically connected to the second end of the light emitting element 140 through the second connection via hole H102.
  • the first connection via hole H101 can be used to electrically connect the negative electrode of the light emitting element 140 at the position (2, 1) to a connection wire 501, and then the connection wire 501 is connected to the position (1, 1) through the connection wire 501.
  • the positive electrode of the light-emitting element 140 is electrically connected
  • the second connection via hole H102 can be used to electrically connect the positive electrode of the light-emitting element 140 at the position (2, 1) with the first driving voltage line 301 to receive the driving voltage, thereby enabling light emission
  • the plurality of light emitting elements 140 in the unit 100 are connected in series with each other between the driving voltage terminal Vled and the output terminal OT.
  • the light-emitting substrate provided by the embodiments of the present disclosure may further include more components and structures, etc., which may be determined according to actual requirements, which are not limited by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device including a display panel and the light-emitting substrate provided in any embodiment of the present disclosure.
  • the display device provided by the embodiment of the present disclosure may be a liquid crystal display device.
  • the display device provided by the embodiments of the present disclosure may also be an organic light-emitting diode display device, a quantum dot light-emitting diode display device, an electronic paper display device, or other devices with a display function or other types of display devices. No restrictions apply.
  • the display device can realize sub-region independent control of luminous brightness, and has the advantages of low power consumption, high integration, simple control method, etc., and can cooperate with, for example, a liquid crystal display device to realize high-contrast display.
  • the light-emitting substrate provided by the embodiments of the present disclosure can be applied to the above-mentioned display device as a backlight unit, or can be used alone as a substrate with a display function or a light-emitting function, which is not limited by the embodiments of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view of a display device according to some embodiments of the disclosure.
  • the display device 70 includes a display panel 710 and a light-emitting substrate 720 .
  • the light-emitting substrate 720 may be the light-emitting substrate provided in any embodiment of the present disclosure, such as the aforementioned light-emitting substrate 10 .
  • the display panel 710 has a display side P1 and a non-display side P2 opposite to the display side P1, and the light emitting substrate 720 is disposed on the non-display side P2 of the display panel 710 as a backlight unit.
  • the light emitting substrate 720 may provide backlight to the display panel 710 as a surface light source.
  • the display panel 710 may be an LCD panel, an electronic paper display panel, or the like, which is not limited by the embodiments of the present disclosure.
  • the display device 70 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an e-book, etc., which is not limited by the embodiments of the present disclosure.
  • the display device may further include more components and structures, which may be determined according to actual requirements, which are not limited by the embodiments of the present disclosure.

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Abstract

一种发光基板及其制备方法、显示装置，该制备方法包括：提供衬底基板（11）；利用第一掩模板在衬底基板（11）上形成第一导电图案（110）；利用第二掩模板在第一导电图案（110）上形成第一绝缘层（151）以及第一过孔（H1）和第二过孔（H2）；利用第一掩模板在第一绝缘层（151）上形成第二导电图案（120），第二导电图案（120）通过第一过孔（H1）和第二过孔（H2）与第一导电图案（110）电连接；利用第二掩模板在第二导电图案（120）上形成第二绝缘层（152）以及第三过孔（H3）和第四过孔（H4）；利用第三掩模板在第二绝缘层（152）上形成第三导电图案（130），第三导电图案（130）通过第三过孔（H3）与第二导电图案（120）电连接。

Description

发光基板及其制备方法、显示装置
本申请要求于2020年6月30日递交的中国专利申请第202010621948.4号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种发光基板及其制备方法、显示装置。
背景技术
随着发光二极管技术的发展，采用亚毫米量级甚至微米量级的发光二极管的背光源得到了广泛的应用。由此，不仅可以使利用该背光源的例如透射式显示产品的画面对比度达到有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品的水平，还可以使产品保留液晶显示(Liquid Crystal Display，LCD)的技术优势，进而提升画面的显示效果，为用户提供更优质的视觉体验。
发明内容
本公开至少一个实施例提供一种发光基板的制备方法，该制备方法包括：提供衬底基板；利用包括第一掩模图案的第一掩模板在所述衬底基板上形成第一导电图案；利用包括第二掩模图案的第二掩模板在所述第一导电图案上形成第一绝缘层，以形成暴露所述第一导电图案的部分区域的第一过孔和第二过孔，其中，所述第二掩模图案不同于所述第一掩模图案；利用所述第一掩模板在所述第一绝缘层上形成第二导电图案，其中，所述第二导电图案在垂直于所述衬底基板的方向上分别与所述第一过孔和所述第二过孔至少部分交叠且通过所述第一过孔和所述第二过孔与所述第一导电图案电连接；利用所述第二掩模板在所述第二导电图案上形成第二绝缘层，以形成暴露所述第二导电图案的部分区域的第三过孔和第四过孔；以及利用包括第三掩模图案的第三掩模板在所述第二绝缘层上形成第三导电图案，其中，所述第三导电图案在垂直于所述衬底基板的方向上与所述第三过孔至少部分交叠且通过所述第三过孔与所述第二导电图案电连接，所述第三掩模图案不同于所述第一掩模图案和所述第二掩模图案。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，所述第一过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影至少部分重叠，所述第二过孔在所述衬底基板上的正投影与所述第四过孔在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，所述第一掩模图案包括用于形成导电图案的第一制备图案和用于定位的第一定位图案，所述第二掩模图案包括用于形成绝缘图案的第二制备图案和用于定位的第二定位图案；所述制备方法还包 括：利用所述第一掩模板在所述衬底基板上形成所述第一导电图案的同时，利用所述第一掩模板的第一定位图案形成第一定位结构；利用所述第二掩模板在所述第一导电图案上形成所述第一绝缘层的过程中，使用所述第一定位结构与所述第二掩模板的第二定位图案配合以定位所述第二掩模板，并且在形成所述第一过孔和所述第二过孔的同时，利用所述第二掩模板的第二定位图案形成第二定位结构；利用所述第一掩模板在所述第一绝缘层上形成所述第二导电图案的过程中，使用所述第二定位结构与所述第一掩模板的第一定位图案配合以定位所述第一掩模板，并且在形成所述第二导电图案的同时，利用所述第一掩模板的第一定位图案形成第三定位结构；以及利用所述第二掩模板在所述第二导电图案上形成所述第二绝缘层的过程中，使用所述第三定位结构与所述第二掩模板的第二定位图案配合以定位所述第二掩模板。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，所述第一定位图案包括第一子图案和第二子图案，所述第二定位图案包括第三子图案和第四子图案；所述第一定位图案的第一子图案用于形成所述第一定位结构和所述第三定位结构，所述第二定位图案的第四子图案用于形成所述第二定位结构；所述第一定位图案的第二子图案与所述第二定位图案的第四子图案对应以用于定位所述第一掩模板，所述第二定位图案的第三子图案与所述第一定位图案的第一子图案对应以用于定位所述第二掩模板。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，利用所述第一掩模板在所述衬底基板上形成所述第一导电图案，包括：通过所述第一掩模板的第一制备图案在所述衬底基板上形成所述第一导电图案；利用所述第一掩模板在所述第一绝缘层上形成所述第二导电图案，包括：通过所述第一掩模板的第一制备图案在所述第一绝缘层上形成所述第二导电图案，其中，所述第一导电图案和所述第二导电图案包括相同的导电图案部分，且所述相同的导电图案部分在垂直于所述衬底基板的方向上至少部分重叠。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，利用所述第二掩模板在所述第一导电图案上形成所述第一绝缘层，包括：通过所述第二掩模板的第二制备图案在所述第一导电图案上形成所述第一绝缘层；利用所述第二掩模板在所述第二导电图案上形成所述第二绝缘层，包括：通过所述第二掩模板的第二制备图案在所述第二导电图案上形成第二绝缘层，其中，所述第一绝缘层和所述第二绝缘层包括相同的过孔图案部分，且所述相同的过孔图案部分在垂直于所述衬底基板的方向上至少部分重叠。
例如，本公开至少一个实施例提供的发光基板的制备方法还包括：利用所述第三掩模板在所述第三导电图案上形成第四导电图案，其中，所述第四导电图案在所述衬底基板上的正投影与所述第三导电图案在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，所述第三导电图案的材料包括第一金属材料，所述第四导电图案的材料包括第二金属材料，所述第一金属材料和所述第二金属材料不同。
例如，本公开至少一个实施例提供的发光基板的制备方法还包括：在利用所述第三掩模板在所述第二绝缘层上形成所述第三导电图案的同时，利用所述第三掩模板在所述 第二绝缘层上形成不同于所述第三导电图案的第五导电图案，其中，所述第五导电图案与所述第一导电图案和所述第二导电图案彼此绝缘，发光元件通过所述第五导电图案与驱动电路的输出端电连接。
例如，本公开至少一个实施例提供的发光基板的制备方法还包括：利用第四掩模板在所述第三导电图案和所述第五导电图案上形成至少部分覆盖所述第三导电图案和所述第五导电图案的第三绝缘层，其中，所述第三绝缘层包括用于使所述第五导电图案与所述发光元件电连接的第一连接过孔，所述第二绝缘层和/或所述第三绝缘层包括用于使所述发光元件与所述第二导电图案电连接的第二连接过孔。
例如，本公开至少一个实施例提供的发光基板的制备方法还包括：在所述第三绝缘层上提供所述发光元件，其中，所述发光元件通过所述第一连接过孔与所述第五导电图案电连接，且通过所述第二连接过孔与所述第二导电图案电连接。
例如，在本公开至少一个实施例提供的发光基板的制备方法中，在利用所述第一掩模板在所述衬底基板上形成所述第一导电图案之前，所述制备方法还包括：在所述衬底基板上形成缓冲层，其中，所述第一导电图案形成在所述缓冲层上。
本公开至少一个实施例还提供一种发光基板，该发光基板包括：衬底基板以及在所述衬底基板上在远离所述衬底基板的方向上依次设置的第一导电图案、第一绝缘层、第二导电图案、第二绝缘层和第三导电图案；其中，所述第一导电图案和所述第二导电图案包括相同的导电图案部分，所述第一绝缘层和所述第二绝缘层包括相同的过孔图案部分；所述第一绝缘层的过孔图案包括第一过孔和第二过孔，所述第二导电图案通过所述第一过孔和所述第二过孔与所述第一导电图案电连接；所述第二绝缘层的过孔图案包括第三过孔和第四过孔，所述第三导电图案通过所述第三过孔与所述第二导电图案电连接；所述第一过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影至少部分重叠，所述第二过孔在所述衬底基板上的正投影与所述第四过孔在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一个实施例提供的发光基板中，所述第一导电图案包括沿第一方向延伸的多个第一导电块，所述第二导电图案包括沿所述第一方向延伸的多个第二导电块，所述第三导电图案包括沿不同于所述第一方向的第二方向延伸的多个第三导电块；所述多个第二导电块中的至少一个在垂直于所述衬底基板的方向上与所述多个第三导电块中的至少一个至少部分交叠，且通过所述第三过孔彼此电连接。
例如，在本公开至少一个实施例提供的发光基板中，所述多个第一导电块中的至少一个在所述衬底基板上的正投影与所述多个第二导电块中的至少一个在所述衬底基板上的正投影至少部分重叠，所述多个第一导电块中的至少一个通过所述第一过孔和所述第二过孔与所述多个第二导电块中的至少一个电连接。
例如，在本公开至少一个实施例提供的发光基板中，所述多个第一导电块中的至少一个和所述多个第二导电块中的至少一个在所述第二方向上具有相同的宽度。
例如，本公开至少一个实施例提供的发光基板还包括第五导电图案和发光元件，第 五导电图案与所述第三导电图案同层设置，发光元件位于所述第三导电图案和所述第五导电图案远离所述衬底基板的一侧，其中，所述第五导电图案与所述第一导电图案和所述第二导电图案彼此绝缘，所述发光元件通过所述第五导电图案与驱动电路的输出端电连接，所述第五导电图案包括沿所述第一方向延伸的至少一个第五导电块，所述发光元件的第一端与一个第五导电块电连接，所述发光元件的第二端与一个第二导电块或另一个第五导电块电连接。
例如，本公开至少一个实施例提供的发光基板还包括第三绝缘层，其中，所述第三绝缘层位于所述第三导电图案和所述第五导电图案与所述发光元件之间，所述第三绝缘层包括第一连接过孔以使所述至少一个第五导电块通过所述第一连接过孔与所述发光元件的第一端和/或第二端电连接，所述第二绝缘层和所述第三绝缘层包括第二连接过孔以使所述一个第二导电块通过所述第二连接过孔与所述发光元件的第二端电连接。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的发光基板。
例如，本公开至少一个实施例提供的显示装置还包括显示面板，其中，所述显示面板具有显示侧和与所述显示侧相对的非显示侧，所述发光基板设置在所述显示面板的非显示侧以作为背光单元。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种发光基板的制备方法的流程图；
图2为本公开一些实施例提供的一种发光基板的示意图；
图3为图2所示的发光基板的发光单元的排列示意图；
图4为图2所示的发光基板中一个发光单元的示意图；
图5为图2所示的发光基板的发光单元中的驱动电路的引脚示意图；
图6为图2所示的发光基板的发光单元中发光元件和驱动电路的排列示意图；
图7为本公开一些实施例提供的一种发光基板的部分结构的平面示意图；
图8为沿图7中所示的A-A’线的发光基板的部分截面结构的示意图；
图9为沿图7中所示的B-B’线的发光基板的部分截面结构的示意图；
图10A为本公开一些实施例提供的一种第一掩模板的第一定位图案的示例的示意图；
图10B为本公开一些实施例提供的一种第二掩模板的第二定位图案的示例的示意图；
图10C为本公开一些实施例中定位结构彼此嵌套以进行定位的示例的示意图；
图10D为图10C的一个具体示例的示意图；以及
图11为本公开一些实施例提供的一种显示装置的剖面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在采用发光二极管的显示产品中，迷你发光二极管(Mini Light Emitting Diode，Mini-LED)或微型发光二极管(Micro Light Emitting Diode，Micro-LED)的尺寸小且亮度高，可以大量应用于显示装置的背光模组中，并对背光进行精细调节，从而实现高动态范围图像(High-Dynamic Range，HDR)的显示。例如，Micro-LED的典型尺寸(例如长度)小于50微米，例如10微米～50微米；Mini-LED的典型尺寸(例如长度)为50微米～150微米，例如80微米～120微米。
在制备采用发光二极管的显示产品的过程中，由于发光二极管的芯片对于金属走线的阻值需求，用于传输例如电源信号的金属走线图案往往需要具有较大的厚度，例如在制备时，该金属走线图案的膜层厚度需要大于1.8微米。因此，为了避免厚度较大的金属走线图案可能发生剥落的风险，在制备过程中该金属走线图案通常需要分为多个膜层分别进行制备。
发明人发现，由于金属走线图案的多个膜层之间需要依次叠加且彼此接触，例如位于上方的膜层图案需要覆盖位于下方的膜层图案，因而位于上方的膜层图案的大小(例如线宽)往往需要大于(宽于)位于下方的膜层图案的大小，以保证相邻膜层之间的接触效果，同时避免制备上方的膜层图案时，由于膜层材料向边缘沉积扩散而导致制备的膜层出现不平整或过度沉积现象，从而保证制备的膜层图案的精度和准确性。而由于金属走线图案的多个膜层图案之间往往存在差异，因此上述多个膜层图案需要采用不同的掩模板分别执行构图工艺形成，从而导致制备过程中所需要的掩模板的数量增加，进而导致产品的制备成本增加，并且还提高了产品的设计和加工难度。
本公开至少一个实施例提供一种发光基板的制备方法，该制备方法包括：提供衬底 基板；利用包括第一掩模图案的第一掩模板在衬底基板上形成第一导电图案；利用包括第二掩模图案的第二掩模板在第一导电图案上形成第一绝缘层，以形成暴露第一导电图案的部分区域的第一过孔和第二过孔，第二掩模图案不同于第一掩模图案；利用第一掩模板在第一绝缘层上形成第二导电图案，第二导电图案在垂直于衬底基板的方向上分别与第一过孔和第二过孔至少部分交叠且通过第一过孔和第二过孔与第一导电图案电连接；利用第二掩模板在第二导电图案上形成第二绝缘层，以形成暴露第二导电图案的部分区域的第三过孔和第四过孔；以及利用包括第三掩模图案的第三掩模板在第二绝缘层上形成第三导电图案，第三导电图案在垂直于衬底基板的方向上与第三过孔至少部分交叠且通过第三过孔与第二导电图案电连接，第三掩模图案不同于第一掩模图案和第二掩模图案。
本公开上述至少一个实施例提供的发光基板的制备方法可以减少制备过程中所需要的掩模板的数量，从而优化发光基板的制备过程，降低发光基板的制备成本，并且还可以降低发光基板在制备过程中的设计和加工难度，有助于大批量的生产及应用。
本公开至少一个实施例还提供一种发光基板及显示装置。
下面，将参考附图详细地说明本公开的一些实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
图1为本公开一些实施例提供的一种发光基板的制备方法的流程图。例如，如图1所示，发光基板的制备方法包括以下步骤。
步骤S101：提供衬底基板。
步骤S102：利用包括第一掩模图案的第一掩模板在衬底基板上形成第一导电图案。
步骤S103：利用包括第二掩模图案的第二掩模板在第一导电图案上形成第一绝缘层，以形成暴露第一导电图案的部分区域的第一过孔和第二过孔，第二掩模图案不同于第一掩模图案。
步骤S104：利用第一掩模板在第一绝缘层上形成第二导电图案，第二导电图案在垂直于衬底基板的方向上分别与第一过孔和第二过孔至少部分交叠且通过第一过孔和第二过孔与第一导电图案电连接。
步骤S105：利用第二掩模板在第二导电图案上形成第二绝缘层，以形成暴露第二导电图案的部分区域的第三过孔和第四过孔。
步骤S106：利用包括第三掩模图案的第三掩模板在第二绝缘层上形成第三导电图案，第三导电图案在垂直于衬底基板的方向上与第三过孔至少部分交叠且通过第三过孔与第二导电图案电连接，第三掩模图案不同于第一掩模图案和第二掩模图案。
在图1所示的实施例的发光基板的制备方法中，第一导电图案和第二导电图案采用同一个第一掩模板形成，第一绝缘层和第二绝缘层采用同一个第二掩模板形成，由此既可以实现发光基板中的第一导电图案、第二导电图案和第三导电图案之间的电连接，又可以减少制备过程中所需要的掩模板的数量，优化发光基板的制备过程，降低发光基板的设计和加工难度，从而降低发光基板的制备成本。
例如，上述第一导电图案和第二导电图案可以为构成发光基板中的同一条走线的不同膜层图案，也即，第一导电图案和第二导电图案在衬底基板上依次设置以形成该条走线。通过利用相同的第一掩模板分别制备同一走线的不同膜层图案可以实现该条走线的分层制备，从而在基本上不增加走线的电阻的情况下，既可以减少或避免由于走线的整体厚度较大而可能出现的剥落现象，又可以减少制备过程中所需的掩模板的数量，由此既可以提升制备的发光基板的稳定性，又可以简化制备工艺，降低发光基板的设计和加工难度，从而降低制备成本。
例如，上述第三导电图案可以用于构成与第一导电图案和第二导电图案构成的上述走线在平行于衬底基板的平面内彼此交叠的另一条走线，以形成网格状走线图案，从而减小信号通过走线传输时的压降，提高信号传输效果的一致性。通过使第二掩模板的第二掩模图案既包括用于形成使第一导电图案与第二导电图案之间电连接的第一过孔和第二过孔的图案，又包括用于形成使第二导电图案与第三导电图案之间电连接的第三过孔和第四过孔的图案，则既可以减少制备过程中所需要的掩模板的数量，还可以降低发光基板的设计和加工难度，优化制备过程，进而降低发光基板的制备成本。
需要说明的是，本公开实施例对于形成上述第一绝缘层和第二绝缘层的具体工艺方法不作限制，例如第一绝缘层和第二绝缘层可以分别采用例如涂覆、曝光、显影等常规工艺形成，具体可参考本领域中形成绝缘层的常规工艺方法，在此不再赘述。
需要说明的是，本公开实施例对于形成上述第一导电图案、第二导电图案和第三导电图案的具体工艺方法不作限制，例如第一导电图案、第二导电图案和第三导电图案可以分别采用形成金属膜层、在金属膜层上涂覆光刻胶层、采用掩模板对光刻胶层曝光、将曝光后的光刻胶层显影以得到光刻胶图案、使用光刻胶图案对金属膜层进行刻蚀、剥离光刻胶图案等工艺步骤形成。例如，形成绝缘层中的过孔(例如上述第一过孔至第四过孔)可以分别采用形成绝缘层、在绝缘层上涂覆光刻胶层、采用掩模板对光刻胶层曝光、将曝光后的光刻胶层显影以得到光刻胶图案、使用光刻胶图案对绝缘层进行刻蚀、剥离光刻胶图案等工艺步骤形成。
上述构图工艺中，形成金属膜层或形成绝缘层的方法、涂覆光刻胶的方法、刻蚀方法(湿法刻蚀或干法刻蚀)、剥离光刻胶图案的方法具体可采用本领域中的常规工艺方法，在此不再赘述。例如，可以采用例如溅射、电镀或者电铸等工艺方法形成金属膜层，而可以采用例如涂覆等方法形成绝缘层。并且，本公开的实施例对于所采用的光刻胶的材料、曝光光源类型以及制备掩模板的材料等不做限制。
下面以本公开实施例提供的制备方法用于制备图2中所示的发光基板10为例，对本公开实施例提供的发光基板的制备方法进行说明。需要说明的是，本公开的实施例包括但并不仅限与此。
图2为本公开一些实施例提供的一种发光基板的示意图，图3为图2所示的发光基板的发光单元的排列示意图。如图2和图3所示，发光基板10包括衬底基板11和在衬底基板11上阵列排布的多个发光单元100。例如，多个发光单元100排列为N行M列， N为大于0的整数，M为大于0的整数。例如，发光单元100的数量可以根据实际需求而定，例如根据发光基板10的尺寸和所需要的亮度而定，虽然图2中仅示出了3行5列发光单元100，但是应当理解，发光单元100的数量不限于此。
例如，该衬底基板11可以为塑料基板、硅基板、陶瓷基板、玻璃基板、石英基板等，衬底基板11中包括有单层或多层线路，本公开的实施例对此不作限制。
例如，每一列发光单元100沿第一方向R1排列，每一行发光单元100沿第二方向R2排列。例如，第一方向R1为列方向且第二方向R2为行方向。当然，本公开的实施例不限于此，第一方向R1和第二方向R2可以为任意的方向，只需使第一方向R1和第二方向R2交叉即可。并且，多个发光单元100也不限于沿直线排列，也可以沿曲线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
图4为图2所示的发光基板中一个发光单元的示意图，图5为图2所示的发光基板的发光单元中的驱动电路的引脚示意图。如图2、图4和图5所示，每个发光单元100包括驱动电路160、多个发光元件140和驱动电压端Vled。
驱动电路160包括第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND。第一输入端Di接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的驱动电路160。例如，不同的驱动电路160的地址可以相同或不同。第一输入信号可以为8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入端Pwr接收第二输入信号，第二输入信号例如为电力线载波通信信号。例如，第二输入信号不仅为驱动电路160提供电能，还向驱动电路160传输通信数据，该通信数据可用于控制相应的发光单元100的发光时长，进而控制其视觉上的发光亮度。输出端OT可在不同的时段内分别输出不同的信号，例如分别输出中继信号和驱动信号。例如，中继信号为提供给其他驱动电路160的地址信号，也即是，其他驱动电路160的第一输入端Di接收该中继信号以作为第一输入信号，从而获取地址信号。例如，驱动信号可以为驱动电流，用于驱动发光元件140发光。公共电压端GND接收公共电压信号，例如接地信号。
驱动电路160配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT提供驱动信号至依次串联的多个发光元件140。在第一时段内，输出端OT输出中继信号，该中继信号被提供给其他驱动电路160以使其他驱动电路160获得地址信号。在第二时段内，输出端OT输出驱动信号，该驱动信号被提供给依次串联的多个发光元件140，使得发光元件140在第二时段内发光。例如，第一时段与第二时段为不同的时段，第一时段例如可以早于第二时段。第一时段可以与第二时段连续相接，第一时段的结束时刻即为第二时段的开始时刻；或者，第一时段与第二时段中间还可以有其他时段，该其他时段可以用于实现其他需要的功能，该其他时段也可以仅用于使第一时段和第二时段间隔开，以避免输出端OT在第一时段和第二时段的信号彼此干扰。关于驱动电路160的具体工作原理可参考本领域中的常规设计方案，此处不再赘述。
需要说明的是，当驱动信号为驱动电流时，驱动电流可以从输出端OT流向发光元件140，也可以从发光元件140流入输出端OT，驱动电流的流动方向可以根据实际需求而定，本公开的实施例对此不作限制。在本文中，“输出端OT输出驱动信号”表示输出端OT提供驱动信号，而驱动信号的方向既可以从输出端OT流出，也可以流入输出端OT。
例如，如图2和图4所示，多个发光元件140依次串联，并且串联连接在驱动电压端Vled和输出端OT之间。例如，发光元件140可以为微型发光二极管(Micro-LED)或迷你发光二极管(Mini-LED)。例如，每个发光元件140包括正极(+)和负极(-)(或者，也可称为阳极和阴极)，多个发光元件140的正极和负极依序首尾串联，从而在驱动电压端Vled和输出端OT之间形成电流路径。驱动电压端Vled向发光元件140提供驱动信号，例如在需要使发光元件140发光的时段(第二时段)内为高电压，而在其他时段内为低电压。由此，在第二时段内，驱动信号(例如驱动电流)从驱动电压端Vled依次流经多个发光元件140，然后流入驱动电路160的输出端OT。多个发光元件140在驱动电流流过时发光，通过控制驱动电流的持续时间，可以控制发光元件140的发光时长，从而控制视觉上的发光亮度。
例如，如图2和图4所示，在一些示例中，一个发光单元100包括6个发光元件140，该6个发光元件140排列为2行3列。例如，按照从左至右、从上至下的方式给该6个发光元件140依次编号为(1,1)、(1,2)、(1,3)、(2,1)、(2,2)和(2,3)，编号在图4中示出。例如，将6个发光元件140串联时，以位置(2,1)处的发光元件140作为串联的起点，依次连接(1,1)、(2,2)、(1,2)、(2,3)和(1,3)位置处的发光元件140，以位置(1,3)处的发光元件140作为串联的终点。例如，位置(2,1)处的发光元件140的正极连接驱动电压端Vled，位置(1,3)处的发光元件140的负极连接驱动电路160的输出端OT。采用这种分布方式和串联方式，可以有效避免走线交叠，便于设计和制备，并且，串联线路上任意的相邻两个发光元件140之间的走线的弯折形状和长度大致相同，使得线路本身的电阻较为均衡，可以提高负载均衡性，提高电路的稳定性。
图6为图2所示的发光基板的发光单元中发光元件和驱动电路的排列示意图。如图6所示，在同一个发光单元100中，多个(例如6个)发光元件140阵列排布，例如排列为多行多列，这样可以使发光更为均为。驱动电路160位于多个发光元件140构成的阵列的空隙中。
需要说明的是，本公开的实施例中，每个发光单元100中的发光元件140的数量不受限制，可以为4个、5个、7个、8个等任意数量，而不限于6个。多个发光元件140可以采用任意的排列方式，例如按照所需要的图案排列，而不限于矩阵排列方式。驱动电路160的设置位置不受限制，可以设置在发光元件140彼此之间的任意空隙中，这可以根据实际需求而定，本公开的实施例对此不作限制。
下面本公开的实施例以图2所示的发光基板10的部分区域REG1中的走线布局为例， 对发光基板中的走线布局进行说明。
图7为本公开一些实施例提供的一种发光基板的部分结构的平面示意图。例如，图7对应图2所示的发光基板10的部分区域REG1中的结构。
例如，如图2、图4和图7所示，在一些实施例中，发光基板10还包括沿第一方向R1延伸的多条第一驱动电压线301和多条第一公共电压线401，以及还包括沿第二方向R2延伸的多条第二驱动电压线302和多条第二公共电压线402。
例如，第一驱动电压线301与每个发光单元100的驱动电压端Vled电连接，例如与位置(2，1)处的发光元件140的正极电连接，且配置为向每个发光单元100传输驱动电压。第二驱动电压线302与第一驱动电压线301电连接且形成网格状走线，以整体上减小传输电阻，从而提高发光基板10内各个位置的电压一致性。
例如，第一公共电压线401与每个发光单元100的驱动电路160的公共电压端GND电连接，且配置为向每个发光单元100传输公共电压(例如接地电压)。例如，第一公共电压线401可以通过在垂直于衬底基板11的方向(例如后文图8中所示的方向R3)上贯穿位于第一公共电压线401和驱动电路160之间的结构或膜层等的过孔H5与驱动电路160的公共电压端GND电连接，以提供公共电压。第二公共电压线402与第一公共电压线401电连接且形成网格状走线，以整体上减小传输电阻，从而提高发光基板10内各个位置的电压一致性。
例如，第一驱动电压线301和第一公共电压线401位于同一层，第二驱动电压线302和第二公共电压线402位于同一层。
需要说明的是，图7的第一驱动电压线301所在的膜层位于发光元件140之下，因此，第一驱动电压线301可以延伸至位置(2，1)处的发光元件140的正极下方，并通过过孔与该位置(2，1)处的发光元件140的正极电连接，也即是，第一驱动电压线301将驱动电压传输至位置(2，1)处的发光元件140的正极(也即传输至驱动电压端Vled)。虽然图7中位置(2，1)处的发光元件140的负极与第一驱动电压线301交叠，但是由于两者位于不同的膜层且由中间绝缘层绝缘间隔开，因此该发光元件140的负极不与第一驱动电压线301电连接。例如，第一公共电压线401所在的膜层位于驱动电路160之下，因此，第一公共电压线401位于驱动电路160下方，并通过过孔与驱动电路160的公共电压端GND电连接。
需要说明的是，本公开的实施例中，第一驱动电压线301、第二驱动电压线302、第一公共电压线401和第二公共电压线402的长度和宽度可以设置为适用的任意数值，其长度可以相同或不同，其宽度也可以相同或不同，这可以根据实际需求而定，本公开的实施例对此不作限制。
下面以第一导电图案和第二导电图案用于构成第一驱动电压线301和第一公共电压线401，第三导电图案用于构成第二驱动电压线302和第二公共电压线402为例，对本公开实施例提供的制备方法进行说明。
图8为沿图7中所示的A-A’线的发光基板10的部分截面结构的示意图，图9为沿 图7中所示的B-B’线的发光基板10的部分截面结构的示意图。
例如，如图7、图8和图9所示，图2中所示的发光基板10的制备方法可以包括以下步骤。
步骤S201：提供衬底基板11。
步骤S202：利用包括第一掩模图案的第一掩模板在衬底基板11上形成第一导电图案110。
例如，步骤S202中可以是先通过例如溅射工艺或电镀工艺在衬底基板11上形成一整层的导电材料层，然后再利用第一掩模板通过例如光刻工艺将该导电材料层图案化以形成第一导电图案110；或者，步骤S202中也可以是将第一掩模板直接贴附在衬底基板11上，从而通过例如溅射工艺或电镀工艺等直接在衬底基板11上形成第一导电图案110。本公开的实施例对步骤202中的具体工艺方法不作限制，具体可参考本领域中的常规工艺设计，在此不作赘述。本公开实施例提供的制备方法中的以下其他步骤均与此基本相同或相似，不再赘述。
步骤S203：利用包括第二掩模图案的第二掩模板在第一导电图案110上形成第一绝缘层151，以形成暴露第一导电图案110的部分区域的第一过孔H1和第二过孔H2，第二掩模图案不同于第一掩模图案。
步骤S204：利用第一掩模板在第一绝缘层151上形成第二导电图案120。第二导电图案120在垂直于衬底基板11的方向R3上分别与第一过孔H1和第二过孔H2至少部分交叠且通过第一过孔H1和第二过孔H2与第一导电图案110电连接。
例如，第一导电图案110和第二导电图案120构成了包括第一驱动电压线301和第一公共电压线401的电源走线图案，由此可以使用同一个第一掩模板实现具有双膜层结构的第一驱动电压线301和第一公共电压线401的制备，从而提升第一驱动电压线301和第一公共电压线401的厚度，以满足阻值需求。例如，第一驱动电压线301和第一公共电压线401在垂直于衬底基板11的方向上的厚度可以为1.2微米～2.4微米，进一步例如1.8微米～2微米。
步骤205：利用第二掩模板在第二导电图案120上形成第二绝缘层152，以形成暴露第二导电图案120的部分区域的第三过孔H3和第四过孔H4。
步骤S206：利用包括第三掩模图案的第三掩模板在第二绝缘层152上形成第三导电图案130。第三导电图案130在垂直于衬底基板11的方向R3上与第三过孔H3至少部分交叠且通过第三过孔H3与第二导电图案120电连接，第三掩模图案不同于第一掩模图案和第二掩模图案。
例如，第三导电图案130构成了包括第二驱动电压线302和第二公共电压线402的电源走线图案。例如，第二驱动电压线302和第二公共电压线402在垂直于衬底基板11的方向上的厚度可以为0.3微米～0.9微米，进一步例如0.6微米～0.8微米。
由此，在制备发光基板10的第一驱动电压线301、第二驱动电压线302、第一公共电压线401和第二公共电压线402的过程中，通过使第二掩模板的第二掩模图案既包括 用于形成使第一导电图案110与第二导电图案120之间电连接的第一过孔H1和第二过孔H2的图案，又包括用于形成使第二导电图案120与第三导电图案130之间电连接的第三过孔H3和第四过孔H4的图案。因此，既可以使用同一个第一掩模板实现具有多膜层结构的第一驱动电压线301和第一公共电压线401中多个导电膜层图案的制备，又可以使用同一个第二掩模板实现第一驱动电压线301与第二驱动电压线302之间的电连接、以及第一公共电压线401与第二公共电压线402之间的电连接，从而本公开的上述实施例减少了发光基板的制备过程中所需的掩模板的数量，降低了发光基板10的设计和加工难度，进而降低发光基板10的制备成本。
例如，第一导电图案110的材料可以包括钼金属及其合金、铜金属及其合金等，或者也可以包括其他适合的金属导电材料，例如第一导电图案110可以包括由铜金属和钼金属形成的金属叠层结构，例如钼-铜-钼(Mo-Cu-Mo)三叠层结构。
例如，第一导电图案110在垂直于衬底基板11的方向上的厚度可以为0.6微米～1.2微米，进一步例如0.9微米～1微米。
例如，第二导电图案120的材料可以包括钼金属及其合金、铜金属及其合金等，或者也可以包括其他适合的金属导电材料，例如第二导电图案120可以包括由铜金属和钼金属形成的金属叠层结构，例如钼-铜-钼(Mo-Cu-Mo)三叠层结构。
例如，第二导电图案120在垂直于衬底基板11的方向上的厚度可以为0.6微米～1.2微米，进一步例如0.9微米～1微米。
例如，第三导电图案130的材料可以包括钼金属及其合金、铜金属及其合金等，或者也可以包括其他适合的金属导电材料，例如第三导电图案130可以包括由铜金属和钼金属形成的金属叠层结构，例如钼-铜(Mo-Cu)双叠层结构。
例如，第三导电图案130在垂直于衬底基板11的方向上的厚度可以为0.3微米～0.9微米，进一步例如0.6微米～0.8微米。
例如，第一绝缘层151和第二绝缘层152中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第一绝缘层151和第二绝缘层152的材料可以彼此相同，也可以彼此不相同，本公开的实施例对此不作限制。
例如，如图7、图8和图9所示，第一过孔H1在衬底基板11上的正投影与第三过孔H3在衬底基板11上的正投影至少部分重叠，例如完全重叠；第二过孔H2在衬底基板11上的正投影与第四过孔H4在衬底基板上的正投影至少部分重叠，例如完全重叠。由此，既可以实现第一导电层110、第二导电层120与第三导电层130之间的定位，又可以提升第三导电130与第一导电层110和第二导电层120之间的电连接效果，进而提升发光基板10的稳定性。
在本公开的一些实施例中，第一掩模板的第一掩模图案包括用于形成导电图案(例如第一导电图案110和第二导电图案120)的第一制备图案和用于定位的第一定位图案；第二掩模板的第二掩模图案包括用于形成绝缘图案(例如第一绝缘层151的包括第一过孔H1和第二过孔H2的绝缘图案以及第二绝缘层152的包括第三过孔H3和第四过孔H4 的绝缘图案)的第二制备图案和用于定位的第二定位图案。例如，以发光基板10为例，第一制备图案可以用于形成第一导电图案110和第二导电图案120，也即，用于形成第一驱动电压线301和第一公共电压线401；第二制备图案可以用于形成包括第一过孔H1和第二过孔H2的第一绝缘层151，以及形成包括第三过孔H3和第四过孔H4的第二绝缘层152，从而实现第一导电图案110与第二导电图案120之间的电连接，以及实现第三导电图案130与第二导电图案120之间的电连接。
例如，发光基板10的制备方法还包括：利用第一掩模板在衬底基板11上形成第一导电图案110的同时，利用第一掩模板的第一定位图案形成第一定位结构；利用第二掩模板在第一导电图案110上形成第一绝缘层151的过程中，使用第一定位结构与第二掩模板的第二定位图案配合以定位第二掩模板，并且在形成第一过孔H1和第二过孔H2的同时，利用第二掩模板的第二定位图案形成第二定位结构；利用第一掩模板在第一绝缘层151上形成第二导电图案120的过程中，使用第二定位结构与第一掩模板的第一定位图案配合以定位第一掩模板，并且在形成第二导电图案120的同时，利用第一掩模板的第一定位图案形成第三定位结构；以及利用第二掩模板在第二导电图案120上形成第二绝缘层152的过程中，使用第三定位结构与第二掩模板的第二定位图案配合以定位第二掩模板。
由此，通过第一定位结构、第二定位结构和第三定位结构可以分别实现例如上述步骤S201～步骤S206中第一掩模板和第二掩模板的定位，从而提升制备的导电图案或绝缘图案在衬底基板11上的准确度和精确度，进而提升制备的发光基板10的良率和稳定性。
例如，第一定位结构、第二定位结构和第三定位结构可以形成在衬底基板11上不设置例如发光元件140、驱动电路160、第一驱动电压线301、第二驱动电压线302、第一公共电压线401和第二公共电压线402等器件或结构的区域，例如发光基板10的周边区域，以避免对发光基板10中器件或结构的制备等产生不良影响。并且，本公开的实施例对于所制备的第一定位结构、第二定位结构和第三定位结构的数量不做限制，例如，当发光基板10是方形的情形，可以在该方形的发光基板的四个角部都分别形成一个或多个第一定位结构、一个或多个第二定位结构和一个或多个第三定位结构，由此更好地实现定位。
例如，以图2所示的发光基板10为例，如图2所示，第一定位结构、第二定位结构和第三定位结构可以形成在多边形(例如矩形)的发光基板10的角部区域REG2和REG3中，或者也可以形成在其他适合的不会对发光基板10中的器件或结构的制备等产生不良影响的区域中，本公开的实施例对第一定位结构、第二定位结构和第三定位结构形成的具体位置不作限制。
图10A为本公开一些实施例提供的一种第一掩模板的第一定位图案的示例的示意图，图10B为本公开一些实施例提供的一种第二掩模板的第二定位图案的示例的示意图，图10C为本公开一些实施例中定位结构彼此嵌套以进行定位的示例的示意图，图10D为图10C的一个具体示例的示意图。
例如，如图10A和图10B所示，第一定位图案包括第一子图案191和第二子图案192，第二定位图案包括第三子图案193和第四子图案194。第一定位图案的第一子图案191用于形成第一定位结构和第三定位结构，第二定位图案的第四子图案194用于形成第二定位结构。第一定位图案的第二子图案192与第二定位图案的第四子图案194对应以用于定位第一掩模板。例如，如图10C所示，第四子图案194形成的第二定位结构P2可以套合在第二子图案192中以实现定位；相同地，第二定位图案的第三子图案193与第一定位图案的第一子图案191对应以用于定位第二掩模板，例如第一子图案191形成的第一定位结构和第三定位结构可以套合在第三子图案193中以实现定位。
例如，以图10A和图10B所示的示例为例，第一子图案191和第四子图案194可以为“井”字型图案，第二子图案192和第三子图案193可以为与该“井”字型图案配合的菱形图案。例如，第一子图案191和第四子图案194的尺寸可以相同，以第四子图案194为例，如图10D所示，构成该“井”字型图案中的一条线段的长度L2可以为1000微米～1400微米，进一步例如1100微米～1200微米，宽度L1可以为30微米～60微米，进一步例如40微米～50微米，宽度L5可以为150微米～250微米，进一步例如180微米～200微米；第二子图案192和第三子图案193的尺寸可以相同，以第二子图案192为例，如图10D所示，该菱形图案的一条边的长度L4可以为400微米～700微米，进一步例如500微米～600微米，宽度L3可以为30微米～60微米，进一步例如40微米～50微米。
需要说明的是，上述图10A和图10B中所示的第一定位图案和第二定位图案只是示例性说明，本公开的实施例对第一定位图案中包括的第一子图案和第二子图案以及第二定位图案中包括的第三子图案和第四子图案的具体结构不作限制，只要满足第一子图案与第三子图案能够配合使用以实现定位且第二子图案与第四子图案能够配合使用以实现定位即可。
需要说明的是，本公开的实施例对形成的第一定位结构、第二定位结构和第三定位结构的具体大小不作限制，只要满足实现第一掩模板和第二掩模板在衬底基板11上的定位且不会对发光基板10中的器件或结构的制备等产生不良影响即可。
例如，在本公开的一些示例中，上述发光基板10的制备方法的步骤S202具体包括：通过第一掩模板的第一制备图案在衬底基板11上形成第一导电图案110。上述发光基板10的制备方法的步骤S204具体包括：通过第一掩模板的第一制备图案在第一绝缘层151上形成第二导电图案120。第一导电图案110和第二导电图案120包括相同的导电图案部分，且相同的导电图案部分在垂直于衬底基板11的方向R3上至少部分重叠，例如完全重叠。由此，第一导电图案110和第二导电图案120可以共同形成具有多膜层结构的第一驱动电压线301或第一公共电压线401。
例如，在本公开的一些示例中，上述发光基板10的制备方法的步骤S203具体包括：通过第二掩模板的第二制备图案在第一导电图案110上形成第一绝缘层151。上述发光基板10的制备方法的步骤S205具体包括：通过第二掩模板的第二制备图案在第二导电图案120上形成第二绝缘层152。第一绝缘层151和第二绝缘层152包括相同的过孔图案部 分，且相同的过孔图案部分在垂直于衬底基板11的方向R3上至少部分重叠，例如完全重叠。由此，在实现第一导电图案110与第二导电图案120之间的电连接、以及第三导电图案130与第二导电图案120之间的电连接的基础上，还可以改善第三导电图案130与第一导电图案110和第二导电图案120之间的电连接效果，进而提升第一驱动电压线301与第二驱动电压线302之间的电连接的稳定性、以及第一公共电压线401与第二公共电压线402之间的电连接的稳定性。
例如，结合图7、图8和图9所示，在本公开的一些实施例中，发光基板10的制备方法还包括：利用第三掩模板在第三导电图案130上形成第四导电图案170，第四导电图案在衬底基板11上的正投影与第三导电图案130在衬底基板11上的正投影至少部分重叠，例如完全重叠。由此，在形成用于构成第二驱动电压线302和第二公共电压线402的第三导电图案130后，通过第四导电图案170形成覆盖且保护第二驱动电压线302和第二公共电压线402的远离衬底基板11的一侧的表面的保护层，进而既可以减弱发光基板10中的其他器件或结构对第二驱动电压线302和第二公共电压线402上的信号的干扰，提升信号传输的稳定性，同时由于第三导电图案130和第四导电图案170可以采用同一个第三掩模板制备，因此还可以减少制备过程中所需的掩模板的数量，从而进一步简化发光基板10的设计和加工难度，减少发光基板10的制备成本。
例如，第三导电图案130的材料包括第一金属材料，第四导电图案170的材料包括第二金属材料，第一金属材料和第二金属材料不同，由此通过使第四导电图案170采用与第一金属材料不同的第二金属材料，可以进一步提升第四导电图案170对第三导电图案130的保护效果，从而进一步提升发光基板10的稳定性。
例如，第一金属材料可以包括钼金属及其合金、铜金属及其合金等，或者也可以包括其他适合的金属导电材料，例如第三导电图案130可以包括由铜金属和钼金属形成的双叠层金属结构。例如，第二金属材料可以包括钼金属及其合金、铜金属及其合金、镍金属及其合金等，或者也可以包括其他适合的金属导电材料，例如第四导电图案170可以包括由例如镍化铜(CuNi)形成的单层金属结构。
在本公开的一些实施例中，结合图4、图7、图8和图9所示，发光基板10的制备方法还包括：在利用第三掩模板在第二绝缘层152上形成第三导电图案130的同时，利用第三掩模板在第二绝缘层152上形成不同于第三导电图案130的第五导电图案150。第五导电图案150与第一导电图案110和第二导电图案120彼此绝缘，发光元件140通过第五导电图案150与驱动电路160的输出端OT电连接。
例如，上述第五导电图案150可以用于形成实现多个发光元件140与驱动电路160的输出端OT电连接的多条连接走线501，例如该多条连接走线501可以包括连接发光单元100中位置(1，3)处的发光元件140的负极与驱动电路160的输出端OT之间的连接走线，以及连接发光单元100中一个发光元件140的负极与另一个发光元件140的正极之间的连接走线，由此使发光单元100中的多个发光元件140之间彼此串联且电连接在驱动电压端Vled与输出端OT之间。
在本公开的一些实施例中，在利用第三掩模板在第二绝缘层152上形成第三导电图案130和第五导电图案150的同时，还可以利用第三掩模板在第二绝缘层152上形成不同于第三导电图案130和第五导电图案150的其他导电图案，从而以形成与例如第二驱动电压线302、第二公共电压线402、连接走线501等位于同层的发光基板中的其他连接走线，例如图4和图7中所示的用于连接驱动电路160的第一输入端Di的连接走线、用于连接驱动电路160的第二输入端Pwr的连接走线等，本公开的实施例对此不作限制。
在本公开的一些实施例中，发光基板10的制备方法还包括：利用第四掩模板在第三导电图案130和第五导电图案150上形成至少部分覆盖(例如完全覆盖)第三导电图案130和第五导电图案150的第三绝缘层153。
第三绝缘层153包括用于使第五导电图案150与发光元件140电连接的第一连接过孔H101，例如该第一连接过孔H101可用于使位置(2，1)处的发光元件140的负极与连接走线501电连接，进而通过该连接走线501与位置(1，1)处的发光元件140的正极电连接。第二绝缘层152和/或第三绝缘层153包括用于使发光元件140与第二导电图案120电连接的第二连接过孔H102，例如该第二连接过孔H102可用于使位置(2，1)处的发光元件140的正极与第一驱动电压线301电连接以接收驱动电压，由此使发光单元100中的多个发光元件140彼此串联连接在驱动电压端Vled与输出端OT之间。
例如，第三绝缘层153的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第一绝缘层151、第二绝缘层152和第三绝缘层153的材料可以彼此相同，也可以彼此不相同，本公开的实施例对此不作限制。
在本公开的一些实施例中，发光基板10的制备方法还包括：在第三绝缘层153上提供发光元件140，发光元件140通过第一连接过孔H101与第五导电图案150电连接，且通过第二连接过孔H102与第二导电图案120电连接。例如，位置(2，1)处的发光元件140的负极通过第一连接过孔H101与连接走线501电连接，位置(2，1)处的发光元件140的正极通过第二连接过孔H102与第一驱动电压线301电连接。
在本公开的一些实施例中，如图7、图8和图9所示，在利用第一掩模板在衬底基板11上形成第一导电图案110之前，发光基板10的制备方法还包括：在衬底基板11上形成缓冲层12，第一导电图案110形成在缓冲层12上。
例如，缓冲层12既可以减弱或防止衬底基板11中的有害物质侵入发光基板10的内部，又可以增加发光基板10中的膜层在衬底基板11上的附着力。例如，缓冲层12的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料，本公开的实施例对此不作限制。
在本公开的一些实施例中，在完成上述步骤后，发光基板10的制备方法还可以包括例如切割、固晶、涂胶、绑定(bonding)等其他常规工艺或步骤，具体可参考本领域中的常规设计及加工方案，在此不再赘述。
本公开至少一个实施例还提供一种发光基板，该发光基板包括衬底基板以及在衬底基板上在远离衬底基板的方向上依次设置的第一导电图案、第一绝缘层、第二导电图案、第二绝缘层和第三导电图案。第一导电图案和第二导电图案包括相同的导电图案部分， 第一绝缘层和第二绝缘层包括相同的过孔图案部分；第一绝缘层的过孔图案包括第一过孔和第二过孔，第二导电图案通过第一过孔和第二过孔与第一导电图案电连接；第二绝缘层的过孔图案包括第三过孔和第四过孔，第三导电图案通过第三过孔与第二导电图案电连接。第一过孔在衬底基板上的正投影与第三过孔在衬底基板上的正投影至少部分重叠，第二过孔在衬底基板上的正投影与第四过孔在衬底基板上的正投影至少部分重叠。
本公开上述至少一个实施例提供的发光基板中，由于第一导电图案和第二导电图案包括相同的导电图案部分，且第一绝缘层和第二绝缘层包括相同的过孔图案部分，因此在制备过程中，第一导电图案和第二导电图案可以采用同一个掩模板形成，第一绝缘层和第二绝缘层可以采用同一个掩模板形成，由此可以减少制备过程中所需要的掩模板的数量，优化发光基板的制备过程，从而降低发光基板的制备成本，并且还可以降低发光基板的设计和加工难度，有助于大批量的生产及应用。
本公开上述至少一个实施例提供的发光基板可以为上述关于发光基板的制备方法的实施例中提供的发光基板10，关于本公开实施例提供的发光基板的详细说明以及技术效果等可以参考上文中关于发光基板10的具体描述，此处不再赘述。
在本公开的一些实施例中，以发光基板10为例，第一导电图案110包括沿第一方向R1延伸的多个第一导电块，第二导电图案120包括沿第一方向R1延伸的多个第二导电块，例如多个第一导电块和多个第二导电块可以用于形成沿第一方向R1延伸的多条第一驱动电压线301和第一公共电压线401。第三导电图案130包括沿不同于第一方向R1的第二方向R2延伸的多个第三导电块，例如多个第三导电块可以分别用于形成沿第二方向R2延伸的多条第二驱动电压线302和第二公共电压线402。多个第二导电块中的至少一个在垂直于衬底基板11的方向R3上与多个第三导电块中的至少一个至少部分交叠，且通过第三过孔H3彼此电连接。例如，多条第一驱动电压线301与多条第二驱动电压线302在垂直于衬底基板11的方向R3上彼此交叠以形成网状结构，多条第一公共电压线401与多条第二公共电压线402在垂直于衬底基板11的方向R3上彼此交叠以形成网状结构，从而整体上减小传输电阻，提高发光基板10内各个位置的电压一致性。
在本公开的一些实施例中，以发光基板10为例，多个第一导电块中的至少一个在衬底基板11上的正投影与多个第二导电块中的至少一个在衬底基板11上的正投影至少部分重叠，例如完全重叠，多个第一导电块中的至少一个通过第一过孔H1和第二过孔H2与多个第二导电块中的至少一个电连接，从而形成具有双膜层结构的多条第一驱动电压线301和多条第一公共电压线401。
在本公开的一些实施例中，以发光基板10为例，多个第一导电块中的至少一个和多个第二导电块中的至少一个在第二方向R2上具有相同的宽度，由此以改善由第一导电块和第二导电块形成的第一驱动电压线301的整体结构和第一公共电压线401的整体结构，进而优化发光基板10中的走线布局设计。
在本公开的一些实施例中，以发光基板10为例，发光基板10还包括第五导电图案150和发光元件140。第五导电图案150与第三导电图案130同层设置，发光元件140位 于第三导电图案130和第五导电图案150远离衬底基板11的一侧。第五导电图案150与第一导电图案110和第二导电图案120彼此绝缘，发光元件140通过第五导电图案150与驱动电路160的输出端OT电连接，第五导电图案150包括沿第一方向R1延伸的至少一个第五导电块，发光元件140的第一端(例如发光元件的正极或负极)与一个第五导电块电连接，发光元件140的第二端(例如发光元件的负极或正极)与一个第二导电块或另一个第五导电块电连接。
例如，第五导电图案150可以包括多个第五导电块，多个第五导电块用于形成多条连接走线501。该多条连接走线501可以包括连接发光单元100中位置(1，3)处的发光元件140的负极与驱动电路160的输出端OT之间的连接走线，以及连接发光单元100中一个发光元件140的负极或正极与另一个发光元件140的正极或负极之间的连接走线，由此使发光单元100中的多个发光元件140之间彼此串联且电连接在驱动电压端Vled与输出端OT之间。
在本公开的一些实施例中，以发光基板10为例，发光基板10还包括第三绝缘层153，第三绝缘层153位于第三导电图案130和第五导电图案150与发光元件140之间，第三绝缘层153包括第一连接过孔H101以使至少一个第五导电块通过第一连接过孔H101与发光元件140的第一端和/或第二端电连接，第二绝缘层152和第三绝缘层153包括第二连接过孔H102以使一个第二导电块通过第二连接过孔H102与发光元件140的第二端电连接。
例如，该第一连接过孔H101可用于使位置(2，1)处的发光元件140的负极与一条连接走线501电连接，进而通过该条连接走线501与位置(1，1)处的发光元件140的正极电连接，该第二连接过孔H102可用于使位置(2，1)处的发光元件140的正极与第一驱动电压线301电连接以接收驱动电压，由此使发光单元100中的多个发光元件140彼此串联连接在驱动电压端Vled与输出端OT之间。
本公开实施例提供的发光基板还可以包括更多的部件和结构等，这可以根据实际需求而定，本公开的实施例对此不作限制。
本公开至少一个实施例还提供一种显示装置，该显示装置包括显示面板和本公开任一实施例提供的发光基板。
例如，本公开实施例提供的显示装置可以为液晶显示装置。或者，本公开实施例提供的显示装置还可以为有机发光二极管显示装置、量子点发光二极管显示装置、电子纸显示装置等具有显示功能的装置或其他类型的显示装置，本公开的实施例对此不作限制。该显示装置可以实现发光亮度的分区域独立控制，且具有功耗小、集成度高、控制方式简单等优点，可以与例如液晶显示器件配合实现高对比度显示。
需要说明的是，本公开实施例提供的上述发光基板既可以作为背光单元应用到上述显示装置中，也可以单独作为具有显示功能或发光功能的基板使用，本公开的实施例对此不作限制。
图11为本公开一些实施例提供的一种显示装置的剖面示意图。例如，如图11所示， 在一些实施例中，显示装置70包括显示面板710和发光基板720。例如，发光基板720可以为本公开任一实施例提供的发光基板，例如前述的发光基板10。
例如，显示面板710具有显示侧P1和与显示侧P1相对的非显示侧P2，发光基板720设置在显示面板710的非显示侧P2以作为背光单元。例如，发光基板720可以作为面光源向显示面板710提供背光。例如，显示面板710可以为LCD面板、电子纸显示面板等，本公开的实施例对此不作限制。
例如，显示装置70可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子书等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
关于本公开实施例的该显示装置的详细说明和技术效果可以参考上文中关于发光基板以及发光基板的制备方法的描述，此处不再赘述。该显示装置还可以包括更多的部件和结构，这可以根据实际需求而定，本公开的实施例对此不作限制。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或第一基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种发光基板的制备方法，包括：
    提供衬底基板；
    利用包括第一掩模图案的第一掩模板在所述衬底基板上形成第一导电图案；
    利用包括第二掩模图案的第二掩模板在所述第一导电图案上形成第一绝缘层，以形成暴露所述第一导电图案的部分区域的第一过孔和第二过孔，其中，所述第二掩模图案不同于所述第一掩模图案；
    利用所述第一掩模板在所述第一绝缘层上形成第二导电图案，其中，所述第二导电图案在垂直于所述衬底基板的方向上分别与所述第一过孔和所述第二过孔至少部分交叠且通过所述第一过孔和所述第二过孔与所述第一导电图案电连接；
    利用所述第二掩模板在所述第二导电图案上形成第二绝缘层，以形成暴露所述第二导电图案的部分区域的第三过孔和第四过孔；以及
    利用包括第三掩模图案的第三掩模板在所述第二绝缘层上形成第三导电图案，其中，所述第三导电图案在垂直于所述衬底基板的方向上与所述第三过孔至少部分交叠且通过所述第三过孔与所述第二导电图案电连接，所述第三掩模图案不同于所述第一掩模图案和所述第二掩模图案。
  2. 根据权利要求1所述的发光基板的制备方法，其中，所述第一过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影至少部分重叠，
    所述第二过孔在所述衬底基板上的正投影与所述第四过孔在所述衬底基板上的正投影至少部分重叠。
  3. 根据权利要求1或2所述的发光基板的制备方法，其中，所述第一掩模图案包括用于形成导电图案的第一制备图案和用于定位的第一定位图案，所述第二掩模图案包括用于形成绝缘图案的第二制备图案和用于定位的第二定位图案；
    所述制备方法还包括：
    利用所述第一掩模板在所述衬底基板上形成所述第一导电图案的同时，利用所述第一掩模板的第一定位图案形成第一定位结构；
    利用所述第二掩模板在所述第一导电图案上形成所述第一绝缘层的过程中，使用所述第一定位结构与所述第二掩模板的第二定位图案配合以定位所述第二掩模板，并且在形成所述第一过孔和所述第二过孔的同时，利用所述第二掩模板的第二定位图案形成第二定位结构；
    利用所述第一掩模板在所述第一绝缘层上形成所述第二导电图案的过程中，使用所述第二定位结构与所述第一掩模板的第一定位图案配合以定位所述第一掩模板，并且在形成所述第二导电图案的同时，利用所述第一掩模板的第一定位图案形成第三定位结构；以及
    利用所述第二掩模板在所述第二导电图案上形成所述第二绝缘层的过程中，使用所 述第三定位结构与所述第二掩模板的第二定位图案配合以定位所述第二掩模板。
  4. 根据权利要求3所述的发光基板的制备方法，其中，所述第一定位图案包括第一子图案和第二子图案，所述第二定位图案包括第三子图案和第四子图案；
    所述第一定位图案的第一子图案用于形成所述第一定位结构和所述第三定位结构，所述第二定位图案的第四子图案用于形成所述第二定位结构；
    所述第一定位图案的第二子图案与所述第二定位图案的第四子图案对应以用于定位所述第一掩模板，所述第二定位图案的第三子图案与所述第一定位图案的第一子图案对应以用于定位所述第二掩模板。
  5. 根据权利要求3或4所述的发光基板的制备方法，其中，利用所述第一掩模板在所述衬底基板上形成所述第一导电图案，包括：
    通过所述第一掩模板的第一制备图案在所述衬底基板上形成所述第一导电图案；
    利用所述第一掩模板在所述第一绝缘层上形成所述第二导电图案，包括：
    通过所述第一掩模板的第一制备图案在所述第一绝缘层上形成所述第二导电图案，
    其中，所述第一导电图案和所述第二导电图案包括相同的导电图案部分，且所述相同的导电图案部分在垂直于所述衬底基板的方向上至少部分重叠。
  6. 根据权利要求3-5中任一项所述的发光基板的制备方法，其中，利用所述第二掩模板在所述第一导电图案上形成所述第一绝缘层，包括：
    通过所述第二掩模板的第二制备图案在所述第一导电图案上形成所述第一绝缘层；
    利用所述第二掩模板在所述第二导电图案上形成所述第二绝缘层，包括：
    通过所述第二掩模板的第二制备图案在所述第二导电图案上形成第二绝缘层，
    其中，所述第一绝缘层和所述第二绝缘层包括相同的过孔图案部分，且所述相同的过孔图案部分在垂直于所述衬底基板的方向上至少部分重叠。
  7. 根据权利要求1-6中任一项所述的发光基板的制备方法，还包括：
    利用所述第三掩模板在所述第三导电图案上形成第四导电图案，
    其中，所述第四导电图案在所述衬底基板上的正投影与所述第三导电图案在所述衬底基板上的正投影至少部分重叠。
  8. 根据权利要求7所述的发光基板的制备方法，其中，所述第三导电图案的材料包括第一金属材料，所述第四导电图案的材料包括第二金属材料，
    所述第一金属材料和所述第二金属材料不同。
  9. 根据权利要求1-8中任一项所述的发光基板的制备方法，还包括：
    在利用所述第三掩模板在所述第二绝缘层上形成所述第三导电图案的同时，利用所述第三掩模板在所述第二绝缘层上形成不同于所述第三导电图案的第五导电图案，
    其中，所述第五导电图案与所述第一导电图案和所述第二导电图案彼此绝缘，发光 元件通过所述第五导电图案与驱动电路的输出端电连接。
  10. 根据权利要求9所述的发光基板的制备方法，还包括：
    利用第四掩模板在所述第三导电图案和所述第五导电图案上形成至少部分覆盖所述第三导电图案和所述第五导电图案的第三绝缘层，
    其中，所述第三绝缘层包括用于使所述第五导电图案与所述发光元件电连接的第一连接过孔，
    所述第二绝缘层和/或所述第三绝缘层包括用于使所述发光元件与所述第二导电图案电连接的第二连接过孔。
  11. 根据权利要求10所述的发光基板的制备方法，还包括：
    在所述第三绝缘层上提供所述发光元件，
    其中，所述发光元件通过所述第一连接过孔与所述第五导电图案电连接，且通过所述第二连接过孔与所述第二导电图案电连接。
  12. 根据权利要求1-11中任一项所述的发光基板的制备方法，在利用所述第一掩模板在所述衬底基板上形成所述第一导电图案之前，所述制备方法还包括：
    在所述衬底基板上形成缓冲层，其中，所述第一导电图案形成在所述缓冲层上。
  13. 一种发光基板，包括：衬底基板以及在所述衬底基板上在远离所述衬底基板的方向上依次设置的第一导电图案、第一绝缘层、第二导电图案、第二绝缘层和第三导电图案；
    其中，所述第一导电图案和所述第二导电图案包括相同的导电图案部分，所述第一绝缘层和所述第二绝缘层包括相同的过孔图案部分；
    所述第一绝缘层的过孔图案包括第一过孔和第二过孔，所述第二导电图案通过所述第一过孔和所述第二过孔与所述第一导电图案电连接；
    所述第二绝缘层的过孔图案包括第三过孔和第四过孔，所述第三导电图案通过所述第三过孔与所述第二导电图案电连接；
    所述第一过孔在所述衬底基板上的正投影与所述第三过孔在所述衬底基板上的正投影至少部分重叠，所述第二过孔在所述衬底基板上的正投影与所述第四过孔在所述衬底基板上的正投影至少部分重叠。
  14. 根据权利要求13所述的发光基板，其中，所述第一导电图案包括沿第一方向延伸的多个第一导电块，所述第二导电图案包括沿所述第一方向延伸的多个第二导电块，所述第三导电图案包括沿不同于所述第一方向的第二方向延伸的多个第三导电块；
    所述多个第二导电块中的至少一个在垂直于所述衬底基板的方向上与所述多个第三导电块中的至少一个至少部分交叠，且通过所述第三过孔彼此电连接。
  15. 根据权利要求14所述的发光基板，其中，所述多个第一导电块中的至少一个在所述衬底基板上的正投影与所述多个第二导电块中的至少一个在所述衬底基板上的正投影至少部分重叠，
    所述多个第一导电块中的至少一个通过所述第一过孔和所述第二过孔与所述多个第 二导电块中的至少一个电连接。
  16. 根据权利要求15所述的发光基板，其中，所述多个第一导电块中的至少一个和所述多个第二导电块中的至少一个在所述第二方向上具有相同的宽度。
  17. 根据权利要求14-16中任一项所述的发光基板，还包括：
    第五导电图案，与所述第三导电图案同层设置，以及
    发光元件，位于所述第三导电图案和所述第五导电图案远离所述衬底基板的一侧，
    其中，所述第五导电图案与所述第一导电图案和所述第二导电图案彼此绝缘，
    所述发光元件通过所述第五导电图案与驱动电路的输出端电连接，
    所述第五导电图案包括沿所述第一方向延伸的至少一个第五导电块，
    所述发光元件的第一端与一个第五导电块电连接，所述发光元件的第二端与一个第二导电块或另一个第五导电块电连接。
  18. 根据权利要求17所述的发光基板，还包括第三绝缘层，
    其中，所述第三绝缘层位于所述第三导电图案和所述第五导电图案与所述发光元件之间，
    所述第三绝缘层包括第一连接过孔以使所述至少一个第五导电块通过所述第一连接过孔与所述发光元件的第一端和/或第二端电连接，
    所述第二绝缘层和所述第三绝缘层包括第二连接过孔以使所述一个第二导电块通过所述第二连接过孔与所述发光元件的第二端电连接。
  19. 一种显示装置，包括如权利要求13-18任一所述的发光基板。
  20. 根据权利要求19所述的显示装置，还包括显示面板，
    其中，所述显示面板具有显示侧和与所述显示侧相对的非显示侧，所述发光基板设置在所述显示面板的非显示侧以作为背光单元。
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