WO2021258706A1 - 半导体装置封装方法及半导体装置 - Google Patents

半导体装置封装方法及半导体装置 Download PDF

Info

Publication number
WO2021258706A1
WO2021258706A1 PCT/CN2020/141626 CN2020141626W WO2021258706A1 WO 2021258706 A1 WO2021258706 A1 WO 2021258706A1 CN 2020141626 W CN2020141626 W CN 2020141626W WO 2021258706 A1 WO2021258706 A1 WO 2021258706A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead frame
chip
layer
semiconductor device
carrier board
Prior art date
Application number
PCT/CN2020/141626
Other languages
English (en)
French (fr)
Inventor
霍炎
涂旭峰
Original Assignee
矽磐微电子(重庆)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽磐微电子(重庆)有限公司 filed Critical 矽磐微电子(重庆)有限公司
Publication of WO2021258706A1 publication Critical patent/WO2021258706A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/84986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This application relates to a semiconductor device packaging method and a semiconductor device.
  • the chip In the semiconductor packaging process, some manufacturers use wire bonding to realize the lead-out of the internal circuit of the chip.
  • the chip is usually arranged on a lead frame, and then a lead is arranged so that one end of the lead is connected to the bonding pad on the front of the chip and the other end is connected to the lead frame pin.
  • Some manufacturers also use chip connectors to bond the internal circuits of the chip. One end of the chip connector is soldered to the pad on the front of the chip, and the other end is soldered to the lead frame pin.
  • the inventor(s) have discovered through research that the semiconductor device using wire bonding and the semiconductor device formed by bonding chip connectors have a smaller interconnection area between the chip and the lead frame, and the current flow capacity is relatively small. Poor; And, limited by the size of the lead frame, the size of the semiconductor device is relatively fixed.
  • One aspect of the present application provides a semiconductor device packaging method, which includes: mounting a lead frame on a carrier, the lead frame includes leads, and the lead frame has a first surface and a second surface opposite to each other , The second surface of the lead frame faces the carrier board; the chip is mounted, the front surface of the chip is provided with conductive posts, the chip is mounted on the first surface of the lead frame and the back of the chip Facing the lead frame, or the chip is mounted on the carrier with the back of the chip facing the carrier; a first encapsulating layer is formed on the carrier, and the first encapsulating layer At least the chip and the lead frame are encapsulated; a metal connection member is formed on the side of the first encapsulation layer away from the carrier board.
  • the metal connector includes a first connecting portion and a second connecting portion that are connected, the first connecting portion is connected to the pin, and the second connecting portion is connected to the conductive pillar of the chip.
  • the chip and the pins are arranged at intervals.
  • the lead frame further includes a lead frame body arranged spaced apart from the pins, the chip is mounted on the first surface of the lead frame body, and the back of the chip faces the lead The main body of the box.
  • forming a first encapsulating layer on the carrier board to encapsulate at least the chip and the lead frame includes: forming a first encapsulating layer on the carrier board to encapsulate the The chip and the lead frame; thin the first encapsulation layer to expose the conductive pillars on the front of the chip; form an opening on the first encapsulation layer, and the opening is opposite to the lead The pins of the box.
  • the opening can be formed by laser opening.
  • connection portion and the second connection portion are simultaneously formed using a rewiring process.
  • forming a metal connector on the side of the first encapsulation layer away from the carrier board includes: A seed layer is formed on the conductive column and in the opening; a photosensitive layer is attached to the side of the seed layer away from the carrier; the photosensitive layer is patterned to form a photosensitive layer pattern, and the seed layer is located in the opening The part in the hole and above the conductive pillar of the chip is exposed from the photosensitive layer pattern; wires are routed in the opening and in the photosensitive layer pattern to form a metal connector, and the second part of the metal connector A connecting portion is located in the opening, the second connecting portion is located in the photosensitive layer pattern; the remaining photosensitive layer is removed, and the part of the seed layer corresponding to the position of the remaining photosensitive layer is removed.
  • forming a metal connector on the side of the first encapsulation layer away from the carrier board includes: A seed layer is formed on the conductive pillar and in the opening; wiring is made on the side of the seed layer away from the carrier to form a first metal wiring layer; the first metal wiring layer is etched to form a metal connection Pieces.
  • forming a metal connector on the side of the first encapsulating layer away from the carrier board includes: attaching a photosensitive layer on the side of the first encapsulating layer away from the carrier board; The photosensitive layer is patterned to form a photosensitive layer pattern, the openings communicate with the outside from the photosensitive layer pattern, and the leads of the lead frame are exposed; wiring is routed in the openings and the photosensitive layer pattern, A metal connecting piece is formed, the first connecting portion of the metal connecting piece is located in the opening, and the second connecting portion is located in the photosensitive layer pattern; and the remaining photosensitive layer is removed.
  • forming a metal connector on the side of the first encapsulation layer away from the carrier board includes: A second metal wiring layer is formed on the conductive pillar and in the opening; the second metal wiring layer is etched to form a metal connection piece.
  • the semiconductor device packaging method includes: forming a second encapsulation layer on a side of the first encapsulation layer away from the carrier, and the second encapsulation layer is at least Encapsulate the exposed part of the metal connector and the first encapsulation layer on the side away from the carrier board; peel off the carrier board to expose the second surface of the lead frame; on the lead frame An outer pin layer is formed on the second surface; tin is plated on the outer pin layer to form an electrical connection key.
  • a semiconductor device which includes: a lead frame, including leads, having a first surface and a second surface opposite to each other;
  • the lead frame is fixed on the first surface of the lead frame or the chip and the lead frame are arranged spaced apart; the first encapsulating layer encapsulates the chip and the lead frame; and the metal connector is located on the
  • the first encapsulating layer is on a side away from the lead frame, and includes a first connecting portion and a second connecting portion that are connected, the first connecting portion is connected to the pin, and the second connecting portion is connected to the chip
  • the conductive pillars on the front are connected.
  • the lead frame further includes a lead frame body arranged at intervals from the pins; correspondingly, the back of the chip faces the lead frame body and is fixed to the first surface of the lead frame body .
  • the semiconductor device further includes a second encapsulation layer that encapsulates the exposed part of the first encapsulation layer on the side where the metal connection member is provided, and the metal connection member
  • the semiconductor device further includes an outer lead layer and an electrical connection key, the outer lead layer is located on the second surface of the lead frame, and the electrical connection key is located on the outer lead layer.
  • the above-mentioned semiconductor device packaging method and the correspondingly formed semiconductor device provided by the embodiments of the present application are realized by providing metal connectors connecting the front surface of the chip and the pins on the front side of the chip and the side of the pins arranged spaced apart from the chip facing the front side of the chip.
  • the circuit inside the chip is led out from the side of the chip's back side, which is beneficial to increase the interconnection area between the chip and the lead frame, which is beneficial to increase the freedom of product design, and makes the size of the product in multiple directions free and controllable. It is beneficial to increase the heat dissipation area of the product and improve the heat dissipation performance of the product.
  • the leadless interconnection can effectively reduce impedance, increase current flow capacity, and have more freedom and flexibility in layout.
  • the chip surface is specially treated with no tin and has high processing efficiency; it will not be affected by materials such as flux, and the high-voltage characteristics of the product are more stable and reliable.
  • FIG. 1 is a flowchart of a method for packaging a semiconductor device according to an exemplary embodiment of the present application.
  • 2A-2M are process flow diagrams of a semiconductor device packaging method proposed according to an exemplary embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a semiconductor device obtained according to the semiconductor device packaging method shown in FIGS. 2A-2M.
  • 4A-4J are process flowcharts of a semiconductor device packaging method proposed according to another exemplary embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a semiconductor device obtained according to the semiconductor device packaging method shown in FIGS. 4A to 4J.
  • FIG. 1 is a flowchart of a method for packaging a semiconductor device according to an exemplary embodiment of the present application. As shown in FIG. 1, the semiconductor device packaging method includes the following steps S10 to S40.
  • Step S10 Mount the lead frame on the carrier board.
  • the lead frame includes pins, the lead frame has a first surface and a second surface opposite to each other, and the second surface of the lead frame faces the carrier board.
  • Step S20 Mount the chip.
  • the front surface of the chip is provided with conductive posts, the chip is mounted on the first surface of the lead frame and the back of the chip faces the lead frame, or the chip is mounted on the carrier board And the back of the chip faces the carrier board.
  • the so-called mounting can be direct contact or contact via a specific connector.
  • the chip when the chip is mounted on the carrier board, the chip may be fixed on the carrier board in direct contact with the carrier board, or the chip may be fixed on the carrier board via a specific connector.
  • Step S30 forming a first encapsulation layer on the carrier board.
  • the first encapsulation layer at least encapsulates the chip and the lead frame.
  • Step S40 forming a metal connector on the side of the first encapsulating layer away from the carrier board.
  • the metal connector includes a first connecting portion and a second connecting portion that are connected, the first connecting portion is connected to the pin, and the second connecting portion is connected to the conductive pillar of the chip.
  • metal connectors for connecting the chip and the pins are provided on one side of the first encapsulation layer (that is, the front side of the chip and the side with the pins facing the chip), so that the chip can be removed from the chip.
  • the side where the back is located leads to the circuit inside the chip, which is beneficial to increase the interconnection area between the chip and the lead frame, increase the flow capacity of the product, and increase the freedom of product design, so that the size of the product in multiple directions Free and controllable, it is beneficial to increase the heat dissipation area of the product and improve the heat dissipation performance of the product.
  • the semiconductor product formed by the semiconductor device packaging method of this embodiment has no lead interconnection, which can effectively reduce impedance, increase current flow capacity, and layout More freedom and flexibility.
  • the chip surface is specially treated with no tin and has high processing efficiency; it will not be affected by materials such as flux, and the high-voltage characteristics of the product are more stable and reliable ; More suitable for multi-chip interconnection design, suitable for multi-chip packaging.
  • the semiconductor products formed by the semiconductor device packaging method of this embodiment can draw out the circuits inside the chip from the side where the back of the chip is located. The heat dissipation area is increased, which helps the product to dissipate heat.
  • the circuits inside the chip are led away from the pins below the chip, and the product space utilization rate is high.
  • 2A-2M is a process flow diagram of a semiconductor device packaging method proposed according to an exemplary embodiment of the present application, which will be described below in conjunction with FIGS. 1 and 2A-2M.
  • the lead frame 300 is mounted on the carrier board 200.
  • the lead frame 300 includes a lead frame main body 301 and pins 302.
  • the lead frame 300 has a first surface 303 and a second surface 304 opposite to each other, and the second surface 304 of the lead frame faces the carrier board 200.
  • the second surface 304 of the lead frame faces the carrier board 200 and is mounted on the carrier board 200.
  • the lead frame 300 may be formed of a metal structure through etching and half etching.
  • the lead frame 300 can be mounted on the carrier board 200 at a predetermined position.
  • the lead frame 300 may be first arranged on the support plate to form a lead frame assembly.
  • the lead frame assembly is disposed on the carrier board 200 so that the side of the lead frame assembly on which the lead frame 300 is arranged faces the carrier board 200 and the lead frame 300 corresponds to a predetermined position.
  • the support plate is removed, and the lead frame 300 is exposed.
  • the support plate may be a transparent structural member, so that it will not affect the alignment of the lead frame 300 with the predetermined position.
  • a predetermined position for arranging the lead frame 300 can be pre-marked on the carrier 200 by means of laser, mechanical engraving, photoetching, etc., and at the same time, the lead frame 300 is also An alignment mark may be provided to aim and align the lead frame 300 with a predetermined position on the carrier board 200 during arrangement.
  • the lead frame 300 may be mounted on the carrier board 200 through an adhesive layer.
  • the adhesive layer can be made of an easily peelable material, so that the carrier 200 and the lead frame 300 can be peeled off in the subsequent process.
  • the adhesive layer may use a thermally separable material that can lose its viscosity by heating.
  • the adhesive layer can be formed on the carrier 200 by laminating, printing, or the like.
  • the chip 201 is mounted on the first surface 303 of the lead frame 300, specifically on the lead frame main body 301 of the lead frame 300. Wherein, the back side of the chip 201 faces the lead frame 300, and the front side of the chip 201 is provided with conductive posts 2011 and faces away from the lead frame 300.
  • the number of chips 201 may be one or more.
  • the chip 201 can also be mounted on the first surface 303 of the lead frame 300 according to a predetermined arrangement position.
  • the chip 201 can be mounted on the first surface 303 of the lead frame 300 through the adhesive layer 203.
  • the material of the glue layer 203 is not further limited here.
  • the conductive pillars 2011 on the front side of the chip 201 can be formed on the surface of the chip 201 by means of ultrasonic welding or the like.
  • the material of the conductive pillar 2011 can be copper or other metals with conductive properties.
  • step S30 as shown in FIG. 2C, a first encapsulation layer 204 is formed on the carrier 200, and the first encapsulation layer 204 at least encapsulates the chip 201 and the lead frame 300.
  • the first encapsulation layer 204 is formed on the front surface of the chip 201, the exposed lead frame 300, and the exposed carrier 200.
  • the first encapsulation layer 204 is used to completely encapsulate the exposed lead frame 300, the exposed carrier 200, and the chip 201, thereby reconstructing a flat panel structure. In this way, after the carrier board 200 is peeled off, wiring and packaging can be performed on the reconstructed flat panel structure.
  • the first encapsulation layer 204 may be formed by laminating epoxy resin film or molding film, or by injection molding or compression molding of the epoxy resin compound. (Compression molding) or transfer molding (Transfer molding) and other methods are formed.
  • a metal connector 209 is formed on the side of the first encapsulation layer 204 away from the carrier board 200. Specifically, a metal connector 209 is formed on the front side of the chip 201 and the lead 302 of the lead frame 300 away from the carrier board 200. As shown in FIG. 2M, the metal connecting member 209 includes a first connecting portion 2092 and a second connecting portion 2091 that are connected. The first connecting portion 2092 is connected to the pin 302 of the lead frame 300, and the second connecting portion 2091 is connected to the conductive pillar 2011 of the chip 201.
  • the metal connection member 209 may be formed by the process shown in FIGS. 2D to 2J.
  • the first surface 2041 of the first encapsulation layer 204 may be ground or polished to reduce the thickness of the first encapsulation layer 204.
  • the thickness of the first encapsulation layer 204 can be reduced to expose the conductive pillars 2011 on the front side of the chip 201.
  • an opening 205 is formed on the first encapsulation layer 204.
  • the pair of openings 205 are located at the pins 302 of the lead frame 300 to expose the pins 302.
  • the opening 205 can be formed by laser drilling with a laser. The laser drilling method is used to make the hole, and the hole opened is smaller, which is beneficial to the subsequent formation of the first connecting portion 2092 and the second connecting portion 2091 at the same time, and the position of the hole is more accurate.
  • the opening 205 can also be formed by directly performing mechanical drilling or chemical etching on the first encapsulation layer 204.
  • a seed layer 206 is formed on the side of the first encapsulation layer 204 away from the carrier 200, on the conductive pillars 2011 exposed on the front surface of the chip 201 and in the openings 205.
  • the seed layer 206 can be formed by sputtering.
  • the material of the seed layer 206 may be copper.
  • a photosensitive layer 207 is attached to the side of the seed layer 206 away from the carrier 200.
  • the photosensitive layer may be photoresist.
  • the photosensitive layer 207 is subjected to photolithography to form a photosensitive layer pattern, so that the seed layer 206 is located in the opening and the part on the conductive pillar 2011 of the chip 201 is exposed.
  • the photosensitive layer pattern can be understood as the vacancy portion 208 corresponding to the removed photosensitive layer material in the photosensitive layer 207.
  • the photosensitive layer pattern can be formed by exposure and development using a mask.
  • wires are routed in the opening 205 and the photosensitive layer pattern to form a metal connector 209.
  • the first connecting portion 2092 of the metal connector 209 is located in the opening 205 and connected to the pin 302, and the second connecting portion 2091 is located in the photosensitive layer pattern and connected to the conductive pillar 2011 of the chip 201.
  • the first connecting portion 2092 and the second connecting portion 2091 can be formed at the same time using a rewiring process, that is, the first connecting portion 2092 and the second connecting portion 2091 are formed integrally.
  • the integrated method effectively saves the process steps of forming the metal connecting piece 209, and the formed metal connecting piece 209 has a more stable structure.
  • the overall connection performance is also better.
  • the above-mentioned wiring in the opening 205 and the photosensitive layer pattern can also be realized by sputtering.
  • the material used for the wiring can be the same as the material of the seed layer 206, which is also a copper material, and the thickness of the metal layer formed by the wiring can be much larger than the thickness of the seed layer 206.
  • the seed layer 206 merges with the metal layer formed by the wiring to form a metal connection 209.
  • the photosensitive layer 207 is cleaned to partially clean the photosensitive layer 207 remaining after the photosensitive layer pattern is formed.
  • the seed layer 206 corresponding to the position of the remaining photosensitive layer 207 is also removed. That is, the part of the seed layer 206 covered by the metal connector 209 remains, and the rest is removed.
  • the second encapsulation layer 210 is formed on the side of the first encapsulation layer 204 away from the carrier board 200.
  • the second encapsulation layer 210 completely encapsulates the metal connector 209 and the first encapsulation layer 204 exposed on the side.
  • the second encapsulation layer 210 can be formed by laminating epoxy resin film or molding film.
  • the carrier 200 is peeled off to expose the second surface 304 of the lead frame 300, and an outer lead layer 212 is formed on the second surface 304 of the lead frame 300.
  • the carrier 200 can be mechanically peeled off directly.
  • the adhesive layer has a thermally separated material, the thermally separated material in the adhesive layer can be heated to reduce its viscosity after being heated.
  • the carrier 200 is peeled off. After the carrier 200 is peeled off, the second surface 2042 of the first encapsulating layer 204 facing the carrier 200 and the second surface 304 of the lead frame 300 are exposed. After the carrier 200 is peeled off, a flat structure including the chip 201, the lead frame 300, the metal connector 209 and the first encapsulation layer 204 is obtained. Furthermore, the outer lead layer 212 may be formed on the second surface 304 of the lead frame 300.
  • the outer pin layer 212 may be formed by a metal wiring method.
  • a photosensitive layer can be mounted on the plate structure including the chip 201, the lead frame 300, the metal connector 209 and the first encapsulation layer 204 obtained after the carrier 200 is peeled off, and the lead frame 300 can be exposed and developed.
  • a wiring opening is formed at the corresponding position, and then the outer pin layer 212 is formed at the wiring opening by electroplating.
  • the material of the outer pin layer 212 may be metallic copper.
  • the outer pin layer 212 can also be made of other conductive materials, which is not limited in this application, and can be set according to a specific application environment.
  • the thickness of the outer lead layer 212 may be 10 ⁇ m-50 ⁇ m. In fact, the thickness of the outer lead layer 212 can be set according to the specific product, which is not limited in this application.
  • tin is plated on the outer pin layer 212 to form the electrical connection key 211.
  • the material of the electrical connection key 211 may be tin, copper, nickel-based alloy or other metal materials capable of achieving electrical connection.
  • the electrical connection key 211 can be formed by soldering or electroplating.
  • the arrangement of the outer pin layer 212 is beneficial to improve the solder climbing ability. Compared with directly providing the electrical connection keys 211 on the lead frame 300 after the carrier board 200 is peeled off, the outer lead layer 212 is formed on the lead frame 300 and the electrical connection keys 211 are provided after the outer lead layer 212 is formed.
  • the electrical connection key 211 is easier to set up, and the setting effect of the electrical connection key 211 is better.
  • the electrical connection key 211 can wrap the outer pin layer 212.
  • the electrical connection key 211 completely wraps the exposed part of the outer pin layer 212.
  • the electrical connection key 211 may not completely wrap the outer pin layer 212, which is not limited in this application, and can be set according to a specific application environment.
  • the metal connecting member 209 may be formed by the following steps S411 to S413.
  • a seed layer 206 is formed on the side of the first encapsulation layer 204 away from the carrier 200, on the conductive pillars 2011 on the front of the chip 201, and in the openings 205 of the first encapsulation layer 204.
  • a seed layer 206 is formed on the side of the first encapsulation layer 204 away from the carrier 200, on the conductive pillars 2011 on the front of the chip 201, and in the openings 205 of the first encapsulation layer 204.
  • step S412 wiring is made on the side of the seed layer 206 away from the carrier 200 to form a first metal wiring layer.
  • the metal layer formed by the wiring and the seed layer are integrated to form the first metal wiring layer.
  • the first metal wiring layer is etched to form a metal connection member 209.
  • etching the first metal wiring layer can be understood as etching both the seed layer 206 formed in step S411 and the metal layer formed by the wiring in step S412.
  • the metal connection member 209 may be formed by a metal etching method such as photolithography.
  • the first connection portion 2092 and the second connection portion 2091 of the metal connection member 209 are simultaneously formed using the same rewiring process.
  • the metal connecting member 209 may be formed by the following steps S421 to S423.
  • a photosensitive layer 207 is attached to a side of the first encapsulation layer 204 away from the carrier 200 to form a photosensitive layer pattern.
  • the opening 205 communicates with the outside from the photosensitive layer pattern, so that the pins 302 of the lead frame 300 are exposed; and, the conductive pillars 2011 on the front of the chip 201 are also from the photosensitive layer pattern. Exposed.
  • step S422 wires are routed in the opening 205 and the photosensitive layer pattern to form a metal connector 209.
  • the first connecting portion 2092 of the metal connecting member 209 is located in the opening 205
  • the second connecting portion 2091 of the metal connecting member 209 is located in the photosensitive layer pattern.
  • the first connecting portion 2092 and the second connecting portion 2091 are simultaneously formed using the same rewiring process.
  • step S423 the remaining photosensitive layer 207 is removed.
  • step S421 to step S423 reference may be made to the relevant descriptions of the foregoing embodiments.
  • the metal connecting member 209 may be formed by the following steps S431 and S432.
  • a second metal wiring layer is formed on the side of the first encapsulation layer 204 away from the carrier 200, on the conductive pillars 2011 on the front side of the chip 201, and in the opening 205.
  • step S432 the second metal wiring layer is etched to form a metal connection member 209.
  • the first connecting portion 2092 located in the opening 205 and the second connecting portion 2091 located on the first encapsulation layer 204 of the metal connecting member 209 are simultaneously formed by the same rewiring process.
  • step S431 and step S432 reference may be made to the relevant descriptions of the foregoing embodiments.
  • step S10 as shown in FIG. 4A, the lead frame 500 is mounted on the carrier 400.
  • the lead frame 500 has a first surface 503 and a second surface 504 opposite to each other.
  • the difference from the lead frame 300 shown in FIG. 2A is that the lead frame 500 only includes pins (therefore, it may also be referred to as pins 500 hereinafter), and does not include the lead frame body.
  • pins 500 for the specific operation of attaching the lead frame 500, reference may be made to the related description of the embodiment shown in FIG. 2A, which will not be repeated here.
  • step S20 as shown in FIG. 4B, the chip 401 is mounted.
  • the back of the chip 401 faces the carrier 400 and is mounted on the carrier 400, so that the chip 401 and the lead frame 500 are arranged on the carrier at intervals Above 400.
  • the structure of the chip 401 may be the same as the structure of the aforementioned chip 201, and a conductive pillar 4011 is provided on the front surface of the chip 401.
  • the chip 401 can be mounted on the carrier through the adhesive layer 403.
  • the thickness of the semiconductor product formed in this embodiment can be made thinner.
  • step S30 as shown in FIG. 4C, a first encapsulation layer 404 is formed on the carrier 400, and the first encapsulation layer 404 at least encapsulates the chip 401 and the lead frame 500.
  • the first encapsulation layer 404 at least encapsulates the chip 401 and the lead frame 500.
  • a metal connector 409 is formed on the side of the first encapsulation layer 404 away from the carrier 400, including the front surface of the chip 401 and the side of the pins 500 away from the carrier 400.
  • the metal connecting member 409 includes a first connecting portion 4092 and a second connecting portion 4091 that are connected.
  • the first connecting portion 4092 of the metal connecting piece 409 is connected to the pin 500, and the second connecting portion 4091 of the metal connecting piece 409 is connected to the conductive pillar 4011 of the chip 401.
  • the metal connection member 409 may be formed by the process shown in FIGS. 4D to 4F.
  • the forming method of the metal connecting member 409 may be the same as the forming method of the metal connecting member 209 shown in FIGS. 2D to 2J, and reference may be made to the above related description.
  • the metal connecting member 409 can also be formed by the method of forming the metal connecting member in the other embodiments described above. For example, after the opening 405 is formed, a seed layer may be formed, and then wiring is formed on the seed layer to form a wiring layer, and finally the wiring layer is etched to form a metal connection 409.
  • a photosensitive layer may be attached and a photosensitive layer pattern may be formed, and then wiring may be routed in the photosensitive layer pattern and the opening 405, thereby forming the metal connection member 409.
  • a metal wiring layer can be formed directly on the side of the opening 405, the conductive pillar 4011 on the front of the chip 401, and the first encapsulation layer 404 away from the carrier 400, and then the metal wiring layer
  • the metal connector 409 is formed by etching.
  • the second encapsulation layer 410 may be further formed; and the carrier 400 may be further peeled off to form the outer pin layer 412 and the electrical connection keys 411.
  • the carrier 400 may be further peeled off to form the outer pin layer 412 and the electrical connection keys 411.
  • FIG. 3 it is a schematic structural diagram of a semiconductor device 1000 provided according to an embodiment of the present application, which can be obtained by the semiconductor device packaging method shown in FIGS. 2A-2M.
  • the semiconductor device 1000 includes a lead frame 300, a chip 201, a metal connector 209 and a first encapsulation layer 204.
  • the lead frame 300 includes a lead frame body 301 and pins 302.
  • the lead frame 300 has a first surface 303 and a second surface 304 opposite to each other.
  • the front surface of the chip 201 is provided with conductive pillars 2011, and the back surface of the chip 201 faces the lead frame 300 and is fixed to the first surface 303 of the lead frame main body 301.
  • the first encapsulation layer 204 encapsulates the chip 201 and the lead frame 300.
  • the metal connector 209 is located on the side of the first encapsulation layer 204 away from the lead frame 300 and the chip 201, and includes a first connection portion 2092 and a second connection portion 2091 that are connected.
  • the first connection portion 2092 is connected to the pin 302, and the second The connecting portion 2091 is connected to the conductive pillar 2011 on the front side of the chip 201.
  • the semiconductor device 1000 further includes a second encapsulation layer 210, and the second encapsulation layer 210 encapsulates the side of the first encapsulation layer 204 provided with the metal connection member 209 (that is, the first encapsulation layer 210).
  • the semiconductor device 1000 further includes an outer pin layer 212 and an electrical connection key 211.
  • the outer lead layer 212 is located on the second surface 304 of the lead frame 300, and the electrical connection key 211 is located on the outer lead layer 212.
  • the material of the electrical connection key 211 may be tin, copper, nickel-based alloy or other metal materials capable of achieving electrical connection.
  • the electrical connection key 211 can be formed by soldering or electroplating.
  • FIG. 5 it is a schematic structural diagram of a semiconductor device 2000 provided according to an embodiment of the present application, which can be obtained by the semiconductor device packaging method shown in FIGS. 4A-4J.
  • the semiconductor device 2000 includes a lead frame 500, a chip 401, a metal connector 409, and a first encapsulation layer 404.
  • the lead frame 500 may also be referred to as a pin 500.
  • the lead frame 500 has a first surface 503 and a second surface 504 opposite to each other, that is, the pin 500 has a first surface 503 and a second surface 504 opposite to each other.
  • the front surface of the chip 401 is provided with conductive posts 4011, and the chip 401 and the lead frame 500 are arranged side by side and spaced apart.
  • the metal connection member 409 is located on the side of the first encapsulation layer 404 away from the pin 500 and the chip 401, and includes a first connection portion 4092 and a second connection portion 4091 that are connected. Wherein, the first connecting portion 4092 is connected to the pin 500, and the second connecting portion 4091 is connected to the conductive pillar 4011 on the front surface of the chip 401.
  • the first encapsulation layer 404 encapsulates the chip 401 and the lead frame 500, and exposes the conductive posts 4011 on the front surface of the chip 401 so as to be able to be connected to the second connection portion 4091 and at least part of the lead frame 500 to be able to be connected to the first connection portion 4092.
  • the semiconductor device 2000 further includes a second encapsulation layer 410, and the second encapsulation layer 410 encapsulates the side of the first encapsulation layer 404 provided with the metal connector 409 (that is, the first encapsulation layer 410).
  • the semiconductor device 2000 further includes an outer pin layer 412 and an electrical connection key 411.
  • the outer lead layer 412 is located on the second surface 504 of the lead frame 500, and the electrical connection key 411 is located on the outer lead layer 412.
  • the material of the electrical connection key 411 can also be tin, copper, nickel-based alloy or other metal materials capable of achieving electrical connection.
  • the electrical connection key 411 can be formed by soldering or electroplating.
  • the semiconductor device provided by the foregoing embodiments of the present application can lead out the circuit inside the chip from the side where the back of the chip is located, so that the interconnect area between the chip and the lead frame is effectively improved, the product space utilization rate is high, and the product design freedom It can be increased, and the size of the semiconductor device in multiple directions is free and controllable.
  • its leadless interconnection can effectively reduce impedance, increase current flow capacity, and have a more free and flexible layout.
  • the chip surface is specially treated without tin and has high processing efficiency; it will not be affected by materials such as flux, and the high-voltage characteristics of the product are more stable and reliable High; more suitable for multi-chip interconnection design, suitable for multi-chip packaging.
  • semiconductor products formed by means of a carrier board and using fan-out wiring it realizes that the circuit inside the chip is drawn from the side where the back of the chip is located, increases the area of the heat dissipation layer, and helps the product to dissipate heat.
  • the structural embodiment and the method embodiment may be complementary to each other if there is no conflict.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本申请提供一种半导体装置封装方法及半导体装置。根据本申请的一个示例，该半导体装置封装方法包括：将引线框贴装于载板之上，该引线框包括有引脚，该引线框具有相对的第一表面和第二表面，该引线框的第二表面朝向所述载板；贴装芯片，该芯片的正面设有导电柱，该芯片贴装于所述引线框的第一表面之上且该芯片的背面朝向所述引线框，或该芯片贴装于所述载板之上而芯片的背面朝向所述载板；在所述载板上形成第一包封层，所述第一包封层至少包封所述芯片和所述引线框；在所述第一包封层远离所述载板的一侧形成金属连接件。其中，所述金属连接件包括相连的第一连接部和第二连接部，所述第二连接部与所述导电柱连接，且所述第一连接部与所述引脚连接。

Description

半导体装置封装方法及半导体装置 技术领域
本申请涉及半导体装置封装方法及半导体装置。
背景技术
在半导体封装工艺中，有些生产厂商采用引线键合的方式来实现芯片内部电路的引出。相关技术中，通常将芯片排布在引线框上，然后设置引线，以使得该引线的一端连接于芯片正面的焊垫、另一端连接于引线框的引脚。也有些生产厂商采用片状连接件键合的方式来实现芯片内部电路的引出，片状连接件的一端焊接于芯片正面的焊垫、另一端焊接于引线框的引脚。然而发明人(们)通过研究发现，采用引线键合的方式的半导体器件以及采用片状连接件键合的方式形成的半导体器件，其中芯片和引线框的互连面积较小，通流能力较差；并且，受限于引线框的尺寸，半导体器件的尺寸较为固定。
发明内容
本申请的一个方面提供一种半导体装置封装方法，其包括：将引线框贴装于载板之上，所述引线框包括有引脚，所述引线框具有相对的第一表面和第二表面，所述引线框的第二表面朝向所述载板；贴装芯片，所述芯片的正面设有导电柱，所述芯片贴装于所述引线框的第一表面之上且所述芯片背面朝向所述引线框，或所述芯片贴装于所述载板之上而所述芯片背面朝向所述载板；在所述载板上形成第一包封层，所述第一包封层至少包封所述芯片和所述引线框；在所述第一包封层远离所述载板的一侧形成金属连接件。其中，所述金属连接件包括相连的第一连接部和第二连接部，所述第一连接部与所述引脚连接，所述第二连接部与所述芯片的导电柱连接。其中，所述芯片与所述引脚间隔排布。根据一示例，所述引线框还包括与所述引脚间隔排布的引线框主体，所述芯片贴装于所述引线框主体的第一表面上，且所述芯片的背面朝向所述引线框主体。
可选的，在所述载板上形成第一包封层，以至少包封所述芯片和所述引线框，包括：在所述载板上形成第一包封层，以包封所述芯片和所述引线框；对所述第一包封层进行减薄，露出所述芯片正面的导电柱；在所述第一包封层上形成开孔，所述开孔对位于所述引线框的所述引脚。其中，所述开孔可采用激光开孔的方式形成。
可选的，所述第一连接部和第二连接部采用再布线工艺同时形成。
可选的，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：在所述第一包封层远离所述载板的一侧上、所述芯片正面的导电柱上以及所述开孔中形成种子层；在所述种子层远离所述载板的一侧贴设感光层；对所述感光层图案化以形成感光层图案，所述种子层位于开孔中以及位于所述芯片的导电柱之上的部分从所述感光层图案中露出；在所述开孔中及所述感光层图案中布线，形成金属连接件，所述金属连接件的第一连接部位于所述开孔，所述第二连接部位于所述感光层图案中；去除剩余的感光层，以及去除所述种子层中与所述剩余的感光层位置对应的部分。
可选的，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：在所述第一包封层远离所述载板的一侧上、所述芯片正面的导电柱上以及所述开孔中形成种子层；在所述种子层远离所述载板的一侧布线以形成第一金属布线层；对所述第一金属布线层进行刻蚀，形成金属连接件。
可选的，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：在所述第一包封层远离所述载板的一侧贴设感光层；对所述感光层图案化以形成感光层图案，所述开孔自所述感光层图案中与外界连通，所述引线框的引脚露出；在所述开孔中及所述感光层图案中布线，形成金属连接件，所述金属连接件的第一连接部位于所述开孔，所述第二连接部位于所述感光层图案中；去除剩余的感光层。
可选的，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：在所述第一包封层远离所述载板的一侧上、所述芯片正面的导电柱上以及所述开孔中形成第二金属布线层；对所述第二金属布线层进行刻蚀，形成金属连接件。
可选的，在形成金属连接件之后，所述半导体装置封装方法包括：在所述第一包封层远离所述载板的一侧形成第二包封层，所述第二包封层至少包封所述金属连接件和所述第一包封层在远离所述载板的一侧所露出的部分；剥离所述载板，露出所述引线框的第二表面；在所述引线框的第二表面形成外引脚层；在所述外引脚层上镀锡以形成电连接键。
本申请的一个方面提供一种半导体装置，其包括：引线框，包括有引脚，具有相对的第一表面和第二表面；芯片，所述芯片正面设有导电柱，所述芯片的背面朝向所述引线框并固定于引线框的第一表面或所述芯片与所述引线框间隔排布；第一包封层，包封所述芯片和所述引线框；金属连接件，位于所述第一包封层远离所述引线框的一侧，包括相连的第一连接部和第二连接部，所述第一连接部与所述引脚连接，所述第二连接部与所述芯片正面的导电柱连接。根据一示例，所述引线框还包括与所述引脚间隔排布的 引线框主体；相应地，所述芯片的背面朝向所述引线框主体，并固定于所述引线框主体的第一表面。
可选的，所述半导体装置还包括第二包封层，所述第二包封层包封所述第一包封层设有金属连接件的一侧所露出的部分以及所述金属连接件；或，所述半导体装置还包括外引脚层和电连接键，所述外引脚层位于所述引线框的第二表面，所述电连接键位于所述外引脚层之上。
本申请实施例提供的上述半导体装置封装方法及相应形成的半导体装置，通过在芯片的正面以及与芯片间隔布置的引脚朝向芯片正面的一侧设置连接芯片正面和引脚的金属连接件，实现了从芯片背面所在一侧引出芯片内部的电路，有利于提升了芯片与引线框之间的互连面积，有利于增加产品设计的自由度，使得产品的多个方向上的尺寸自由可控，有利于增加产品的散热面积，提高产品散热性能。此外，相对于采用引线键合的方式所形成的半导体产品而言，其无引线互连，能够有效减少阻抗，增加通流能力，布局更自由灵活。相对于采用片状连接件的方式所形成的半导体而言，芯片表面无锡特殊处理，加工效率高；不会受助焊剂等材料的影响，产品的高压特性更稳定，可靠性高。
附图说明
图1是根据本申请一示例性实施例提出的半导体装置封装方法的流程图。
图2A-图2M是根据本申请一示例性实施例提出的半导体装置封装方法的工艺流程图。
图3是根据图2A-图2M所示半导体装置封装方法得到的半导体装置的结构示意图。
图4A-图4J是根据本申请另一示例性实施例提出的半导体装置封装方法的工艺流程图。
图5是根据图4A-图4J所示半导体装置封装方法得到的半导体装置的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。事实上，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示两个或两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“上”和/或“下”等类似词语只是为了便于说明，而非限于一个位置或者一种空间定向。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
图1是根据本申请一示例性实施例提出的半导体装置封装方法的流程图。如图1所示，所述半导体装置封装方法包括下述步骤S10至S40。
步骤S10：将引线框贴装于载板之上。其中，所述引线框包括有引脚，所述引线框具有相对的第一表面和第二表面，所述引线框的第二表面朝向所述载板。
步骤S20：贴装芯片。其中，所述芯片的正面设有导电柱，所述芯片贴装于所述引线框的第一表面之上且所述芯片背面朝向所述引线框，或所述芯片贴装于所述载板之上而所述芯片背面朝向所述载板。此外，所谓贴装，可以是直接接触，也可以是经由特定的连接件接触。例如，芯片贴装于载板之上，可以是芯片与载板直接接触地固定于载板之上，也可以是芯片经由特定连接件地固定于载板之上。
步骤S30：在所述载板上形成第一包封层。其中，所述第一包封层至少包封所述芯片和所述引线框。
步骤S40：在所述第一包封层远离所述载板的一侧形成金属连接件。其中，所述金属连接件包括相连的第一连接部和第二连接部，所述第一连接部与所述引脚连接，所述第二连接部与所述芯片的导电柱连接。
本实施例的半导体装置封装方法，通过在第一包封层的一侧(即芯片的正面以及引脚朝向芯片的一侧)设置用于连接芯片与引脚的金属连接件，使得可从芯片背面所在的一侧引出芯片内部的电路，有利于提升芯片与引线框之间的互连面积，增加产品的通流能力，有利于增加产品设计的自由度，使得产品的多个方向上的尺寸自由可控，有利于增加产品的散热面积，提高产品散热性能。此外，相对于采用引线键合的方式所形成的 半导体产品而言，采用本实施例的半导体装置封装方法所形成的半导体产品，其无引线互连，能够有效减少阻抗，增加通流能力，布局更自由灵活。相对于采用片状连接件进行键合的方式所形成的半导体产品而言，芯片表面无锡特殊处理，加工效率高；不会受助焊剂等材料的影响，产品的高压特性更稳定，可靠性高；更适用于多芯片互连设计，适合多芯片封装。相对于借助载板并采用扇出布线的方式所形成的半导体产品而言，采用本实施例的半导体装置封装方法所形成的半导体产品，由于可从芯片背面所在一侧引出芯片内部的电路，增加了散热面积，有助于产品的散热。此外，芯片内部的电路从引脚远离芯片的下面引出，产品空间利用率高。
如图2A-图2M所示是根据本申请一示例性实施例提出的半导体装置封装方法的工艺流程图，如下结合图1和图2A-图2M所示进行说明。
在步骤S10中，如图2A所示，将引线框300贴装于载板200之上。其中，引线框300包括有引线框主体301和引脚302。引线框300具有相对的第一表面303和第二表面304，引线框的第二表面304朝向载板200。
将引线框的第二表面304朝向载板200，贴装于载板200之上。该引线框300可由金属结构通过蚀刻及半蚀刻等方法而形成。
具体实施时，可将引线框300按预定位置贴装于载板200上。比如，在一些实施例中，可先将引线框300排布于支撑板上形成引线框组件。进而将该引线框组件设于载板200，以使得该引线框组件的排布有引线框300的一面朝向载板200，并且引线框300与预定位置对应。最后，去除支撑板，露出引线框300。该支撑板可以是透明的结构件，如此不会影响引线框300与预定位置的对位。
需要说明的是，在设置引线框300之前，可采用激光、机械刻图、光刻等方式在载板200上预先标识出用于排布引线框300的预定位置，而同时引线框300上也可设置有对位标识，以在排布时将引线框300与载板200上的预定位置瞄准对位。
在一些可选实施例中，可以通过粘接层将引线框300贴装于载板200上。粘接层可采用易剥离的材料，以便在后续工序中，将载板200和引线框300剥离开来。例如，粘接层可采用通过加热能够使其失去粘性的热分离材料。在一实施例中，可通过层压、印刷等方式，在载板200上形成粘接层。
在步骤S20中，如图2B所示，在一些实施例中，将芯片201贴装于引线框300的第一表面303之上，具体贴装于引线框300的引线框主体301之上。其中，芯片201的 背面朝向引线框300，芯片201的正面设有导电柱2011并背离引线框300。
芯片201的数量可以是一个也可以是多个。芯片201同样可以按照预定的排布位置贴装于引线框300的第一表面303。
芯片201可通过胶层203贴装于引线框300的第一表面303。在此对胶层203的材料不做进一步限定。
芯片201正面的导电柱2011可以通过超声焊接等方式在芯片201表面形成。该导电柱2011的材料可以是铜，也可以是其他具有导电性能的金属。
在步骤S30中，如图2C所示，在载板200上形成第一包封层204，第一包封层204至少包封芯片201和引线框300。
在一些实施例中，如图2C所示，第一包封层204形成在芯片201的正面、露出的引线框300以及露出的载板200上。第一包封层204用于将露出的引线框300、露出的载板200以及芯片201完全包封住，从而重新构造一平板结构。这样，在将载板200剥离后，可在重新构造的该平板结构上进行布线和封装。
在一些实施例中，第一包封层204可采用层压环氧树脂膜或塑封膜(Molding film)的方式形成，也可以通过对环氧树脂化合物进行注塑成型(Injection molding)、压模成型(Compression molding)或转移成型(Transfer molding)等的方式形成。
在步骤S40中，在第一包封层204的远离载板200的一侧形成金属连接件209。具体地，在芯片201的正面以及引线框300的引脚302远离载板200的一侧形成金属连接件209。如图2M所示，该金属连接件209包括相连的第一连接部2092和第二连接部2091。第一连接部2092与引线框300的引脚302连接，第二连接部2091与芯片201的导电柱2011连接。
在一些实施例中，可通过如图2D至2J所示的工艺来形成金属连接件209。
在一些实施例中，在形成第一包封层204之后，可以通过对第一包封层204的第一表面2041进行研磨或抛光的方式，来减薄第一包封层204的厚度。
如图2D所示，第一包封层204的厚度可减薄至露出芯片201正面的导电柱2011。
如图2E所示，在第一包封层204上形成开孔205。其中开孔205对位于引线框300的引脚302处，以将引脚302暴露出来。开孔205可以通过镭射进行激光打孔而形成。采用激光开孔的方式进行开孔，其所开的孔较小，有利于后续第一连接部2092和第二 连接部2091的同时形成，且开孔位置更加精确。当然，在其它一些实施例中，也可通过直接在第一包封层204上进行机械打孔或者化学腐蚀等方法来形成开孔205。
如图2F所示，在第一包封层204远离载板200的一侧上、芯片201正面露出的导电柱2011上以及开孔205中形成种子层206。比如，可通过溅射的方式形成该种子层206。该种子层206的材料可以是铜。
如图2G所示，在种子层206远离载板200的一侧贴设感光层207。在一些实施例中，该感光层可以是光刻胶。
如图2H所示，对所述感光层207进行光刻形成感光层图案，使得种子层206位于开孔中以及位于芯片201的导电柱2011之上的部分外露。感光层图案可以理解为感光层207中被去除的感光层材料所对应的空缺部208。该感光层图案可以利用掩模版通过曝光显影的方式形成。
如图2I所示，在开孔205中及感光层图案中布线，形成金属连接件209。其中，金属连接件209的第一连接部2092位于开孔205中而与引脚302连接，第二连接部2091位于感光层图案中而与芯片201的导电柱2011连接。该第一连接部2092和第二连接部2091可采用再布线工艺同时形成，也即第一连接部2092和第二连接部2091为一体形成。相比于分别形成第一连接部2092和第二连接部2091的实施方式而言，一体形成的方法有效节省了形成金属连接件209的流程步骤，且所形成的金属连接件209结构更加稳固，整体的连接性能也更好。
上述在开孔205中及感光层图案中布线也可通过溅射的方式实现。布线所采用的材料可以与种子层206的材料一样，也是铜材料，且布线所形成的金属层厚度可比种子层206的厚度大的多。布线后，种子层206与此次布线所形成的金属层融合，形成金属连接件209。
如图2J所示，对感光层207进行清洗，将形成感光层图案后所剩余的感光层207部分清洗掉。
在对感光层207进行清洗之后，将与该剩余的感光层207位置所对应的种子层206也去除。即种子层206中被金属连接件209所覆盖的部分保留，其余部分均被去除。
进一步，如图2K所示，在一些实施例中，形成金属连接件209之后，在第一包封层204远离载板200的一侧形成第二包封层210。该第二包封层210将金属连接件209以及该侧所露出的第一包封层204完全包封。该第二包封层210可采用层压环氧树脂膜 或塑封膜(Molding film)的方式形成。
进一步，如图2L所示，剥离载板200，露出引线框300的第二表面304，并在引线框300的第二表面304形成外引脚层212。
在一些实施例中，可直接机械地剥离载板200。对于通过粘接层将引线框300设于载板200之上的，如果粘接层具有热分离材料时，还可以通过加热的方式使得粘接层中的热分离材料在遇热后降低粘性，进而剥离载板200。载板200剥离后，暴露出了朝向载板200的第一包封层204的第二表面2042和引线框300的第二表面304。剥离载板200后，得到了包括芯片201、引线框300、金属连接件209以及第一包封层204的平板结构。进而可以在引线框300的第二表面304形成外引脚层212。
在一些实施例中，该外引脚层212可采用金属布线的方法来形成。比如，可在剥离载板200后所得到的包括芯片201、引线框300、金属连接件209以及第一包封层204的平板结构上贴装感光层，通过曝光显影的方式在引线框300的对应位置处形成布线开口，进而在布线开口处通过电镀的方式形成外引脚层212。
在一些实施例中，该外引脚层212的材料可以是金属铜。当然，外引脚层212也可是其他导电材料，本申请对此不做限定，可根据具体应用环境进行设置。
在一些实施例中，该外引脚层212的厚度可为10μm～50μm。实际上，外引脚层212的厚度可根据具体产品进行设置，本申请对此不做限定。
进一步，如图2M所示，在一些实施例中，在形成外引脚层212之后，在外引脚层212上镀锡而形成电连接键211。
电连接键211的材料可以是锡、铜、镍基合金或其他能够实现电连接的金属材料。相应地，电连接键211可以通过焊锡的方式或者电镀的方式形成。
该外引脚层212的设置有利于提升爬锡能力。相比于在剥离载板200后直接在引线框300上设置电连接键211而言，在引线框300上形成外引脚层212并在形成外引脚层212之后再设置电连接键211，电连接键211更容易设置，且该电连接键211的设置效果更好。在一些实施例中，电连接键211能够包裹住外引脚层212。比如，如图2M所示，电连接键211将外引脚层212所露出的部分完全包裹住。当然，在其他一些实施例中，电连接键211也可不完全包裹住外引脚层212，本申请对此不做限定，可根据具体应用环境进行设置。
在另一些实施例中，在第一包封层204上形成上述图2E所示的开孔205之后，还 可以通过如下步骤S411至步骤S413形成金属连接件209。
在步骤S411中，在第一包封层204远离载板200的一侧上、芯片201正面的导电柱2011上以及第一包封层204的开孔205中形成种子层206，具体可参照上述图2F所示的相关描述。
在步骤S412中，在种子层206远离载板200的一侧布线以形成第一金属布线层。在种子层206远离载板200的一侧布线时，该布线所形成的金属层与种子层融为一体，共同形成该第一金属布线层。
在步骤S413中，对第一金属布线层进行刻蚀，形成金属连接件209。具体地，对第一金属布线层进行刻蚀，可以理解为对于步骤S411所形成的种子层206以及步骤S412中布线所形成的金属层均进行刻蚀。具体可以通过光刻等金属刻蚀方式形成金属连接件209。金属连接件209的具体结构等可参考上述相关描述，此处不予以赘述。该实施例中，金属连接件209的第一连接部2092和第二连接部2091采用同一再布线工艺同时形成。
在另一些实施例中，在第一包封层204上形成上述图2E所示的开孔205之后，还可以通过如下步骤S421至步骤S423形成金属连接件209。
在步骤S421中，在所述第一包封层204远离所述载板200的一侧贴设感光层207并形成感光层图案。其中，所述开孔205自所述感光层图案中与外界连通，以使得所述引线框300的引脚302露出；并且，所述芯片201正面的导电柱2011也自所述感光层图案中露出。
在步骤S422中，在所述开孔205及所述感光层图案中布线，形成金属连接件209。其中，所述金属连接件209的第一连接部2092位于所述开孔205，所述金属连接件209的第二连接部2091位于所述感光层图案中。该第一连接部2092和第二连接部2091采用同一再布线工艺同时形成。
在步骤S423中，去除剩余的感光层207。
步骤S421至步骤S423的具体实施方式可参照上述各实施例的相关描述。
在其它一些实施例中，在第一包封层204上形成上述图2E所示的开孔205之后，还可以通过如下步骤S431和步骤S432形成金属连接件209。
在步骤S431中，在所述第一包封层204远离所述载板200的一侧上、所述芯片201 正面的导电柱2011上以及所述开孔205中形成第二金属布线层。
在步骤S432中，对所述第二金属布线层进行刻蚀，形成金属连接件209。该金属连接件209的位于开孔205内的第一连接部2092和位于第一包封层204上的第二连接部2091采用同一再布线工艺同时形成。
步骤S431和步骤S432的具体实施方式可参照上述各实施例的相关描述。
如图4A-图4J所示是根据本申请另一示例性实施例提出的半导体装置封装方法的工艺流程图。如下结合图1和图4A-图4J所示进行说明。在步骤S10中，如图4A所示，将引线框500贴装于载板400之上。该引线框500具有相对的第一表面503和第二表面504。与上述图2A所示引线框300不同的是，该引线框500仅包括引脚(故以下也可称为引脚500)，而不包括引线框主体。贴装引线框500的具体操作可参考上述图2A所示实施方式的相关描述，此处不予以赘述。
在步骤S20中，如图4B所示，贴装芯片401。与上述图2B所示实施方式不同的是，本实施例中，将芯片401的背面朝向载板400并贴装于载板400之上，使得该芯片401与引线框500间隔排布于载板400之上。其中，芯片401的结构与上述芯片201的结构可相同，该芯片401的正面设有导电柱4011。芯片401可通过胶层403贴装于载板之上。相较于上述将芯片201贴设于引线框主体301的实施方式而言，本实施例所形成的半导体产品，其厚度可以做到更薄。其他相同或相似的操作可参照上述图2B所示实施方式的相关描述，此处不予以赘述。
在步骤S30中，如图4C所示，在载板400上形成第一包封层404，第一包封层404至少包封芯片401和引线框500。具体可参照上述图2C实施方式的相关描述，此处不予以赘述。
在步骤S40中，在第一包封层404的远离载板400的一侧，包括芯片401的正面以及引脚500远离载板400的一侧上，形成金属连接件409。该金属连接件409包括相连的第一连接部4092和第二连接部4091。其中，该金属连接件409的第一连接部4092与引脚500连接，该金属连接件409的第二连接部4091与芯片401的导电柱4011连接。
在一些实施例中，可通过如图4D至图4F所示的工艺来形成金属连接件409。具体的，在一些实施例中，该金属连接件409的形成方式可与上述图2D至图2J所示的金属连接件209的形成方式一样，可参考上述相关描述。当然，该金属连接件409同样可以采用上述其他实施方式中形成金属连接件的方式而形成。比如，在形成开孔405之后， 可以形成种子层，而后在种子层上布线形成布线层，最后对布线层进行刻蚀而形成金属连接件409。再比如，在形成开孔405之后可以贴设感光层并形成感光层图案，再在感光层图案及开孔405中布线，从而形成金属连接件409。还比如，在形成开孔405之后可直接在开孔405、芯片401正面的导电柱4011及第一包封层404远离载板400的一侧布线形成一金属布线层，再对该金属布线层刻蚀而形成金属连接件409。具体可参考上述相关描述，此处不予以赘述。
进一步，如图4G至图4J所示，在形成金属连接件409之后，可进一步形成第二包封层410；以及，可进一步剥离载板400，形成外引脚层412以及电连接键411。具体可参照上述图2K至图2M所示实施方式的相关描述，此处不予以赘述。
如图3所示，是根据本申请的实施例提供的半导体装置1000的结构示意图，其可利用上述图2A-图2M所示半导体装置封装方法得到。该半导体装置1000包括引线框300、芯片201、金属连接件209以及第一包封层204。
引线框300包括有引线框主体301和引脚302。且该引线框300具有相对的第一表面303和第二表面304。
芯片201的正面设有导电柱2011，芯片201的背面朝向引线框300并固定于引线框主体301的第一表面303。
第一包封层204包封芯片201及引线框300。
金属连接件209位于第一包封层204远离引线框300及芯片201的一侧，包括相连的第一连接部2092和第二连接部2091，第一连接部2092与引脚302连接，第二连接部2091与芯片201正面的导电柱2011连接。
进一步，在一些实施例中，半导体装置1000还包括第二包封层210，第二包封层210包封第一包封层204设有金属连接件209的一侧(也即第一包封层204远离引线框300的一侧)所露出的部分以及金属连接件209的第一连接部2092和第二连接部2091。
进一步，在一些实施例中，半导体装置1000还包括外引脚层212和电连接键211。该外引脚层212位于引线框300的第二表面304，电连接键211位于外引脚层212之上。该电连接键211的材料可以是锡、铜、镍基合金或其他能够实现电连接的金属材料。相应地，该电连接键211可以通过焊锡的方式或者电镀的方式形成。
如图5所示，是根据本申请的实施例提供的半导体装置2000的结构示意图，其可利用上述图4A-图4J所示半导体装置封装方法得到。该半导体装置2000包括引线框500、 芯片401、金属连接件409以及第一包封层404。
引线框500也可称为引脚500。且该引线框500具有相对的第一表面503和第二表面504，即该引脚500具有相对的第一表面503和第二表面504。
芯片401的正面设有导电柱4011，芯片401与引线框500并排间隔排布。
金属连接件409位于第一包封层404远离引脚500及芯片401的一侧，包括相连的第一连接部4092和第二连接部4091。其中，第一连接部4092与引脚500连接，第二连接部4091与芯片401正面的导电柱4011连接。
第一包封层404包封芯片401及引线框500，并露出芯片401正面的导电柱4011以能够与第二连接部4091连接及引线框500的至少部分以能够与第一连接部4092连接。
进一步，在一些实施例中，半导体装置2000还包括第二包封层410，第二包封层410包封第一包封层404设有金属连接件409的一侧(也即第一包封层404远离引线框500的一侧)所露出的部分以及金属连接件409的第一连接部4092和第二连接部4091。
进一步，在一些实施例中，半导体装置2000还包括外引脚层412和电连接键411。该外引脚层412位于引线框500的第二表面504，电连接键411位于外引脚层412之上。该电连接键411的材料同样可以是锡、铜、镍基合金或其他能够实现电连接的金属材料。相应地，该电连接键411可以通过焊锡的方式或者电镀的方式形成。
本申请上述实施例提供的半导体装置，其能够从芯片背面所在一侧引出芯片内部的电路，使得芯片与引线框之间的互连面积得到有效提升，产品空间利用率高，产品设计的自由度得以增加，且半导体装置的多个方向上的尺寸自由可控。相对于采用引线键合的方式所形成的半导体产品而言，其无引线互连，能够有效减少阻抗，增加通流能力，布局更自由灵活。相对于采用片状连接件进行键合的方式所形成的半导体产品而言，其芯片表面无锡特殊处理，加工效率高；不会受助焊剂等材料的影响，产品的高压特性更稳定，可靠性高；更适用于多芯片互连设计，适合多芯片封装。相对于借助载板并采用扇出布线的方式所形成的半导体产品而言，其实现了从芯片背面所在一侧引出芯片内部的电路，增加了散热层面积，有助于产品的散热。
在本申请中，所述结构实施例与方法实施例在不冲突的情况下，可以互为补充。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (14)

  1. 一种半导体装置封装方法，包括：
    将引线框贴装于载板之上，其中，所述引线框包括有引脚，所述引线框具有相对的第一表面和第二表面，所述引线框的第二表面朝向所述载板；
    贴装芯片，其中，所述芯片的正面设有导电柱，所述芯片贴装于所述引线框的第一表面之上且所述芯片的背面朝向所述引线框，或所述芯片贴装于所述载板之上而所述芯片的背面朝向所述载板；
    在所述载板上形成第一包封层，其中，所述第一包封层至少包封所述芯片和所述引线框；
    在所述第一包封层远离所述载板的一侧形成金属连接件，其中，所述金属连接件包括相连的第一连接部和第二连接部，所述第一连接部与所述引脚连接，所述第二连接部与所述芯片的导电柱连接。
  2. 如权利要求1所述的半导体装置封装方法，其特征在于，
    所述引线框还包括与所述引脚间隔排布的引线框主体，
    所述芯片贴装于所述引线框的第一表面之上且所述芯片背面朝向所述引线框，包括：所述芯片贴装于所述引线框主体的第一表面上，且所述芯片的背面朝向所述引线框主体。
  3. 如权利要求1或2所述的半导体装置封装方法，其特征在于，所述芯片与所述引脚间隔排布。
  4. 如权利要求1至3中任一所述的半导体装置封装方法，其特征在于，在所述载板上形成第一包封层，以至少包封所述芯片和所述引线框，包括：
    在所述载板上形成第一包封层，以包封所述芯片和所述引线框；
    对所述第一包封层进行减薄，露出所述芯片正面的导电柱；
    在所述第一包封层上形成开孔，其中，所述开孔对位于所述引线框的所述引脚。
  5. 如权利要求4所述的半导体装置封装方法，其特征在于，所述开孔采用激光开孔的方式形成。
  6. 如权利要求1至5中任一所述的半导体装置封装方法，其特征在于，所述第一连接部和第二连接部采用再布线工艺同时形成。
  7. 如权利要求4所述的半导体装置封装方法，其特征在于，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：
    在所述第一包封层远离所述载板的一侧上、所述芯片正面的导电柱上以及所述开孔中形成种子层；
    在所述种子层远离所述载板的一侧贴设感光层；
    对所述感光层图案化以形成感光层图案，其中，所述种子层位于所述开孔中以及所述芯片的导电柱之上的部分从所述感光层图案中露出；
    在所述开孔及所述感光层图案中布线，形成所述金属连接件，其中，所述金属连接件的第一连接部位于所述开孔中，所述第二连接部位于所述感光层图案中；
    去除剩余的所述感光层；以及
    去除所述种子层中与所述剩余的感光层位置对应的部分。
  8. 如图权利要求4所述的半导体装置封装方法，其特征在于，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：
    在所述第一包封层远离所述载板的一侧上、所述芯片正面的导电柱上以及所述开孔中形成种子层；
    在所述种子层远离所述载板的一侧布线以形成第一金属布线层；
    对所述第一金属布线层进行刻蚀，形成所述金属连接件。
  9. 如权利要求4所述的半导体装置封装方法，其特征在于，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：
    在所述第一包封层远离所述载板的一侧贴设感光层；
    对所述感光层图案化以形成感光层图案，其中，所述开孔自所述感光层图案中与外界连通，所述引线框的所述引脚露出；
    在所述开孔中及所述感光层图案中布线，形成所述金属连接件，其中，所述金属连接件的第一连接部位于所述开孔，所述第二连接部位于所述感光层图案中；
    去除剩余的所述感光层。
  10. 如权利要求4所述的半导体装置封装方法，其特征在于，在所述第一包封层远离所述载板的一侧形成金属连接件，包括：
    在所述第一包封层远离所述载板的一侧上、所述芯片正面的导电柱上以及所述开孔中形成第二金属布线层；
    对所述第二金属布线层进行刻蚀，形成所述金属连接件。
  11. 如权利要求1至10中任一所述的半导体装置封装方法，其特征在于，在形成所述金属连接件之后，所述半导体装置封装方法包括：
    在所述第一包封层远离所述载板的一侧形成第二包封层，其中，所述第二包封层至少包封所述金属连接件和所述第一包封层在远离所述载板的一侧所露出的部分；
    剥离所述载板，露出所述引线框的第二表面；
    在所述引线框的第二表面形成外引脚层；
    在所述外引脚层上镀锡以形成电连接键。
  12. 一种半导体装置，包括：
    引线框，包括有引脚，具有相对的第一表面和第二表面；
    芯片，所述芯片的正面设有导电柱，所述芯片的背面朝向所述引线框并固定于所述引线框的第一表面或所述芯片与所述引线框间隔排布；
    第一包封层，包封所述芯片和所述引线框；
    金属连接件，位于所述第一包封层远离所述引线框的一侧，包括相连的第一连接部和第二连接部，所述第一连接部与所述引脚连接，所述第二连接部与所述芯片正面的导电柱连接。
  13. 如权利要求12所述的半导体装置，其特征在于，
    所述引线框还包括与所述引脚间隔排布的引线框主体；
    所述芯片的背面朝向所述引线框并固定于所述引线框的第一表面，包括：所述芯片的背面朝向所述引线框主体，并固定于所述引线框主体的第一表面。
  14. 如权利要求12所述的半导体装置，其特征在于，
    所述半导体装置还包括第二包封层，所述第二包封层包封所述第一包封层设有金属连接件的一侧所露出的部分以及所述金属连接件；或，
    所述半导体装置还包括外引脚层和电连接键，所述外引脚层位于所述引线框的第二表面，所述电连接键位于所述外引脚层之上。
PCT/CN2020/141626 2020-06-22 2020-12-30 半导体装置封装方法及半导体装置 WO2021258706A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010576178.6A CN111739810B (zh) 2020-06-22 2020-06-22 半导体封装方法及半导体装置
CN202010576178.6 2020-06-22

Publications (1)

Publication Number Publication Date
WO2021258706A1 true WO2021258706A1 (zh) 2021-12-30

Family

ID=72650445

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/141626 WO2021258706A1 (zh) 2020-06-22 2020-12-30 半导体装置封装方法及半导体装置

Country Status (2)

Country Link
CN (1) CN111739810B (zh)
WO (1) WO2021258706A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739810B (zh) * 2020-06-22 2022-09-30 矽磐微电子(重庆)有限公司 半导体封装方法及半导体装置
CN112701049A (zh) * 2020-12-22 2021-04-23 杰群电子科技（东莞）有限公司 一种半导体模块的封装方法及半导体模块
CN113327900A (zh) * 2021-06-18 2021-08-31 广东佛智芯微电子技术研究有限公司 基于铜箔载板的高散热板级扇出封装结构及其制备方法
CN114497234B (zh) * 2022-01-25 2022-12-06 先之科半导体科技(东莞)有限公司 一种低损耗小体积的肖特基二极管

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514080A (zh) * 2014-10-11 2016-04-20 意法半导体有限公司 具有再分布层和加强件的电子器件及相关方法
CN106328619A (zh) * 2015-06-30 2017-01-11 台湾积体电路制造股份有限公司 3d封装件结构及其形成方法
CN107293518A (zh) * 2016-04-13 2017-10-24 台湾积体电路制造股份有限公司 叠层封装结构及其形成方法
CN108172551A (zh) * 2016-11-29 2018-06-15 Pep创新私人有限公司 芯片封装方法及封装结构
CN111739810A (zh) * 2020-06-22 2020-10-02 矽磐微电子(重庆)有限公司 半导体封装方法及半导体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04171775A (ja) * 1990-11-02 1992-06-18 Sumitomo Electric Ind Ltd 発光ダイオードチップ及びその製造方法
US5670418A (en) * 1996-12-17 1997-09-23 International Business Machines Corporation Method of joining an electrical contact element to a substrate
JP2009016608A (ja) * 2007-07-05 2009-01-22 Mitsui High Tec Inc 半導体装置及びその製造方法
WO2009084597A1 (ja) * 2007-12-28 2009-07-09 Mitsui High-Tec, Inc. 半導体装置の製造方法及び半導体装置、半導体装置の中間製品の製造方法及び半導体装置の中間製品、並びにリードフレーム
CN101335218A (zh) * 2008-07-30 2008-12-31 江苏长电科技股份有限公司 金属平板式新型半导体封装方法
US7915082B2 (en) * 2008-10-23 2011-03-29 Infineon Technologies Ag Semiconductor device
CN202275822U (zh) * 2010-04-28 2012-06-13 先进封装技术私人有限公司 半导体封装件以及其基板
CN103824784B (zh) * 2010-05-05 2016-10-12 万国半导体有限公司 用连接片实现连接的半导体封装的方法
CN104505382A (zh) * 2014-12-30 2015-04-08 华天科技（西安）有限公司 一种圆片级扇出PoP封装结构及其制造方法
CN104779220A (zh) * 2015-03-27 2015-07-15 矽力杰半导体技术(杭州)有限公司 一种芯片封装结构及其制造方法
CN106684050A (zh) * 2017-01-25 2017-05-17 江苏长电科技股份有限公司 一种金属柱导通埋芯片线路板结构及其工艺方法
CN109494202B (zh) * 2017-09-12 2023-01-31 Pep创新私人有限公司 一种半导体芯片封装方法及封装结构
US11127661B2 (en) * 2018-06-13 2021-09-21 Tongfu Microelectronics Co., Ltd. Semiconductor chip package method and semiconductor chip package device
CN210467806U (zh) * 2019-11-20 2020-05-05 长华科技股份有限公司 具有外凸微型引脚的半导体封装组件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514080A (zh) * 2014-10-11 2016-04-20 意法半导体有限公司 具有再分布层和加强件的电子器件及相关方法
CN106328619A (zh) * 2015-06-30 2017-01-11 台湾积体电路制造股份有限公司 3d封装件结构及其形成方法
CN107293518A (zh) * 2016-04-13 2017-10-24 台湾积体电路制造股份有限公司 叠层封装结构及其形成方法
CN108172551A (zh) * 2016-11-29 2018-06-15 Pep创新私人有限公司 芯片封装方法及封装结构
CN111739810A (zh) * 2020-06-22 2020-10-02 矽磐微电子(重庆)有限公司 半导体封装方法及半导体装置

Also Published As

Publication number Publication date
CN111739810A (zh) 2020-10-02
CN111739810B (zh) 2022-09-30

Similar Documents

Publication Publication Date Title
WO2021258706A1 (zh) 半导体装置封装方法及半导体装置
TWI255538B (en) Semiconductor package having conductive bumps on chip and method for fabricating the same
JP5690466B2 (ja) 半導体チップパッケージの製造方法
TWI241700B (en) Packaging assembly with integrated circuits redistribution routing semiconductor die and method for fabrication
TWI316749B (en) Semiconductor package and fabrication method thereof
US6515361B2 (en) Cavity down ball grid array (CD BGA) package
TWI260060B (en) Chip electrical connection structure and fabrication method thereof
JP5605222B2 (ja) ３次元実装半導体装置及びその製造方法
TWI352412B (en) Multi-chip package structure and method of fabrica
TW201916197A (zh) 包含雙面重佈層之堆疊半導體封裝組件
TW201041103A (en) Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
JP2008244437A (ja) ダイ収容開口部を備えたイメージセンサパッケージおよびその方法
JP2002246535A (ja) 半導体集積回路
US20100230823A1 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device
TW200421960A (en) Semiconductor device, and the manufacturing method of the same
TWI279175B (en) Circuit board structure and method for fabricating the same
TWM563659U (zh) 薄膜覆晶封裝結構
JP2009070882A (ja) 半導体チップパッケージ及びその製造方法
US6936927B2 (en) Circuit device having a multi-layer conductive path
TW202322333A (zh) 一種雙面互聯嵌入式晶片封裝結構及其製造方法
TW200910561A (en) Packaging substrate structure with capacitor embedded therein and method for fabricating the same
TW200910560A (en) Packaging substrate structure with capacitor embedded therein and method for fabricating the same
CN110718529A (zh) 半导体装置以及半导体装置的制造方法
TWI615936B (zh) 基板結構及其製法
TW201123391A (en) Lead frame and manufacturing method of the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20941591

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20941591

Country of ref document: EP

Kind code of ref document: A1