WO2021249509A1 - 半导体装置和包括该半导体装置的电子设备 - Google Patents

半导体装置和包括该半导体装置的电子设备 Download PDF

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WO2021249509A1
WO2021249509A1 PCT/CN2021/099498 CN2021099498W WO2021249509A1 WO 2021249509 A1 WO2021249509 A1 WO 2021249509A1 CN 2021099498 W CN2021099498 W CN 2021099498W WO 2021249509 A1 WO2021249509 A1 WO 2021249509A1
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layer
chip
semiconductor
hole
semiconductor device
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PCT/CN2021/099498
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English (en)
French (fr)
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徐焰
姬忠礼
陈余
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华为技术有限公司
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Priority to EP21822556.3A priority Critical patent/EP4152375A4/en
Priority to KR1020237000555A priority patent/KR20230021717A/ko
Publication of WO2021249509A1 publication Critical patent/WO2021249509A1/zh
Priority to US18/063,529 priority patent/US20230104555A1/en

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Definitions

  • the embodiments disclosed in the present application relate to the field of semiconductor technology, and more specifically to semiconductor devices and electronic equipment including the semiconductor devices.
  • 3D IC three-dimensional integrated circuit
  • heat may accumulate in the internal area at the bottom of the chip stack, resulting in significant local temperatures Peak (also called hot spot).
  • Peak also called hot spot
  • hot spots caused by the heat generated by high-power chips may cause thermal crosstalk to surrounding chips, thereby adversely affecting the performance of surrounding chips and the reliability of the entire 3D IC package.
  • This kind of local hot issues discussed using 3D IC as an example also widely exists in other semiconductor chip packaging structures (for example, 2.5D IC packaging).
  • the present application provides a semiconductor device for solving the problem of local hot spots in the semiconductor device to a certain extent.
  • the present application also provides an electronic device, which includes the aforementioned semiconductor device.
  • a semiconductor device includes: a first semiconductor layer; a second chip; a heat conduction layer, which is stacked with the first semiconductor layer and the second chip and is located between the first semiconductor layer and the second chip, and For conducting heat from the first semiconductor layer and/or the second chip in the thermally conductive layer, the thermal conductivity of the thermally conductive layer in the horizontal direction is greater than or equal to the thermal conductivity in the vertical direction; and the first electrical conductivity
  • the pillar penetrates the thermally conductive layer, so that the first semiconductor layer and the second chip are electrically interconnected through the first conductive pillar, wherein the first conductive pillar is electrically insulated from the thermally conductive layer, so
  • the extension direction of the first conductive pillar is the vertical direction, and the thermal conductivity of the thermal conductive layer in the horizontal direction is greater than the thermal conductivity of the first semiconductor layer.
  • the first semiconductor layer and/or the second chip may generate heat during operation, and the heat may be unevenly distributed in the horizontal direction. Since the thermal conductive layer is stacked on the first semiconductor layer and the second chip, and the thermal conductivity of the thermal conductive layer in the horizontal direction is greater than or equal to the thermal conductivity in the vertical direction, the heat can be diffused in the horizontal direction to achieve the effect of horizontal heat. , Thereby slowing down or eliminating the effect of local hot spots.
  • a first conductive pillar is arranged in the thermally conductive layer to realize electrical interconnection between the first semiconductor layer and the second chip. Since the thermal conductive layer is usually also a conductive material, by electrically isolating the thermal conductive layer from the first conductive pillar, the electrical function of the first conductive pillar will not be affected, ensuring that the semiconductor device can work normally.
  • the thermally conductive layer has a plurality of through holes, and one or more of the first conductive pillars penetrate through one of the through holes.
  • the number of through holes and conductive pillars can be determined according to the specific requirements of the chip. Generally speaking, the interconnection between chips is achieved through multiple vias.
  • the size of the conductive pillar is usually determined by the semiconductor manufacturing process and the size and performance of the chip. Because the large-diameter through hole is easier to manufacture, the cost is lower. Therefore, in order to reduce the production cost of the thermally conductive layer, a through hole capable of accommodating a plurality of conductive pillars may be used. In some cases, in order to improve the thermal soaking performance, smaller through holes can be made so as to retain the thermal conductive layer as much as possible. That is, one through hole only accommodates one conductive pillar.
  • the thermally conductive layer and the first semiconductor layer are bonded and connected.
  • Bonded connection is a connection without adhesive and no soldering layer, which can significantly reduce the thermal resistance between the thermally conductive layer and the first semiconductor layer, so that heat can be rapidly expanded in the horizontal direction through the thermally conductive layer to improve the heat equalization effect.
  • the semiconductor device further includes an insulating material, the insulating material covers the surface of the thermally conductive layer, and the first conductive pillar also penetrates the insulating material.
  • the insulating material covers the surface of the heat-conducting layer, the conductive path between the heat-conducting layer and other components is cut off, so that the electrical operation of the semiconductor device will not be affected.
  • the semiconductor device further includes an insulating layer arranged to at least partially surround the first conductive pillar and extend along the first conductive pillar for connecting the first conductive pillar and the first conductive pillar.
  • the thermal conductive layer is isolated to achieve electrical insulation.
  • the first conductive pillar By arranging an insulating layer around the first conductive pillar, the first conductive pillar can be electrically insulated from the heat conductive layer.
  • the semiconductor device further includes: a filling material arranged in the thermally conductive layer and located between the thermally conductive layer and the insulating layer.
  • the filling material is compatible with a through silicon via (TSV) process
  • TSV through silicon via
  • the through silicon via refers to an electrical interconnection realized by filling a conductive material in a through hole of a silicon wafer.
  • the process of perforating the filling material can be achieved by using a known semiconductor manufacturing process, thereby having good process compatibility.
  • the first semiconductor layer is a first chip or a first interconnection layer.
  • the first conductive pillar when the first semiconductor layer is the first chip, the first conductive pillar also penetrates the first chip.
  • the semiconductor device further includes: a third semiconductor layer arranged on a side of the first semiconductor layer away from the thermally conductive layer, and the third semiconductor layer is electrically coupled with the conductive pillar.
  • the thermally conductive layer includes a carbon-based material, a metal material, or a combination thereof.
  • the carbon-based material includes a graphene film.
  • the thickness of the thermally conductive layer is at least 5um.
  • an electronic device including: the semiconductor device according to the first aspect.
  • the electronic device includes: a switch, a router, a mobile phone, a personal digital assistant (PDA), a navigation device, a set-top box, a music player, or a video player.
  • PDA personal digital assistant
  • a heat spreader comprising: a carbon-based material layer, the thermal conductivity of the carbon-based material layer in the horizontal direction is greater than or equal to the thermal conductivity in the vertical direction; and, a first non-metal pillar, Through the carbon-based material layer, the extending direction of the first non-metallic pillar is the vertical direction, the material of the first non-metallic pillar is insulating or semiconductor, wherein the first non-metallic pillar and the The contact part of the carbon-based material layer is an insulating material.
  • the heat spreading sheet can be used in the semiconductor packaging structure to heat the chips in the semiconductor packaging structure.
  • the first non-metallic pillar allows an electrical interconnection structure to be fabricated therein, and therefore, the semiconductor chip is uniformly heated without affecting its electrical performance. Since the portion of the first non-metallic pillar in contact with the carbon-based material layer is an insulating material, if a conductive pillar is formed in the first non-metallic pillar, the insulating material can achieve electrical insulation to the conductive pillar.
  • the surface roughness of the thermally conductive layer is less than or equal to 1 nm.
  • the diameter of the first non-metal pillar is between 10 ⁇ m and 40 ⁇ m.
  • FIG. 1A shows a cross-sectional view of a semiconductor device according to some embodiments disclosed in the present application
  • FIG. 1B shows a cross-sectional view of a semiconductor device according to some embodiments disclosed in the present application
  • FIG. 2 shows a cross-sectional view of a CoWoS packaged semiconductor device according to the conventional technology
  • 3A shows a cross-sectional view of a CoWoS packaged semiconductor device according to some embodiments disclosed in the present application
  • FIG. 3B shows an enlarged cross-sectional view of a part of the semiconductor device shown in FIG. 3A;
  • Fig. 4 shows a schematic diagram of a simulation structure according to an embodiment disclosed in the present application
  • 5A to 5Q respectively show schematic diagrams of various stages in the process of manufacturing a semiconductor device according to the first embodiment disclosed in the present application;
  • 6A and 6B respectively show schematic diagrams of a first modification of the manufacturing method according to the first embodiment disclosed in the present application
  • FIG. 7A to 7D respectively show schematic diagrams of a second modification of the manufacturing method according to the first embodiment disclosed in the present application.
  • 8A to 8H respectively show schematic diagrams of several stages in the process of manufacturing a semiconductor device according to a second embodiment disclosed in the present application;
  • 9A to 9C respectively show schematic diagrams of several stages in the process of manufacturing a semiconductor device according to the third embodiment disclosed in the present application.
  • 10A to 10I respectively show schematic diagrams of several stages in the process of manufacturing a semiconductor device according to a fourth embodiment disclosed in the present application;
  • 11A to 11J respectively show schematic diagrams of several stages in the process of manufacturing a semiconductor device according to a fifth embodiment disclosed in the present application.
  • FIG. 12 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments disclosed in the present application.
  • a semiconductor device and a manufacturing method thereof for alleviating or eliminating a local hot spot problem are provided.
  • the intermediate stages of forming the semiconductor device are shown here, and various embodiments and variations thereof are discussed.
  • similar reference numerals are used to represent similar elements.
  • FIG. 1A shows a cross-sectional view of a semiconductor device 100.
  • the semiconductor device 100 includes a first semiconductor layer 114, for example, a first chip (a logic chip or a memory chip) or a first interconnection layer (interposer).
  • the heat-conducting layer 102 and the first semiconductor layer 114 are laminated and arranged.
  • the heat-conducting layer 102 allows conduction from any side of the heat-conducting layer 102 in its interior (it is worth noting that the first semiconductor layer 114 is located on the heat-conducting layer 102 On one side, the other side of the thermal conductive layer 102 is away from the first semiconductor layer 114) heat.
  • FIG. 1A shows a cross-sectional view of a semiconductor device 100.
  • the semiconductor device 100 includes a first semiconductor layer 114, for example, a first chip (a logic chip or a memory chip) or a first interconnection layer (interposer).
  • the heat-conducting layer 102 and the first semiconductor layer 114 are laminate
  • the thermally conductive layer 102 allows heat from above and/under the thermally conductive layer 102 to be conducted inside.
  • orientation of each component will be described below in conjunction with the drawings. However, as described above, these orientation-related terms are only for ease of description, and do not require the device to be configured or operated in a specific orientation.
  • a second chip may be provided above the thermally conductive layer 102, and the first semiconductor layer 114 may also be composed of a first chip, and a third semiconductor layer may also be provided below the first semiconductor layer 114, and the third semiconductor layer may also be May be composed of a third chip. Therefore, there may be heat sources above and below the thermal conductive layer 102.
  • the thermal conductivity of the thermal conductive layer 102 in the horizontal direction may be greater than or equal to the thermal conductivity in the vertical direction to facilitate heat conduction in the horizontal direction.
  • the thermal conductivity of the thermal conductive layer 102 in the horizontal direction is greater than the thermal conductivity of the first semiconductor layer 114.
  • the heat from above and/or below the thermally conductive layer 102 can be distributed as evenly as possible in the entire plane of the thermally conductive layer 102. In this way, the local hot spot problem in the semiconductor device can be alleviated or eliminated.
  • the thermally conductive layer 102 and the first semiconductor layer 114 may be connected by bonding, for example, through a wafer bonding process or a surface activation bonding (SAB) process for bonding connection or bonding without an adhesive or a solder layer.
  • SAB surface activation bonding
  • the conductive pillar 130 penetrates the thermal conductive layer 102 to electrically interconnect the second chip above the thermal conductive layer 102 and the first semiconductor layer 114.
  • the electrical contact of the first semiconductor layer 114 may be provided on the upper surface to form a conductive interconnection with the conductive pillar 130.
  • the electrical contact of the first semiconductor chip 114 may be provided on the lower surface of the first semiconductor layer 114, and the conductive pillar 130 may penetrate through the first semiconductor layer 114 and the thermally conductive layer 102, so as to realize the first semiconductor layer above the thermally conductive layer 102
  • the two chips are electrically interconnected with the first semiconductor layer 114.
  • the conductive pillar 130 may also penetrate the first semiconductor layer 114 and the thermal conductive layer 102 to provide the second chip and the first semiconductor layer above the thermal conductive layer 102.
  • the conductive pillar 130 is electrically insulated from the thermal conductive layer 102 to achieve insulation isolation.
  • electrical insulation can be achieved by disposing one or more layers of dielectric between the conductive pillar 130 and the conductive layer 102.
  • the thickness of one layer of the dielectric can be several tens of nanometers.
  • openings with larger diameters are made in the thermally conductive layer 102.
  • silicon or silicon dioxide and other filling materials compatible with the through-silicon via (TSV) process can be used to fill these openings. Realized electrical interconnection.
  • the conductive pillar 130 may include a barrier layer, a seed layer, and a through conductor (for example, copper), which may be achieved by a TSV process.
  • a through conductor for example, copper
  • the term "conductive pillar” does not mean that the cross-sectional shape is circular.
  • the cross-sectional shape may also be an ellipse, a polygon, and other suitable shapes.
  • the term "conductive pillar” does not mean that the cross-sectional shape or size is the same along the length of the entire conductive pillar. Can have different shapes, sizes, etc.
  • the shape of the conductive pillar is related to the shape of the opening, and the shape of the opening is affected by different opening processes.
  • the shape of the hole is usually a structure with a larger size on the upper side and a smaller size on the lower side.
  • the shape of the hole is generally cylindrical.
  • the structure of the conductive pillar may also cause holes in the interior due to process limitations.
  • the thermally conductive layer 102 may be made of various thermally conductive materials, for example, a carbon-based material, a metal material, or a combination thereof, especially a graphene film.
  • the thickness of the thermally conductive layer 102 may be at least 5um, for example, 5um ⁇ 1000um, for example, 10um ⁇ 300um, for example, 20um ⁇ 100um, especially, 30um ⁇ 60um.
  • the functional layer of a semiconductor device is usually made by a thin film deposition process such as chemical vapor deposition (CVD) or a thin film synthesis process, and the thickness of the thin film formed by these semiconductor processes is usually on the order of nanometers.
  • the embodiments disclosed in the present application can achieve a good heat equalization effect and better eliminate the effect of local hot spots.
  • the in-plane thermal conductivity of the thermally conductive layer 102 can be above 600 W/mk, and the use of graphene-based films can achieve the in-plane thermal conductivity above 1,000 W/mk, or even above 1200 W/mk.
  • the graphene film is formed by stacking multiple graphene layers in a spiral stacking manner. Unlike graphite, graphene uses a regular AB stack (half of the carbon atoms of the graphene layer is located on the other atom of the lower graphene, and the other half is located on the center of the hexagon formed by the carbon atoms in the lower graphene) constitute.
  • the graphene film may be made of graphene nanosheets, for example, it may be made of graphene nanosheets with a thickness of less than 5 nm and a plane size of 1-100 microns.
  • Graphene film can also be composited with other materials, such as Cu, SiC, Si, SiO 2 , Al 2 O 3 and other materials to achieve higher strength while maintaining high planar thermal conductivity, and match in the thermal conductive layer 102
  • the process of making through holes may be CVD deposition of enhanced materials on the surface and inside of the graphene film, such as the deposition of metal, non-metal or metal/non-metal oxides, nitrides, carbides, and fluorides.
  • the composite process can also be to infiltrate metal, such as Al, Cu, etc., on the surface and inside of the graphene film under high temperature and high pressure.
  • suitable processes can also be used to perform the composite of the graphene film with other materials.
  • the in-plane thermal conductivity of the graphene film is excellent.
  • the in-plane thermal conductivity of the graphene film can reach 1500 to 1700 W/mk, resulting in effective heat conduction in the plane of the graphene film.
  • the material of the thermally conductive layer 102 is not limited to the graphene-based film.
  • Graphene-based composite films can also be used, for example, graphite/metal composite films, graphite films, graphite/metal composite films, metal/carbon composite films, Even copper alloy film and so on.
  • the graphene film is more suitable for conducting heat in the plane of the thermally conductive layer 102 due to its higher in-plane thermal conductivity, thereby alleviating or eliminating the problem of local hot spots.
  • the semiconductor device 100 may also include an insulating material covering the surface of the thermally conductive layer 102 to achieve insulation isolation.
  • the surface of the thermally conductive layer 102 includes not only the upper surface and the lower surface, but also the side surface in the through hole.
  • the insulating material can include different structures. For example, in the example shown in FIG. On the lower surface and side surfaces of 102, and the second insulating layer 116 is provided on the upper surface of the thermally conductive layer 102. The existence of these insulating layers prevents the conductive coupling of the thermally conductive layer 102 to various components in the semiconductor device 102, thereby avoiding damage to the electrical performance of the semiconductor device 102.
  • the material of the insulating layer can be a low-dielectric insulating material, and the performance such as temperature resistance can satisfy the subsequent semiconductor manufacturing process.
  • Optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymers.
  • Both the first insulating layer 110 and the second insulating layer 116 may include multiple layers of materials, for example, a passivation layer, a barrier layer, a dielectric layer, etc., and may be made by physical deposition or chemical deposition methods.
  • the insulating layer 128 at least partially surrounds the conductive pillar 130 and extends along the conductive pillar 130 to electrically insulate the conductive pillar 130 from the thermal conductive layer 102.
  • the conductive pillar 130 may be arranged in the first through hole 126, wherein the first through hole 126 may penetrate the first semiconductor layer 114, the first insulating layer 110, the thermal conductive layer 102, the second insulating layer 116, and so on.
  • the insulating layer 128 is formed on the sidewall of the first through hole 126.
  • the insulating material forming the insulating layer 128 may be at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymer.
  • the insulating layer 128 may include multiple layers of materials, for example, a passivation layer, a barrier layer, a dielectric layer, etc., and may be made by physical deposition or chemical deposition methods. It should be understood that the dashed frame only represents the horizontal range of the first through hole 126.
  • the semiconductor device 100 may further include a second through hole 104, the second through hole 104 at least penetrates the thermally conductive layer 102, and the aperture size of the second through hole 104 is larger than the aperture size of the first through hole 126, thereby surrounding First through hole 126.
  • the second via 104 can reduce the process requirements for manufacturing the semiconductor device 100.
  • the larger second through hole 106 reduces the alignment requirements when forming the first through hole 126, thereby helping to improve the yield and reduce the manufacturing cost.
  • the semiconductor device 100 may further include a filling material 112 arranged between the thermal conductive layer 102 and the insulating layer 128. Due to the process of forming the insulating layer by deposition or the like, the second through hole 104 may not be filled up. Therefore, the filling material 112 may be formed to fill the second through hole 104.
  • the filling material 112 may be an insulating material (for example, silicon oxide), a semiconductor material (for example, silicon), or a combination of the two.
  • the filling material 112 is generally compatible with a through silicon via (TSV) process, thereby facilitating the formation of the first through hole 126.
  • TSV through silicon via
  • Through silicon vias refer to electrical interconnections realized by filling conductive materials in through holes of a silicon wafer.
  • the semiconductor device 100 may further include an insulating layer 124, which may play a role of passivation or protection during the manufacturing process.
  • the semiconductor device 100 may be compatible with various packaging processes.
  • the semiconductor device 100 can be applied to 3D or 2.5D IC packaging.
  • the first semiconductor layer 114 may be a first chip, and a second chip may be disposed above the semiconductor device 100, and the second chip may be electrically coupled with the conductive pillar 130.
  • the first chip and the second chip can be vertically interconnected through TSV.
  • the thickness of the first chip may be 55 um, a silicon-based material, and a thermal conductivity of about 90 W/mK. It should be understood that the above parameters are only provided as examples, and can be adaptively modified according to specific applications.
  • the third semiconductor layer may be disposed under the first semiconductor layer 114, where the third semiconductor layer may be a third chip or an interconnection layer.
  • the third semiconductor chip may be electrically coupled with the conductive pillar 130 through bumps, solder balls, etc., so as to achieve interconnection with the second chip or other chips above the second chip.
  • a high-bandwidth memory (HBM) chip stack includes a bottom chip and a stack of multiple core chips above the bottom chip. The bottom chip may be implemented as the first semiconductor layer 114 shown in FIG. 1A, and the core chip may be disposed above the structure shown in FIG. 1A.
  • the semiconductor device 100 is not limited to being implemented in an interconnection layer application, the semiconductor device 100 can also be applied to 2.5D IC or 3D IC packaging without an interconnection layer, for example, an integrated fan-out (INFO) package
  • INFO integrated fan-out
  • FIG. 1B shows a cross-sectional view of a semiconductor device 100 according to some embodiments disclosed in the present application.
  • the difference in FIG. 1A is that in FIG. 1B, the aperture size of the second through hole 104 is larger, so as to be able to accommodate the first through hole 126 and the third through hole 132.
  • the third through hole 132 is provided with a second conductive pillar 134 and is surrounded by the second through hole 104. It should be understood that more than two through holes may also be formed in the second through hole 104.
  • the other parts of FIG. 1B are basically the same as those of FIG. 1A, and will not be repeated here.
  • the semiconductor device 100 shown in FIG. A the semiconductor device 100 shown in FIG.
  • 1B has further reduced requirements on the size and shape of the second through hole 104, which reduces the technical difficulty and cost of opening holes.
  • it is also allowed to use a coating process to form the filling material, so that the cost can be significantly reduced.
  • the semiconductor device 100 can be applied to various electronic devices, especially communication devices, such as switches, routers, mobile phones, personal digital assistants (PDAs), navigation devices, set-top boxes, music players, video players, and so on.
  • the semiconductor device 100 may also be compatible with various different package types, for example, CoWoS package and INFO package.
  • the application of the semiconductor device 100 according to some embodiments disclosed in the present application will be introduced below in conjunction with a specific application.
  • FIG. 2 shows a cross-sectional view of a CoWoS packaged semiconductor device 200 according to the conventional technology. CoWoS packaging technology can realize the integration of logic chips and memory chips in the same chip package. As shown in FIG.
  • the semiconductor device 200 includes a controller 202, a core chip 204, and a bottom chip 206, wherein the number of core chips 204 is four. It should be understood that more or fewer core chips 204 may also be used.
  • the core chip 204 and the bottom chip 206 form a multi-layer memory chip stack, for example, a high bandwidth memory (HBM) chip stack.
  • HBM high bandwidth memory
  • the controller 202 and the bottom chip 206 are arranged side by side on the interconnection layer 208, and the interconnection layer 208 is arranged on the packaging substrate 210.
  • the packaging material 212 encapsulates these components and forms external contacts on the packaging substrate 210, thereby forming a chip package.
  • the controller 202 and the bottom chip 206 may be provided with a physical layer (PHY) interface to allow data communication between the chips.
  • PHY physical layer
  • HBM2 high-bandwidth memory
  • the existing mainstream HBM chip cooling measures in the industry include: arranging more thermally conductive dummy solder balls, and adopting a hybrid bonding process with higher interconnection density.
  • These solutions improve the thermal resistance between layers by increasing the heat conduction area between stacked HBM chips, which can alleviate the effect of heat accumulation on the temperature rise of the bottom chip, but they cannot solve the local hot spot problem of the HBM chip from the level of improving the chip plane and expanding the thermal resistance. It is necessary to improve the heat-distribution capability of the chip plane, realize the rapid expansion of the local hot spot heat of the chip in the plane direction, and reduce the plane thermal resistance of the chip.
  • FIG. 3A shows a cross-sectional view of a CoWoS packaged semiconductor device 300 according to some embodiments disclosed in the present application. Unlike the semiconductor device 200 shown in FIG. 2, the semiconductor device 300 is provided with a thermally conductive layer 314 at the bottom chip 306. The other parts of FIG. 3A are basically the same as those of FIG. 2 and will not be repeated here.
  • FIG. 3B shows an enlarged view of a portion 316 of the semiconductor device 300.
  • the semiconductor device 300 includes a bottom chip 306, a first insulating layer 318 disposed above the bottom chip 306, a thermally conductive layer 314 disposed above the first insulating layer 318, and a second insulating layer 314 disposed above the thermally conductive layer 314. ⁇ 320.
  • the insulating layer 322 may be disposed on the sidewall of the through hole 330 and above the second insulating layer 320.
  • the conductive pillar 328 is disposed inside the through hole 330 to form a through silicon via (TSV) structure, and is insulated from the thermal conductive layer 314 by the insulating layer 322.
  • TSV through silicon via
  • the interconnection layer 308 is interconnected with the conductive pillars 328 through solder balls 324, and the core chip 304 is interconnected with the conductive pillars 328 through solder balls 326.
  • the I/O pins of the core chip 304 are vertically interconnected with the I/O pins of the bottom chip 306 through the conductive pillars 328, and the bottom chip 306 is electrically interconnected with the interconnect layer 308 through the solder balls 326.
  • Logic chips, such as the controller 302 can also be assembled on other areas of the interconnection layer 308.
  • the electrical interconnection of the bottom chip 306, the core chip 304, the controller 302, and the packaging substrate 310 is realized through the interconnection layer 308. It should be understood that the semiconductor device 100 shown in FIGS. 1A-1B can also be used to implement the portion 316 of the semiconductor device 300.
  • a thermally conductive layer may also be provided above the controller 302.
  • the packaging space in the semiconductor device 300 can be fully utilized, and the heat equalization effect of the controller 302 can be improved.
  • the controller 302 can also be thinned to accommodate the thermally conductive layer more conveniently.
  • Fig. 4 shows a schematic diagram of a simulation structure according to an embodiment disclosed in the present application.
  • the graphene-based thermal conductive layer is integrated above the bottom chip, as shown in FIGS. 3A-3B, for example.
  • the 4-layer HBM2 chip has a maximum temperature of 24°C higher than the minimum temperature in the bottom chip under the 2.0Gbps operating mode.
  • a simulation model is constructed for the above-mentioned 4-layer HBM2 chip scenario, and a scenario where the highest temperature point in the underlying chip is 24°C higher than the lowest temperature is reconstructed. On this basis, a set of simulation conditions was added, and a thermally conductive material with a thickness of 50um and a plane thermal conductivity of 1500W/mk was added to the bottom chip.
  • the size of the HBM chip stack 404 is 11mm x 8mm, and the power of the bottom chip is 4W, and the power of each DRAM HBM chip is 0.75W (4W in total).
  • the temperature of EMC 402 was fixed at room temperature of 25 degrees.
  • Thermal simulation results show that the plane temperature difference of the bottom chip can be reduced from 24°C to 12°C, that is, the plane heat dissipation capacity of the silicon substrate layer chip is doubled.
  • the chip temperature specification of the memory chip module equivalent to the 3D IC chip package has increased by 12°C.
  • thermally conductive materials can also be used, such as graphene-based composite films, graphite films, graphite/metal composite films, metal/carbon composite films, and even copper alloy films.
  • the exemplary embodiments disclosed in the present application will be described with reference to a specific environment, for example, a chip-on-wafer (CoWoS) package. More specifically, the CoWoS package includes a multi-layer memory chip stack, which includes a bottom layer chip and one or more layers of core chips disposed on the bottom layer chip.
  • the exemplary embodiments disclosed in this application are also applicable to other package types and chip structures, including other three-dimensional integrated circuit (3D IC) packages, 2.5D IC packages, and the like.
  • FIG. 5A-5Q show schematic diagrams of various stages of manufacturing a semiconductor device according to the first embodiment disclosed in the present application.
  • FIG. 5A shows a cross-sectional view of the graphene film 502.
  • the thickness of the graphene film 502 may be about 55 um, and the in-plane thermal conductivity may be 1500 to 1700 W/mk. It should be understood that the thickness and planar thermal conductivity of the graphene film can also be changed according to specific application requirements and manufacturing processes.
  • the graphene film 502 can be purchased commercially.
  • a large-size (planar size above 20um) single-layer graphene oxide dispersion can be used, formulated into a slurry and then coated to form a film. After multiple heat treatment processes and compaction processes, the desired thickness of graphene can be produced ⁇ 502 ⁇ Film 502.
  • any other suitable process can also be used to manufacture the graphene film 502.
  • a through hole 504 may be formed in the graphene film 502.
  • FIG. 5B shows a plan view of the graphene film 502
  • FIG. 5C shows a cross-sectional view at a position corresponding to the cross-section A-A' of FIG. 5B.
  • FIG. 5B and FIG. 5C show a plurality of through holes 504.
  • the number, shape, size, and distribution position of the through holes 504 shown in FIGS. 5B and 5C are all provided as examples, and the number, shape, size, and distribution position of the through holes 504 can be changed according to the specific application.
  • the size and distribution position of the through holes 504 can be determined according to the requirements of the vertical interconnection between the bottom chip and the core chip in the HBM chip stack.
  • the diameter size of the through hole 504 may be larger than the aperture of the through-silicon via (TSV) of the bottom chip and the core chip in the HBM stack.
  • TSV through-silicon via
  • the number of I/Os is 5024, corresponding to an area of about 1 ⁇ 6mm, and the through hole density can be about 170 per square millimeter.
  • Typical through holes The diameter is about 10-40um, and the maximum diameter of the through hole is about 76um. It should be understood that these numbers are provided as examples only, and are not intended to limit the scope of the present invention.
  • Various hole-opening processes can be used to make the through hole 504, including laser drilling, drill drilling, and the like.
  • a mask can be made to determine the position of the opening according to a preset position requirement, so as to facilitate the making of the through hole 504. It should be understood that any other suitable technique may be used to make the through hole 504.
  • the graphene film 502 can be bonded to the first carrier wafer 508 to facilitate subsequent processing.
  • the graphene film 502 may be bonded to the first carrier wafer 508 through an adhesive material 506.
  • the bonding material 506 is a peelable bonding material, such as a heat-sensitive or UV-sensitive bonding material, so as to facilitate subsequent peeling of the first carrier wafer 508.
  • the bonding strength will be greatly reduced, while the bonding strength of the UV-sensitive adhesive material will be greatly reduced under UV light. It should be understood that any other suitable method may be used to bond the graphene film 502 to the first carrier wafer 508.
  • the first carrier wafer 508 may be made of materials such as glass or silicon.
  • the size of the first carrier wafer 508 may be the same as the size of the graphene film 502, for example, 4 inches, 6 inches, 8 inches, 12 inches, and so on. In some cases, the size and shape of the graphene film 502 may be inconsistent with the first carrier wafer 508. To this end, the graphene film 502 can be cut to a circular size, and then the graphene film 502 is attached to the surface of the first carrier wafer 508 through an adhesive material 506.
  • the graphene film 502 is thinned.
  • chemical mechanical polishing can be used to polish the back surface of the graphene film 502 to reduce the thickness of the graphene film 502 from 55 um to 50 um.
  • the surface roughness of the graphene film 502 can reach the nanometer level, for example, less than or equal to 1 nm, for example, less than 0.5 nm.
  • a graphene film 502 having an appropriate thickness and a surface roughness that meets the desired requirements may be used, thereby eliminating the step of thinning.
  • an insulating material 510 is formed on the exposed surface of the graphene film 502.
  • an insulating material is deposited on the upper surface of the graphene film 502 and the sidewall of the through hole 504.
  • the insulating material 510 may be a low-dielectric material, and the performance such as temperature resistance can satisfy the subsequent semiconductor manufacturing process, such as silicon oxide.
  • Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymers.
  • the thickness of the insulating material 510 may be about 100 nm. It should be understood that the numerical value is only provided as an example, and the purpose is not to limit the scope of the present invention.
  • the insulating material 510 may include multiple layers of materials, for example, a passivation layer, a barrier layer, a dielectric layer, and the like.
  • the insulating material 510 may be deposited by various methods, for example, physical deposition or chemical deposition.
  • a filling material 512 compatible with the semiconductor TSV process such as an insulating material (for example, silicon oxide), can be formed in the through hole 504.
  • semiconductor materials e.g., silicon
  • the surface can be leveled by various appropriate polishing processes. For example, a surface roughness of less than or equal to 1 nm (for example, less than 0.5 nanometer) can be achieved, thereby facilitating subsequent bonding with the underlying chip.
  • the first carrier wafer 508 can be removed by means of the peelable properties of the bonding material 506, thereby forming a heat spreader that includes a carbon-based material layer (for example, graphene Film 502), the thermal conductivity of the carbon-based material layer in the horizontal direction is greater than or equal to the thermal conductivity in the vertical direction.
  • the heat spreader further includes a first non-metallic pillar that penetrates the carbon-based material layer (for example, the graphene film 502), and the material of the first non-metallic pillar is insulating or semiconductor, for example, silicon or silicon oxide. In the example shown in FIG.
  • the first non-metallic pillar may include the insulating material 510 and the filling material 512 on both sides of the insulating material 510 as shown in FIG. It is an insulating material 510.
  • the diameter of the first non-metal main pillar may be between 10um and 40um.
  • the graphene film 502 is bonded to the first semiconductor layer 514.
  • the first semiconductor layer 514 may be a wafer including a plurality of first chips or a plurality of first interconnection layers, and may be diced into a plurality of first chips or a plurality of first interconnections.
  • the first semiconductor layer 514 may include active structures such as circuits to implement corresponding chip functions, and may be cut into a plurality of first chips.
  • bonding between the graphene film 502 and the first semiconductor layer 514 may be performed through a wafer bonding process.
  • Various suitable wafer bonding processes can be used, in particular, surface activation bonding (SAB) bonding processes.
  • silicon oxide with a thickness of nm is deposited on the surface of the first semiconductor layer 514, and silicon oxide with a thickness of nm is deposited on the surface of the insulating material 510, and directly bonded under certain temperature and pressure conditions.
  • the through holes 504 in the graphene film 502 and the first semiconductor layer 514 where TSV through holes need to be formed can be preliminarily aligned as needed.
  • the first carrier wafer 508 is separated from the graphene film 502. Based on the peelable characteristics of the bonding material 506, the first carrier wafer 508 may be peeled from the graphene film 502.
  • the bonding material 506 is a heat-sensitive adhesive material
  • the bonding strength of the heat-sensitive adhesive material between the first carrier wafer 508 and the graphene film 502 can be significantly reduced by heating. Then, by applying a force, the first carrier wafer 508 and the graphene film 502 are separated.
  • the adhesive strength of the UV-sensitive adhesive material between the first carrier wafer 508 and the graphene film 502 can be significantly reduced by means such as UV light. Then, by applying a force, the first carrier wafer 508 and the graphene film 502 are separated.
  • the first semiconductor layer 514 is bonded to the second carrier wafer 520. Similar to FIG. 5D, the first semiconductor layer 514 can be bonded to the second carrier wafer 520 by an adhesive material 518.
  • the bonding material 518 is a peelable bonding material, such as a heat-sensitive or UV-sensitive bonding material, so as to facilitate subsequent peeling of the second carrier wafer 520.
  • an insulating material 516 is formed on the exposed surface of the graphene film 502.
  • the insulating material 516 may be formed by a deposition method, for example, physical deposition or chemical deposition.
  • the surface of the graphene film 502 may be subjected to surface treatment such as grinding/cleaning to improve the surface flatness.
  • the insulating material 516 may be a low-dielectric material, and the performance such as temperature resistance can satisfy the subsequent semiconductor manufacturing process, such as silicon oxide.
  • Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymers.
  • the thickness of the insulating material 516 may be about 100 nm. It should be understood that the numerical value is only provided as an example, and the purpose is not to limit the scope of the present invention.
  • a through hole 522 is formed in the graphene film 502 according to a set position.
  • the through hole 522 may pass through the insulating material 516 and the filling material 512.
  • the opening treatment can be performed by reactive ion etching (RIE).
  • RIE reactive ion etching
  • oxygen plasma can be used, or hydrogen or argon plasma can be selected.
  • RIE reactive ion etching
  • the opening can be designed according to actual requirements, and the diameter of the aperture of the through hole 522 can be, for example, in the range of 2-20 um.
  • an insulating material 524 is formed on the exposed upper surface of the structure shown in FIG. 5J, specifically, an insulating material is formed on the surface of the insulating material 516 and the filling material 512 (ie, the sidewall of the through hole 522) 524.
  • the insulating material 524 may be a passivation layer, for example, silicon nitride.
  • the thickness of the insulating material 524 may be about 100 to 300 nm.
  • the insulating material 524 may be formed by a deposition process, for example, a physical deposition or a chemical deposition process.
  • a through hole 526 is formed in the first semiconductor layer 514 according to a set position. This is similar to the via last process.
  • a Bosch process or a deep reactive ion etching process may be used to form the via 526.
  • the through hole 526 can be realized by alternating cycles of SF 6 and C 4 F 8 plasma.
  • the position of the through hole 526 corresponds to the position of the through hole 522, for example, the center positions of the two remain the same, and the sizes can be the same or very close.
  • the opening is designed according to actual needs, and the diameter of the hole is usually in the range of 2-20um.
  • an insulating layer 528 is formed on the upper surface of the structure of FIG. 5L. Specifically, an insulating layer 528 is formed on the surface of the insulating material 524 and on the sidewall of the through hole 526.
  • the insulating layer 528 may be formed by a deposition method, for example, a physical deposition or a chemical deposition process.
  • the insulating layer 528 may include silicon oxide or silicon nitride, and its thickness may be about 100 nm.
  • a conductive material is filled in the through hole 526 to form a conductive pillar 530.
  • electrolytic plating may be used to form the conductive pillars 530.
  • a barrier layer and a seed layer are sequentially deposited on the exposed surface of the through hole 526.
  • the material of the barrier layer may include tantalum nitride, titanium nitride, tungsten titanide, titanium, tantalum, chromium, or a combination thereof.
  • the thickness of the barrier layer may be about 300 nm.
  • the material of the seed layer may include copper or the like, and the thickness of the seed layer may be 200 nm.
  • electroplating copper is formed in the through hole 126 by an electrolytic plating process to fill the through hole 526.
  • suitable methods such as an electroless plating process, may also be used to form the conductive pillars 530.
  • the excess copper and barrier material on the upper surface can be removed by chemical mechanical polishing or the like, so as to form a structure as shown in FIG. 5N.
  • pads such as pads 532 and 534, may be formed at one or both ends of the through hole 526 according to requirements.
  • the pads 532 and 534 can be made by electroplating, such as gold plating or copper plating on the surface.
  • the pad 532 near the side of the graphene film 502 can be fabricated first, and the first semiconductor layer 514 and the second carrier wafer 520 can be separated after the fabrication is completed.
  • the second carrier wafer 520 may be peeled from the first semiconductor layer 514 based on the peelable characteristics of the adhesive material 518.
  • a bonding pad 534 is formed on the bottom of the first semiconductor layer 514, and then an array of solder balls 536, such as micro bump copper pillars, is formed.
  • the first semiconductor layer 514 may be separated from the second carrier wafer 520 first, and then the pads 532 and 534 may be formed on both ends of the through hole 526, respectively.
  • a wafer-to-wafer (wafer-to-wafer) process may be used to realize the bonding of the second chip 540 and the first semiconductor layer 514.
  • the second chip 540 may be the fourth core chip wafer in a four-layer HBM2 chip stack
  • the first semiconductor layer 514 may be the bottom chip wafer in a four-layer HBM2 chip stack.
  • chip dicing can be performed to produce a 4-layer HBM2 stacked memory chip module.
  • a die-to-wafer or die-to-die process may be used to solder the memory chip module on the third semiconductor layer 542.
  • the third semiconductor layer 542 may be a third interconnection layer or a third chip.
  • the memory chip module can be interconnected with other logic chips and packaging substrates through the third semiconductor layer 542.
  • a graphene film is integrated on one side of the underlying chip, and a TSV penetrating the graphene film is used as a vertical interconnection between the underlying chip and the core chip.
  • a TSV penetrating the graphene film is used as a vertical interconnection between the underlying chip and the core chip.
  • FIGS. 6A-6B show schematic diagrams of a first modification of the manufacturing method according to the first embodiment.
  • the first modification of the first embodiment starts with the structure shown in FIG. 5I.
  • a through hole 526 passing through the insulating material 516, the filling material 512, and the first semiconductor layer 514 is formed, as shown in FIG. 6A.
  • the structure shown in FIG. 6B is formed.
  • the main difference between the first modification of the first embodiment and the first embodiment is that the openings shown in FIGS. 5J and 5L are modified to be performed simultaneously.
  • FIG. 7A-7D show schematic diagrams of a second modification of the manufacturing method according to the first embodiment.
  • the second modification of the first embodiment starts with the structure shown in FIG. 5E.
  • FIG. 5F in the second modification of the first embodiment, only the insulating material 510 is formed, and the through hole 504 is not filled with the filling material 512, as shown in FIG. 7A.
  • FIG. 7B similar to FIG. 5G, the first semiconductor layer 514 is bonded to the graphene film 502. Then, the same process flow as that of FIG. 5H-FIG. 5I is performed. As shown in FIG.
  • an insulating material 516 is formed on the exposed surface of the graphene film 502, and a filling material 512 is used to fill the through hole 504.
  • a through hole 522 is formed in the filling material 512.
  • the subsequent steps are the same as those shown in FIG. 5K-FIG. 5Q, and will not be described again.
  • the main difference between the second modification of the first embodiment and the first embodiment is that the process of filling the material in FIG. 5F is modified to be performed before the opening in FIG. 5J.
  • FIG. 8A-8H show schematic diagrams of several stages of manufacturing a semiconductor device according to the second embodiment disclosed in the present application.
  • FIG. 8A is the same as FIG. 5A, and a graphene film 502 is provided.
  • FIG. 8B similar to FIG. 5D, the graphene film 502 is bonded to the first carrier wafer 508 by an adhesive material 506.
  • FIG. 8C similar to FIG. 5E, the graphene film 502 is thinned.
  • an insulating material 510 is deposited on the graphene film 502.
  • FIG. 8E similar to FIG. 5G
  • the first semiconductor layer 514 is bonded to the insulating material 510.
  • FIG. 8F similar to FIG.
  • the first carrier wafer 508 is peeled off.
  • the first semiconductor layer 514 is bonded to the second carrier wafer 520, and an insulating material 516 is formed on the graphene film 502.
  • a through hole 522 penetrating the insulating material 510, the thermally conductive layer 502, and the insulating material 516 is formed. The subsequent steps are the same as in Fig. 5K-Fig. 5Q.
  • the difference between the second embodiment and the first embodiment lies in the process of making through holes in the graphene film 502.
  • the first embodiment in the process flow of FIGS. 5B and 5C, multiple through holes are made in the graphene film 502. 504.
  • the second embodiment does not require pre-opening holes for the graphene film 502.
  • the opening process shown in FIG. 5B and FIG. 5C is removed, so that there is no need to fill through holes in FIG.
  • the second embodiment avoids the challenge of aligning the positions of the through holes of the graphene film and the through holes of the underlying chip that may be encountered in the first embodiment.
  • FIGS. 5A to 5H in the first embodiment can be applied to the third embodiment, but in the opening process shown in FIGS. 5B and 5C, larger through holes can be realized.
  • the size of the through hole 504 can be at the millimeter level.
  • the maximum size of the through hole 504 can be designed as the entire effective I/O pin area, such as 1 ⁇ 6mm, or the size of the through hole 504 can be made 110 ⁇ 110um or more.
  • the shape of the through hole 504 may have various suitable shapes, for example, a circular shape, a square shape, and the like.
  • the opening method of the through hole 504 can adopt other suitable processes such as a simpler die-cutting process suitable for low-cost mass production.
  • an insulating material 510 is formed on the exposed surface of the graphene film 502. Then, the through hole 504 is filled with a material compatible with the TSV process, for example, silicon. Since the through hole 504 has a relatively large size, various processes can be used to fill the through hole 504. For example, a coating process can be used to fill a slurry made of silicon powder, and a dense filling material can be formed after being sintered and solidified under certain process conditions.
  • FIG. 9A After the process flow shown in FIG. 5H, the structure shown in FIG. 9A may be formed, in which the filling material 512 fills the via 504, similar to that in FIG. 5I.
  • FIG. 9B similar to FIG. 5J, an insulating material 516 is formed on the graphene film 502.
  • FIG. 9C similar to FIG. 5K, a through hole 522 is formed in the graphene film 502. Unlike FIG. 5K, in FIG. 9C, two through holes 522 and 538 are formed in one through hole 504. It should be understood that there may also be more than two through holes formed in the through hole 504.
  • the other process flow is basically the same as that of the first embodiment, and will not be repeated here.
  • the third embodiment is similar to the first embodiment, and can also significantly reduce the plane temperature difference of the bottom chip and improve the plane heat conduction ability of the bottom chip.
  • the actual area of the graphene film 502 of the third embodiment is reduced, and the planar temperature difference performance of the underlying chip may be slightly reduced, depending on the size of the through hole 504.
  • the third embodiment can significantly reduce the technical difficulty of opening the through hole of the graphene film 502.
  • FIGS. 5A to 5F show schematic diagrams of several stages of manufacturing a semiconductor device according to the fourth embodiment disclosed in the present application.
  • the process flow shown in FIGS. 5A to 5F is first performed.
  • the second carrier wafer 520 is bonded to the upper surface of the graphene film 502, especially the insulating material 510.
  • the bonding material 518 may be used to bond the second carrier wafer 520 to the graphene film 502.
  • the bonding material 508 may be different from the bonding material 506 so that the bonding material 508 is not removed at the same time when the bonding material 506 is removed.
  • the adhesive material 506 may be a heat-sensitive adhesive material, and the adhesive material 518 may be a UV-sensitive adhesive material.
  • the adhesive material 506 may be a UV-sensitive adhesive material
  • the adhesive material 518 may be a heat-sensitive adhesive material.
  • other suitable bonding processes may also be used to bond the second carrier wafer 520 to the graphene film 502.
  • FIG. 10B similar to FIG. 5H, the first carrier wafer 508 is removed, and the graphene film 502 is turned upside down.
  • FIG. 10C similar to FIG. 5J, an insulating material 516 is formed on the graphene film 502, and a through hole 522 is formed in the filling material 512 and the insulating material 516.
  • FIG. 10D similar to FIG. 5K, an insulating material 524 is formed on the sidewall of the through hole 522 and the surface of the insulating material 516.
  • FIG. 10E similar to FIG. 5N, a conductive material is used to fill the via 522 to form a conductive pillar 530.
  • FIG. 5F similar to FIG. 50, the second carrier wafer 520 is stripped to form a soaking layer structure including vertical interconnections.
  • a conductive pillar 550 and an insulating material 548 surrounding the conductive pillar 550 are formed in the first semiconductor layer 514 through a TSV process.
  • pads 534 and 544 are formed on both ends of the conductive pillar 550, respectively.
  • FIG. 10H the structure shown in FIG. 10F and the structure shown in FIG. 10G are joined together.
  • the conductive pillar 530 may be aligned with the corresponding pad 544 of the first semiconductor layer 514 to form a vertical interconnection. You can use wafer bonding to achieve bonding, or you can use soldering to achieve bonding. Before bonding, an insulating material 546 can be formed to achieve passivation, and can play an additional supporting role after bonding.
  • the conductive pillar 530 and the conductive pillar 550 may not have the same lateral size, and a pad 534 is embedded in the middle as a part of the entire vertical interconnection.
  • the process of manufacturing the conductive pillar 530 is relatively simple, easy to implement, and low in cost.
  • the lateral dimension of the conductive pillar 530 may also be equal to or smaller than the lateral dimension of the conductive pillar 550.
  • a pad 552 is formed on the conductive pillar 530, and the second chip 540 is bonded to the pad 552 through a solder ball 538.
  • the underlying chip 514 is bonded to the third semiconductor layer 542 through solder balls 536.
  • the fourth embodiment it is possible to avoid the problem of excessively high TSV aperture ratio caused by the simultaneous production of TSV in the graphene film and the chip wafer, which leads to increase in process difficulty, complexity and cost.
  • FIGS. 8A to 8G show schematic diagrams of various stages of manufacturing a semiconductor device according to a fifth embodiment disclosed in the present application.
  • the process flow shown in FIGS. 8A to 8G is first performed.
  • the first semiconductor layer 514 is separated from the second carrier wafer 520 by means of the peelable property of the adhesive material 518.
  • the graphene film 502, particularly the insulating material 516 is bonded to the third carrier wafer 556, for example, by the bonding material 554.
  • the bonding material 554 may be similar to the bonding materials 506 and 518, and is a peelable bonding material.
  • a through hole 558 is formed in the first semiconductor layer 514.
  • the through hole 558 may be formed by etching or a laser drilling process. This hole-opening scheme is compatible with the TSV process and can ensure high-precision positioning of the through-holes.
  • the size of the through hole 558 can be determined according to the specific requirements of the first semiconductor layer 514, for example, the diameter is about 10 um. It should be understood that the numerical value is only provided as an example, and is not intended to limit the scope of the disclosure of the present application.
  • an insulating material 560 is formed on the exposed surface of the first semiconductor layer 514.
  • the insulating material 560 may be formed by a physical or chemical deposition method.
  • the insulating material 560 can be used as a dielectric layer or a passivation layer.
  • the insulating material 560 can be a low-dielectric material whose performance such as temperature resistance can satisfy the subsequent semiconductor manufacturing process, such as silicon oxide.
  • Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymers.
  • the passivation step shown in FIG. 11C may not be performed.
  • a through hole 526 is formed in the graphene film 502 and the insulating materials 510, 516.
  • the through hole 526 may be formed by etching or a laser drilling process.
  • other suitable hole-opening processes can also be used.
  • opening a hole through a non-etching solution, especially a laser opening can have a higher hole-opening efficiency.
  • the insulating material 562 is formed in the through hole 526, specifically, the insulating material 562 is formed on the sidewall of the through hole 526 and the surface of the insulating material 560.
  • the insulating material 562 can be formed by a physical or chemical deposition method.
  • the insulating material 562 can be used as a dielectric layer or a passivation layer.
  • the insulating material 562 can be a low-dielectric material, and the performance such as temperature resistance can satisfy the subsequent semiconductor manufacturing process, such as silicon oxide.
  • Other optional materials include at least one of silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, fluorine-containing silicon glass, carbon-doped silicon oxide, and polymers.
  • the thickness of the insulating material 562 may be about 100 nm. It should be understood that the numerical value is only provided as an example, and is not intended to limit the scope of the disclosure of the present application.
  • a conductive material is formed to fill the through hole 526 to form a conductive pillar 530.
  • electrolytic plating can be used to form the conductive material.
  • first, a barrier layer and a seed layer are sequentially deposited on the exposed surface of the through hole 526.
  • the thickness of the barrier layer may be about 300 nm.
  • the material of the seed layer may include copper or the like, and the thickness of the seed layer may be 200 nm. It should be understood that the numerical value is only provided as an example, and is not intended to limit the scope of the disclosure of the present application.
  • electroplating copper is formed in the through hole 126 by an electrolytic plating process to fill the through hole 526.
  • other suitable methods such as an electroless plating process can also be used to form the conductive material.
  • the third carrier wafer 556 is removed by means of the peelable property of the bonding material 554. Then, the seed layer that may remain at the bottom of the through hole 526 is removed, and the pads 532 and 534 are formed on both ends of the conductive pillar 530 through a metallization process, respectively.
  • solder balls 536 are formed on pads 534.
  • the first semiconductor layer 514 is bonded to the third semiconductor layer 542 by solder balls 536.
  • the third semiconductor layer 542 may be a third chip or a third interconnection layer.
  • solder balls 538 are formed on the pads 532, and the first semiconductor layer 514 is bonded to the second chip 540 through the solder balls 538.
  • the second chip 540 may be the fourth core chip wafer in a four-layer HBM2 chip stack
  • the first semiconductor layer 514 may be the bottom chip wafer in a four-layer HBM2 chip stack.
  • the fifth embodiment has holes on the chip side, which is compatible with the TSV process, and at the same time ensures the high precision of the positioning of the through holes. Then, a hole is opened from the graphene side, and a non-etching solution (for example, laser opening) can be used to open the hole, which can achieve higher hole-opening efficiency.
  • a non-etching solution for example, laser opening
  • graphene films are used as examples for illustration.
  • the material of the thermally conductive layer 502 is not limited to graphene-based films, and graphene-based composite films may also be used, for example , Graphite/metal composite film, graphite film, graphite/metal composite film, metal/carbon composite film, even copper alloy film, etc. can also be used.
  • graphite/metal composite film graphite film, graphite/metal composite film, metal/carbon composite film, even copper alloy film, etc.
  • metal/carbon composite film even copper alloy film, etc.
  • FIG. 12 shows a flowchart of a method 1200 for manufacturing a semiconductor device according to some embodiments disclosed in the present application.
  • a thermally conductive layer is provided.
  • the thermally conductive layer may be the thermally conductive layer 102, 314 or the graphene film 502 as described above.
  • a first semiconductor layer laminated with the thermally conductive layer is formed.
  • the first semiconductor layer may be the first semiconductor layer 114 or the first semiconductor layer 514.
  • a conductive pillar penetrating the first semiconductor layer is formed, wherein the conductive pillar is electrically insulated from the thermal conductive layer.
  • the conductive pillar may be a conductive pillar 130, 134, 530, or 550.
  • the method 1200 may further include forming a first insulating layer on the first surface of the thermally conductive layer, for example, as shown in FIG. 5F, forming an insulating material 510 on the surface of the graphene film 502.
  • the first semiconductor layer e.g., the first semiconductor layer 514
  • the first insulating layer e.g., the insulating material 510
  • the thermally conductive layer e.g., graphene film
  • the method 1200 may further include forming a second insulating layer (for example, the insulating material 516) on the second surface of the thermally conductive layer (for example, the graphene film 502), and the second surface is opposite to the first surface, such as Shown in Figure 5J.
  • a penetrating second insulating layer e.g., insulating material 516
  • a thermally conductive layer e.g., graphene film 502
  • a first insulating layer e.g., insulating material 510
  • a first semiconductor layer e.g., The first through hole (for example, through hole 526) of the first semiconductor layer 514) is as shown in FIG. 5L.
  • a conductive pillar for example, a conductive pillar 530
  • the first through hole for example, the through hole 526
  • forming the first insulating layer includes: forming a second through hole (for example, the through hole 504) in the thermally conductive layer (for example, the graphene film 502), as shown in FIG. 5B and FIG. 5C; and forming a first insulating layer (for example, insulating material 510) on the first surface of the thermally conductive layer (for example, graphene film 502) and the sidewall of the second through hole (for example, through hole 504), such as Shown in Figure 5F.
  • bonding the first semiconductor layer (for example, the first semiconductor layer 514) to the first insulating layer (for example, the insulating material 510) includes: filling the second via with a filling material (for example, the filling material 512) Hole (e.g., via 504), as shown in FIG. 5F; and bonding the first semiconductor layer (e.g., first semiconductor layer 514) to the first insulating layer (e.g., insulating material 510) and filling material (e.g., filling Material 512), as shown in Figure 5G.
  • a filling material for example, the filling material 512
  • Hole e.g., via 504
  • forming the second insulating layer includes: in the second through hole (for example, the through hole 504) and on the first surface of the thermally conductive layer (for example, the graphene film 502) A second insulating layer (for example, the insulating material 516) is formed; and the second through hole (for example, the through hole 504) is filled with a filling material (for example, the filling material 512), as shown in FIG. 7C.
  • forming the first through hole includes forming a third through hole (for example, the filling material 512) penetrating through the second insulating layer (for example, the insulating material 516) and the filling material , Through hole 522), as shown in FIG. 5J; a third insulating layer (for example, Insulating material 524), as shown in FIG.
  • forming the first via hole includes forming a through second insulating layer (e.g., insulating material 516), a filler material (e.g., filler material 512), and a first semiconductor layer (e.g., The first through hole (for example, the through hole 526) of the first semiconductor layer 514) is as shown in FIG. 6A.
  • forming the first through hole includes forming a fifth through hole (for example, the filling material 512) penetrating the second insulating layer (for example, the insulating material 516) and the filling material , The through hole 522) and the sixth through hole (for example, the through hole 538), as shown in FIG. 9C; in the second insulating layer (for example, the insulating material 516) and the fifth through hole (for example, the through hole 522) and the first A fourth insulating layer (e.g., insulating material 524) is formed on the sidewalls and bottom of the six through holes (e.g., through hole 538), as shown in FIG.
  • the fifth through hole (e.g., through hole 522) and the first Six through holes (for example, through holes 538) are respectively formed with seventh through holes and eighth through holes penetrating through the fourth insulating layer (for example, insulating material 524) and the first semiconductor layer (for example, first semiconductor layer 514),
  • the fifth through hole (for example, through hole 522) and the seventh through hole form a first through hole (for example, through hole 526), and the sixth through hole (for example, through hole 538) and the eighth through hole form a ninth through hole.
  • Through holes as shown in Figure 5L.
  • forming the conductive pillar includes: forming a fifth insulating layer (for example, an insulating layer 528) on the sidewall of the first through hole (for example, the through hole 526), as shown in FIG. 5M As shown; and with a conductive material (for example, conductive pillar 530) filling the first through hole (for example, through hole 526) to form a conductive pillar (for example, conductive pillar 530).
  • the conductive material can be formed through an electrolytic plating process.
  • the first end of the conductive pillar (for example, the conductive pillar 530) is interconnected with the contact of the first chip (for example, the second chip 540); and the first end of the conductive pillar (for example, the conductive pillar 530) is interconnected.
  • the two ends are interconnected with the contacts of the third semiconductor layer (for example, the third semiconductor layer 542).
  • forming the first through hole includes forming a through second insulating layer (e.g., insulating material 516), a thermally conductive layer (e.g., graphene film 502), and a first insulating layer ( For example, the tenth through hole (for example, through hole 522) of the insulating material 510), as shown in FIG. 8H; A sixth insulating layer (for example, insulating material 524) is formed on the sidewalls and bottom, as shown in FIG. 5K; and a through sixth insulating layer (for example, insulating material 524) is formed at the tenth through hole (for example, through hole 522).
  • a through second insulating layer e.g., insulating material 516
  • a thermally conductive layer e.g., graphene film 502
  • a first insulating layer for example, the tenth through hole (for example, through hole 522) of the insulating material 510), as shown in FIG. 8H;
  • the thermally conductive layer includes a first conductive pillar (for example, the conductive pillar 530 as shown in FIG. 10H) and the first semiconductor layer includes a second conductive pillar (for example, the conductive pillar 550 as shown in FIG. 10H), And forming a conductive pillar penetrating the first semiconductor layer and the thermal conductive layer includes: aligning the first conductive pillar and the second conductive pillar and interconnecting each other, as shown in FIG. 10H.
  • forming the first through hole includes: forming a twelfth through hole (for example, the through hole 558) in the first semiconductor layer (for example, the first semiconductor layer 514), such as 11B; and at the twelfth through hole (for example, through hole 558), a first insulating layer (for example, insulating material 510), a thermally conductive layer (for example, graphene film 502), and a second insulating layer are formed (For example, insulating material 516) thirteenth through hole, wherein the twelfth through hole (for example, through hole 558) and the thirteenth through hole form a first through hole (for example, through hole 526), as shown in FIG. 11D Show.

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Abstract

本申请公开的实施例涉及半导体装置和包括该半导体装置的电子设备。该半导体装置包括：第一半导体层；第二芯片；导热层，与所述第一半导体层和所述第二芯片层叠设置并且位于所述第一半导体层与所述第二芯片之间，用于在所述导热层内传导来自所述第一半导体层和/或所述第二芯片的热量，所述导热层在水平方向的导热系数大于或等于在垂直方向的导热系数；以及第一导电柱，贯穿所述导热层，以使得所述第一半导体层与所述第二芯片通过所述第一导电柱实现电互连，其中所述第一导电柱与所述导热层电绝缘，所述第一导电柱的延伸方向为所述垂直方向，其中所述导热层在水平方向的导热系数大于所述第一半导体层的导热系数。通过设置导热层，这种半导体装置可以降低局部热点效应。

Description

半导体装置和包括该半导体装置的电子设备 技术领域
本申请公开的实施例涉及半导体技术领域，更具体地涉及半导体装置和包括该半导体装置的电子设备。
背景技术
在集成电路的封装过程中，半导体芯片可以接合至互连层或封装基板等其他部件上，形成的封装结构称为三维集成电路(3D IC)。在3D IC中，散热是一种挑战。
在典型的3D IC(例如，基板上晶圆上的芯片(Chip-on-Wafer-on-Substrate，CoWoS)封装)中，热量可能聚集在芯片堆叠底部的内部区域中，从而导致明显的局部温度峰值(也称热点)。此外，由于高功耗芯片所产生的热量而引起的热点可能会对周围的芯片产生热串扰问题，从而对周围芯片的性能和整个3D IC封装的可靠性产生不利影响。这种以3D IC为例讨论的局部热点问题同样广泛存在于其他半导体芯片封装结构(例如，2.5D IC封装)中。
发明内容
本申请提供一种半导体装置，用于在一定程度上解决半导体装置中的局部热点的问题。另外，本申请还提供了一种电子设备，该电子设备包括前述半导体装置。
根据本申请公开的第一方面，提供了一种半导体装置。该半导体装置包括：第一半导体层；第二芯片；导热层，与所述第一半导体层和所述第二芯片层叠设置并且位于所述第一半导体层与所述第二芯片之间，用于在所述导热层内传导来自所述第一半导体层和/或所述第二芯片的热量，所述导热层在水平方向的导热系数大于或等于在垂直方向的导热系数；以及第一导电柱，贯穿所述导热层，以使得所述第一半导体层与所述第二芯片通过所述第一导电柱实现电互连，其中所述第一导电柱与所述导热层电绝缘，所述第一导电柱的延伸方向为所述垂直方向，其中所述导热层在水平方向的导热系数大于所述第一半导体层的导热系数。
第一半导体层和/或第二芯片在工作中可能产生热量，并且热量在水平方向上可能分布不均匀。由于导热层与第一半导体层和第二芯片层叠设置并且导热层在水平方向的导热系数大于或等于在垂直方向的导热系数，可以将热量在水平方向上扩散开来，实现水平均热的效果，从而减缓或消除局部热点效应。此外，在导热层中设置有第一导电柱，以实现第一半导体层与第二芯片的电互连。由于导热层通常也是导电材料，通过将导热层与第一导电柱进行电隔离，第一导电柱的电功能不会受到影响，确保半导体装置可以正常工作。
在一些实施例中，所述导热层上具有多个通孔，一个或多个所述第一导电柱贯穿一个所述通孔。
通孔和导电柱的数量可以根据芯片的具体要求来确定。通常而言，芯片之间的互连通过多个通孔来实现。导电柱的尺寸通常由半导体制造工艺以及芯片的尺寸、性能等决定。由于大孔径的通孔更容易制造，成本更低。因此，为了降低导热层的生产成本，可以使用能够容纳多个导电柱的通孔。在一些情况下，为了提升均热性能，可以制造较小的通孔，从而尽可能保留导热层。即，一个通孔仅容纳一个导电柱。
在一些实施例中，所述导热层与所述第一半导体层之间键合连接。
键合连接是一种无胶粘剂、无焊接层的连接，可以显著降低导热层与第一半导体层之间的热阻，从而热量可以通过导热层在水平方向上快速扩展，提升均热效果。
在一些实施例中，所述半导体装置还包括绝缘材料，所述绝缘材料包覆所述导热层的表面，所述第一导电柱还贯穿所述绝缘材料。
由于绝缘材料包覆导热层的表面，导热层与其他元件之间的导电路径被切断，从而不会影响半导体装置的电性操作。
在一些实施例中，所述半导体装置还包括：绝缘层，被布置为至少部分围绕所述第一导电柱且沿所述第一导电柱延伸，用于将所述第一导电柱与所述导热层隔离以实现电绝缘。
通过围绕第一导电柱设置绝缘层，可以将第一导电柱与导热层电绝缘。
在一些实施例中，所述半导体装置还包括：填充材料，被布置在所述导热层中并且位于在所述导热层与所述绝缘层之间。
在对导热层钻孔过程中，为了降低成本，可能制造孔径相对较大的通孔，因此，需要填充材料来填充这些通孔，以降低形成导电柱的难度。
在一些实施例中，所述填充材料与硅通孔(TSV)工艺兼容，所述硅通孔是指通过在硅晶圆的通孔中填充导电材料以实现的电互连。
由于填充材料与TSV工艺兼容，在对填充材料进行打孔的过程中，可以使用已知的半导体制造工艺来实现，从而具有良好的工艺兼容性。
在一些实施例中，所述第一半导体层为第一芯片或第一互连层。
在一些实施例中，在所述第一半导体层为第一芯片时，所述第一导电柱还贯穿所述第一芯片。
在一些实施例中，所述半导体装置还包括：第三半导体层，被布置在所述第一半导体层远离所述导热层的一侧，所述第三半导体层与所述导电柱电耦合。
在一些实施例中，所述导热层包括碳基材料、金属材料或其组合。
在一些实施例中，所述碳基材料包括石墨烯膜。
在一些实施例中，所述导热层的厚度至少为5um。
在第二方面，提供了一种电子设备，包括：根据第一方面所述的半导体装置。
在一些实施例中，所述电子设备包括：交换机、路由器、移动电话、个人数字助理(PDA)、导航设备、机顶盒、音乐播放器或视频播放器。
在第三方面，提供了一种均热片，包括：碳基材料层，所述碳基材料层在水平方向的导热系数大于或等于在垂直方向的导热系数；以及，第一非金属柱，贯穿所述碳基材料层，所述第一非金属柱的延伸方向为所述垂直方向，所述第一非金属柱的材质为绝缘或半导体的，其中所述第一非金属柱与所述碳基材料层接触的部分是绝缘材料。
均热片可以用于半导体封装结构中，用于对半导体封装结构中的芯片进行均热。第一非金属柱允许在其中制造电互连结构，因此，在对半导体芯片进行均热的同时不影响其电学性能。由于第一非金属柱与碳基材料层接触的部分是绝缘材料，因此如果在第一非金属柱中形成导电柱，绝缘材料可以实现对导电柱的电绝缘。
在一些实施例中，所述导热层的表面的粗糙度是小于或等于1nm。
在一些实施例中，所述第一非金属柱的直径在10μm至40μm之间。
提供发明内容部分是为了以简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本申请公开的关键特征或主要特征，也无意限制本申请公开的范围。
附图说明
通过结合附图对本申请公开的示例性实施例进行更详细的描述，本申请公开的上述以及其他目的、特征和优势将变得更加明显，其中，在本申请公开的示例性实施例中，相同的附图标记通常代表相同部件。
图1A示出了根据本申请公开的一些实施方式的半导体装置的截面图；
图1B示出了根据本申请公开的一些实施方式的半导体装置的截面图；
图2示出了根据传统技术的CoWoS封装的半导体装置的截面图；
图3A示出了根据本申请公开的一些实施方式的CoWoS封装的半导体装置的截面图；
图3B示出了图3A所示的半导体装置的一部分的放大截面图；
图4示出了根据本申请公开的一个实施例的仿真结构的示意图；
图5A至图5Q分别示出了根据本申请公开的第一实施例在制造半导体装置的过程中的各个阶段的示意图；
图6A和图6B分别示出了根据本申请公开的第一实施例的制造方法的第一变型的示意图；
图7A至图7D分别示出了根据本申请公开的第一实施例的制造方法的第二变型的示意图；
图8A至图8H分别示出了根据本申请公开的第二实施例在制造半导体装置的过程中的若干阶段的示意图；
图9A至图9C分别示出了根据本申请公开的第三实施例在制造半导体装置的过程中的若干阶段的示意图；
图10A至图10I分别示出了根据本申请公开的第四实施例在制造半导体装置的过程中的若干阶段的示意图；
图11A至图11J分别示出了根据本申请公开的第五实施例在制造半导体装置的过程中的若干阶段的示意图；以及
图12示出了根据本申请公开的一些实施方式的用于制造半导体装置的方法的流程图。
根据通常的做法，附图中示出的各种特征部可能未按比例绘制。因此，为了清楚起见，可以任意地扩展或减小各种特征部的尺寸。另外，一些附图可能未描绘给定的系统、方法或设备的所有部件。最后，在整个说明书和附图中，类似的附图标号可用于表示类似的特征部。
具体实施方式
下面将参照附图更详细地描述本申请涉及的实施例。在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。下文还可能包括其他明确的和隐含的定义。
对方向或方位的任何参考仅旨在便于描述，而不以任何方式限制本发明的范围。例如“下部”、“上部”、“水平”、“竖直”、“上方”、“下方”、“朝上”、“朝下”、“顶部”和“底部”及其派生(例如“水平地”、“向上”、“向下”等)等相关术语在讨论中用来指代下文描述的或者 在附图中示出的方位。这些相关术语仅仅是为了便于描述，而不要求装置以特定方位构造或操作。
根据各个示例性实施例提供了用于缓解或消除局部热点问题的半导体装置及其制造方法。这里示出了形成该半导体装置的中间阶段，并论述了多个实施例及其变型。在各个视图和示例实施例中，相似的附图标记用于代表相似的元件。
图1A示出了一种半导体装置100的截面图。该半导体装置100包括第一半导体层114，例如，第一芯片(逻辑芯片或存储芯片)或第一互连层(interposer)。导热层102与第一半导体层114层叠设置，借助于其导热特性，导热层102允许在其内部传导来自导热层102的任意一侧(值得注意的是，第一半导体层114位于导热层102的一侧，导热层102的另一侧与第一半导体层114相背离)的热量。在图1A所示的示例中，导热层102允许在其内部传导来自导热层102上方和/下方的热量。为了方便起见，以下将结合附图来描述各个部件的方位，然而如上所述，这些方位相关术语仅仅是为了便于描述，而不要求装置以特定方位构造或操作。
例如，导热层102上方可能设置有第二芯片，并且第一半导体层114也可能由第一芯片构成，并且在第一半导体层114下方也可能设置有第三半导体层，而第三半导体层也可能由第三芯片构成。因此，导热层102的上方和下方均有可能存在热量源。导热层102在水平方向的导热系数可以大于或等于在垂直方向的导热系数，以有利于水平方向上的热传导。另外，导热层102在水平方向的导热系数大于第一半导体层114的导热系数。借助于导热层102，来自导热层102上方和/或下方的热量可以尽可能均匀分布于导热层102的整个平面中。以这种方式，可以缓解或消除半导体装置中的局部热点问题。
导热层102与第一半导体层114之间可以键合连接，例如，通过晶圆键合工艺或者表面活化键合(SAB)工艺进行无胶粘剂或者无焊接层的键合连接或键合固定。这样可以显著降低导热层102与第一半导体层114之间的热阻，从而第一半导体层114内的热点可通过导热层102快速扩展。
导电柱130贯穿导热层102，以使导热层102上方的第二芯片与第一半导体层114实现电互连。在一个示例中，第一半导体层114的电接触可以设置在上表面上，与导电柱130形成导电互连。在另一个示例中，第一半导体芯片114的电接触可以设置在第一半导体层114的下表面上，导电柱130可以贯穿第一半导体层114和导热层102，以实现导热层102上方的第二芯片与第一半导体层114的电互连。在又一个示例中，在第一半导体层114下方设置有第三半导体层时，导电柱130也可以贯穿第一半导体层114和导热层102，以提供导热层102上方的第二芯片与第一半导体层114下方的第三半导体层之间的垂直互连。
导电柱130与导热层102电绝缘，以实现绝缘隔离。例如，可以通过在导电柱130与导电层102之间设置一层或多层介质来实现电绝缘，取决于具体的工艺，一层介质的厚度可以在几十纳米。在一些示例中，为了降低导热层102的开孔难度，在导热层102中制作了较大孔径的开孔。在这种情况下，可以使用硅或二氧化硅等与硅通孔(TSV)工艺兼容的填充材料来填充这些开孔，硅通孔是指通过在硅晶圆的通孔中填充导电材料以实现的电互连。这种结构与3D或2.5D IC封装等兼容，从而非常方便地应用于相关领域中。导电柱130可以包括阻挡层、种子层和贯通导体(例如，铜)，这可以通过TSV工艺来实现。应当理解，术语“导电柱”不表示截面形状为圆形，例如，截面形状也可以是椭圆形、多边形等各种合适的形状。另外，术语“导电柱”也不表示截面形状或尺寸沿着整个导电柱的长度方向是相同的，例如，导电柱在其延伸方向(例如，图1A中的垂直方向)上的不同的截面中可以具有不同的形状、 尺寸等。
例如，导电柱的形状和开孔的形状关联，开孔的形状受不同开孔工艺的影响。例如，在激光开孔工艺中，孔的形状通常为上面尺寸较大，下面尺寸较小的结构。在TSV的博世工艺中，孔的形状则大体为圆柱形。导电柱的结构成型可能还会由于工艺限制导致内部出现孔洞。
导热层102可以由各种导热材料制成，例如，碳基材料、金属材料或其组合，特别是石墨烯膜。导热层102的厚度可以至少为5um，例如，5um～1000um，又例如，10um～300um，再例如，20um～100um，特别是，30um～60um。在常规半导体制程中，半导体装置的功能层通常采用化学气相沉积(CVD)等薄膜沉积工艺或者薄膜合成工艺制作，这些半导体工艺形成薄膜的厚度通常为纳米级别。通过使用较大厚度的导热层102，本申请公开的实施方式可以实现良好的均热效果，更好地消除局部热点效应。导热层102的平面导热系数可以在600W/mk以上，使用石墨烯基膜可实现平面导热系数1000W/mk以上，甚至1200W/mk以上。
石墨烯膜是通过多层石墨烯层采用螺旋堆叠方式堆叠形成的。不同于石墨，石墨烯采用规则的AB堆叠(石墨烯层的一半碳原子位于下层石墨烯的另一个原子上，而另一半位于由下层石墨烯中的碳原子形成的六边形的中心上)构成。例如，石墨烯膜可以由石墨烯纳米片制作而成，例如，可以由厚度在5nm以下，1～100微米平面尺寸大小的石墨烯纳米片制作而成。石墨烯膜也可以与其他材料复合,比如与Cu、SiC、Si、SiO 2、Al 2O 3等材料复合，在维持高平面导热系数的情况下，实现更高强度，匹配在导热层102中制作通孔的工艺。例如，复合工艺可以是在石墨烯膜表面及内部CVD沉积增强材料，比如沉积金属、非金属或者金属/非金属的氧化物、氮化物、碳化物及氟化物等。复合工艺也可以是在石墨烯膜表面及内部在高温高压下浸渗金属，比如Al、Cu等。本领域技术人员应当理解，也可以使用其他合适的工艺来进行石墨烯膜与其他材料的复合。
石墨烯膜的平面导热性优异，例如，石墨烯膜的平面导热系数可以达到1500～1700W/mk，从而导致热量可以在石墨烯膜的平面内进行有效传导。然而，导热层102的材料不局限于石墨烯基膜，也可以采用石墨烯基复合膜，例如，石墨/金属复合膜，也可采用石墨膜、石墨/金属复合膜、金属/碳复合膜、甚至铜合金膜等。在这些材料中，石墨烯膜由于具有更高的平面导热系数，从而更加适合在导热层102的平面内传导热量，从而缓解或消除局部热点问题。
由于大部分导热材料同时也是导电材料，因此半导体装置100还可以包括包覆导热层102的表面的绝缘材料，以实现绝缘隔离。导热层102的表面不仅包括上表面、下表面，而且还包括通孔内的侧表面。根据不同的制造工艺，绝缘材料可以包括不同的结构，例如，在图1A所示的示例中，绝缘材料包括第一绝缘层110和第二绝缘层116，其中第一绝缘层110设置在导热层102的下表面以及侧表面上，并且第二绝缘层116设置在导热层102的上表面上。这些绝缘层的存在防止导热层102对半导体装置102内的各个部件的导电耦合，从而避免损坏半导体装置102的电学性能。这些绝缘层的材料可以是低介电绝缘材料，耐温性等性能可满足后续半导体制作工艺。可选材料包括氮化硅、碳化硅、氧化硅、碳氧化硅、含氟硅玻璃、碳掺杂氧化硅和聚合物中的至少一种。第一绝缘层110和第二绝缘层116均可以包含多层材料，例如，钝化层、阻挡层、介质层等，并且可采用物理沉积或者化学沉积方法制作。
另外，如图1A所示，绝缘层128至少部分围绕导电柱130并沿导电柱130延伸，用于将导电柱130与导热层102电绝缘。导电柱130可以布置在第一通孔126内，其中第一通孔126可以贯穿第一半导体层114、第一绝缘层110、导热层102和第二绝缘层116等。绝缘层128形成在第一通孔126的侧壁上。形成绝缘层128的绝缘材料可以是氧化硅、氮化硅、碳化硅、碳氧化硅、含氟硅玻璃、碳掺杂氧化硅和聚合物中的至少一种。绝缘层128可以包含多层材 料，例如，钝化层、阻挡层、介质层等，并且可采用物理沉积或者化学沉积方法制作。应当理解，虚线框仅表示第一通孔126的水平范围。
在一些实施例中，半导体装置100还可以包括第二通孔104，第二通孔104至少贯穿导热层102，并且第二通孔104的孔径尺寸大于第一通孔126的孔径尺寸，从而包围第一通孔126。第二通孔104可以降低制造半导体装置100的工艺要求。例如，较大的第二通孔106降低了在形成第一通孔126时的对准要求，从而有利于提高良率和降低制造成本。
可选地，半导体装置100还可以包括填充材料112，填充材料112布置在导热层102与绝缘层128之间。由于在以沉积等方式来形成绝缘层的过程中，第二通孔104可能无法填满。因此，可以形成填充材料112，以填充第二通孔104。填充材料112可以是绝缘材料(例如，氧化硅)，也可以是半导体材料(例如，硅)，或者两者的结合。填充材料112通常兼容硅通孔(TSV)工艺，从而便于制作第一通孔126。硅通孔是指通过在硅晶圆的通孔中填充导电材料以实现的电互连。可选地，半导体装置100还可以包括绝缘层124，其可以在制造过程中起到钝化或保护作用。
如上所述，半导体装置100可以与各种封装工艺兼容。例如，半导体装置100可以应用于3D或2.5D IC封装中。例如，第一半导体层114可以是第一芯片，并且半导体装置100上方可以设置第二芯片，第二芯片可以与导电柱130电耦合。以这种方式，第一芯片与第二芯片之间可以通过TSV实现垂直互连。例如，第一芯片的厚度可以是55um，硅基材质，导热系数约90W/mK。应当理解，以上参数仅作为示例提供，根据具体应用可以进行适应性修改。
此外，第三半导体层可以设置在第一半导体层114下方，其中第三半导体层可以是第三芯片或者互连层。例如，第三半导体芯片可以通过凸点、焊球等与导电柱130电耦合，从而实现与第二芯片或者第二芯片上方的其他芯片的互连。在一个具体示例中，高带宽存储器(HBM)芯片堆叠包括底层芯片以及底层芯片上方的多个内核芯片的堆叠。底层芯片可以实现为图1A所示的第一半导体层114，并且内核芯片可以设置在图1A所示的结构上方。
应当理解，由于半导体装置100不局限于在互连层的应用中实现，半导体装置100也可以应用于没有互连层的2.5D IC或者3D IC封装方式，例如，集成扇出型(INFO)封装内部的多层芯片的平面均热能力的提升。
图1B示出了根据本申请公开的一些实施方式的半导体装置100的截面图。如图1A不同的是，在图1B中，第二通孔104的孔径尺寸较大，从而能够容纳第一通孔126和第三通孔132。第三通孔132内设置有第二导电柱134，并且被第二通孔104包围。应当理解，也可以超过两个通孔形成在第二通孔104内。图1B的其他部分与图1A基本相同，在此不再赘述。与图A所示的半导体装置100相比，图1B所示的半导体装置100对第二通孔104的尺寸和形状等要求进一步降低，降低开孔技术难度和成本。另外，除了使用沉积工艺之外，还允许使用涂布工艺来形成填充材料，从而可以显著降低成本。
半导体装置100可以应用在各种电子设备中，特别是通信设备中，例如，交换机、路由器、移动电话、个人数字助理(PDA)、导航设备、机顶盒、音乐播放器、视频播放器等等。此外，半导体装置100也可以与各种不同的封装类型兼容，例如，CoWoS封装和INFO封装。以下将结合一个具体应用来介绍根据本申请公开的一些实施方式的半导体装置100的应用。图2示出了根据传统技术的CoWoS封装的半导体装置200的截面图。CoWoS封装技术可以实现逻辑芯片与存储芯片在同一芯片封装的集成。如图2所示，半导体装置200包括控制器202、内核芯片204和底层芯片206，其中内核芯片204的数目为四个。应当理解，也可以使用更多或更少的内核芯片204。内核芯片204与底层芯片206形成多层存储芯片堆叠，例如，高 带宽存储器(HBM)芯片堆叠。
控制器202和底层芯片206并排设置在互连层208上，而互连层208又设置在封装基板210上。封装材料212包封这些部件，并且在封装基板210上形成外部接触，从而形成芯片封装。控制器202和底层芯片206上可以设置有物理层(PHY)接口，从而允许芯片之间的数据通信。
如上所述，在3D IC(例如，HBM芯片)中存在局部热点问题，芯片过热超温可能成为后续3D IC芯片散热的关键问题之一。例如，采用DRAM工艺的HBM芯片结温规格仅95度，显著低于周边CMOS芯片结温规格105度。多层HBM芯片堆叠后底层芯片热量无法有效导出，底层芯片成为芯片散热瓶颈。
HBM芯片过热主要原因是硅基芯片本身的均热性不够。以4层第二代高带宽存储器(HBM2)芯片堆叠为例，底部芯片的局部热点最高温度比最低温度可相差24℃。
业界已有的HBM芯片降温主流措施包括：布置更多的导热假焊球、采用互连密度更高的混合键合工艺等。这些方案通过提升堆叠HBM芯片之间的导热面积改善层间热阻，可缓解热量累积对底部芯片温升影响，但无法从改善芯片平面扩展热阻层面解决HBM芯片局部热点问题。需要改善芯片平面均热能力，实现芯片局部热点热量在平面方向上的快速扩展，降低芯片平面热阻。
图3A示出了根据本申请公开的一些实施方式的CoWoS封装的半导体装置300的截面图。与如图2所示的半导体装置200不同，半导体装置300在底层芯片306处设置有导热层314。图3A的其他部分与图2基本相同，在此不再赘述。
图3B示出了半导体装置300的一部分316的放大视图。如图3所示，半导体装置300包括底层芯片306、设置在底层芯片306上方的第一绝缘层318、设置在第一绝缘层318上方的导热层314以及设置在导热层314上方的第二绝缘层320。另外，绝缘层322可以设置在通孔330的侧壁上以及第二绝缘层320上方。导电柱328设置在通孔330内部，形成硅通孔(TSV)结构，并通过绝缘层322与导热层314绝缘。互连层308通过焊球324与导电柱328互连，并且内核芯片304通过焊球326与导电柱328互连。以这种方式，内核芯片304的I/O引脚通过导电柱328实现与底层芯片306的I/O引脚的垂直互连，并且底层芯片306通过焊球326与互连层308实现电气互连。互连层308的其他区域上还可以组装逻辑芯片，例如，控制器302。通过互连层308实现了底层芯片306、内核芯片304、控制器302以及封装基板310的电气互连。应当理解，还可以使用图1A-图1B所示的半导体装置100来实现半导体装置300的部分316。
附加地或备选地，在图3A所示的半导体装置300中，还可以在控制器302上方设置导热层(未示出)。以这种方式，可以充分利用半导体装置300内的封装空间，并提高控制器302的均热效果。在一个示例实施例中，还可以对控制器302进行减薄，从而更方便地容纳导热层。
图4示出了根据本申请公开的一个实施例的仿真结构的示意图。在该实施例中，印刷电路板(PCB)408、设置在PCB 408上方的衬底406、设置在衬底406上方的HBM2存储芯片模组404以及设置在HBM芯片堆叠404上方的环氧树脂(EMC)402。在该实施例中，石墨烯基导热层集成在底层芯片上方，例如如图3A-图3B所示。
在传统技术中，4层HBM2芯片在2.0Gbps工作模式下底层芯片中最高温度点温度比最低温度高24℃。针对上述4层HBM2芯片场景构建仿真模型，重构出底层芯片中最高温度点温度比最低温度高24℃场景。在此基础上，增加一组仿真条件，在底层芯片上增加50um厚度、 平面导热系数为1500W/mk的导热材料。
HBM芯片堆叠404的尺寸为11mm x 8mm，并且底层芯片的功率为4W，每个DRAM HBM芯片的功率是0.75W(一共4W)。在仿真过程中，EMC 402的温度固定在室温25度。传统技术中的底层芯片的表面温度为63～87℃(ΔT＝24℃)。根据本申请公开的实施例，底层芯片的表面温度为65～75℃(ΔT＝12℃)。热仿真结果表明底层芯片的平面温差可从24℃降低至12℃，即硅基底层芯片的平面均热能力提升1倍。等同3D IC芯片封装中存储芯片模组的芯片温度规格提升了12℃。
如上所述，除了石墨烯膜之外，还可以使用其他导热材料，例如，石墨烯基复合膜、石墨膜、石墨/金属复合膜、金属/碳复合膜、甚至铜合金膜等。
这些非石墨烯膜材料虽然平面导热系数难以实现1500W/mk以上，但容易实现400W/mk以上。根据如图4所示的仿真模型，在底层芯片表面集成50um厚度，导热系数为400W/mk的导热材料时，热仿真结果表明底层芯片的平面温差可从24℃降至18.8℃。因此，即使不采用石墨烯膜，依然可改善硅基芯片平面导热能力50％以上。
以下将参照具体环境来描述本申请公开的示例实施例，例如，衬底上晶圆上芯片(CoWoS)封装。更具体地，该CoWoS封装包括多层存储芯片堆叠，其包括底层芯片以及设置在底层芯片上的一层或多层内核芯片。然而，本申请公开的示例实施例也适用于其他封装类型和芯片结构，包括其他三维集成电路(3D IC)封装以及2.5D IC封装等。
图5A-图5Q示出了根据本申请公开的第一实施例在制造半导体装置的各个阶段的示意图。图5A示出了石墨烯膜502的截面图。例如，石墨烯膜502的厚度可以是约55um，并且平面导热系数可以是1500～1700W/mk。应当理解，石墨烯膜的厚度和平面导热系数也可以根据具体应用要求和制造工艺而改变。例如，可以通过商业方式购买石墨烯膜502。另外，可以使用大尺寸(平面尺寸在20um以上)的单层氧化石墨烯分散液，配制成浆料后涂布成膜，经过多次热处理工艺及压实工艺后制作成所需厚度的石墨烯膜502。本领域技术人员应当理解，也可以使用任何其他合适的工艺来制造石墨烯膜502。
根据预定义位置，在石墨烯膜502中可以形成通孔504。图5B示出了石墨烯膜502的平面图，图5C示出了与图5B的截面A-A’对应的位置处的截面图。图5B和图5C示出了多个通孔504。应当理解，图5B和图5C中示出了的通孔504的数目、形状、大小和分布位置均是作为示例提供，通孔504的数目、形状、大小和分布位置可以根据具体应用的情况来确定。例如，在诸如高带宽存储器(HBM)等芯片堆叠中，通孔504的大小和分布位置可以根据HBM芯片堆叠中的底层芯片与内核芯片的垂直互连的要求来确定。
为了降低对后端工艺的高精度对位需求，通孔504的直径尺寸可以大于HBM堆叠中的底层芯片与内核芯片的硅通孔(TSV)的孔径。例如，在4层第二代高带宽存储器(HBM2)芯片堆叠的示例中，I/O数为5024个，对应面积约1×6mm，通孔密度可以是约170个每平方毫米，典型通孔直径约10～40um，通孔直径最大约76um。应当理解，这些数字仅作为示例提供，目的并不在于限制本发明的范围。
可以使用各种开孔工艺来制作通孔504，包括激光打孔、钻头钻孔等。在制作通孔504之前，可以根据预先设定的位置需求，制作掩膜确定开孔位置，以方便制作通孔504。应当理解，也可以使用任何其他合适的技术来制作通孔504。
接下来，可以将石墨烯膜502接合到第一载具晶圆508，从而方便后续处理。例如，如图5D所示，可以通过粘结材料506将石墨烯膜502接合到第一载具晶圆508。例如，粘结材料506是可剥离粘结材料，例如，热敏或者UV敏感胶合材料，从而方便后续剥离第一载具晶 圆508。热敏胶合材料在改变温度时，粘结强度会大幅度下降，而UV敏感胶合材料在UV光照下，粘结强度会大幅度下降。应当理解，也可以使用任何其他合适的方法将石墨烯膜502接合到第一载具晶圆508。
第一载具晶圆508可以由玻璃或硅等材料制成。第一载具晶圆508的尺寸可以与石墨烯膜502的尺寸保持一致，例如，4英寸、6英寸、8英寸、12英寸等。在一些情况下，石墨烯膜502的尺寸和形状可能与第一载具晶圆508不一致。为此，可以将石墨烯膜502裁剪成与圆形尺寸,再通过粘结材料506将石墨烯膜502贴合在第一载具晶圆508的表面上。
如图5E所示，对石墨烯膜502进行减薄。例如，可以使用采用化学机械研磨将石墨烯膜502的背面做研磨，将石墨烯膜502从55um减薄至50um。以这种方式，石墨烯膜502的表面粗糙度可以达到纳米级别，例如，小于或等于1nm，例如，在0.5nm以下。备选地，可以使用厚度适当并且表面粗糙度达到期望要求的石墨烯膜502，从而省去减薄的步骤。
如图5F所示，在石墨烯膜502的暴露表面上形成绝缘材料510。例如，在石墨烯膜502的上表面和通孔504的侧壁上沉积绝缘材料。例如，绝缘材料510可以是低介电材料，耐温性等性能可满足后续半导体制作工艺，比如氧化硅。其他可选材料包括氮化硅、碳化硅、氧化硅、碳氧化硅、含氟硅玻璃、碳掺杂氧化硅和聚合物中的至少一种。例如，绝缘材料510的厚度可以是约100nm。应当理解，该数值仅作为示例提供，目的并不在于限制本发明的范围。
根据具体工艺方法及要求，绝缘材料510可以包括多层材料，例如，钝化层、阻挡层、介质层等。例如，可以通过各种方法来沉积绝缘材料510，例如，物理沉积或者化学沉积。
由于石墨烯膜502的通孔504的尺寸较大，膜沉积工艺可能难以均匀填满。在这种情况下，可在通孔504的侧壁上通过绝缘材料510实现绝缘隔离后，再在通孔504内形成与半导体TSV工艺兼容的填充材料512，例如，绝缘材料(例如，氧化硅)和/或半导体材料(例如，硅)。
在通孔504内形成填充材料512后，可通过各种适当的抛光工艺实现表面整平。例如，可以实现在小于或等于1nm(例如，0.5纳米以下)的表面粗糙度，从而方便进行后续与底层芯片的键合。
在一些实施例中，可以借助于粘结材料506的可剥离特性将第一载具晶圆508去除，从而形成了一种均热片，该均热片包括碳基材料层(例如，石墨烯膜502)，碳基材料层在水平方向上的导热系数大于或等于在垂直方向上的导热系数。另外，该均热片还包括第一非金属柱，其贯穿碳基材料层(例如，石墨烯膜502)，并且第一非金属柱的材质为绝缘或半导体的，例如，硅或氧化硅。在图5F所示的示例中，第一非金属柱可以包括如图5F所示的绝缘材料510和绝缘材料510两侧的填充材料512，其中第一非金属柱与石墨烯膜502接触的部分是绝缘材料510。例如，第一非金属主柱的直径可以在10um至40um之间。
在图5G中，将石墨烯膜502接合到第一半导体层514。在晶圆级封装工艺中，第一半导体层514可以是包括多个第一芯片或多个第一互连层的晶圆，并且可以被切割为多个第一芯片或多个第一互连层。例如，第一半导体层514可以包括电路等有源结构，以实现相应芯片功能，并且可以切割成多个第一芯片。例如，可以通过晶圆键合工艺在石墨烯膜502和第一半导体层514之间进行接合。可以使用各种适当晶圆键合工艺，特别是，表面活化键合(SAB)键合工艺。在SAB键合工艺中，在第一半导体层514的表面沉积nm级厚度的氧化硅，并且在绝缘材料510的表面上沉积nm级厚度的氧化硅，在一定温度和压力条件下直接键合。
在将石墨烯膜502和第一半导体层514进行键合时，可根据需要，将石墨烯膜502内的 通孔504和第一半导体层514上需要制作TSV通孔的位置进行初步对位。
在图5H中，将第一载具晶圆508与石墨烯膜502分离。基于粘结材料506的可剥离特性，可以将第一载具晶圆508从石墨烯膜502剥离。例如，在粘结材料506为热敏胶合材料的实施例中，可以通过加热的方式显著降低第一载具晶圆508和石墨烯膜502之间的热敏胶合材料的粘接强度。然后，通过施加作用力，实现第一载具晶圆508与石墨烯膜502的分离。在粘结材料506为UV敏感胶合材料的实施例中，可以通过UV光照等方式显著降低第一载具晶圆508和石墨烯膜502之间的UV敏感胶合材料的粘接强度。然后，通过施加作用力，实现第一载具晶圆508与石墨烯膜502的分离。
在图5I中，将第一半导体层514接合到第二载具晶圆520。与图5D相似，可以通过粘结材料518将第一半导体层514接合到第二载具晶圆520。例如，粘结材料518是可剥离粘结材料，例如，热敏或者UV敏感胶合材料，从而方便后续剥离第二载具晶圆520。
另外，在石墨烯膜502的暴露表面上形成绝缘材料516。例如，可以通过沉积方法形成绝缘材料516，例如，物理沉积或化学沉积。在形成绝缘材料516之前，可对石墨烯膜502的表面做研磨/清洗等表面处理，以提高表面平整度。
在一些示例中，绝缘材料516可以是低介电材料，耐温性等性能可满足后续半导体制作工艺，比如氧化硅。其他可选材料包括氮化硅、碳化硅、氧化硅、碳氧化硅、含氟硅玻璃、碳掺杂氧化硅和聚合物中的至少一种。例如，绝缘材料516的厚度可以是约100nm。应当理解，该数值仅作为示例提供，目的并不在于限制本发明的范围。
如图5J所示，在石墨烯膜502中根据设定位置形成通孔522。通孔522可以穿过绝缘材料516和填充材料512。例如，可以通过反应离子蚀刻(RIE)来进行开孔处理。在RIE中，可以使用氧等离子体，也可选取氢、氩等离子体。使用RIE需要事先对石墨烯膜502的表面做掩膜处理，以定义要形成通孔522的位置。开孔可以根据实际需求进行设计，通孔522的孔径直径例如可以在2～20um范围内。
在图5K中，在图5J所示的结构的暴露的上表面上形成绝缘材料524，具体地，在绝缘材料516和填充材料512的表面(即，通孔522的侧壁)上形成绝缘材料524。绝缘材料524可以是钝化层，例如，氮化硅。绝缘材料524的厚度可以是约100～300nm。例如，可以通过沉积工艺来形成绝缘材料524，例如，物理沉积或化学沉积工艺。
如图5L所示，在第一半导体层514上根据设定位置形成通孔526。这类似于后通孔(via last)工艺。例如，可以使用博世工艺或者深反应离子蚀刻工艺来形成通孔526。在博世工艺中，可以通过SF 6和C 4F 8等离子体交替循环来实现通孔526。通孔526的位置与通孔522的位置对应，例如，两者的中心位置保持一致，并且尺寸可以相同或者非常接近。开孔根据实际需求进行设计，孔径直径通常在2～20um范围内。
如图5M所示，在图5L的结构的上表面上形成绝缘层528。具体地，在绝缘材料524的表面上以及在通孔526的侧壁上形成绝缘层528。可以通过沉积的方式来形成绝缘层528，例如，物理沉积或化学沉积工艺。绝缘层528可以包括氧化硅或者氮化硅，其厚度可以是约100nm。
在图5N中，在通孔526中填充导电材料，以形成导电柱530。例如，可以使用电解镀来形成导电柱530。在电解镀中，首先在通孔526的暴露表面上依次沉积阻挡层和种子层。阻挡层的材料可以包括氮化钽、氮化钛、钛化钨、钛、钽、铬或其组合等。阻挡层的厚度可以是约300nm。种子层的材料可以包括铜等，并且种子层的厚度可以是200nm。应当理解，该数值仅作为示例提供，目的不在于限制本申请公开的范围。然后，通过电解镀工艺在通孔126 内形成电镀铜，以填充通孔526。备选地，也可以使用无电镀工艺等其他合适的方法来形成导电柱530。
在填充通孔526之后，可以通过化学机械研磨等方式去除上表面上多余的铜和阻挡层材料，从而形成如图5N所示的结构。
然后，如图5O所示，根据需求可以在通孔526的一端或两端形成焊盘，例如，焊盘532、534。例如，可以通过电镀的方式制作焊盘532、534，比如表面镀金、镀铜等。
在一个示例中，可以首先制作靠近石墨烯膜502一侧的焊盘532，制作完成后将第一半导体层514与第二载具晶圆520分离。例如，可以基于粘结材料518的可剥离特性，将第二载具晶圆520从第一半导体层514剥离。然后，在第一半导体层514的底部制作焊盘534，再制作焊球536的阵列，比如微凸台铜柱。在另一示例中，可以首先将第一半导体层514与第二载具晶圆520分离，然后在通孔526的两端分别形成焊盘532、534。
如图5P所示，可以使用晶圆到晶圆(wafer to wafer)工艺实现第二芯片540与第一半导体层514的键合。例如，第二芯片540可以是四层HBM2芯片堆叠中的第四内核芯片晶圆，并且第一半导体层514可以是四层HBM2芯片堆叠中的底层芯片晶圆。根据实际需求，在多层HBM芯片堆叠完成之后，可以进行芯片切割，制作出4层HBM2堆叠存储芯片模组。
如图5Q所示，可以使用芯片到晶圆(die to wafer)或者芯片到芯片(die to die)工艺，将存储芯片模组焊接在第三半导体层542上。第三半导体层542可以是第三互连层或第三芯片。在第三半导体层542是第三互连层时，可以实现存储芯片模组通过第三半导体层542与其他逻辑芯片、封装基板的互连。
根据第一实施例，在底层芯片的一侧集成了石墨烯膜，并且底层芯片与内核芯片之间使用贯通石墨烯膜的TSV作为垂直互连。通过对石墨烯膜预先进行较大通孔及表面隔离措施，实现集成本体导电的高导热石墨烯膜后也可实现三维芯片之间的垂直互连。另外，在石墨烯膜预先制作的较大通孔内填充与TSV工艺兼容的材料，显著降低后端三维芯片集成中TSV工艺难度。
以上结合图5A-图5Q介绍了根据本申请公开的第一实施例的制造方法。应当理解，本领域技术人员可以对该流程进行各种可能的修改，而不超出本申请公开的范围。以下将结合图6A-图7D介绍根据第一实施例的制造方法的若干变型，以进行说明。
图6A-图6B示出了根据第一实施例的制造方法的第一变型的示意图。第一实施例的第一变型开始于图5I所示的结构。然后，不同于图5J，在第一实施例的第一变型中，形成穿过绝缘材料516、填充材料512和第一半导体层514的通孔526，如图6A所示。然后，根据与图5M-图5Q相同的步骤，形成如图6B所示的结构。第一实施例的第一变型与第一实施例的主要区别在于将图5J和图5L所示的开孔修改为同时进行。
图7A-图7D示出了根据第一实施例的制造方法的第二变型的示意图。第一实施例的第二变型开始于图5E所示的结构。然后，不同于图5F，在第一实施例的第二变型中，仅形成绝缘材料510，而不通过填充材料512来填充通孔504，如图7A所示。在图7B，与图5G相似，将第一半导体层514接合到石墨烯膜502。然后，执行与图5H-图5I相同的工艺流程。在图7C所示，在石墨烯膜502的暴露表面上形成绝缘材料516，并使用填充材料512来填充通孔504。接下来，在图7D中，在填充材料512内形成通孔522。后续步骤与图5K-图5Q所示步骤相同，不再赘述。第一实施例的第二变型与第一实施例的主要区别在于图5F中填充材料的工艺修改到图5J中的开孔之前执行。
图8A-图8H示出了根据本申请公开的第二实施例在制造半导体装置的若干阶段的示意 图。图8A与图5A相同，提供石墨烯膜502。在图8B，与图5D相似，通过粘结材料506将石墨烯膜502接合到第一载具晶圆508。在图8C，与图5E相似，对石墨烯膜502进行减薄。在图8D，与图5F相似，在石墨烯膜502上沉积绝缘材料510。在图8E，与图5G相似，将第一半导体层514接合到绝缘材料510。在图8F，与图5H相似，剥离第一载具晶圆508。在图8G，与图5I和图5J相似，将第一半导体层514接合到第二载具晶圆520，并且在石墨烯膜502上形成绝缘材料516。在图8H，与图5J相似，形成贯穿绝缘材料510、导热层502和绝缘材料516的通孔522。后续步骤与图5K-图5Q相同。
第二实施例与第一实施例的区别在于在石墨烯膜502中制作通孔的流程上，第一实施例在图5B和图5C的工艺流程，在石墨烯膜502上制作多个通孔504，在图5F的工艺流程填充石墨烯膜504中的通孔504，在图5J所示的工艺流程对石墨烯膜502的填充材料512进行开孔处理。与之相比，第二实施例不需要对石墨烯膜502进行预先开通孔。具体地，将第一实施例中，图5B和图5C所示的开孔工艺去掉，从而在图5F中也无需进行通孔填充，而只在图5J中对石墨烯膜102的对应位置开通孔即可。与第一实施例相比，第二实施例避免第一实施例中可能遇到的石墨烯膜的通孔和底层芯片的通孔位置对齐的挑战。
图9A-图9C示出了根据本申请公开的第三实施例在制造半导体装置的若干阶段的示意图。第一实施例中的图5A-图5H可以应用于第三实施例，然而在图5B和图5C所示的开孔工艺中，可以实现更大的通孔。例如，通孔504的尺寸可在毫米级别，针对HBM2场景，通孔504的最大尺寸可设计为整个有效I/O引脚面积，比如1×6mm，也可将通孔504的尺寸制作为110×110um以上。这种情况下，通孔504的形状可以具有各种适当的形状，例如，圆形、方形等形状。由于通孔504的尺寸变大，通孔504的开孔方式可采用更为简单、适合低成本量产的模切工艺等其他合适的工艺。
在图5F中，在石墨烯膜502的暴露表面上形成绝缘材料510。然后，在通孔504内填充与TSV工艺兼容的材料，例如，硅。由于通孔504具有较大的尺寸，可以使用各种工艺来填充通孔504。例如，可以使用涂布工艺填充采用硅粉制作的浆料，在一定工艺条件下烧结固化后形成致密的填充材料。
在图5H所示的工艺流程之后，可以形成如图9A所示的结构，其中填充材料512填充通孔504，与图5I相似。然后，在图9B，与图5J相似，在石墨烯膜502上形成绝缘材料516。在图9C，与图5K相似，在石墨烯膜502中形成通孔522。与图5K不同的是，在图9C，两个通孔522和538形成在一个通孔504内。应当理解，也可以有超过两个通孔形成在通孔504内。其他工艺流程与第一实施例基本相同，在此不再赘述。
第三实施例与第一实施例相似，也可以显著降低底层芯片的平面温差，提升底层芯片的平面导热能力。相对于第一实施例而言，第三实施例的石墨烯膜502的实际面积有所降低，改善底层芯片的平面温差性能可能略有下降，具体视通孔504的大小而定。然而，由于通孔504的尺寸显著变大，第三实施例可显著降低石墨烯膜502的开通孔技术难度。另外，第三实施例有可能采用涂布等工艺对通孔504进行填充，相对沉积工艺而言，可显著降低成本。
图10A-图10I示出了根据本申请公开的第四实施例在制造半导体装置的若干阶段的示意图。在第四实施例中，首先执行如图5A-图5F所示的工艺流程。然后，将第二载具晶圆520接合到石墨烯膜502的上表面，特别是绝缘材料510上。具体地，可以使用粘结材料518将第二载具晶圆520接合到石墨烯膜502。例如，粘结材料508可以与粘结材料506不同，从而在去除粘结材料506时不会同时将粘结材料508去除。例如，粘结材料506可以是热敏胶合材料，而粘结材料518可以是UV敏感胶合材料。或者，粘结材料506可以是UV敏感胶合 材料，而粘结材料518可以是热敏胶合材料。备选地，也可以使用其他合适的接合工艺将第二载具晶圆520接合到石墨烯膜502。
在图10B，与图5H相似，将第一载具晶圆508去除，并将石墨烯膜502倒置。在图10C，与图5J相似，在石墨烯膜502上形成绝缘材料516，并且在填充材料512和绝缘材料516中形成通孔522。在图10D中，与图5K相似，在通孔522的侧壁以及绝缘材料516的表面上形成绝缘材料524。在图10E中，与图5N相似，使用导电材料来填充通孔522，以形成导电柱530。在图5F中，与图5O相似，剥离第二载具晶圆520，从而形成包含垂直互连的均热层结构。
在图10G，通过TSV工艺在第一半导体层514中形成导电柱550和围绕导电柱550的绝缘材料548。另外，在导电柱550的两端分别形成焊盘534、544。
在图10H，将如图10F所示的结构与如图10G所示的结构接合在一起。在接合的过程中，可以将导电柱530与第一半导体层514的相应焊盘544对齐，从而形成垂直互连。可以使用晶圆键合的方式来实现接合，也可以使用焊接的方式来实现接合。在接合之前，可以形成绝缘材料546来实现钝化作用，并在接合之后能够起到附加的支撑作用。
如图10H所示，导电柱530与导电柱550可以不具有相同的横向尺寸，并且中间嵌入了焊盘534作为整个垂直互连的一部分。在导电柱530的横向尺寸大于导电柱550的横向尺寸的情况下，制造导电柱530的工艺相对比较简单，容易实现，成本也低。然而，应当理解，导电柱530的横向尺寸也可以等于或者小于导电柱550的横向尺寸。
在图10I，在导电柱530上形成焊盘552，并通过焊球538将第二芯片540接合到焊盘552。另外，通过焊球536将底层芯片514接合到第三半导体层542。
根据第四实施例，可以避免在石墨烯膜和芯片晶圆中同时制作TSV导致TSV孔径比过高，导致工艺难度、复杂度和成本增加的问题。
图11A-图11J示出了根据本申请公开的第五实施例在制造半导体装置的各个阶段的示意图。在第五实施例中，首先执行如图8A-图8G所示的工艺流程。然后，在图11A，借助于粘结材料518的可剥离特性将第一半导体层514与第二载具晶圆520分离。接着，将石墨烯膜502，特别是绝缘材料516接合到第三载具晶圆556，例如，通过粘结材料554。粘结材料554可以与粘结材料506、518相似，为可剥离粘结材料。
在图11B，在第一半导体层514中形成通孔558。例如，可以通过蚀刻或激光开孔工艺来形成通孔558。这种开孔方案兼容TSV工艺，并且可以保证通孔定位的高精度。通孔558的大小可以根据第一半导体层514的具体要求来确定，例如，直径约10um。应当理解，该数值仅作为示例提供，目的不在于限制本申请公开的范围。
在图11C，在第一半导体层514的暴露表面上形成绝缘材料560。例如，可以通过物理或化学沉积方法来形成绝缘材料560。绝缘材料560可以作为介电层或钝化层，例如，绝缘材料560可以是低介电材料，耐温性等性能可满足后续半导体制作工艺，比如氧化硅。其他可选材料包括氮化硅、碳化硅、氧化硅、碳氧化硅、含氟硅玻璃、碳掺杂氧化硅和聚合物中的至少一种。备选地，可以不执行图11C所示的钝化步骤。
在图11D，在石墨烯膜502和绝缘材料510、516中形成通孔526。例如，可以通过蚀刻或激光开孔工艺来形成通孔526。备选地，也可以使用其他合适的开孔工艺。例如，通过非蚀刻方案开孔，特别是激光开孔，可以具有较高的开孔效率。
在图11E，在通孔526内形成绝缘材料562，具体地，在通孔526的侧壁以及绝缘材料560的表面上形成绝缘材料562。例如，可以通过物理或化学沉积方法来形成绝缘材料562。 绝缘材料562可以作为介电层或钝化层，例如，绝缘材料562可以是低介电材料，耐温性等性能可满足后续半导体制作工艺，比如氧化硅。其他可选材料包括氮化硅、碳化硅、氧化硅、碳氧化硅、含氟硅玻璃、碳掺杂氧化硅和聚合物中的至少一种。例如，绝缘材料562的厚度可以是约100nm。应当理解，该数值仅作为示例提供，目的不在于限制本申请公开的范围。
在图11F，形成导电材料来填充通孔526，以形成导电柱530。例如，可以使用电解镀来形成导电材料。在电解镀中，首先在通孔526的暴露表面上依次沉积阻挡层和种子层。阻挡层的厚度可以是约300nm。种子层的材料可以包括铜等，并且种子层的厚度可以是200nm。应当理解，该数值仅作为示例提供，目的不在于限制本申请公开的范围。然后，通过电解镀工艺在通孔126内形成电镀铜，以填充通孔526。备选地，也可以使用无电镀工艺等其他合适的方法来形成导电材料。
在图11G，借助于粘结材料554的可剥离特性来去除第三载具晶圆556。然后，去除可能残留在通孔526的底部的种子层，并在导电柱530的两端通过金属化工艺分别形成焊盘532和534。在图11H，在焊盘534上形成焊球536。在图11I，通过焊球536将第一半导体层514接合到第三半导体层542。例如，第三半导体层542可以是第三芯片或第三互连层。
在图11J，在焊盘532上形成焊球538，并通过焊球538将第一半导体层514接合到第二芯片540。例如，第二芯片540可以是四层HBM2芯片堆叠中的第四内核芯片晶圆，并且第一半导体层514可以是四层HBM2芯片堆叠中的底层芯片晶圆。
与第一实施例相比，第五实施例在芯片侧开孔，兼容TSV工艺，并同时保证通孔定位的高精度。然后从石墨烯侧开孔，可采用非刻蚀方案开孔(例如，激光开口)，可以实现更高的开孔效率。
在以上结合图5A-图11J描述的实施例中，均以石墨烯膜为例来进行说明，然而，导热层502的材料不局限于石墨烯基膜，也可以采用石墨烯基复合膜，例如，石墨/金属复合膜，也可采用石墨膜、石墨/金属复合膜、金属/碳复合膜、甚至铜合金膜等。此外，尽管以上将这些实施例分开描述，应当理解，可以将这些实施例进行各种适当的组合以形成另外的实施例，而仍然不脱离本申请公开的范围。
图12示出了根据本申请公开的一些实施方式的用于制造半导体装置的方法1200的流程图。在框1202，提供导热层。例如，导热层可以是如上所述的导热层102、314或石墨烯膜502。
在框1204，形成与导热层层叠的第一半导体层。例如，第一半导体层可以是第一半导体层114或者第一半导体层514。
在框1206，形成贯穿第一半导体层的导电柱，其中导电柱与导热层电绝缘。导电柱可以是导电柱130、134、530或550。
在一些实施例中，方法1200还可以包括在导热层的第一表面上形成第一绝缘层，例如，如图5F所示，在石墨烯膜502的表面上形成绝缘材料510。在该实施例中，如图5G所示，将第一半导体层(例如，第一半导体层514)接合到第一绝缘层(例如，绝缘材料510)，以在导热层(例如，石墨烯膜502)下方形成第一半导体层。
在一些实施例中，方法1200还可以包括在导热层(例如，石墨烯膜502)的第二表面上形成第二绝缘层(例如，绝缘材料516)，第二表面与第一表面相对，如图5J所示。在该实施例中，形成贯穿第二绝缘层(例如，绝缘材料516)、导热层(例如，石墨烯膜502)、第一绝缘层(例如，绝缘材料510)和第一半导体层(例如，第一半导体层514)的第一通孔(例如，通孔526)，如图5L所示。然后，在第一通孔(例如，通孔526)内形成导电柱(例如， 导电柱530)，如图5N所示。
在一些实施例中，形成第一绝缘层(例如，绝缘材料510)包括：在导热层(例如，石墨烯膜502)中形成第二通孔(例如，通孔504)，如图5B和图5C所示；以及在导热层(例如，石墨烯膜502)的第一表面和第二通孔(例如，通孔504)的侧壁上形成第一绝缘层(例如，绝缘材料510)，如图5F所示。
在一些实施例中，将第一半导体层(例如，第一半导体层514)接合到第一绝缘层(例如，绝缘材料510)包括：用填充材料(例如，填充材料512)来填充第二通孔(例如，通孔504)，如图5F所示；以及将第一半导体层(例如，第一半导体层514)接合到第一绝缘层(例如，绝缘材料510)和填充材料(例如，填充材料512)，如图5G所示。
在一些实施例中，形成第二绝缘层(例如，绝缘材料516)包括：在第二通孔(例如，通孔504)内和在导热层(例如，石墨烯膜502)的第一表面上形成第二绝缘层(例如，绝缘材料516)；以及用填充材料(例如，填充材料512)填充第二通孔(例如，通孔504)，如图7C所示。
在一些实施例中，形成第一通孔(例如，通孔526)包括：形成贯穿第二绝缘层(例如，绝缘材料516)和填充材料(例如，填充材料512)的第三通孔(例如，通孔522)，如图5J所示；在第二绝缘层(例如，绝缘材料516)和第三通孔(例如，通孔522)的侧壁和底部上形成第三绝缘层(例如，绝缘材料524)，如图5K所示；以及在第三通孔(例如，通孔522)处形成贯穿第三绝缘层(例如，绝缘材料524)和第一半导体层(例如，第一半导体层514)的第四通孔，其中第三通孔(例如，通孔522)与第四通孔形成第一通孔(例如，通孔526)，如图5L所示。
在一些实施例中，形成第一通孔(例如，通孔526)包括形成贯穿第二绝缘层(例如，绝缘材料516)、填充材料(例如，填充材料512)和第一半导体层(例如，第一半导体层514)的第一通孔(例如，通孔526)，如图6A所示。
在一些实施例中，形成第一通孔(例如，通孔526)包括：形成贯穿第二绝缘层(例如，绝缘材料516)和填充材料(例如，填充材料512)的第五通孔(例如，通孔522)和第六通孔(例如，通孔538)，如图9C所示；在第二绝缘层(例如，绝缘材料516)和第五通孔(例如，通孔522)和第六通孔(例如，通孔538)的侧壁和底部上形成第四绝缘层(例如，绝缘材料524)，如图5K所示；以及在第五通孔(例如，通孔522)和第六通孔(例如，通孔538)处分别形成贯穿第四绝缘层(例如，绝缘材料524)和第一半导体层(例如，第一半导体层514)的第七通孔和第八通孔，其中第五通孔(例如，通孔522)与第七通孔形成第一通孔(例如，通孔526)，并且第六通孔(例如，通孔538)和第八通孔形成第九通孔，如图5L所示。
在一些实施例中，形成导体柱(例如，导电柱530)包括：在第一通孔(例如，通孔526)的侧壁上形成第五绝缘层(例如，绝缘层528)，如图5M所示；以及用导电材料(例如，导电柱530)填充第一通孔(例如，通孔526)，以形成导体柱(例如，导电柱530)。例如，可以通过电解镀工艺来形成导电材料。
在一些实施例中，将导体柱(例如，导电柱530)的第一端与第一芯片(例如，第二芯片540)的接触互连；以及将导体柱(例如，导电柱530)的第二端与第三半导体层(例如，第三半导体层542)的接触互连。
在一些实施例中，形成第一通孔(例如，通孔526)包括：形成贯穿第二绝缘层(例如，绝缘材料516)、导热层(例如，石墨烯膜502)和第一绝缘层(例如，绝缘材料510)的第十通孔(例如，通孔522)，如图8H所示；在第二绝缘层(例如，绝缘材料516)和第十通孔 (例如，通孔522)的侧壁和底部上形成第六绝缘层(例如，绝缘材料524)，如图5K所示；以及在第十通孔(例如，通孔522)处形成贯穿第六绝缘层(例如，绝缘材料524)和第一半导体层(例如，第一半导体层514)的第十一通孔，其中第十通孔(例如，通孔522)与第十一通孔形成第一通孔(例如，通孔526)，如图5L所示。
在一些实施例中，导热层包括第一导电柱(例如，如图10H所示的导电柱530)并且第一半导体层包括第二导电柱(例如，如图10H所示的导电柱550)，并且形成贯穿第一半导体层与导热层的导电柱包括：将所述第一导电柱与所述第二导电柱对齐并且彼此互连，如图10H所示。
在一些实施例中，形成第一通孔(例如，通孔526)包括：在第一半导体层(例如，第一半导体层514)中形成第十二通孔(例如，通孔558)，如图11B所示；以及在第十二通孔(例如，通孔558)处，形成贯穿第一绝缘层(例如，绝缘材料510)、导热层(例如，石墨烯膜502)和第二绝缘层(例如，绝缘材料516)的第十三通孔，其中第十二通孔(例如，通孔558)与第十三通孔形成第一通孔(例如，通孔526)，如图11D所示。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，在不脱离所附权利要求所限定的本发明的精神和范围的情况下，可对本发明做出各种改变、替代和变化。而且，本申请的范围不旨在限于本说明书中所述的工艺、机器装置、制造、物质组成、工具、方法和步骤的具体实施例。本领域的技术人员通过本发明容易理解，根据本发明，可以利用已有的或今后将开发的、与本发明所述相应实施例执行基本相同的功能或者实现基本相同的结果的工艺、机器装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这些工艺、机器装置、制造、物质组成、工具、方法或步骤包括在它们的保护范围内。另外，每个权利要求组成单独的实施例，并且各个权利要求和实施例的组合都在本发明的范围内。

Claims (17)

  1. 一种半导体装置，其特征在于，包括：
    第一半导体层；
    第二芯片；
    导热层，与所述第一半导体层和所述第二芯片层叠设置并且位于所述第一半导体层与所述第二芯片之间，用于在所述导热层内传导来自所述第一半导体层和/或所述第二芯片的热量，所述导热层在水平方向的导热系数大于或等于在垂直方向的导热系数；以及
    第一导电柱，贯穿所述导热层，以使得所述第一半导体层与所述第二芯片通过所述第一导电柱实现电互连，其中所述第一导电柱与所述导热层电绝缘，所述第一导电柱的延伸方向为所述垂直方向，其中所述导热层在水平方向的导热系数大于所述第一半导体层的导热系数。
  2. 根据权利要求1所述的半导体装置，其特征在于，所述导热层上具有多个通孔，一个或多个所述第一导电柱贯穿一个所述通孔。
  3. 根据权利要求1或2所述的半导体装置，其特征在于，所述导热层与所述第一半导体层之间键合连接。
  4. 根据权利要求1至3任一项所述的半导体装置，其特征在于，还包括绝缘材料，所述绝缘材料包覆所述导热层的表面，所述第一导电柱还贯穿所述绝缘材料。
  5. 根据权利要求1至4任一项所述的半导体装置，其特征在于，还包括：
    绝缘层，被布置为至少部分围绕所述第一导电柱且沿所述第一导电柱延伸，用于将所述第一导电柱与所述导热层隔离以实现电绝缘。
  6. 根据权利要求5所述的半导体装置，其特征在于，还包括：
    填充材料，被布置在所述导热层中并且位于在所述导热层与所述绝缘层之间。
  7. 根据权利要求6所述的半导体装置，其特征在于，所述填充材料与硅通孔(TSV)工艺兼容，所述硅通孔是指通过在硅晶圆的通孔中填充导电材料以实现的电互连。
  8. 根据权利要求1至7任一项所述的半导体装置，其特征在于，所述第一半导体层为第一芯片或第一互连层。
  9. 根据权利要求1至8任一项所述的半导体装置，其特征在于，在所述第一半导体层为第一芯片时，所述第一导电柱还贯穿所述第一芯片。
  10. 根据权利要求9所述的半导体装置，其特征在于，所述半导体装置还包括：
    第三半导体层，被布置在所述第一半导体层远离所述导热层的一侧，所述第三半导体层与所述导电柱电耦合。
  11. 根据权利要求1至10任一项所述的半导体装置，其特征在于，所述导热层包括碳基材料、金属材料或其组合。
  12. 根据权利要求11所述的半导体装置，其特征在于，所述碳基材料包括石墨烯膜。
  13. 根据权利要求1所述的半导体装置，其特征在于，所述导热层的厚度至少为5um。
  14. 一种电子设备，其特征在于，包括：根据权利要求1-13中任一项所述的半导体装置。
  15. 一种均热片，其特征在于，包括：
    碳基材料层，所述碳基材料层在水平方向的导热系数大于或等于在垂直方向的导热系数；以及，
    第一非金属柱，贯穿所述碳基材料层，所述第一非金属柱的延伸方向为所述垂直方向，所述第一非金属柱的材质为绝缘或半导体的，其中所述第一非金属柱与所述碳基材料层接触 的部分是绝缘材料。
  16. 根据权利要求15所述的均热片，其特征在于，所述导热层的表面的粗糙度是小于或等于1nm。
  17. 根据权利要求15或16所述的均热片，其特征在于，所述第一非金属柱的直径在10μm至40μm之间。
PCT/CN2021/099498 2020-06-11 2021-06-10 半导体装置和包括该半导体装置的电子设备 WO2021249509A1 (zh)

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