WO2021246227A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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WO2021246227A1
WO2021246227A1 PCT/JP2021/019635 JP2021019635W WO2021246227A1 WO 2021246227 A1 WO2021246227 A1 WO 2021246227A1 JP 2021019635 W JP2021019635 W JP 2021019635W WO 2021246227 A1 WO2021246227 A1 WO 2021246227A1
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inclined surface
layer
semiconductor device
barrier layer
substrate
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French (fr)
Japanese (ja)
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裕介 神田
賢一 宮島
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Priority to EP21818171.7A priority Critical patent/EP4016586B1/en
Priority to JP2021572061A priority patent/JP7057473B1/ja
Priority to US17/765,765 priority patent/US11876120B2/en
Priority to CN202180005475.8A priority patent/CN114521293B/zh
Publication of WO2021246227A1 publication Critical patent/WO2021246227A1/ja
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Definitions

  • This disclosure relates to a patent application relating to the results of commissioned research by the national government, etc. regarding semiconductor devices, in particular, regarding group III nitride semiconductor devices using group III nitride semiconductors (FY2 of Ordinance, Ministry of Internal Affairs and Communications, 5G dissemination / This is a contracted business for research and development related to basic technology for development, and a patent application subject to Article 17 of the Industrial Technology Strengthening Law).
  • Group III nitride semiconductors especially group III nitride semiconductor devices using GaN (gallium nitride) or AlGaN (aluminum gallium nitride), have a high breakdown voltage due to the wide bandgap of the material. Further, in the group III nitride semiconductor device, a heterostructure such as AlGaN / GaN can be easily formed.
  • high-concentration electrons (hereinafter referred to as "two-dimensional electrons") are located on the GaN layer side of the AlGaN / GaN interface due to the difference between the piezo polarization generated from the lattice constant difference between the materials and the spontaneous polarization of AlGaN and GaN.
  • a channel is formed by the gas layer).
  • the group III nitride semiconductor device using the channel of this two-dimensional electron gas layer is a high-frequency power device because the electron saturation rate is relatively high, the insulation resistance is relatively high, and the thermal conductivity is also relatively high. It has been applied to.
  • ohmic contact the contact between the ohmic electrode and the two-dimensional electron gas layer in the group III nitride semiconductor device (hereinafter referred to as ohmic contact) and the paralysis of channel resistance, etc. It is advisable to reduce the resistance component as much as possible.
  • FIG. 8 is a cross-sectional view showing the configuration of the vicinity of the ohmic electrode in the group III nitride semiconductor device described in Patent Document 1.
  • a buffer layer 1102 a GaN layer 1103A, an AlN layer 1119, and an AlGaN layer 1104A are sequentially formed on the substrate 1101, and the AlN layer 1119 and the GaN are formed in this order.
  • the two-dimensional electron gas layer 1105 is provided on the GaN layer 1103A side.
  • the ohmic electrode 1108 is formed on the recess 1106 from which a part of the AlGaN layer 1104A, the AlN layer 1119, and the GaN layer 1103A is removed.
  • the angle of the recess 1106 that intersects the hetero interface between the AlN layer 1119 and the GaN layer 1103A with respect to the surface of the substrate 1101 is larger than 0 degrees on the acute angle side and 5 or less degrees on the acute angle side.
  • the two-dimensional electron gas layer 1105 and the ohmic electrode 1108 are brought into contact with each other, and the contact area can be increased, so that the resistance of the ohmic contact can be reduced.
  • the acute-angled side of the angle of the recess 1106 with respect to the surface of the substrate 1101 intersecting the hetero interface between the AlN layer 1119 and the GaN layer 1103A is a two-dimensional electron by reducing the angle.
  • the contact area between the gas layer 1105 and the ohmic electrode 1108 is increased, but it is still insufficient.
  • the AlN layer 1119 is indispensable for improving the performance of the group III nitride semiconductor device because it can improve the electron mobility and the sheet carrier concentration of the two-dimensional electron gas layer 1105, but it is in the upper layer because the band gap is large.
  • the contact from the AlGaN layer 1104A also has a problem that the AlN layer 1119 becomes a barrier and the resistance becomes very high.
  • the recess 1106 is formed by dry etching, the high resistance layer 1122 including crystal defects is formed on the exposed surfaces of the AlGaN layer 1104A, the AlN layer 1119 and the GaN layer 1103A by the recess 1106. Therefore, the two-dimensional electron gas layer 1105 and the ohmic electrode 1108 are not in direct contact with each other, and the distance is separated by the width of the high resistance layer 1122, so that the resistance of the ohmic contact increases.
  • the present disclosure has been made in view of such problems, and an object of the present disclosure is to provide a semiconductor device capable of reducing the resistance of ohmic contact.
  • the semiconductor device includes a substrate, a channel layer of an Al-free group III nitride provided on the substrate, and a group III nitride containing Al provided on the channel layer.
  • the Al composition ratio distribution of the barrier layer in the first direction orthogonal to the substrate surface is provided with an ohmic electrode provided in the recess and ohmic-connected to the two-dimensional electron gas layer generated in the channel layer.
  • the first inclined surface of the barrier layer having the maximum point at the first position and including the first position and in contact with the ohmic electrode in the first direction, and the first inclined surface below the first inclined surface.
  • the angle of the second inclined surface with respect to the substrate surface is such that the first inclined surface intersects with the second inclined surface of the barrier layer and is in contact with the ohmic electrode.
  • the second position which is smaller than the angle with respect to the angle and is the position of the first crossing line in the first direction, is lower than the first position.
  • the method for manufacturing a semiconductor device includes a step of forming a channel layer of Group III nitride containing no Al on a substrate and a barrier of Group III nitride containing an Al composition on the channel layer. 65 ° C. after the step of forming the layer, the dry etching step of forming a recess so as to form at least a part of the barrier layer from the surface of the laminated semiconductor including the channel layer and the barrier layer, and the dry etching step.
  • It has a wet etching step using the above alkaline chemical solution having a ph value of 10 to 14, a step of forming an ohmic electrode so as to embed the recess after the wet etching step, and a step of heat-treating the ohmic electrode.
  • the method for manufacturing a semiconductor device includes a step of forming a channel layer of Group III nitride on a substrate and a barrier of Group III nitride larger than the band gap of the channel layer on the channel layer.
  • a semiconductor device capable of reducing ohmic resistance is provided.
  • FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the embodiment.
  • FIG. 2 is an enlarged cross-sectional view showing a configuration in the vicinity of an ohmic electrode of the semiconductor device according to the embodiment.
  • FIG. 3 is a plan view and a cross-sectional view of the semiconductor device according to the embodiment after the dry etch step, the wet etch step, and the ohmic electrode formation.
  • FIG. 4 is an enlarged plan view showing a configuration in the vicinity of the gate electrode of the semiconductor device according to the embodiment.
  • FIG. 5A is a cross-sectional view and an enlarged cross-sectional view showing the structure of the semiconductor device according to the embodiment in the process of manufacturing.
  • FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the embodiment.
  • FIG. 2 is an enlarged cross-sectional view showing a configuration in the vicinity of an ohmic electrode of the semiconductor device according to the embodiment.
  • FIG. 3 is a plan view and
  • FIG. 5B is a cross-sectional view and an enlarged cross-sectional view showing the structure of the semiconductor device according to the embodiment in the process of manufacturing.
  • FIG. 5C is a cross-sectional view and an enlarged cross-sectional view showing the structure of the semiconductor device according to the embodiment in the process of manufacturing.
  • FIG. 5D is a cross-sectional view and an enlarged cross-sectional view showing the structure of the semiconductor device according to the embodiment in the process of manufacturing.
  • FIG. 5E is a cross-sectional view and an enlarged cross-sectional view showing the structure of the semiconductor device according to the embodiment in the process of manufacturing.
  • FIG. 5F is a cross-sectional view and an enlarged cross-sectional view showing the structure of the semiconductor device according to the embodiment in the process of manufacturing.
  • FIG. 6 is a TEM diagram showing a cross section of an ohmic electrode in the semiconductor device according to the embodiment.
  • FIG. 7 is an SEM diagram showing a plane of recess after the wet etching step in the semiconductor device according to the embodiment.
  • FIG. 8 is an enlarged cross-sectional view showing a configuration near an ohmic electrode of a conventional semiconductor device.
  • the inventors have conducted extensive studies and experiments in order to provide a semiconductor device that can reduce the resistance of ohmic contact. As a result, the inventors came up with the following semiconductor devices and the like.
  • the semiconductor device includes a substrate, a channel layer of an Al-free group III nitride provided on the substrate, and a group III nitride containing Al provided on the channel layer.
  • the Al composition ratio distribution of the barrier layer in the first direction orthogonal to the substrate surface is provided with an ohmic electrode provided in the recess and ohmic-connected to the two-dimensional electron gas layer generated in the channel layer.
  • the first inclined surface of the barrier layer having the maximum point at the first position and including the first position and in contact with the ohmic electrode in the first direction, and the first inclined surface below the first inclined surface.
  • the angle of the second inclined surface with respect to the substrate surface is such that the first inclined surface intersects with the second inclined surface of the barrier layer and is in contact with the ohmic electrode.
  • the second position which is smaller than the angle with respect to the angle and is the position of the first crossing line in the first direction, is lower than the first position.
  • the barrier layer on the second inclined surface can be made very thin. Therefore, the ohmic electrode and the two-dimensional electron gas layer can be ohmic-connected via the second inclined surface, and the contact area can be increased. Further, the contact area can be increased by reducing the angle of the second inclined surface with respect to the substrate surface. Further, since the second inclined surface is formed by wet etching, there is at least a part of the high resistance layer formed by dry etching. Therefore, in the second inclined surface where the contact area is increased, the distance between the two-dimensional electron gas layer and the ohmic electrode is short, and there is no resistance component, so that the resistance of the ohmic contact can be reduced.
  • the distance from the first position to the second position may be larger than 0.5 nm and 4 nm or less.
  • the angle of the second inclined surface with respect to the substrate surface becomes smaller. Therefore, since the area of the second inclined surface can be further increased, the resistance of the ohmic contact can be further reduced.
  • the first crossing line has three or more recesses recessed on the first inclined surface side in the second direction in which the first inclined surface and the second inclined surface are lined up.
  • the three or more recesses may be arranged irregularly.
  • the area of the second inclined surface can be further increased, so that the resistance of the ohmic contact can be further reduced.
  • the semiconductor device includes a substrate, a channel layer of Al-free Group III nitride provided on the substrate, and Group III nitride containing Al provided on the channel layer.
  • the Al composition ratio distribution of the barrier layer in the first direction orthogonal to the substrate surface is provided with an ohmic electrode provided in the recess and ohmic-connected to the two-dimensional electron gas layer generated in the channel layer.
  • the first inclined surface of the barrier layer having a maximum point at the first position and including the first position and in contact with the ohmic electrode in the first direction, and the first inclined surface below the first inclined surface.
  • the first crossing line has a second inclined surface of the barrier layer that intersects with the first crossing line and is in contact with the ohmic electrode. It has three or more recesses recessed on the second inclined surface side in the second direction in which the two inclined surfaces are lined up, and the three or more recesses in the third direction which is the extending direction of the first crossing line. Are lined up irregularly.
  • the area of the second inclined surface can be increased by forming the concave portion, so that the resistance of the ohmic contact can be reduced. Further, since the second inclined surface is formed by wet etching, there is at least a part of the high resistance layer formed by dry etching, so that the ohmic contact is made while shortening the distance between the two-dimensional electron gas layer and the ohmic electrode. Resistance can be reduced.
  • angle of the second inclined surface with respect to the substrate surface in each of the three or more recesses may be less than 90 degrees.
  • the area of the second inclined surface in the recess can be further increased, so that the resistance of the ohmic contact can be further reduced.
  • first crossing line in each of the three or more recesses may include a curved line.
  • the electric field concentration at the end of the ohmic electrode of the recess can be relaxed.
  • each of the three or more recesses may be 10 nm or more and 40 nm or less in the second direction.
  • the barrier layer may include an AlN layer, and the first position may be within the thickness range of the AlN layer in the first direction.
  • the Al composition ratio of the barrier layer at the first position may be 90% or more.
  • the distance between the first position and the bottom surface position of the barrier layer may be 10% or less of the thickness of the barrier layer.
  • the channel layer has a third inclined surface of the channel layer that intersects the second inclined surface at a second crossing line below the second inclined surface and is in contact with the ohmic electrode, and has the third inclined surface of the second inclined surface.
  • the angle with respect to the surface of the substrate may be smaller than the angle of the third inclined surface with respect to the surface of the substrate.
  • the channel layer has a third inclined surface of the channel layer that intersects the second inclined surface at a second crossing line below the second inclined surface and is in contact with the ohmic electrode, and has the third inclined surface of the third inclined surface.
  • the angle with respect to the surface of the substrate may be smaller than the angle of the first inclined surface with respect to the surface of the substrate.
  • the second inclined surface is formed by wet etching, so that the angle of the second inclined surface with respect to the substrate surface becomes small. Therefore, since the area of the second inclined surface can be further increased, the resistance of the ohmic contact can be further reduced.
  • the angle of the first inclined surface with respect to the substrate surface may be less than 90 degrees.
  • the second inclined surface may be a semi-polar surface of the semiconductor crystal constituting the barrier layer.
  • the second inclined surface is a semi-polar surface of the semiconductor crystal constituting the barrier layer, it is easier to form nitrogen vacancies by the heat treatment when forming the ohmic electrode, and it is easier to make it n-type. Therefore, the resistance of the ohmic contact can be further reduced.
  • angle of the second inclined surface with respect to the substrate surface may be 5 degrees or less.
  • the area of the second inclined surface can be further increased, so that the resistance of the ohmic contact can be further reduced.
  • the distance between the first position and the recess bottom surface position may be 1 nm or more and 10 nm or less.
  • the distance between the first position and the bottom surface of the recess can be made relatively small, so that the dry etching time at the time of recess formation can be shortened. Therefore, the amount of the high resistance layer formed on the recess side surface can be suppressed, so that the increase in the resistance value can be suppressed. Therefore, the resistance of the ohmic contact can be further reduced.
  • the ⁇ 0001> direction of the semiconductor crystal constituting the channel layer may be the first direction.
  • the sheet carrier concentration of the two-dimensional electron gas layer can be increased, so that the resistance of ohmic contact can be further reduced.
  • the stretching direction of the gate electrode in the plan view of the substrate may be the ⁇ 11-20> direction of the semiconductor crystal constituting the channel layer.
  • the method for manufacturing a semiconductor device includes a step of forming a channel layer of Group III nitride containing no Al on a substrate and a barrier of Group III nitride containing an Al composition on the channel layer. 65 ° C. after the step of forming the layer, the dry etching step of forming a recess so as to form at least a part of the barrier layer from the surface of the laminated semiconductor including the channel layer and the barrier layer, and the dry etching step.
  • It has a wet etching step using the above alkaline chemical solution having a ph value of 10 to 14, a step of forming an ohmic electrode so as to embed the recess after the wet etching step, and a step of heat-treating the ohmic electrode.
  • the second position which is the position of the first crossing line in the first direction, is lower than the first position where the Al composition ratio distribution is the maximum point, so that the second inclined surface is formed.
  • a barrier layer can be made very thin. Therefore, the ohmic electrode and the two-dimensional electron gas layer can be ohmic-connected via the second inclined surface, and the contact area can be increased.
  • the second inclined surface is formed by the wet etching process, there is at least a part of the high resistance layer formed by the dry etching. Therefore, the second inclined surface having a large contact area has a short distance between the two-dimensional electron gas layer and the ohmic electrode and has no resistance component, so that the resistance of the ohmic contact can be reduced.
  • the first crossing line can have a recess on the first inclined surface side in the second direction in which the first inclined surface and the second inclined surface are lined up.
  • the recesses are irregularly formed in the third direction, which is the extending direction of the first crossing line. Therefore, since the area of the second inclined surface can be further increased, the resistance of the ohmic contact can be further reduced.
  • the method for manufacturing a semiconductor device includes a step of forming a channel layer of Group III nitride on a substrate and a barrier of Group III nitride larger than the band gap of the channel layer on the channel layer.
  • FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device 100 according to the embodiment.
  • FIG. 2 is an enlarged cross-sectional view showing a configuration in the vicinity of the ohmic electrode of the semiconductor device 100.
  • FIG. 3 is a plan view and a cross-sectional view of the semiconductor device 100 after the dry etch step, after the wet etch step, and after forming the ohmic electrode.
  • the semiconductor device 100 is a heterojunction field effect transistor (HFET)
  • HFET heterojunction field effect transistor
  • the semiconductor device 100 includes a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104, a two-dimensional electron gas layer 105, a recess 106, a gate electrode 107, and a source electrode. It includes a 108S and a drain electrode 108D.
  • the source electrode 108S and the drain electrode 108D are also referred to as an ohmic electrode 108.
  • the substrate 101 is, for example, a substrate made of Si.
  • the substrate 101 is not limited to a substrate made of Si, and may be a substrate made of sapphire, SiC, GaN, AlN, or the like.
  • the buffer layer 102 is formed on the substrate 101.
  • the buffer layer 102 is, for example, a group III nitride semiconductor layer having a plurality of laminated structures of AlN and AlGaN having a thickness of 2 ⁇ m.
  • the buffer layer 102 may also be composed of a single layer or a plurality of layers of group III nitride semiconductors such as GaN, AlGaN, AlN, InGaN, and AlInGaN.
  • the channel layer 103 is formed above the substrate 101.
  • the channel layer 103 is formed on the buffer layer 102 in the + c plane direction ( ⁇ 0001> direction), for example.
  • the channel layer 103 is a group III nitride semiconductor layer containing no Al, and is composed of, for example, GaN having a thickness of 200 nm.
  • the channel layer 103 is not limited to GaN as long as it is a group III nitride semiconductor layer containing no Al, and may be composed of a group III nitride semiconductor such as InGaN. Further, the channel layer 103 may contain n-type impurities.
  • the barrier layer 104 is formed on the channel layer 103.
  • the barrier layer 104 is formed on the channel layer 103 in the + c plane direction ( ⁇ 0001> direction), for example.
  • the barrier layer 104 is a group III nitride semiconductor layer containing Al.
  • the Al composition ratio distribution of the barrier layer 104 in the first direction orthogonal to the substrate 101 has a maximum point at the first position 109.
  • high-concentration two-dimensional electron gas is generated on the channel layer 103 side of the hetero interface between the barrier layer 104 and the channel layer 103 laminated in the + c plane direction ( ⁇ 0001> direction), and is two-dimensional.
  • a channel of the electron gas layer 105 is formed.
  • a cap layer having a thickness of about 1 to 2 nm made of, for example, GaN may be provided on the barrier layer 104 as a cap layer.
  • the recess 106 is formed so as to remove the entire barrier layer 104 and a part of the channel layer 103 from the surface of the laminated semiconductor including the channel layer 103 and the barrier layer 104. Further, the recess 106 is formed so that the distance between the first position 109 and the bottom surface position of the recess 106 is 6 nm.
  • the recess 106 may be formed so as to remove at least a part of the barrier layer 104 from the surface of the laminated semiconductor composed of the channel layer 103 and the barrier layer 104, and the recess 106 does not necessarily have to be formed so as to remove the entire barrier layer 104 and the channel layer. It is not necessary to be limited to the example formed so as to remove a part of 103.
  • the gate electrode 107 is formed on the barrier layer 104.
  • the gate electrode 107 comes into contact with the barrier layer 104. More specifically, the gate electrode 107 is Schottky bonded to the barrier layer 104.
  • the gate electrode 107 has, for example, a multilayer film structure in which a Ni film and an Au film are laminated in order.
  • the gate electrode 107 may have a single-layer structure, or may have a multilayer film structure in which Ti, TiN, Ta, TaN, Pt, Pd, Al, W, WN, WSi, Cu, etc. are laminated in this order. good. Further, the gate electrode 107 and the barrier layer 104 do not necessarily have to be in contact with each other by Schottky junction, and may be contacted by, for example, a PN junction, or the gate electrode 107 and the barrier layer 104 may come into contact with each other.
  • a MIS (Metal-Insulator-Semiconductor) structure, a MOS (Metal-Oxide-Semiconductor) structure, or the like may be formed.
  • the ohmic electrode 108 is formed above the substrate 101.
  • the ohmic electrode 108 is, for example, a multilayer electrode film having a laminated structure in which a Ti film and an Al film are laminated in order.
  • the ohmic electrode 108 is not limited to the combination of Ti and Al, and may be a single-layer electrode film made of one metal such as Ti, Au, Ta, Al, Mo, Hf, Zr, Au, and Cu. , It may be a multilayer electrode film formed by combining two or more of these metals.
  • the ohmic electrode 108 is provided in the recess 106 and is electrically connected to the two-dimensional electron gas layer 105.
  • the barrier layer 104 and the channel layer 103 on the side surface of the recess 106 react with the ohmic electrode 108 by heat treatment to form nitrogen vacancies and are n-typed.
  • the exposed surface of the barrier layer 104 and the channel layer 103 on the side surface of the recess 106 is a semi-polar surface, it is easier to form nitrogen vacancies and more easily to form an n-shape.
  • the ohmic electrode 108 is ohmicly connected to the two-dimensional electron gas layer 105.
  • the semi-polar plane refers to a plane other than the plane in which atoms are regularly arranged in the GaN crystal.
  • the barrier layer 104 has, for example, an Al diffusion layer 120 having a thickness of 1 nm, an AlN layer 119 having a thickness of 1 nm, an Al diffusion layer 120 having a thickness of 1 nm, and a thickness of 20 nm.
  • the AlGaN layer 104A having an Al composition ratio of 25% is a group III nitride semiconductor layer laminated in this order.
  • Al is diffused from the AlN layer 119 by the heat generated when the AlN layer 119 and the barrier layer 104 are formed, and the Al diffusion layer 120 is formed on the channel layer 103 side and the AlGaN layer 104A side. Will be done.
  • the barrier layer 104 contains the AlN layer 119, which is a spacer layer, has been described, but the AlN layer 119 may not be present.
  • the AlGaN layer 104A may contain In, and the barrier layer 104 may contain n-type impurities.
  • the recess 106 has a first inclined surface 110 having a maximum point of Al composition ratio distribution at a first position 109 in contact with the ohmic electrode 108, a second inclined surface 111 below the first inclined surface 110, and a third inclined surface. It is provided with a surface 112. Specifically, as shown in the column (b) of FIG. 3, in the first direction, the first inclined surface 110, the second position 115 in the cross-sectional view, and the first crossing line 114 in the plan view are the first inclined surface 110.
  • It includes a second inclined surface 111 that intersects with the second inclined surface 111, a third position 124 in a cross-sectional view, and a third inclined surface 112 that intersects the second inclined surface 111 at the second crossing line 116 in a plan view.
  • the third inclined surface 112 intersects the bottom surface of the recess 106 at the fourth position 126, which is the end of the bottom surface of the recess 106 in the cross-sectional view, and the third crossing line 125 in the plan view.
  • the angle of the second inclined surface 111 with respect to the surface of the substrate 101 is smaller than the angle of the first inclined surface 110 with respect to the surface of the substrate 101, and the second position 115 is lower than the first position 109.
  • the distance from the first position 109 to the second position 115 is, for example, 1 nm.
  • the distance from the first position 109 to the second position 115 may be 0.5 to 4 nm or less. By reducing the distance from the first position 109 to the second position 115 in this way, the contact area between the ohmic electrode 108 and the two-dimensional electron gas layer 105 can be increased.
  • the angle of the second inclined surface 111 with respect to the surface of the substrate 101 is smaller than the angle of the third inclined surface 112 with respect to the surface of the substrate 101. Further, the angle of the third inclined surface 112 with respect to the surface of the substrate 101 is smaller than the angle of the first inclined surface 110 with respect to the surface of the substrate 101.
  • the angles of the first inclined surface 110, the second inclined surface 111, and the third inclined surface 112 with respect to the surface of the substrate 101 are, for example, the angle of the first inclined surface 110 of 70 degrees and the second inclined surface.
  • the angle of 111 is formed to be 2 degrees
  • the angle of the third inclined surface 112 is formed to be 45 degrees.
  • the angle of the second inclined surface 111 with respect to the surface of the substrate 101 may be 5 degrees or less. In this way, by reducing the angle of the second inclined surface 111 with respect to the surface of the substrate 101, the contact area between the ohmic electrode 108 and the two-dimensional electron gas layer 105 can be increased.
  • the first crossing line 114 has a recess 117 on the first inclined surface 110 side in the second direction in which the first inclined surface 110 and the second inclined surface 111 are lined up.
  • the recesses 117 are irregularly arranged in the third direction, which is the extending direction of the first crossing line 114. Since the second position 115A in the recess 117 can be recessed toward the first inclined surface 110 side to increase the area of the second inclined surface 111 as compared with the second position 115 in a position other than the recess 117, the resistance of the ohmic contact is further increased. Can be reduced.
  • the angle of the second inclined surface 111 with respect to the surface of the substrate 101 in the recess 117 may be less than 90 degrees. In this way, by making the angle of the second inclined surface 111 with respect to the surface of the substrate 101 less than 90 degrees, the contact area between the ohmic electrode 108 and the two-dimensional electron gas layer 105 can be increased.
  • the recess 117 may be formed so as to have a curved portion in a plan view. In this case, by having the curved portion in the concave portion 117, the electric field concentrated on the end portion of the ohmic electrode can be relaxed, so that the destruction of the device can be suppressed.
  • the depth of the recess 117 in the second direction may be 10 to 40 nm.
  • the width of the plurality of recesses 117 may be 100 to 500 nm in the third direction. Further, a plurality of recesses 117 may be arranged, the intervals between them may be 100 to 600 nm in the third direction, and the period may be 200 to 1100 nm.
  • the second position 115 is lower than the first position 109 as compared with the conventional technique of Patent Document 1, so that the barrier layer on the second inclined surface 111 is provided.
  • 104 can be made very thin. Therefore, the ohmic electrode 108 and the two-dimensional electron gas layer 105 can be ohmic-connected via the second inclined surface 111, and the contact area can be increased.
  • FIG. 4 is an enlarged plan view showing a configuration in the vicinity of the gate electrode of the semiconductor device 100.
  • the stretching direction of the gate electrode 107 in the plan view of the substrate 101 may be the ⁇ 11-20> direction of the direction 118 of the semiconductor crystals constituting the channel layer 103.
  • the temperature characteristics of Vth can be improved.
  • 5A to 5F are a cross-sectional view and an enlarged cross-sectional view showing the configuration of the semiconductor device 100 in the process of manufacturing, respectively.
  • the left side is a cross-sectional view showing the overall configuration of the semiconductor device 100
  • the right side is an enlarged cross-sectional view showing the configuration near the ohmic electrode 108.
  • a buffer having a thickness of 2 ⁇ m and a laminated structure of AlN and AlGaN is used on a substrate 101 made of Si by using a metalorganic vapor phase growth method (MOCVD: Metalorganic Chemical Vapor Deposition).
  • MOCVD Metalorganic Chemical Vapor Deposition
  • the layer 102, the channel layer 103 having a thickness of 200 nm and made of i-type GaN, the AlN layer 119 having a thickness of 1 nm, and the i-type AlGaN layer 104A having a thickness of 20 nm and an Al composition ratio of 25% are + c. It is sequentially epitaxially grown in the plane direction ( ⁇ 0001> direction).
  • the heat generated when the AlN layer 119 and the AlGaN layer 104A are formed causes Al to diffuse from the AlN layer 119, and the Al diffusion layer 120 is formed on the channel layer 103 side and the AlGaN layer 104A side.
  • the barrier layer 104 composed of the Al diffusion layer 120, the AlN layer 119, and the AlGaN layer 104A, in which the maximum point of the Al composition ratio distribution is provided at the first position 109, is formed.
  • the lower surface of the Al diffusion layer 120 on the substrate 101 side serves as a hetero interface.
  • High-concentration two-dimensional electron gas is generated on the channel layer 103 side of the hetero interface between the barrier layer 104 and the channel layer 103, and the channel of the two-dimensional electron gas layer 105 is formed.
  • an insulating layer 121 made of SiN having a thickness of 50 nm is deposited on the barrier layer 104 by a plasma CVD method, and then a resist 127 is applied to a region forming a recess 106. After that, the resist 127 is patterned using a lithography method. Next, a wet etching method is used to form an opening in the insulating layer 121 so that the barrier layer 104 is exposed.
  • a side etch is applied to the insulating layer 121 by a wet etching method, and the side surface of the insulating layer 121 is retracted to the inside of the resist 127 with respect to the side surface of the resist 127 to form an opening so as to be located below the resist 127. do.
  • the wet etching method is used in this embodiment, the insulating layer 121 may be opened by using a chemical dry etching method. Further, the insulating layer 121 may be SiO 2 , SiON, or SiCN.
  • the barrier layer 104 and the channel are subjected to an etching process containing Cl 2 gas using an inductively coupled (ICP: Inductively Coupled Plasma) dry etching apparatus using the resist 127 as a mask.
  • ICP Inductively Coupled Plasma
  • the fourth position 126 is formed at the end of the bottom surface of the recess, and becomes the third crossing line 125 as shown in the row (a) of FIG. 3 in a plan view.
  • crystal defects are generated on the surfaces of the barrier layer 104 and the channel layer 103 exposed by the dry etching process, and the high resistance layer 122 is formed.
  • the distance between the first position 109 and the bottom surface position of the recess 106 is 6 nm in this embodiment. By doing so, it is possible to shorten the dry etching time at the time of forming the recess 106 and suppress the increase in the resistance of the high resistance layer 122. Further, in the first direction, the distance between the first position 109 and the bottom surface position of the recess 106 may be 1 nm or more and 10 nm or less. Further, the side surface of the insulating layer 121 is protected by the resist 127 because the side surface of the insulating layer 121 is retracted to the inside of the resist 127 with respect to the side surface of the resist 127 during wet etching and is under the resist 127.
  • the surface and the side surface of the insulating layer 121 are not damaged by dry etching. Therefore, during the heat treatment for forming the ohmic contact, the mutual diffusion between the ohmic electrode 108 and the insulating layer 121 can be reduced.
  • the recess 106 is formed by using the resist 127 as a mask, but the recess 106 may be formed by using the insulating layer 121 as a mask after removing the resist 127.
  • plasma processing by an ICP dry etching apparatus will be described, but capacitively coupled (CCP: Capacitively Coupled Plasma) or electron cyclone resonance (ECR) dry.
  • CCP Capacitively Coupled Plasma
  • ECR electron cyclone resonance
  • the etching process by the ICP dry etching apparatus is performed, for example, by using Cl 2 as a gas raw material and introducing CL 2 gas at a gas flow rate of 10 to 30 sccm.
  • Cl 2 as a gas raw material
  • CL 2 gas at a gas flow rate of 10 to 30 sccm.
  • the inert gas Ar (argon) or He (helium) may be introduced to dilute the mixture.
  • the pressure of the etching process atmosphere is 0.5 to 3 Pa
  • the applied power to the upper electrode by the 13.56 MHz power supply is 50 to 200 W
  • the applied power to the lower electrode by the 13.56 MHz power supply is 5 to 20 W
  • the substrate temperature is 0 to 20 ° C.
  • the resist 127 is removed with a resist removing solution, the polymer is removed with a polymer washing solution, and then an alkaline chemical solution having a pH value of 10 to 14 and a temperature of 65 ° C. or higher is applied.
  • the channel layer 103 and the barrier layer 104 exposed on the side surface of the resist 106 are wet-etched only in the side surface direction with the barrier layer 104 highly selected with respect to the channel layer 103.
  • the barrier layer 104 is formed with the first inclined surface 110 including the first position 109 and the second inclined surface 111, and the channel layer 103 is formed with the third inclined surface 112.
  • a third position 124 is formed where the surface 111 and the third inclined surface 112 intersect.
  • the second position 115 and the third position 124 in the cross-sectional view are the first crossing line 114 and the second crossing line 116 in the plan view, respectively.
  • the second position 115 is formed below the first position 109.
  • the angles of the first inclined surface 110, the second inclined surface 111, and the third inclined surface 112 with respect to the surface of the substrate 101 are, for example, 70 degrees for the angle of the first inclined surface 110 and the second inclined surface.
  • the angle of 111 is formed to be 2 degrees
  • the angle of the third inclined surface 112 is formed to be 45 degrees.
  • the barrier layer 104 is removed to form the first inclined surface 110 and the second inclined surface 111, so that the height of the first inclined surface 110 and the second inclined surface 111 is increased. At least a part of the resistance layer 122 is removed. Since the insulating layer 121 covers at least a part of the surface of the barrier layer 104 on which the gate electrode 107 is formed, the barrier layer 104 under the gate electrode 107 suppresses the increase of crystal defects due to the alkaline chemical solution. be able to.
  • the dislocation 123 is present in the barrier layer 104.
  • the barrier layer 104 is etched starting from the dislocation 123, and a plurality of concave portions 117 including curves are irregularly formed in the barrier layer 104. Ru.
  • the angle of the first inclined surface 110 with respect to the surface of the substrate 101 in the recess 117 is less than 90 degrees, and the depth of the recess 117 in the second direction is 10 to 40 nm.
  • the width of the recess 117 may be 100 to 500 nm in the third direction. Further, three or more recesses 117 may be arranged, the interval between them may be 100 to 600 nm in the third direction, and the period may be 200 to 1100 nm.
  • the barrier layer 104 is highly selectively etched only in the side surface direction with respect to the channel layer 103 using an alkaline chemical solution, so that the first inclined surface 110, the second inclined surface 111, and the third inclined surface 112 are etched.
  • Etching of AlGaN with an alkaline chemical solution is dependent on the crystal orientation, and it is difficult to etch from the upper surface, but it can be etched from the side surface.
  • the polar surface is composed of Group III Al and Ga, and the etching rate is significantly slowed down.
  • the side surface is a semi-polar surface, it can be etched at a certain speed.
  • the alkaline chemical solution has a pH value of 10 to 14 and a temperature of 65 ° C. or higher so that the GaN containing no Al is not etched, and the etching rate gradually increases as the Al GaN content of Al increases. Becomes faster.
  • the barrier layer 104 containing Al without etching the channel layer 103 containing no Al, and the first point in the barrier layer 104, which is composed of the maximum points in the Al composition ratio distribution.
  • the AlN layer 119 including the position 109 is most etched.
  • the first inclined surface 110, the second inclined surface 111, and the third inclined surface 112 are formed with high accuracy. Further, since the Al diffusion layer 120 on the substrate side is at least partially etched, the second position 115 is formed below the first position 109.
  • the angle of the second inclined surface 111 with respect to the surface of the substrate 101 is smaller than the angle of the first inclined surface 110 with respect to the surface of the substrate 101. Further, the angle of the second inclined surface 111 with respect to the substrate surface is smaller than the angle of the third inclined surface 112 with respect to the surface of the substrate 101. Further, the angle of the third inclined surface 112 with respect to the surface of the substrate 101 is smaller than the angle of the first inclined surface 110 with respect to the surface of the substrate 101. Further, the angle of the first inclined surface 110 with respect to the surface of the substrate 101 is less than 90 degrees.
  • the angle of the second inclined surface 111 with respect to the substrate surface may be 5 degrees or less.
  • a barrier layer 104 and the channel layer 103 on the surface of the recess 106 may be n-type by inclusive plasma treatment SiCl 4 gas. Further, after the recess 106 is formed, the barrier layer 104 and a part of the channel layer 103 may be n-shaped in a predetermined region by an ion implantation device.
  • an etching treatment with an ammonia hydrogen peroxide solution (APM: Ammonia-Hydrogen Peroxide Mixture) will be described, but tetramethylammonium hydroxide (TMAH: Tetramethylammonium Hydroxide) will be described.
  • TMAH Tetramethylammonium Hydroxide
  • KOH Potassium hydroxide
  • the pH value of the alkaline chemical solution may be 10 to 14, and the temperature of the chemical solution may be 65 ° C. or higher.
  • the barrier layer 104 can be more selectively etched only on the side surface with respect to the channel layer 103.
  • the Ti film and the Al film are sequentially deposited by the sputtering method after pre-cleaning with hydrochloric acid, and then the lithography method and the dry etching method are sequentially applied to form the Ti film and the Al film.
  • an ohmic electrode 108 having a predetermined shape is formed on the recess 106.
  • the Ti film and the Al film may be deposited in order by a vapor deposition method instead of a sputtering method to form an ohmic electrode 108 having a predetermined shape.
  • the ohmic electrode 108 is not limited to the combination of Ti and Al, and may be a single-layer electrode film made of one metal such as Ti, Au, Ta, Al, Mo, Hf, Zr, Au, and Cu. , It may be a multilayer electrode film formed by combining two or more of these metals.
  • the angle of the first inclined surface 110 with respect to the surface of the substrate 101 is less than 90 degrees, metal atoms can be driven into the second inclined surface 111 when the ohmic electrode 108 is formed by sputtering, and further, ohmic.
  • the resistance of the contact can be reduced.
  • the film can be formed with good coverage, and the resistance of the ohmic contact can be stably reduced.
  • the second inclined surface 111 is a semi-polar surface of the semiconductor crystal constituting the barrier layer 104, it is easier to form nitrogen vacancies and more easily to form an n-type.
  • the temperature of the heat treatment is 500 ° C. in this embodiment, it may be 500 ° C. or lower, or 500 ° C. or higher to less than 1000 ° C.
  • the Ni film and the Au film are sequentially deposited by the sputtering method, and then the lithography method and the dry etching method are sequentially applied to pattern the laminated film of the Ni film and the Au film, thereby performing the gate.
  • the electrode 107 is formed on the barrier layer 104.
  • a Ni film and an Au film may be sequentially deposited by a vapor deposition method instead of a sputtering method to form a gate electrode 107 having a predetermined shape.
  • the stretching direction of the gate electrode 107 in the plan view of the substrate 101 may be the ⁇ 11-20> direction of the semiconductor crystal constituting the channel layer 103.
  • the barrier layer 104 on the second inclined surface 111 is very large. Can be thinned to. Therefore, the ohmic electrode 108 and the two-dimensional electron gas layer 105 can be ohmic-connected via the second inclined surface 111, and the contact area can be increased. Further, since the second inclined surface 111 is formed by wet etching, at least a part of the high resistance layer 122 formed by dry etching is removed.
  • the second inclined surface 111 having a large contact area has a short distance between the two-dimensional electron gas layer 105 and the ohmic electrode 108, and has no resistance component, so that the resistance of the ohmic contact can be further reduced.
  • FIG. 6 shows a cross-sectional TEM (Transmission Electron Microscope) photograph showing a cross section in the vicinity of the ohmic electrode in the configuration example shown in FIG. 2 for the semiconductor device 100 manufactured by using the manufacturing method in the present embodiment.
  • the second position 115 is below the first position 109 where the Al composition ratio distribution is the maximum point, and the angle with respect to the surface of the substrate 101 is 70 degrees with respect to the angle of the first inclined surface 110. It can be seen that the angle of the second inclined surface 111 is 2 degrees and the angle of the third inclined surface 112 is 45 degrees.
  • the semiconductor device according to the present disclosure is useful for communication devices and inverters that require high-speed operation, power switching elements used in power supply circuits, and the like.

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  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Cited By (2)

* Cited by examiner, † Cited by third party
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JP2024141592A (ja) * 2023-03-29 2024-10-10 豊田合成株式会社 半導体素子およびその製造方法
JP7821387B2 (ja) 2023-03-29 2026-02-27 豊田合成株式会社 半導体素子およびその製造方法

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