WO2021227569A1 - 电容打开孔的形成方法和存储器电容的形成方法 - Google Patents

电容打开孔的形成方法和存储器电容的形成方法 Download PDF

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Publication number
WO2021227569A1
WO2021227569A1 PCT/CN2021/075035 CN2021075035W WO2021227569A1 WO 2021227569 A1 WO2021227569 A1 WO 2021227569A1 CN 2021075035 W CN2021075035 W CN 2021075035W WO 2021227569 A1 WO2021227569 A1 WO 2021227569A1
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layer
capacitor
forming
initial
sidewall structure
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PCT/CN2021/075035
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to EP21803389.2A priority Critical patent/EP4002504A4/en
Priority to US17/379,064 priority patent/US20210358914A1/en
Publication of WO2021227569A1 publication Critical patent/WO2021227569A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of semiconductors, and in particular to a method for forming a capacitor opening hole and a method for forming a storage capacitor.
  • DRAM Dynamic Random Access Memory
  • a memory capacitor of a DRAM When forming a memory capacitor of a DRAM, it is necessary to first form a sacrificial layer on the surface of the substrate as a supporting structure for the capacitor hole, and after forming an electrode of the capacitor, the sacrificial layer is removed and the remaining capacitor structure is formed. Therefore, it is necessary to connect the capacitor hole through the capacitor opening hole to expose the sacrificial layer to the etching environment, thereby removing the sacrificial layer.
  • the size of the opening of the capacitor is also continuously shrinking, and the existing manufacturing technology can no longer meet the rapidly developing requirements for the size and accuracy of the opening of the capacitor.
  • a method for forming a capacitor opening hole and a method for forming a storage capacitor are provided.
  • a method for forming a capacitor opening hole includes:
  • first sidewall structure and the second sidewall structure as masks to etch the sacrificial layer and the support layer to form the capacitor opening hole.
  • a method for forming a storage capacitor includes:
  • the capacitor opening hole being used to communicate with a plurality of adjacent capacitor holes;
  • a capacitor dielectric layer and a second electrode layer are sequentially formed on the inner wall of the capacitor opening hole and the surface of the first electrode layer.
  • the first electrode layer, the capacitor dielectric layer, and the second electrode layer together constitute a ⁇ Storage capacitance.
  • Fig. 1 is a flowchart of a method for forming a capacitor opening hole according to one or more embodiments
  • FIG. 2 is a schematic cross-sectional view of a substrate on which a sacrificial layer and a supporting layer have been formed according to one or more embodiments;
  • FIG. 3 is a schematic top view of the device structure of the embodiment shown in FIG. 2;
  • FIG. 4 is a schematic top view of a first side wall structure according to one or more embodiments
  • FIG. 5 is a schematic top view of the first side wall structure and the second side wall structure after step S300 according to one or more embodiments;
  • Fig. 6 is a sub-flow chart of step S200 according to one or more embodiments.
  • FIG. 7 is a schematic top view of the initial sidewall structure after step S210 according to one or more embodiments.
  • step S220 is a schematic top view of the initial sidewall structure and the first material layer after step S220 according to one or more embodiments;
  • Fig. 9 is a sub-flow chart of step S210 according to one or more embodiments.
  • FIG. 10 is a schematic top view of the device structure after step S211 according to one or more embodiments.
  • FIG. 11 is a schematic top view of the device structure after step S212 in the embodiment shown in FIG. 10;
  • FIG. 12 is a schematic diagram of the positional relationship between the sidewall structure and the capacitor hole according to one or more embodiments
  • FIG. 13 is a method for forming a storage capacitor according to one or more embodiments.
  • step S10 is a schematic cross-sectional view of the device structure after step S10 according to one or more embodiments
  • step S30 is a schematic cross-sectional view of the device structure after step S30 according to one or more embodiments;
  • step S40 is a schematic cross-sectional view of the device structure after step S40 according to one or more embodiments
  • 17 is a schematic cross-sectional view of the device structure after S50 according to one or more embodiments.
  • FIG. 18 is a schematic cross-sectional view of the device structure after step S60 according to one or more embodiments.
  • first element, component, region, layer, doping type or portion discussed below may be expressed as a second element, component, region, layer or portion.
  • Spatial relationship terms such as “under”, “below”, “below”, “below”, “above”, “above”, etc., in This can be used to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is turned over, elements or features described as “under” or “under” or “under” other elements will be oriented “on” the other elements or features. Therefore, the exemplary terms “below” and “below” can include both an orientation of above and below. In addition, the device may also include other orientations (for example, rotated by 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • the embodiment of the invention is described here with reference to a cross-sectional view which is a schematic diagram of an ideal embodiment (and intermediate structure) of the invention, so that changes in the shown shape due to, for example, manufacturing technology and/or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shape of the regions shown here, but include shape deviations due to, for example, manufacturing techniques. For example, an implanted area shown as a rectangle usually has rounded or curved features and/or an implanted concentration gradient at its edges, rather than a binary change from an implanted area to a non-implanted area. Likewise, the buried region formed by the implantation can result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figure are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present invention.
  • FIG. 1 is a flowchart of a method for forming a capacitor opening hole according to one or more embodiments. As shown in FIG. 1, in this embodiment, the method for forming a capacitor opening hole includes steps S100 to S400.
  • a substrate is provided, and a sacrificial layer 110 and a supporting layer 120 are stacked on the surface of the substrate.
  • multiple active regions and isolation structures have been formed in the substrate, the multiple active regions are arranged in an array, and the isolation structure is provided between adjacent active regions, and each active region At least one transistor and a word line structure penetrating the active area are formed in each of them, and a bit line structure is formed on the surface of the active area.
  • the gate of each transistor is electrically connected to the word line structure
  • the drain is electrically connected to the bit line structure
  • the source is electrically connected to the first electrode layer 400 of the memory capacitor, thereby accessing data to the memory capacitor.
  • FIG. 2 is a schematic cross-sectional view of a substrate on which a sacrificial layer 110 and a supporting layer 120 have been formed in an embodiment.
  • a plurality of contact pads 101 are also formed in the substrate, and the plurality of contact pads 101 are It is arranged regularly in the horizontal plane, and each contact pad 101 corresponds to a capacitor hole 200.
  • 3 is a schematic top view of the device structure of the embodiment of FIG. 2.
  • a plurality of capacitor holes 200 are formed in the sacrificial layer 110 and the support layer 120, and the capacitor holes 200 extend along The straight direction penetrates through the sacrificial layer 110 and the support layer 120 to the surface of the substrate.
  • the six adjacent capacitor holes 200 are arranged in a regular hexagon in the horizontal plane. Each vertex of the regular hexagon is provided with a capacitor hole 200, and A capacitor hole 200 is provided in the center of the regular hexagon.
  • the arrangement of the capacitor holes 200 is a Hexagonal Closest Packed (HCP) structure. Based on the HCP structure, densely arranged memory capacitors can be formed in subsequent steps, thereby improving the arrangement density and integration of memory capacitors in the DRAM.
  • HCP Hexagonal Closest Packed
  • the arrangement of six adjacent capacitor holes 200 in a regular hexagon in the horizontal plane means that the center point of each capacitor hole 200 forms a virtual regular hexagon in the horizontal plane as shown in FIG. 3, and in other implementations
  • the definition of the regular hexagonal arrangement in the horizontal plane is the same as the definition in this embodiment, and will not be repeated.
  • a spacer layer is formed between adjacent contact pads 101 to isolate different contact pads 101, so as to prevent a short circuit phenomenon between different contact pads 101, so as to improve the reliability of the DRAM.
  • the material of the contact pad 101 may be one or more of tungsten, aluminum, copper, titanium, tantalum, and polysilicon.
  • the material of the spacer layer may be one or more of silicon nitride (SiN), silicon oxide (SiO2), and aluminum oxide (Al2O3).
  • the material of the sacrificial layer 110 may be one or more of silicon dioxide (SiO2), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), and fluorosilicate glass (FSG). kind.
  • the material of the support layer 120 may be, but is not limited to, silicon nitride (Si3N4).
  • S200 forming a plurality of hollow first sidewall structures 310 arranged at intervals on the surface of the supporting layer 120.
  • FIG. 4 is a schematic top view of the first side wall structure 310 of an embodiment.
  • the first side wall structure 310 is in the shape of a hollow column.
  • the structures 310 are arranged in an array, wherein the hollow column shape may be a hollow cylindrical shape, a quadrangular prism shape, a hexagonal prism shape, an octagonal prism shape, etc.
  • the specific shape of the column shape is not limited in this embodiment. It should be noted that, in FIG. 4, only the first sidewall structure 310 is shown, and structures such as the support layer 120 and the capacitor hole 200 located on the lower side of the first sidewall structure 310 are not shown.
  • the shape of the first sidewall structure 310 so as to obtain better device structure and device performance, that is, the first sidewall structure 310 may not be limited to the above-mentioned regular columnar structure, and in the design layout of other structures in other embodiments Also, the layout graphics will be adjusted appropriately to obtain better device structure and device performance, which will not be repeated in other embodiments.
  • the six adjacent first side wall structures 310 are arranged in a regular hexagon in the horizontal plane, and each vertex of the regular hexagon is provided with a first side wall structure 310.
  • a first side wall structure 310 is provided in the center of the regular hexagon.
  • the size of the first sidewall structure 310 matches the size of the capacitor hole 200, that is, the larger the size of the capacitor hole 200 and the distance between the adjacent capacitor holes 200, the larger the size of the first sidewall structure 310 and the size of the adjacent first sidewall structure.
  • the distance between the side wall structures 310 is correspondingly larger, so that the capacitor opening 300 can effectively communicate with the corresponding plurality of capacitor holes 200.
  • a second material layer is formed on the surface of the first sidewall structure 310 to form the second sidewall structure 320.
  • FIG. 5 is a schematic top view of the first side wall structure 310 and the second side wall structure 320 after step S300 in an embodiment.
  • the second material layer covers the first side wall structure
  • the second material layer may also cover the top of the first sidewall structure 310.
  • the forming method of this embodiment can effectively improve the manufacturing accuracy of the capacitor opening 300.
  • the first sidewall structure 310 as a hollow cylinder as an example, assuming that the minimum process dimension d1 of the exposure process is used to form the first sidewall structure 310, the inner contour of the first sidewall structure 310 The diameter is d1. If the capacitor opening hole 300 is formed based on the first sidewall structure 310, the diameter of the capacitor opening hole 300 is also d1.
  • a second sidewall with an inner profile diameter d2 can be obtained Structure 320, and d2 ⁇ d1, so that a smaller-sized capacitor opening 300 can be prepared, which improves the manufacturing precision of the capacitor opening 300 and also improves the manufacturing yield of the capacitor opening 300 at the same time.
  • S400 Use the first sidewall structure 310 and the second sidewall structure 320 as masks to etch the sacrificial layer 110 and the support layer 120 to form the capacitor opening hole 300.
  • a dry etching process can be used to remove the sacrificial layer 110 and the support layer 120.
  • the etching gas can be a mixture of carbon tetrafluoride and chloroform.
  • the etching selection ratio of 120 and the sacrificial layer 110 is to etch the support layer 120 and the sacrificial layer 110.
  • a dry etching process may be used to remove the support layer 120, and a wet etching process may be used to remove the sacrificial layer 110.
  • the operation of the wet etching process is simpler, and there is no need to consider the etching selection ratio of the support layer 120 and the sacrificial layer 110, but it will increase the number of steps in the process and thus lengthen the production cycle. Therefore, it can be prepared according to actual production requirements. , Choose a more appropriate etching process.
  • the first sidewall structure 310 and the second sidewall structure 320 that are closely arranged can be formed to further form the capacitor opening holes 300.
  • the formation method of the double sidewall structure can not only realize the connection effect of the capacitor opening hole 300, but also can prepare the capacitor opening hole 300 with a smaller volume, thereby improving the preparation accuracy of the capacitor opening hole 300.
  • Fig. 6 is a sub-flow chart of step S200 in an embodiment. As shown in Fig. 6, in this embodiment, step S200 includes steps S210 to S230.
  • a plurality of initial sidewall structures 330 are formed at intervals on the surface of the support layer 120, and the initial sidewall structures 330 are columnar.
  • FIG. 7 is a schematic top view of the initial side wall structure 330 after step S210 of an embodiment, wherein the cylindrical initial side wall structure 330 may be cylindrical, quadrangular prism, hexagonal prism, octagonal prism, etc. .
  • the initial sidewall structure 330 is used as a supporting structure to form the first sidewall structure 310 in subsequent steps.
  • the six adjacent initial side wall structures 330 are arranged in a regular hexagon in the horizontal plane, and each vertex of the regular hexagon is provided with an initial side wall structure 330, and the regular hexagon An initial side wall structure 330 is provided in the center of the.
  • the initial sidewall structure 330 is a photoresist material
  • the initial sidewall structure 330 is formed by the following steps: forming a first photoresist layer on the surface of the support layer 120, and then exposing the first sidewall structure through the photomask of the initial sidewall structure A photoresist layer is developed and the remaining first photoresist layer serves as the initial sidewall structure 330.
  • the preparation process of the initial sidewall structure 330 formed by the method of this example is simple, and the preparation period can be effectively shortened.
  • the initial sidewall spacer structure 330 is a silicon compound doped with elements such as carbon, nitrogen, oxygen, etc., and the initial sidewall spacer structure 330 is formed by the following steps: an initial sidewall spacer material layer and The second photoresist layer is exposed and developed through the mask of the initial sidewall structure to form a patterned second photoresist layer, and the patterned second photoresist layer shields the initial In the area of the sidewall structure 330, the initial sidewall material layer is finally etched using the patterned second photoresist layer as a mask, and the remaining initial sidewall material layer is used as the initial sidewall structure 330.
  • the initial sidewall structure 330 formed by the method of this example has greater strength and is not easily deformed. Therefore, the first sidewall structure 310 prepared based on the initial sidewall structure 330 has better shape accuracy. Among them, the initial sidewall structure 330 and the first sidewall structure 310 have a larger etching selection ratio.
  • S220 forming a first material layer on the sidewalls of the initial sidewall structure 330.
  • FIG. 8 is a schematic top view of the initial sidewall structure 330 and the first material layer after step S220 of an embodiment.
  • the first material layer is formed on the sidewalls of the initial sidewall structure 330.
  • the material of the first material layer may be nitride, for example, silicon nitride, and physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer Deposition (ALD) and other methods are formed.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer Deposition
  • the first material layer needs to expose a part of the initial sidewall structure 330 so as to facilitate the removal of the initial sidewall structure 330 in subsequent steps.
  • the strength of silicon nitride is relatively high, so it has good structural stability, so that it can effectively support the second sidewall structure 320 to be formed later.
  • steps S210 to S230 a plurality of first sidewall structures 310 arranged at intervals as shown in FIG. 4 can be formed. Furthermore, by changing the deposition time of the first material layer, the deposition thickness of the first sidewall structure 310 can be changed accurately and quickly without changing the pattern in the photomask, thereby providing higher manufacturing flexibility. To be compatible with capacitor holes 200 of different sizes or different pitches.
  • Fig. 9 is a sub-flow chart of step S210 in an embodiment. As shown in Fig. 9, in this embodiment, step S210 includes steps S211 to S212.
  • S212 Form a plurality of second initial sidewalls 332 on the surface of the supporting layer 120.
  • the first initial side wall 331 and the second initial side wall 332 have the same shape and are arranged at intervals.
  • the multiple first initial side walls 331 and the multiple second initial side walls 332 together form the initial side wall structure 330.
  • 10 is a schematic top view of the device structure after step S211 in an embodiment
  • FIG. 11 is a schematic top view of the device structure after step S212 in the embodiment of FIG. 10, as shown in FIGS. 10 to 11, in this embodiment
  • the number of initial sidewall structures 330 to be formed in each step can be reduced, thereby reducing the difficulty of preparing the initial sidewall structures 330 and improving the production yield of the initial sidewall structures 330 .
  • the arrangement density of the multiple initial sidewall structures 330 is too high, it can also be split into multiple steps for preparation, and the splitting method is not limited to the splitting method shown in FIGS. 10 to 11.
  • step S300 includes: forming an oxide layer on the surface of the first sidewall structure 310 by a growth process to form the second sidewall structure 320.
  • the oxide layer may be a silicon oxide layer.
  • an oxide layer is simultaneously grown on the inner and outer sidewalls of the first sidewall structure 310 through a one-step process. Therefore, the second sidewall structure can be adjusted according to the size and spacing of the capacitor holes 200 to be formed The growth time of 320 can easily adjust the thickness of the oxide layer to change the size and spacing of the second sidewall structure 320.
  • FIG. 12 is a schematic diagram of the positional relationship between the side wall structure and the capacitor hole 200 according to an embodiment. As shown in FIG. 12, in this embodiment, the outer contours of two adjacent second side wall structures 320 are both tangent In order to ensure the effective connection of the plurality of capacitor holes 200, the size of the capacitor opening hole 300 is reduced, so that the storage capacitor can obtain a larger charge storage capacity.
  • the inner contour of the second sidewall structure 320 constitutes a first etching pattern 341
  • the first etching pattern 341 is approximately circular
  • the second etching pattern 342 is formed together, and the second etching pattern 342 is approximately triangular.
  • Both the first etching pattern 341 and the second etching pattern 342 correspond to the capacitor opening holes 300 to be formed one-to-one, and each capacitor opening hole 300 is used for communication.
  • Three capacitor holes 200 are arranged adjacently, and each capacitor hole 200 is connected to only one capacitor opening hole 300. Based on the arrangement of the capacitor opening holes 300 in this embodiment, the communication efficiency of the capacitor opening holes 300 can be effectively improved .
  • step S400 further includes: removing the first side wall structure 310 and the second side wall structure 320, by removing the first side wall structure 310 and the second side wall structure 320, it is convenient to continue in subsequent steps
  • the capacitor dielectric layer 500 and the second electrode layer 600 are formed.
  • FIG. 13 is a method for forming a storage capacitor according to an embodiment. As shown in FIG. 13, in this embodiment, the method for forming a storage capacitor includes steps S10 to S60.
  • S10 Provide a substrate, and form a stacked sacrificial layer 110 and a supporting layer 120 on the surface of the substrate.
  • the sacrificial layer 110 is formed on the surface of the substrate, and the support layer 120 is formed on the surface of the sacrificial layer 110.
  • the support layer 120 is used to improve the structural strength of the storage capacitor to prevent damage to the structure of the storage capacitor, thereby improving the stability of the device.
  • a chemical vapor deposition process can be used to form the support layer 120 to support
  • the material of the layer 120 may be, but is not limited to, silicon nitride (Si3N4).
  • the material of the sacrificial layer 110 may be one or more of silicon dioxide (SiO2) phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG) and fluorosilicate glass (FSG) .
  • SiO2 silicon dioxide
  • PSG phosphosilicate glass
  • TEOS tetraethyl orthosilicate
  • BPSG borophosphosilicate glass
  • FSG fluorosilicate glass
  • a plurality of sacrificial layers 110 and a plurality of supporting layers 120 may also be sequentially formed at intervals to further improve the structural strength of the memory capacitor.
  • S20 Etch the sacrificial layer 110 and the support layer 120 to the surface of the substrate according to the layout of the capacitor hole 200 to form the capacitor hole 200.
  • step S20 may include: forming a third photoresist layer on the surface of the support layer 120 through a squeegee coating or spin coating process; exposing and developing the third photoresist layer according to the layout of the capacitor hole 200 to form a patterned photoresist layer.
  • the third photoresist layer using the patterned third photoresist layer as a mask, the support layer 120 and the sacrificial layer 110 are etched to the surface of the substrate to expose the contact pad 101 in the substrate, and the etched area forms a capacitor Hole 200; Use a photoresist stripper to remove the remaining third photoresist layer.
  • a first electrode layer 400 is formed in the capacitor hole 200, and the first electrode layer 400 covers the inner wall of the capacitor hole 200 and the exposed substrate.
  • step S30 is a schematic cross-sectional view of the device structure after step S30 in an embodiment.
  • the first electrode layer 400 covers the inner wall of the capacitor hole 200 and the exposed substrate.
  • step S30 may include: forming a first metal layer using an atomic layer deposition process, the first metal layer covering the surface of the support layer 120, the inner wall of the capacitor hole 200 and the exposed substrate; and removing the first metal on the top of the support layer 120 The remaining first metal layer serves as the first electrode layer 400, and the first electrode layer 400 covers the inner wall of the capacitor hole 200 and the exposed substrate.
  • the material of the first electrode layer 400 is titanium nitride (TiN), and the first electrode layer 400 is connected to the contact pad 101 in the substrate for acquiring the signal from the transistor, thereby realizing data storage and reading. Pick.
  • the capacitor opening hole 300 is formed by using the aforementioned method for forming the capacitor opening hole, and the capacitor opening hole 300 is used to communicate with a plurality of adjacent capacitor holes 200.
  • FIG. 16 is a schematic cross-sectional view of the device structure after step S40 in an embodiment.
  • the first sidewall structure 310 and the second sidewall structure 320 are formed first to expose the to-be-formed structure In the area of the capacitor opening hole 300, using the first sidewall structure 310 and the second sidewall structure 320 as a mask, the sacrificial layer 110 and the support layer 120 are etched to form the capacitor opening hole 300.
  • FIG. 17 is a schematic cross-sectional view of the device structure after S50 in an embodiment.
  • a wet etching solution is injected into the device through the capacitor opening 300 to remove the remaining sacrificial layer 110.
  • a corresponding wet etching solution can be selected according to the material of the sacrificial layer 110, so as to improve the efficiency of wet etching and ensure that the sacrificial layer 110 is completely etched.
  • a capacitor dielectric layer 500 and a second electrode layer 600 are sequentially formed on the inner wall of the capacitor opening hole 300 and the surface of the first electrode layer 400.
  • the first electrode layer 400, the capacitor dielectric layer 500 and the second electrode layer 600 together form a storage capacitor .
  • FIG. 18 is a schematic cross-sectional view of the device structure after step S60 in an embodiment.
  • the capacitor dielectric layer 500 covers the surface of the first electrode layer 400
  • the second electrode layer 600 covers the capacitor The surface of the dielectric layer 500.
  • the material of the capacitor dielectric layer 500 may be hafnium oxide (HfO2), hafnium orthosilicate (HfSiO4), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), lanthanum oxide (La2O3)
  • high dielectric constant materials such as strontium titanate (SrTiO3), lanthanum aluminate (LaAlO3), cerium oxide (CeO2), yttrium oxide (Y2O3), etc., by using a high dielectric constant capacitor dielectric layer
  • the 500 material can effectively increase the charge storage capacity of the capacitor without increasing the size of the capacitor hole 200.
  • steps in the flowcharts are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless specifically stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different moments. The order of execution of these steps or stages is also It is not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.

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Abstract

本申请涉及一种电容打开孔的形成方法和存储器电容的形成方法，电容打开孔的形成方法包括提供衬底，衬底的表面形成有层叠设置的牺牲层和支撑层(S100)；在支撑层的表面形成多个间隔设置的中空的第一侧墙结构(S200)；在第一侧墙结构的表面形成第二材料层以构成第二侧墙结构(S300)；以第一侧墙结构和第二侧墙结构为掩膜蚀刻牺牲层和支撑层以形成电容打开孔(S400)。

Description

电容打开孔的形成方法和存储器电容的形成方法
相关申请的交叉引用
本申请要求于2020年5月12日提交中国专利局，申请号为202010396954.4，发明名称为“电容打开孔的形成方法和存储器电容的形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，特别是涉及一种电容打开孔的形成方法和存储器电容的形成方法。
背景技术
科学技术的不断发展使人们对半导体技术的要求越来越高，半导体器件的面积不断缩小，因此对半导体制造工艺的精密程度要求和精确程度提出了更高的要求。半导体存储器是一种利用半导体电路进行存取的存储器,其中，动态随机存取存储器(Dynamic Random Access Memory，DRAM)以其快速的存储速度和高集成度被广泛应用于各个领域。
在形成DRAM的存储器电容时，需要先在衬底表面形成牺牲层以作为电容孔的支撑结构，在形成电容的一个电极后，再去除牺牲层并形成剩余的电容结构。因此，需要通过电容打开孔对电容孔进行连通，以使牺牲层暴露在蚀刻环境中，从而去除牺牲层。但是，随着动态随机存储器的尺寸不断缩小、集成度不断提高，电容打开孔的尺寸也在不断微缩，现有的制备技术已无法满足飞速发展的电容打开孔的尺寸和精度需求。
发明内容
根据本申请的各种实施例，提供一种电容打开孔的形成方法和存储器电容的形成方法。
一种电容打开孔的形成方法，包括：
提供衬底，所述衬底的表面形成有层叠设置的牺牲层和支撑层；
在所述支撑层的表面形成多个间隔设置的中空的第一侧墙结构；
在所述第一侧墙结构的表面形成第二材料层以构成第二侧墙结构；
以所述第一侧墙结构和所述第二侧墙结构为掩膜蚀刻所述牺牲层和所述支撑层以形成所述电容打开孔。
一种存储器电容的形成方法，包括：
提供衬底，在所述衬底的表面形成层叠设置的牺牲层和支撑层；
根据电容孔版图蚀刻所述牺牲层和支撑层至所述衬底的表面以形成电容孔；
在所述电容孔中形成第一电极层，所述第一电极层覆盖所述电容孔的内壁以及暴露的所述衬底；
采用上述的形成方法形成电容打开孔，所述电容打开孔用于连通相邻设置的多个所述电容孔；
通过所述电容打开孔蚀刻剩余的所述牺牲层；
在所述电容打开孔的内壁和所述第一电极层的表面依次形成电容介质层和第二电极层，所述第一电极层、所述电容介质层和所述第二电极层共同构成所述存储器电容。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为根据一个或多个实施例的电容打开孔的形成方法的流程图；
图2为根据一个或多个实施例的已形成牺牲层和支撑层的衬底的截面示意图；
图3为图2所示实施例的器件结构的俯视示意图；
图4为根据一个或多个实施例的第一侧墙结构的俯视示意图；
图5为根据一个或多个实施例的步骤S300后的第一侧墙结构和第二侧墙结构的俯视示意图；
图6为根据一个或多个实施例的步骤S200的子流程图；
图7为根据一个或多个实施例的步骤S210后的初始侧墙结构的俯视示意图；
图8为根据一个或多个实施例的步骤S220后的初始侧墙结构和第一材料层的俯视示意图；
图9为根据一个或多个实施例的步骤S210的子流程图；
图10为根据一个或多个实施例的步骤S211后的器件结构的俯视示意图；
图11为图10所示实施例的步骤S212后的器件结构的俯视示意图；
图12为根据一个或多个实施例的侧墙结构和电容孔的位置关系的示意图；
图13为根据一个或多个实施例的存储器电容的形成方法；
图14为根据一个或多个实施例的步骤S10后的器件结构的截面示意图；
图15为根据一个或多个实施例的步骤S30后的器件结构的截面示意图；
图16为根据一个或多个实施例的步骤S40后的器件结构的截面示意图；
图17为根据一个或多个实施例的S50后的器件结构的截面示意图；
图18为根据一个或多个实施例的步骤S60后的器件结构的截面示意图。
元件标号说明：
接触焊盘：101；牺牲层：110；支撑层：120；电容孔：200；电容打开孔：300；第一侧墙结构：310；第二侧墙结构：320；初始侧墙结构：330；第一初始侧墙：331；第二初始侧墙：332；第一蚀刻图形：341；第二蚀刻图形：342；第一电极层：400；电容介质层：500；第二电极层：600
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、 部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
图1为根据一个或多个实施例的电容打开孔的形成方法的流程图，如图1所示，在本实施例中，电容打开孔的形成方法包括步骤S100至S400。
S100：提供衬底，衬底的表面形成有层叠设置的牺牲层110和支撑层120。
具体地，衬底中已形成多个有源区和隔离结构，多个有源区呈阵列式排布，且相邻设置的有源区之间均设有隔离结构，而且每个有源区中均形成有至少一个晶体管以及贯穿有源区的字线结构，有源区的表面形成有位线结构。其中，每个晶体管的栅极电性连接至字线结构，漏极电性连接至位线结构，源极电性连接至存储器电容的第一电极层400，从而向存储器电容存取数据。
图2为一实施例的已形成牺牲层110和支撑层120的衬底的截面示意图，如图2所示，衬底中还形成有多个接触焊盘101，且多个接触焊盘101在水平面内规则排列，每个接触焊盘101对应一个电容孔200。图3为图2实施例的器件结构的俯视示意图，如图2至图3所示，在本实施例中，牺牲层110和支撑层120中形成有多个电容孔200，电容孔200沿竖直方向贯穿牺牲层110和支撑层120至衬底的表面，相邻的六个电容孔200在水平面内呈正六边形排列，正六边形的每个顶角均设有一个电容孔200，且正六边形的中心设有一个电容孔200。在本示例中，电容孔200的排列方式为六边形最密堆积结构(Hexagonal Closest Packed，HCP)。基于该HCP结构，可以在后续步骤中形成紧密排列的存储器电容，从而提高DRAM中存储器电容的排布密度和集成度。
需要说明的是，相邻的六个电容孔200在水平面内呈正六边形排列是指，每个电容孔200的中心点在水平面内构成如图3所示的虚拟正六边形，在其他实施例中，在水平面内呈正六边形排列的定义与本实施例中的定义相同，将不再进行赘述。
进一步地，相邻的接触焊盘101之间形成有间隔层，以隔离不同的接触焊盘101，从而防止不同的接触焊盘101之间发生短路现象，以提高DRAM的可靠性。可选地，接触焊盘101的材料可以为钨、铝、铜、钛、钽、多晶硅中的一种或多种。间隔层的材料可以为氮化硅(SiN)、氧化硅(SiO2)、氧化铝(Al2O3)中的一种或多种。牺牲层110的材料可以为二氧化硅(SiO2)、磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、硼磷硅玻璃(BPSG)和氟硅玻璃(FSG)中的一种或多种。支撑层120的材料可以为但不局限于氮化硅(Si3N4)。
S200：在支撑层120的表面形成多个间隔设置的中空的第一侧墙结构310。
具体地，图4为一实施例的第一侧墙结构310的俯视示意图，如图4所示，在本实施例中，第一侧墙结构310为中空的柱形，多个第一侧墙结构310形成阵列式排布，其中，中空的柱形可以是中空的圆柱形、四棱柱形、六棱柱型、八棱柱形等，本实施例不限定柱形的具体形状。需要说明的是，图4中仅示出第一侧墙结构310，而未示出位于第一侧墙结构310下侧的支撑层120和电容孔200等结构。
进一步地，由于第一侧墙结构310的尺寸较小，在曝光工艺制程中会存在光学邻近效应，从而导致曝光后形成的图形与版图图形不完全吻合，因此，在版图设计时，会适当调整第一侧墙结构310的形状，从而获得更好的器件结构和器件性能，即第一侧墙结构310可以不局限于上述规则的柱形结构，而且，在其他实施例的其他结构的设计版图中，也会适当调整版图图形以获得更好的器件结构和器件性能，在其他实施例中将不再进行赘述。
再进一步地，继续如图4所示，相邻的六个第一侧墙结构310在水平面内呈正六边形排列，正六边形的每个顶角均设有一个第一侧墙结构310，且正六边形的中心设有一个第一侧墙结构310。并且，第一侧墙结构310的尺寸与电容孔200的尺寸相匹配，即电容孔200的尺寸和相邻电容孔200之间的距离越大，第一侧墙结构310的尺寸和相邻第一侧墙结构310之间的距离相应地越大，从而使电容打开孔300能够有效地连通相应的多个电容孔200。
S300：在第一侧墙结构310的表面形成第二材料层以构成第二侧墙结构320。
图5为一实施例的步骤S300后的第一侧墙结构310和第二侧墙结构320的俯视示意图，如图5所示，在本实施例中，第二材料层覆盖第一侧墙结构310的内侧壁和外侧壁，在其他实施例中，第二材料层还可以覆盖第一侧墙结构310的顶部。
在本实施例中，在竖直方向上，支撑层120和牺牲层110未被第一侧墙结构310和第二侧墙结构320覆盖的区域，即为后续步骤中形成电容打开孔300的区域，本实施例的形成方法可以有效地提高电容打开孔300的制备精度。具体地，继续参考图5，以第一侧墙结构310为空心圆柱形为例，假设以曝光工艺的最小工艺尺寸d1形成第一侧墙结构310，则第一侧墙结构310的内轮廓的直径为d1，若基于该第一侧墙结构310形成电容打开孔300，则电容打开孔300的直径也为d1，本实施例通过步骤S300，可以获得内轮廓的直径为d2的第二侧墙结构320，且d2＜d1，从而制备更小尺寸的电容打开孔300，即提高了电容打开孔300的制备精度，也同时提高了电容打开孔300的制备良率。
S400：以第一侧墙结构310和第二侧墙结构320为掩膜蚀刻牺牲层110和支撑层120以形成电容打开孔300。
具体地，在本实施例中，可以采用干法蚀刻工艺去除牺牲层110和支撑层120，蚀刻气体可以为四氟化碳和三氯甲烷的混合物，通过设置不同蚀刻气体的比例，利用支撑层120和牺牲层110的蚀刻选择比对支撑层120和牺牲层110进行蚀刻。在其他实施例中，也可以采用干法蚀刻工艺去除支撑层120，并采用湿法蚀刻工艺去除牺牲层110。可以理解的是，湿法蚀刻工艺的操作更加简单，无需考量支撑层120和牺牲层110的蚀刻选择比，但会增加工艺制程的步骤数量，从而拉长制备周期，因此，可以根据实际制备需求，选择更加恰当的蚀刻工艺。
本实施例的上述电容打开孔的形成方法，通过步骤S100至S400，可以形成紧密排列的第一侧墙结构310和第二侧墙结构320，以进一步形成电容打开孔300，基于上述紧密排列的双重侧墙结构的形成方法，既可以实现电容打开孔300的连通作用，又可以制备更小体积的电容打开孔300，从而提高了电容打开孔300的制备精度。
图6为一实施例的步骤S200的子流程图，如图6所示，在本实施例中，步骤S200包括步骤S210至S230。
S210：在支撑层120的表面形成多个间隔设置的初始侧墙结构330，初始侧墙结构330为柱形。
具体地，图7为一实施例的步骤S210后的初始侧墙结构330的俯视示意图，其中，柱形 的初始侧墙结构330可以为圆柱形、四棱柱形、六棱柱型、八棱柱形等。初始侧墙结构330用作支撑结构，以在后续步骤中形成第一侧墙结构310。进一步地，如图7所示，相邻的六个初始侧墙结构330在水平面内呈正六边形排列，正六边形的每个顶角均设有一个初始侧墙结构330，且正六边形的中心设有一个初始侧墙结构330。
在一示例中，初始侧墙结构330为光阻材料，并通过以下步骤形成初始侧墙结构330：在支撑层120的表面形成第一光阻层，再通过初始侧墙结构的光罩曝光第一光阻层并进行显影，剩余的第一光阻层作为初始侧墙结构330。本示例的方法形成的初始侧墙结构330的制备工艺简单，可以有效缩短制备周期。
在另一示例中，初始侧墙结构330为碳、氮、氧等元素掺杂的硅化合物，并通过以下步骤形成初始侧墙结构330：在支撑层120的表面依次形成初始侧墙材料层和第二光阻层，再通过初始侧墙结构的光罩曝光第二光阻层并进行显影，以形成图形化的第二光阻层，且图形化的第二光阻层遮挡住待形成初始侧墙结构330的区域，最后以图形化的第二光阻层作为掩膜蚀刻初始侧墙材料层，剩余的初始侧墙材料层作为初始侧墙结构330。本示例的方法形成的初始侧墙结构330的强度较大，且不易发生形变，因此，基于该初始侧墙结构330制备的第一侧墙结构310具有更好的形状准确度。其中，初始侧墙结构330和第一侧墙结构310具有较大的蚀刻选择比。
S220：在初始侧墙结构330的侧壁上形成第一材料层。
具体地，图8为一实施例的步骤S220后的初始侧墙结构330和第一材料层的俯视示意图，如图8所示，第一材料层形成在初始侧墙结构330的侧壁上。进一步地，第一材料层的材料可以为氮化物，例如可以为氮化硅，并可以采用物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、原子层沉积(ALD)等方式中的一种形成。在本实施例中，第一材料层需暴露出部分初始侧墙结构330，以便于在后续步骤中去除初始侧墙结构330。在本实施例中，氮化硅的强度较大，因此具有较好的结构稳定性，从而可以有效支撑后续待形成的第二侧墙结构320。
S230：去除初始侧墙结构330，剩余的第一材料层作为第一侧墙结构310。
在本实施例中，通过步骤S210至S230可以形成如图4所示的多个间隔设置的第一侧墙结构310。进一步地，而且还可以通过改变第一材料层的沉积时间，准确、快速地改变第一侧墙结构310的沉积厚度，而无需改变光罩中的图形，从而提供了更高的制备灵活性，以兼容不同尺寸或不同间距的电容孔200。
图9为一实施例的步骤S210的子流程图，如图9所示，在本实施例中，步骤S210包括步骤S211至S212。
S211：在支撑层120的表面形成多个第一初始侧墙331。
S212：在支撑层120的表面形成多个第二初始侧墙332。
其中，第一初始侧墙331和第二初始侧墙332的形状相同且互相间隔设置，多个第一初始侧墙331和多个第二初始侧墙332共同构成初始侧墙结构330。图10为一实施例的步骤S211后的器件结构的俯视示意图，图11为图10实施例的步骤S212后的器件结构的俯视示意图，如图10至图11所示，在本实施例中，通过分次形成多个初始侧墙结构330，可以减少每个步骤中待形成的初始侧墙结构330的数量，从而降低初始侧墙结构330的制备难度，提高初始侧墙结构330的制备良率。进一步地，当多个初始侧墙结构330的排布密度过高时，也可以拆分为多个步骤进行制备，且拆分方式也不局限于图10至图11所示的拆分方式。
在一实施例中，步骤S300包括：采用生长工艺在第一侧墙结构310的表面形成氧化物层以构成第二侧墙结构320。具体地，氧化物层可以是氧化硅层。进一步地，本实施例通过一步工艺制程在第一侧墙结构310的内侧壁和外侧壁同时生长氧化物层，因此，可以根据待形成的电容孔200的尺寸和间距，调节第二侧墙结构320的生长时间，从而便捷地调节氧化物层的厚度，以改变第二侧墙结构320的尺寸和间距。
图12为一实施例的侧墙结构和电容孔200的位置关系的示意图，如图12所示，在本实 施例中，相邻设置的两个第二侧墙结构320的外轮廓均相切，以保证有效连通多个电容孔200的前提下，缩小电容打开孔300的尺寸，从而使存储电容器获得更大的电荷存储量。
进一步地，如图12所示，第二侧墙结构320的内轮廓构成第一蚀刻图形341，第一蚀刻图形341近似为圆形，相邻设置的三个第二侧墙结构320的外轮廓共同构成第二蚀刻图形342，第二蚀刻图形342近似为三角形，第一蚀刻图形341和第二蚀刻图形均342与待形成的电容打开孔300一一对应，每个电容打开孔300用于连通相邻设置的三个电容孔200，而且每个电容孔200只连通至一个电容打开孔300，基于本实施例的上述电容打开孔300的排列方式，可以有效地提高电容打开孔300的连通效率。
在一实施例中，步骤S400后，还包括：去除第一侧墙结构310和第二侧墙结构320，通过去除第一侧墙结构310和第二侧墙结构320，便于在后续步骤中继续形成电容介质层500和第二电极层600。
图13为一实施例的存储器电容的形成方法，如图13所示，在本实施例中，存储器电容的形成方法包括步骤S10至S60。
S10：提供衬底，在衬底的表面形成层叠设置的牺牲层110和支撑层120。
图14为一实施例的步骤S10后的器件结构的截面示意图，如图14所示，在本实施例中，牺牲层110形成于衬底的表面，支撑层120形成于牺牲层110的表面。具体地，支撑层120用于提升存储器电容的结构强度，以防止存储器电容的结构发生损伤，从而提高器件的稳定性，在本实施例中，可以采用化学气相沉积工艺制程形成支撑层120，支撑层120的材料可以为但不局限于氮化硅(Si3N4)。牺牲层110的材料可以为二氧化硅(SiO2)磷硅玻璃(PSG)、正硅酸乙酯(TEOS)、硼磷硅玻璃(BPSG)和氟硅玻璃(FSG)中的一种或多种。在其他实施例中，也可以间隔依次形成多个牺牲层110和多个支撑层120，从而进一步提升存储器电容的结构强度。
S20：根据电容孔200版图蚀刻牺牲层110和支撑层120至衬底的表面以形成电容孔200。
继续参考图2，在本实施例中，电容孔200形成于支撑层120和牺牲层110中，且暴露出衬底中的接触焊盘101。具体地，步骤S20可以包括：通过刮涂或旋涂工艺制程在支撑层120的表面形成第三光阻层；依据电容孔200版图对第三光阻层进行曝光和显影，以形成图形化的第三光阻层；以图形化的第三光阻层为掩膜，蚀刻支撑层120和牺牲层110至衬底的表面，以暴露出衬底中的接触焊盘101，被蚀刻区域形成电容孔200；使用光阻剥离液去除剩余的第三光阻层。
S30：在电容孔200中形成第一电极层400，第一电极层400覆盖电容孔200的内壁以及暴露的衬底。
图15为一实施例的步骤S30后的器件结构的截面示意图，如图15所示，在本实施例中，第一电极层400覆盖电容孔200的内壁以及暴露的衬底。具体地，步骤S30可以包括：采用原子层沉积工艺制程形成第一金属层，第一金属层覆盖支撑层120表面、电容孔200的内壁以及暴露的衬底；去除支撑层120顶部的第一金属层，剩余的第一金属层作为第一电极层400，第一电极层400覆盖电容孔200的内壁以及暴露的衬底。可选地，第一电极层400的材料为氮化钛(TiN)，第一电极层400与衬底中的接触焊盘101连接，用于获取来自晶体管的信号，从而实现数据的存储和读取。
S40：采用前述电容打开孔的形成方法形成电容打开孔300，电容打开孔300用于连通相邻设置的多个电容孔200。
图16为一实施例的步骤S40后的器件结构的截面示意图，如图16所示，在本实施例中，先形成第一侧墙结构310和第二侧墙结构320，以暴露出待形成电容打开孔300的区域，再以第一侧墙结构310和第二侧墙结构320为掩膜，蚀刻牺牲层110和支撑层120以形成电容打开孔300。
S50：通过电容打开孔300蚀刻剩余的牺牲层110。
图17为一实施例的S50后的器件结构的截面示意图，具体地，在本实施例中，通过电容 打开孔300向器件内注入湿法蚀刻溶液，从而去除剩余的牺牲层110。需要说明的是，可以根据牺牲层110的材料，选择相应的湿法蚀刻溶液，从而提高湿法蚀刻的效率，并保证牺牲层110被完全蚀刻干净。
S60：在电容打开孔300的内壁和第一电极层400的表面依次形成电容介质层500和第二电极层600，第一电极层400、电容介质层500和第二电极层600共同构成存储器电容。
图18为一实施例的步骤S60后的器件结构的截面示意图，如图18所示，在本实施例中，电容介质层500覆盖第一电极层400的表面，且第二电极层600覆盖电容介质层500的表面。可选地，电容介质层500的材料可以为为氧化铪(HfO2)、正硅酸铪(HfSiO4)、二氧化锆(ZrO2)、氧化铝(Al2O3)、二氧化钛(TiO2)、氧化镧(La2O3)、钛酸锶(SrTiO3)、铝酸镧(LaAlO3)、氧化铈(CeO2)、氧化钇(Y2O3)等高介电常数材料中的一种或多种，通过使用高介电常数的电容介质层500材料，可以在不增大电容孔200尺寸的前提下，有效提升电容的电荷存储量。
应该理解的是，虽然各流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种电容打开孔的形成方法，包括：
    提供衬底，所述衬底的表面形成有层叠设置的牺牲层和支撑层；
    在所述支撑层的表面形成多个间隔设置的中空的第一侧墙结构；
    在所述第一侧墙结构的表面形成第二材料层以构成第二侧墙结构；
    以所述第一侧墙结构和所述第二侧墙结构为掩膜蚀刻所述牺牲层和所述支撑层以形成所述电容打开孔。
  2. 根据权利要求1所述的形成方法，其中，所述在所述支撑层的表面形成多个间隔设置的中空的第一侧墙结构，包括：
    在所述支撑层的表面形成多个间隔设置的初始侧墙结构，其中，所述初始侧墙结构为柱形；
    在所述初始侧墙结构的侧壁上形成第一材料层；
    去除所述初始侧墙结构，剩余的所述第一材料层作为所述第一侧墙结构。
  3. 根据权利要求2所述的形成方法，其中，所述在所述支撑层的表面形成多个间隔设置的初始侧墙结构，包括：
    在所述支撑层的表面形成多个第一初始侧墙；
    在所述支撑层的表面形成多个第二初始侧墙；
    其中，所述第一初始侧墙和所述第二初始侧墙的形状相同且互相间隔设置，多个所述第一初始侧墙和多个所述第二初始侧墙共同构成多个所述初始侧墙结构。
  4. 根据权利要求2所述的形成方法，其中，所述在所述初始侧墙结构的侧壁上形成第一材料层，包括：
    在所述初始侧墙结构的侧壁上形成氮化物层。
  5. 根据权利要求2所述的形成方法，其中，所述初始侧墙结构为光阻材料，并通过以下步骤形成所述初始侧墙结构：在所述支撑层的表面形成第一光阻层；通过所述初始侧墙结构的光罩曝光所述第一光阻层并进行显影；将剩余的所述第一光阻层作为所述初始侧墙结构。
  6. 根据权利要求2所述的形成方法，其中，所述初始侧墙结构为碳、氮、氧等元素掺杂的硅化合物，并通过以下步骤形成所述初始侧墙结构：在所述支撑层的表面依次形成初始侧墙材料层和第二光阻层；通过所述初始侧墙结构的光罩曝光所述第二光阻层并进行显影，以形成图形化的所述第二光阻层，其中，图形化的所述第二光阻层遮挡住待形成所述初始侧墙结构的区域；以图形化的所述第二光阻层作为掩膜蚀刻所述初始侧墙材料层，剩余的所述初始侧墙材料层作为所述初始侧墙结构。
  7. 根据权利要求2所述的形成方法，其中，通过改变所述第一材料层的沉积时间来改变所述第一侧墙的沉积厚度。
  8. 根据权利要求1所述的形成方法，其中，所述在所述第一侧墙结构的表面形成第二材料层以构成第二侧墙结构，包括：
    采用生长工艺在所述第一侧墙结构的表面形成氧化物层以构成所述第二侧墙结构。
  9. 根据权利要求1所述的形成方法，其中，所述牺牲层和所述支撑层中形成有多个电容孔，所述电容孔沿竖直方向贯穿所述牺牲层和所述支撑层至所述衬 底的表面，相邻的六个所述电容孔在水平面内呈正六边形排列，所述正六边形的每个顶角均设有一个所述电容孔，且所述正六边形的中心设有一个所述电容孔。
  10. 根据权利要求9所述的形成方法，其中，所述第一侧墙结构的尺寸与所述电容孔的尺寸相匹配。
  11. 根据权利要求9所述的形成方法，其中，所述电容孔的排列方式为六边形最密堆积结构(Hexagonal Closest Packed，HCP)。
  12. 根据权利要求9所述的形成方法，其中，所述第二侧墙结构的内轮廓构成第一蚀刻图形，相邻设置的三个所述第二侧墙结构的外轮廓共同构成第二蚀刻图形，所述第一蚀刻图形和所述第二蚀刻图形均与所述电容打开孔一一对应；
    每个所述电容打开孔用于连通相邻设置的三个所述电容孔，且每个所述电容孔只连通至一个所述电容打开孔。
  13. 根据权利要求1所述的形成方法，其中，所述以所述第一侧墙结构和所述第二侧墙结构为掩膜蚀刻所述牺牲层和所述支撑层以形成所述电容打开孔后，还包括：
    去除所述第一侧墙结构和所述第二侧墙结构。
  14. 根据权利要求1所述的形成方法，其中，相邻设置的两个所述第二侧墙结构的外轮廓相切。
  15. 根据权利要求1所述的形成方法，其中，所述衬底中形成有多个接触焊盘，且所述多个接触焊盘在水平面内规则排列，每个所述接触焊盘对应一个所述电容孔。
  16. 根据权利要求11所述的形成方法，其中，相邻的所述接触焊盘之间形成有间隔层。
  17. 一种存储器电容的形成方法，包括：
    提供衬底，在所述衬底的表面形成层叠设置的牺牲层和支撑层；
    根据电容孔版图蚀刻所述牺牲层和支撑层至所述衬底的表面以形成电容孔；
    在所述电容孔中形成第一电极层，所述第一电极层覆盖所述电容孔的内壁以及暴露的所述衬底；
    在所述支撑层的表面形成多个间隔设置的中空的第一侧墙结构；
    在所述第一侧墙结构的表面形成第二材料层以构成第二侧墙结构；
    以所述第一侧墙结构和所述第二侧墙结构为掩膜蚀刻所述牺牲层和所述支撑层以形成电容打开孔，所述电容打开孔用于连通相邻设置的多个所述电容孔；
    通过所述电容打开孔蚀刻剩余的所述牺牲层；
    在所述电容打开孔的内壁和所述第一电极层的表面依次形成电容介质层和第二电极层，所述第一电极层、所述电容介质层和所述第二电极层共同构成所述存储器电容。
  18. 根据权利要求17所述的存储器电容的形成方法，其中，所述根据电容孔版图蚀刻所述牺牲层和支撑层至所述衬底的表面以形成电容孔的步骤，还包括：
    通过刮涂或旋涂工艺制程在所述支撑层的表面形成第三光阻层；
    依据电容孔版图对所述第三光阻层进行曝光和显影，以形成图形化的所述第 三光阻层；
    以图形化的所述第三光阻层为掩膜，蚀刻支撑层和牺牲层至衬底的表面；
    使用光阻剥离液去除剩余的所述第三光阻层。
  19. 根据权利要求17所述的存储器电容的形成方法，其中，所述在所述电容孔中形成第一电极层，所述第一电极层覆盖所述电容孔的内壁以及暴露的所述衬底的步骤，还包括：
    采用原子层沉积工艺制程形成第一金属层，其中，所述第一金属层覆盖所述支撑层表面、所述电容孔的内壁以及暴露的所述衬底；
    去除所述支撑层顶部的所述第一金属层，剩余的所述第一金属层作为第一电极层。
  20. 根据权利要求17所述的存储器电容的形成方法，其中，所述电容介质层的材料为高介电常数材料中的一种或多种。
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