WO2024036718A1 - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- WO2024036718A1 WO2024036718A1 PCT/CN2022/123847 CN2022123847W WO2024036718A1 WO 2024036718 A1 WO2024036718 A1 WO 2024036718A1 CN 2022123847 W CN2022123847 W CN 2022123847W WO 2024036718 A1 WO2024036718 A1 WO 2024036718A1
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- 238000000034 method Methods 0.000 title claims abstract description 110
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 125000006850 spacer group Chemical group 0.000 claims abstract description 183
- 239000000758 substrate Substances 0.000 claims abstract description 125
- 230000000873 masking effect Effects 0.000 claims abstract description 97
- 230000003667 anti-reflective effect Effects 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims description 79
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 description 17
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000001154 acute effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 3
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- 238000000576 coating method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.
- DRAM Dynamic Random Access Memory
- SAQP Self-Aligned Quadruple Patterning
- CD critical dimension
- the critical dimension of the sidewall pattern cannot be accurately controlled, and the sidewall pattern
- the bottom of the pattern becomes concave and convex, which affects subsequent pattern transfer and destroys the final capacitor tube structure.
- the final capacitor hole size uniformity is poor and insufficient etching occurs. , etching hole bridging and hole misalignment and other defects.
- embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
- an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
- a substrate is provided, a first insulating layer is formed on the surface of the substrate, and first initial spacing layers are located on the surface of the first insulating layer, arranged at intervals along the first direction, and extending along the second direction, and the first initial spacing layer is formed on the surface of the substrate.
- the spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer;
- the pattern of the first masking layer is multiplied and transferred to the first insulating layer to form a first pattern layer.
- the first pattern layer at least includes first spacers spaced apart along the first direction. layer;
- a second pattern layer is formed on the surface of the first pattern layer; the second pattern layer at least includes second spacer layers arranged at intervals along the first direction and extending along the third direction; the first The direction, the second direction and the third direction are any three directions in the plane where the base is located;
- the initial pattern defined by the second spacer layer and the first spacer layer is transferred to the substrate.
- the etching selectivity ratio between the first anti-reflection layer and the substrate is 3 to 10 times the etching selectivity ratio between the first insulating layer and the substrate.
- multiplying the pattern of the first masking layer and transferring it to the first insulating layer includes:
- the second initial covering layer located on the top surface of the first masking layer and the surface of the first insulating layer is removed, and the remaining second initial covering layer located on the sidewall of the first masking layer constitutes the First side wall layer.
- the first pattern layer further includes a first sacrificial layer; after forming the first spacer layer, the method of forming a semiconductor structure further includes:
- the first spacer layer is flush with the surface of the first sacrificial layer.
- the first initial spacer layer is formed by the following steps:
- a first initial mask layer and a second initial mask layer are sequentially formed on the surface of the first insulating layer; the first initial mask layer includes the first mask layer and the first anti-reflection layer;
- the first initial mask layer is etched through the first covering layer to form the first initial spacer layers alternately arranged along the first direction.
- the second initial spacer layer is formed by the following steps:
- a first photoresist layer with a first preset pattern is formed on the surface of the second initial mask layer; wherein the first preset pattern includes sequentially arranged along the first direction and along the first A plurality of first sub-patterns extending in two directions, the first sub-patterns exposing part of the second initial mask layer;
- the second initial mask layer exposed by the first sub-pattern is removed to form the second initial spacer layer.
- the second pattern layer is formed by the following steps:
- the third initial spacer layer includes a third masking layer and a third anti-reflective layer located on the surface of the third masking layer;
- the etching selectivity ratio between the third anti-reflective layer and the substrate is greater than the etching selectivity ratio between the second insulating layer and the substrate;
- the pattern of the third masking layer is multiplied and transferred to the second insulating layer to form the second pattern layer.
- the etching selectivity ratio between the third anti-reflection layer and the substrate is 3 to 10 times that of the second insulating layer and the substrate.
- multiplying the pattern of the third masking layer and transferring it to the second insulating layer includes:
- the fourth initial covering layer located on the top surface of the third masking layer and the surface of the first insulating layer is removed, and the remaining fourth initial covering layer located on the sidewall of the third masking layer constitutes the Second side wall layer.
- the second pattern layer further includes a second sacrificial layer; after forming the second spacer layer, the method of forming a semiconductor structure further includes:
- the second spacer layer is flush with the bottom surface of the second sacrificial layer.
- the third initial spacer layer is formed by the following steps:
- a third initial mask layer and a fourth initial mask layer are sequentially formed on the surface of the second insulating layer; the third initial mask layer includes the third mask layer and the third anti-reflection layer;
- the third initial mask layer is etched through the third covering layer to form the third initial spacer layers alternately arranged along the first direction.
- the fourth initial spacer layer is formed by the following steps:
- a second photoresist layer with a second preset pattern is formed on the surface of the fourth initial mask layer; wherein the second preset pattern includes sequentially arranged along the first direction, and a second photoresist layer along the first direction.
- a plurality of second sub-patterns extending in three directions, the second sub-patterns exposing part of the fourth initial mask layer;
- the fourth initial mask layer exposed by the second sub-pattern is removed to form the fourth initial spacer layer.
- the substrate includes an array region and a peripheral region, and after forming the second pattern layer, the method further includes:
- the initial pattern is transferred to the substrate corresponding to the array area exposed by the third preset pattern.
- the method of forming a semiconductor structure further includes:
- a dielectric layer is formed on the surface of the first pattern layer.
- the substrate includes a fourth mask layer; transferring the initial pattern defined by the second spacer layer and the first spacer layer to the substrate includes:
- the initial pattern is transferred to the fourth mask layer to form a fourth mask layer with an initial pattern; the initial The pattern includes a plurality of third sub-patterns.
- the base further includes a substrate, and the fourth mask layer is located on the surface of the substrate; after forming the fourth mask layer with the initial pattern, the method further includes:
- the portion of the substrate exposed by the third sub-pattern is removed to transfer the initial pattern into the substrate.
- the substrate further includes a stacked structure, and the fourth mask layer is located on the surface of the stacked structure; after forming the fourth mask layer with the initial pattern, the method further includes :
- the portion of the stacked structure exposed by the third sub-pattern is removed to transfer the initial pattern into the stacked structure.
- the initial pattern includes a capacitive hole pattern.
- embodiments of the present disclosure provide a semiconductor structure formed by the method for forming a semiconductor structure described in the above claims, and the semiconductor structure includes:
- the substrate includes an initial pattern; the initial pattern is defined by a first spacer layer in the first pattern layer and a second spacer layer in the second pattern layer;
- the first pattern layer is located on the surface of the substrate, the first spacer layers are arranged at intervals along the first direction and extend along the second direction; the second pattern layer is located on the first On the surface of the pattern layer, the second sidewall layers are arranged at intervals along the first direction and extend along the third direction; the first direction, the second direction and the third direction are the base any three directions in the plane.
- a first insulating layer is formed on the surface of the substrate, and first initial intervals are located on the surface of the first insulating layer, arranged at intervals along the first direction, and extending along the second direction.
- the first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer.
- the first insulating layer will not be damaged during the removal of the first anti-reflective layer, so that the pattern at the bottom of the first masking layer will not have a concave and convex structure.
- the etching load effect during the downward transfer of the first masking layer is reduced. In this way, the critical dimensions of the first spacer layer can be easily controlled without affecting the subsequent pattern transfer, and thus will not damage the final semiconductor structure. .
- Figures 1a to 1c are structural schematic diagrams of the formation process of semiconductor structures in related technologies
- Figure 2 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure
- 3a to 3l and 4a to 4p are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure.
- FIGS. 1a and 1b are structural schematic diagrams of the formation process of semiconductor structures in related technologies.
- the semiconductor structures in related technologies are divided into array areas (Array Area, AA) and peripheral areas (Periphery Area, PA).
- the semiconductor structure in the related art includes a substrate (not shown in FIGS. 1a and 1b ), a mask layer 100 located on the surface of the substrate 10 , a first pattern layer A located on the surface of the mask layer 100 , and a first pattern layer A located on the surface of the mask layer 100 .
- the second pattern layer B on the surface of pattern layer A.
- the mask layer 100 includes a first hard mask layer 101, a second hard mask layer 102 and a third hard mask layer 103 stacked in sequence.
- the first pattern layer A includes spaced apart layers arranged along the X-axis direction in Figure 1a.
- the first spacer layer 111 and the second pattern layer B include second spacer layers 112 spaced apart along the X-axis direction; in the related art, after the first pattern layer A and the second pattern layer B are formed, the first pattern layer
- the capacitor hole pattern defined by the pattern layer A and the second pattern layer B is sequentially transferred downward, for example, first transferred to the third hard mask layer 103, and then transferred to the second hard mask layer 103 through the etched third hard mask layer.
- an etched second hard mask layer 102a having a capacitor hole 104 is formed (as shown in FIG. 1b), and finally the etched second hard mask layer 102a is transferred to the first hard mask layer 102a. in the mask layer 101 and the substrate.
- the size uniformity of the finally formed capacitor hole is poor (as shown in the capacitor hole 104-1, the capacitor hole 104-2 and the capacitor hole 104-3 in Figure 1c ), and defects such as insufficient etching (shown in the dotted box in Figure 1b), etching hole bridging, and hole misalignment (shown in Figure 1c) will occur.
- pseudo capacitance holes 103 are easily generated in the corners of the array area AA (as shown in Figure 1c), resulting in abnormal edge patterns of the array area AA, thereby affecting the performance and production yield of the dynamic random access memory. .
- embodiments of the present disclosure provide a new method for forming a semiconductor structure, which can accurately control the key dimensions of the sidewall pattern so that the bottom of the sidewall pattern will not be concave and convex, thereby not affecting subsequent patterns.
- the transfer process will not cause damage to the finally formed pattern;
- the formation method of the semiconductor structure provided by the embodiment of the present disclosure can make the size of the finally formed pattern have good uniformity, and there will be no insufficient etching, etching hole bridging and etching. Defects such as hole misalignment.
- the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction of intersection (eg, perpendicular) with the top and bottom surfaces of the substrate is defined as Fourth direction.
- the direction of the top surface and bottom surface of the substrate i.e., the plane on which the substrate is located
- three directions that intersect with each other are defined.
- the extension direction of the first initial spacer layer can be defined as the second direction
- the extension of the second sidewall layer can be defined.
- the direction is the third direction
- the second direction forms an acute angle or an obtuse angle with the third direction
- the first direction intersects the second direction and the third direction
- the plane direction of the substrate can be determined based on the first direction, the second direction and the third direction.
- the first direction is defined as the X-axis direction
- the second direction is defined as the Y1-axis direction
- the third direction is defined as the Y2-axis direction
- the fourth direction is defined as the Z-axis direction.
- FIG. 2 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 2, the method for forming a semiconductor structure includes the following steps:
- Step S201 Provide a substrate.
- a first insulating layer is formed on the surface of the substrate, and first initial spacer layers are located on the surface of the first insulating layer, arranged at intervals along the first direction, and extending along the second direction.
- the first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer.
- the substrate at least includes a substrate, and the substrate may include a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (Germanium) substrate. on Insulator, GOI) substrate, etc.; the substrate can also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc. In other embodiments, the substrate may also be an ion-doped substrate, such as a P-type doped substrate or an N-type doped substrate.
- the substrate may further include a stacked structure, which is used to form a capacitor hole of the semiconductor structure.
- the stacked structure includes a bottom support layer, a bottom sacrificial layer, a middle support layer, a top sacrificial layer, and a top support layer.
- the substrate may further include a multi-layer mask layer located on the surface of the substrate or the surface of the stacked structure, and the multi-layer mask layer is used to transfer the pattern to be transferred to the surface of the substrate or stacked structure.
- the first insulating layer may be used as a mask layer, and the first insulating layer may be a spin-coated silicon anti-reflection coating (Si-ARC).
- Si-ARC spin-coated silicon anti-reflection coating
- the first initial spacer layer includes a first masking layer and a first anti-reflection layer located on the surface of the first masking layer, wherein the first masking layer may be a Spin On Hardmask (SOH) layer.
- the first anti-reflection layer may be a silicon oxide layer or a silicon oxynitride layer.
- the first initial spacer layers are spaced apart along the first direction and extend along the second direction, wherein the first direction and the second direction may form an acute angle or an obtuse angle.
- Step S202 remove the first anti-reflection layer.
- the first anti-reflective layer can be removed by wet etching technology, for example, using strong acid etching such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.
- the etching selectivity ratio between the first anti-reflective layer and the substrate is greater than the etching selectivity ratio between the first insulating layer and the substrate, for example, the etching selectivity ratio between the first anti-reflective layer and the substrate The ratio is 3 to 10 times the etching selectivity ratio between the first insulating layer and the substrate. Since the etching selectivity ratio between the first anti-reflective layer and the substrate is greater than the etching selectivity ratio between the first insulating layer and the substrate, the first insulating layer will not be damaged when the first anti-reflective layer is removed.
- Step S203 Multiply the pattern of the first masking layer and transfer it to the first insulating layer to form a first pattern layer.
- the first pattern layer at least includes first spacer layers spaced apart along the first direction.
- the first masking layer pattern can be multiplied through self-aligned double imaging technology (Self-aligned Double Patterning, SADP), and the multiplied pattern can be transferred to the first insulating layer to form the first side wall layer.
- SADP Self-aligned Double Patterning
- the method for forming the semiconductor structure further includes: forming a first sacrificial layer in a gap between the first spacer layers; wherein the first spacer layer and the first spacer layer The surface of the sacrificial layer is flush.
- the first sacrificial layer may be an SOH or silicon oxynitride layer.
- the top surface and the bottom surface of the first spacer layer and the first sacrificial layer along the third direction are both flush.
- Step S204 forming a second pattern layer on the surface of the first pattern layer; the second pattern layer at least includes second spacer layers arranged at intervals along the first direction and extending along the third direction.
- the second sidewall layers are arranged at intervals along the first direction and extend along the third direction, wherein the second direction and the third direction may form an acute angle or an obtuse angle, and the first direction and the second direction may form an acute angle or an obtuse angle. right angle.
- the second pattern layer is formed on the surface of the first spacer layer and the first sacrificial layer.
- the second pattern layer also includes a second sacrificial layer located between the second spacer layers, wherein the second spacer layer is flush with the surface of the second sacrificial layer, that is, along the edges of the second spacer layer and the second sacrificial layer The top and bottom surfaces in the third direction are flush.
- the second sacrificial layer may be an SOH or silicon oxynitride layer.
- Step S205 Transfer the initial pattern defined by the second spacer layer and the first spacer layer to the substrate.
- the angle between the second direction and the third direction can be determined according to the layout design of the initial pattern.
- the angle between the second direction and the third direction can be 20 degrees (°) to 90°.
- the initial pattern may be a capacitive hole pattern.
- a first insulating layer is formed on a surface of a substrate, and a first initial spacer layer is located on the surface of the first insulating layer, is spaced along the first direction, and extends along the second direction.
- the first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer.
- the first insulating layer will not be damaged during the removal of the first anti-reflective layer, so that the pattern at the bottom of the first masking layer will not have a concave and convex structure, reducing The etching load effect during the downward transfer of the first masking layer is reduced. In this way, the critical dimensions of the first spacer layer can be easily controlled, without affecting subsequent pattern transfer, and thus without damaging the final semiconductor structure.
- FIGs 3a to 3l and Figures 4a to 4p are structural schematic diagrams during the formation process of the semiconductor structure provided by the embodiment of the present disclosure.
- the formation of the semiconductor structure provided by the embodiment of the present disclosure will be described below in conjunction with Figures 3a to 3l and Figure 4a to 4p. The process is explained in detail.
- step S201 is performed to provide a substrate.
- a first insulating layer is formed on the surface of the substrate, and first initial spacer layers are located on the surface of the first insulating layer, arranged at intervals along the first direction, and extending along the second direction.
- the first initial spacer layer is formed on the surface of the substrate.
- the spacer layer includes a first masking layer and a first anti-reflection layer located on the surface of the first masking layer.
- the substrate includes a fourth mask layer 12 and a first insulating layer 13 located on the surface of the fourth mask layer 12; in the embodiment of the present disclosure, the fourth mask layer 12 includes a first hard mask layer 121 , the second hard mask layer 122 and the third hard mask layer 123; wherein, the first hard mask layer 121 can be a polysilicon layer, the second hard mask layer 122 can be a silicon oxide layer, and the third hard mask layer 123 may be an amorphous carbon layer (ACL) or a polysilicon layer; the first insulating layer 13 may be a silicon nitride layer or a silicon oxynitride layer.
- ACL amorphous carbon layer
- the fourth mask layer 12 is used to transfer the initial pattern defined by the first spacer layer and the second spacer layer. Since the initial pattern is transferred during the transfer process, the critical dimensions of the initial pattern are changed each time it is transferred. It will be reduced in sequence, and the initial pattern is transferred through the fourth mask layer 12 with multiple hard mask layers until the required pattern size is reached, which can achieve continuous shrinkage of process nodes and improve the integration of the semiconductor structure. Therefore, in the embodiment of the present disclosure, the number of hard mask layers in the fourth mask layer 12 can be set according to actual needs.
- the fourth mask layer 12 can also be composed of one hard mask layer or five hard mask layers. Composed of layers of hard mask layers.
- the first insulating layer 13 may be a spin-coated silicon-containing anti-reflective layer.
- the substrate includes an array area AA and a peripheral area PA.
- the first initial spacer layer may be formed by the following steps: sequentially forming a first initial mask layer and a second initial mask layer on the surface of the substrate; the first initial mask layer includes a first mask layer and a first anti-reflection layer; etching the second initial mask layer to form second initial spacer layers arranged at intervals along the first direction; forming a first covering layer on the sidewall of the second initial spacer layer; etching the first covering layer through the first covering layer An initial mask layer forms first initial spacer layers alternately arranged along the first direction.
- a first initial mask layer 14 and a second initial mask layer 15 are sequentially formed on the surface of the first insulating layer 13.
- the first initial mask layer 14 includes a first initial mask layer 141 and a first initial resistor. Reflective layer 142; the second initial mask layer 15 includes a second initial mask layer 151 and a second initial anti-reflective layer 152.
- the first initial masking layer 141 and the second initial masking layer 151 may be a spin-on hard mask layer or an amorphous carbon layer (ACL); the first initial anti-reflective layer 142 and the second initial anti-reflective layer 152
- the material can be silicon oxynitride.
- the first initial mask layer and the second initial mask layer can be formed by any of the following suitable deposition processes: chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition) , PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process, spin coating process or coating process.
- CVD chemical Vapor Deposition
- PVD physical vapor deposition
- ALD atomic layer deposition
- spin coating process or coating process spin coating process.
- the first initial mask layer 14 may only include the first initial mask layer 141
- the second initial mask layer 15 may only include the second initial mask layer 151 .
- etching the second initial mask layer to form second initial spacer layers spaced apart along the first direction may include the following steps: forming a first preset pattern on the surface of the second initial mask layer. A first photoresist layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along the first direction and extending along the second direction, and the first sub-patterns expose part of the second initial mask layer; The second initial mask layer exposed by the first sub-pattern is removed to form a second initial spacer layer.
- a first photoresist layer 16 with a first preset pattern is formed on the surface of the second initial mask layer 15; wherein the first preset pattern includes a line located in the array area AA and along A plurality of first sub-patterns E are arranged sequentially in the X-axis direction, and the first sub-patterns E expose part of the second initial mask layer 15 (ie, the second initial anti-reflective layer 152).
- the second initial mask layer 15 is etched through the first photoresist layer 16 to remove the second initial mask layer 15 (including the second initial anti-reflection layer) exposed by the first sub-pattern E. layer 152 and the second initial masking layer 151) located within the projection area of the second initial anti-reflection layer 152 along the Z-axis direction, forming the second initial spacer layer 17.
- the second initial spacer layer 17 includes a second masking layer 171 and a second anti-reflective layer 172 located on the surface of the second masking layer 171 .
- the method of forming the semiconductor structure further includes: removing the first photoresist layer 16 with the first preset pattern.
- the process of forming the first covering layer on the sidewall of the second initial spacer layer may include the following steps: forming the first initial covering layer on the surfaces of the second initial spacer layer and the first initial mask layer; removing The first initial covering layer located on the top surface of the second initial spacer layer and the surface of the first initial mask layer, and the remaining first initial covering layer located on the second initial spacer layer, constitute the first covering layer.
- a first initial covering layer 18 is formed on the surface of the second initial spacer layer 17 and the first initial mask layer 14, wherein the first initial covering layer 18 covers the side walls and top of the second initial spacer layer 17. surface and the surface of the first initial mask layer 14 .
- an atomic layer deposition process may be used to form the first initial covering layer 18 to improve the film quality of the first initial covering layer 18 .
- a dry etching process is used to simultaneously remove the first initial covering layer 18 on the top surface of the second initial spacer layer 17 and the surface of the first initial mask layer 14, leaving The first initial covering layer 18 located on the side wall of the second initial spacer layer 17 and the remaining first initial covering layer 18 constitute the first covering layer 181 (as shown in Figure 3e).
- the method of forming the semiconductor structure further includes: removing the second initial spacer layer 17.
- wet etching technology may be used to remove the second initial spacer layer 17, for example, strong acid etching such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc. may be used.
- the first initial mask layer 14 is etched through the first cover layer 181, that is, the portion of the first initial mask layer 14 (including the first initial anti-reflection layer) exposed by the first cover layer 181 is removed.
- layer 142 and the first initial masking layer 141) located within the projection area of the first initial anti-reflection layer 142 along the Z-axis direction to form the first initial spacer layer 19.
- the first initial spacer layer 19 includes the first masking layer 191 and the A masking layer 191 is formed on the surface of the first anti-reflective layer 192 .
- step S202 is performed to remove the first anti-reflection layer.
- wet etching technology is used to remove the first anti-reflective layer 192.
- a dilute hydrofluoric acid solution (the volume ratio of water and hydrofluoric acid is 1:200) can be used to etch and remove the first anti-reflective layer 192.
- the etching selectivity ratio between the first anti-reflective layer 192 and the substrate is greater than the etching selectivity ratio between the first insulating layer 13 and the substrate (for example, the etching selectivity ratio between the first anti-reflective layer 192 and the substrate).
- the etching selectivity ratio is 3 to 10 times the etching selectivity ratio between the first insulating layer and the substrate). Therefore, when the first anti-reflection layer 192 is removed, the first insulating layer 13 will not be damaged.
- step S203 is performed to multiply the pattern of the first masking layer and transfer it to the first insulating layer to form a first pattern layer.
- the first pattern layer at least includes first spacer layers spaced apart along the first direction. .
- step S203 may include the following steps: forming a second initial covering layer on the surface of the first masking layer and the surface of the first insulating layer; removing the second initial covering layer located on the top surface of the first masking layer and the surface of the first insulating layer. Two initial covering layers, the remaining second initial covering layer located on the side wall of the first shielding layer, constitutes the first side wall layer.
- a second initial covering layer 20 is formed on the surface of the first masking layer 191 and the first insulating layer 13; wherein, the second initial covering layer 20 covers the sidewalls, top surface and first surface of the first masking layer 191.
- an atomic layer deposition process may be used to form the second initial covering layer 20 to improve the film quality of the second initial covering layer 20 .
- a dry etching process is used to simultaneously remove the second initial covering layer 20 on the top surface of the first masking layer 191 and the surface of the first insulating layer 13 , leaving the third initial covering layer 20 on the sidewall of the first masking layer 191 .
- Two initial covering layers 20 remove the first masking layer 191 through wet etching technology; etch the first insulating layer 13 through the remaining second initial covering layer 20a to form the first spacer layer 201, the first spacer layer 201 It includes the remaining second initial covering layer 20a and the etched first insulating layer 13a.
- the method of forming the semiconductor structure further includes: forming a first sacrificial layer in the gap between the first spacer layers 201 .
- the first initial sacrificial layer can be formed in the gap between the first spacer layers, on the surface of the first spacer layer, and on the surface of the gap between the first spacer layers; the first initial sacrificial layer can be etched back , until the surface of the remaining second initial sacrificial layer 20a in the first spacer layer is exposed, forming a first sacrificial layer.
- a first initial sacrificial layer 22 is formed in the gap between the first spacer layer and the first shielding layer, on the surface of the first spacer layer, and on the surface of the gap between the first shielding layers.
- the first initial sacrificial layer 22 is etched back until the surface of the first spacer layer 201 is exposed, and the remaining first initial sacrificial layer in the gap between the first spacer layers 201 22 constitutes the first sacrificial layer 23.
- the surfaces of the first spacer layer 201 and the first sacrificial layer 23 are flush, that is, the top and bottom surfaces of the first spacer layer 201 and the first sacrificial layer 23 along the Z-axis direction are flush. In this way, the subsequent pattern transfer process can be made more accurate.
- the etching selectivity ratio between the first anti-reflective layer and the substrate is greater than the etching selectivity ratio between the first insulating layer and the substrate, when removing the first anti-reflective layer The first insulating layer will not be damaged during the layering process, so that the pattern at the bottom of the first masking layer will not have a concave and convex structure, and the etching load effect during the downward transfer of the first masking layer will be reduced. In this way, the first The critical dimensions of the sidewall layer are easy to control and will not affect subsequent pattern transfer, nor will it damage the final semiconductor structure.
- the first pattern layer is also formed.
- Figure 3l is a top view of the first pattern layer.
- the first pattern layer 300 includes first spacer layers 201 arranged at intervals along the X-axis direction and extending along the Y1-axis direction.
- step S204 is performed to form a second pattern layer on the surface of the first pattern layer; the second pattern layer at least includes second spacer layers arranged at intervals along the first direction and extending along the third direction.
- the second pattern layer is formed by the following steps: forming a second insulation layer on the surface of the first pattern layer, and a third layer located on the surface of the second insulation layer, spaced along the first direction, and extending along the third direction.
- the third initial spacer layer includes a third masking layer and a third anti-reflective layer located on the surface of the third masking layer; removing the third anti-reflective layer; wherein, etching between the third anti-reflective layer and the substrate
- the selectivity ratio is greater than the etching selectivity ratio between the second insulating layer and the substrate; the pattern of the third masking layer is multiplied and transferred to the second insulating layer to form a second pattern layer.
- the third initial spacer layer may be formed by the following steps: sequentially forming a third initial mask layer and a fourth initial mask layer on the surface of the first pattern layer; the third initial mask layer includes a third mask layer and a third anti-reflective layer; etching the fourth initial mask layer to form fourth initial spacer layers arranged at intervals along the first direction; forming a third covering layer on the sidewall of the fourth initial spacer layer; through the third covering layer The third initial mask layer is etched to form third initial spacer layers alternately arranged along the first direction.
- the method of forming the semiconductor structure before forming the second pattern layer, further includes: forming a dielectric layer located on the first pattern layer 300 .
- a dielectric layer 202 is formed on the surface of the first pattern layer 300.
- the material of the dielectric layer 202 may be silicon nitride or silicon oxynitride.
- a second insulating layer 24 is formed on the surface of the dielectric layer.
- the material of the second insulating layer 24 may be a spin-coated silicon-containing anti-reflective layer.
- a third initial mask layer 25 and a fourth initial mask layer 26 are sequentially formed on the surface of the second insulating layer 24.
- the third initial mask layer 25 includes a third initial mask layer 251 and a third initial resistor. Reflective layer 252; the fourth initial masking layer 26 includes a fourth initial masking layer 261 and a fourth initial anti-reflective layer 262.
- the third initial masking layer 251 and the fourth initial masking layer 261 may be a spin-on hard mask layer or an amorphous carbon layer; the material of the third initial anti-reflective layer 252 and the fourth initial anti-reflective layer 262 may both be silicon nitride oxide. .
- the first initial mask layer and the second initial mask layer may be formed through any suitable deposition process.
- the third initial mask layer 25 may only include the third initial mask layer 251
- the fourth initial mask layer 26 may only include the fourth initial mask layer 261 .
- the fourth initial spacer layer may be formed by the following steps: forming a second photoresist layer with a second preset pattern on the surface of the fourth initial mask layer; wherein the second preset pattern includes along A plurality of second sub-patterns arranged in sequence in the first direction, the second sub-pattern exposes part of the fourth initial mask layer; the second sub-pattern extends along the third direction; the fourth initial mask exposed by the second sub-pattern is removed layer to form the fourth initial spacer layer.
- a second photoresist layer 27 with a second preset pattern is formed on the surface of the fourth initial mask layer 26; wherein, the second preset pattern includes a second photoresist layer 27 located in the array area AA and along A plurality of second sub-patterns F are arranged sequentially in the X-axis direction and extend along the Y2-axis direction. The second sub-patterns F expose part of the fourth initial mask layer 26 .
- the fourth initial mask layer 26 is etched through the second photoresist layer 27 to remove the fourth initial mask layer 26 exposed by the second sub-pattern F (including the fourth initial anti-reflection layer). layer 262 and the fourth initial masking layer 261) located within the projection area of the fourth initial anti-reflection layer 262 along the Z-axis direction to form the fourth initial spacer layer 28.
- the fourth initial spacer layer 28 includes a fourth masking layer 281 and a fourth anti-reflection layer 282 located on the surface of the fourth masking layer 281 .
- the method of forming the semiconductor structure further includes: removing the second photoresist layer 27 having the second preset pattern.
- forming the third covering layer on the sidewall of the fourth initial spacer layer may include the following steps: forming a third initial covering layer on the surface of the fourth initial spacer layer and the third initial mask layer; removing the third initial covering layer on the surface of the fourth initial spacer layer and the third initial mask layer; The third initial covering layer on the top surface of the fourth initial spacer layer and the surface of the third initial mask layer, and the remaining third initial covering layer located on the sidewall of the fourth initial spacer layer constitute a third covering layer.
- a third initial covering layer 29 is formed on the surface of the fourth initial spacer layer 28 and the third initial mask layer 25, wherein the third initial covering layer 29 covers the side walls and top of the fourth initial spacer layer 28. surface and the surface of the third initial mask layer 25 .
- an atomic layer deposition process may be used to form the third initial covering layer 29 to improve the film quality of the third initial covering layer 29 .
- the third initial covering layer 29 may be an oxide layer, such as a silicon oxide layer.
- a dry etching process is used to simultaneously remove the third initial covering layer 29 on the top surface of the fourth initial spacer layer 28 and the surface of the third initial mask layer 25, leaving The third initial covering layer 29 located on the side wall of the fourth initial spacer layer 28 and the remaining third initial covering layer 29 constitute the third covering layer 291 (as shown in Figure 4f).
- the method of forming the semiconductor structure further includes: removing the fourth initial spacer layer 28.
- wet etching technology may be used to remove the fourth initial spacer layer 28 , for example, strong acid etching such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc. may be used.
- the third initial mask layer 25 is etched through the third cover layer 291, that is, the portion of the third initial mask layer 25 (including the third initial anti-reflection layer) exposed by the third cover layer 291 is removed.
- layer 252 and the third initial masking layer 251) located within the projection area of the third initial anti-reflection layer 252 along the Z-axis direction to form the third initial spacer layer 30.
- the third initial spacer layer 30 includes a third masking layer 301 and a third anti-reflection layer 302 located on the surface of the third masking layer 301 .
- wet etching technology is used to remove the third anti-reflective layer 302.
- a dilute hydrofluoric acid solution (the volume ratio of water and hydrofluoric acid is 1:200) can be used to etch and remove the third anti-reflective layer 302.
- the etching selectivity ratio between the third anti-reflective layer 302 and the substrate is greater than the etching selectivity ratio between the second insulating layer 24 and the substrate (for example, the etching selectivity ratio between the third anti-reflective layer 302 and the substrate).
- the etching selectivity ratio is 3 to 10 times the etching selectivity ratio between the second insulating layer 24 and the substrate). Therefore, when the third anti-reflection layer 302 is removed, the second insulating layer 24 will not be damaged.
- multiplying the pattern of the third masking layer and transferring it to the second insulating layer includes the following steps: forming a fourth initial covering layer on the surface of the third masking layer and the surface of the second insulating layer; removing The fourth initial covering layer located on the top surface of the third masking layer and the surface of the second insulating layer, and the remaining fourth initial covering layer located on the sidewalls of the third masking layer constitute the second spacer layer.
- a fourth initial covering layer 31 is formed on the surfaces of the third masking layer 301 and the second insulating layer 24; wherein the fourth initial covering layer 31 covers the sidewalls, top surface and third surface of the third masking layer 301.
- the surface of the second insulating layer 24 In the embodiment of the present disclosure, an atomic layer deposition process may be used to form the fourth initial covering layer 31 to improve the film quality of the fourth initial covering layer 31 .
- the method of forming the semiconductor structure further includes: using a dry etching process to simultaneously remove the top surface of the third masking layer 301 and the surface of the second insulating layer 24 .
- the method of forming the semiconductor structure further includes: forming a second sacrificial layer 34 in the gap between the second spacer layers 311 .
- the formation process of the second sacrificial layer 34 is the same as the formation process of the first sacrificial layer 23, and will not be described again here.
- FIG. 4l is a top view of the second pattern layer. To facilitate understanding, only a limited number of second spacer layers are shown in FIG. 4l , and the second sacrificial layer 34 in the second pattern layer 400 is not shown in FIG. 4l . As shown in FIG. 4k , the second pattern layer 400 includes second spacer layers 311 arranged at intervals along the X-axis direction and extending along the Y2-axis direction.
- the second insulating layer will not be damaged during the layering process, so that the pattern at the bottom of the third masking layer will not have a concave and convex structure, and the etching load effect during the downward transfer of the third masking layer will be reduced.
- the second insulating layer can be The critical dimensions of the sidewall layer are easy to control and will not affect subsequent pattern transfer, nor will it damage the final semiconductor structure.
- the method for forming the semiconductor structure further includes: forming a third photoresist layer with a third preset pattern on the surface of the second pattern layer, wherein the third preset pattern Including exposing a portion of the array area away from the peripheral area.
- a third photoresist layer 36 having a third preset pattern is formed on the surface of the second pattern layer 400, where the third preset pattern includes a third sub-pattern.
- the second sacrificial layer 34 in the exposed second pattern layer 400 is removed by etching the third photoresist layer 36 with the third preset pattern, and the second sacrificial layer 34 is projected along the Z-axis direction.
- the dielectric layer 202 within the area and the first sacrificial layer 23 in the first pattern layer 300 form an initial pattern H defined by the first spacer layer 201 and the second spacer layer 311 as shown in FIG. 4n.
- step S205 is performed to transfer the initial pattern defined by the second spacer layer and the first spacer layer to the substrate.
- the substrate includes a fourth mask layer 12, and the fourth mask layer 12 includes a first hard mask layer 121, a second hard mask layer 122 and a third hard mask layer. 123.
- the fourth mask layer 12 includes a first hard mask layer 121, a second hard mask layer 122 and a third hard mask layer. 123.
- the first hard mask layer 121 is etched through the second hard mask layer having the initial pattern H to transfer the initial pattern H to In the first hard mask layer 121, a first hard mask layer 121a having an initial pattern H is formed to transfer the initial pattern H into the substrate. It should be noted that, for ease of understanding, only part of the initial pattern H is shown in FIG. 4p.
- the initial pattern may be a capacitive hole pattern.
- the etching selectivity ratio between the first anti-reflective layer and the substrate is greater than the etching selectivity ratio between the first insulating layer and the substrate, when removing the first anti-reflective layer The first insulating layer will not be damaged during the layering process, so that the pattern at the bottom of the first masking layer will not have a concave and convex structure, which reduces the etching load effect during the downward transfer of the first masking layer; and due to the third anti-reflection
- the etching selectivity ratio between the layer and the substrate is greater than the etching selectivity ratio between the second insulating layer and the substrate.
- the second insulating layer will not be damaged during the removal of the third anti-reflective layer, so that the third masking layer
- the pattern at the bottom will not have a concave and convex structure, which reduces the etching load effect during the downward transfer of the third masking layer.
- the critical dimensions of the first spacer layer and the second spacer layer can be easily controlled. It will affect the subsequent pattern transfer and will not damage the final semiconductor structure.
- the formation method of the semiconductor structure provided by the embodiments of the present disclosure can make the size of the finally formed pattern have good uniformity, and there will be no defects such as insufficient etching, etching hole bridging, etching hole misalignment, etc., which improves the preparation of semiconductor structures. Yield.
- inventions of the present disclosure also provide a semiconductor structure. Please continue to refer to Figures 4m to 4p.
- the semiconductor structure includes: a substrate; the substrate includes an initial pattern H.
- the substrate includes a fourth mask layer 12, and the fourth mask layer 12 includes a first hard mask layer 121, a second hard mask layer 122, and a third hard mask layer. 123.
- the base further includes a substrate and a stacked structure located on the surface of the substrate.
- the initial pattern H is defined by the first spacer layer 201 in the first pattern layer 300 and the second spacer layer 311 in the second pattern layer 400; the first pattern layer 300 includes alternating patterns along the X-axis direction.
- the first spacer layer 201 and the first sacrificial layer 23 are arranged and extend along the Y1 axis direction (please refer to FIG. 3i).
- the second pattern layer 400 is located on the surface of the first pattern layer 300.
- the second pattern layer 400 includes second sidewalls that are alternately arranged along the X-axis direction and extend along the Y2-axis (please refer to Figure 4l) direction.
- layer 311 and the second sacrificial layer 34 are alternately arranged along the X-axis direction and extend along the Y2-axis (please refer to Figure 4l) direction.
- the initial pattern may be a capacitive hole pattern.
- the semiconductor structure provided by the embodiments of the present disclosure is similar to the formation method of the semiconductor structure in the above-mentioned embodiments.
- a semiconductor structure provided by embodiments of the present disclosure includes a substrate having an initial pattern defined by a first spacer layer in a first pattern layer and a second spacer layer in a second pattern layer. Since the semiconductor structure provided by the embodiment of the present disclosure is formed by the above-mentioned formation method of the semiconductor structure, the critical dimensions of the first spacer layer and the second spacer layer in the embodiment of the present disclosure are easy to control and will not affect subsequent pattern transfer. , and will not damage the final semiconductor structure. Therefore, the semiconductor structure in the embodiment of the present disclosure has a high production yield.
- the disclosed devices and methods can be implemented in a non-target manner.
- the device embodiments described above are only illustrative.
- the division of units is only a logical function division.
- the components shown or discussed are coupled to each other, or directly coupled.
- a first insulating layer is formed on the surface of the substrate, and first initial intervals are located on the surface of the first insulating layer, arranged at intervals along the first direction, and extending along the second direction.
- the first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer.
- the first insulating layer will not be damaged during the removal of the first anti-reflective layer, so that the pattern at the bottom of the first masking layer will not have a concave and convex structure.
- the etching load effect during the downward transfer of the first masking layer is reduced. In this way, the critical dimensions of the first spacer layer can be easily controlled without affecting the subsequent pattern transfer, and thus will not damage the final semiconductor structure. .
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Abstract
本公开实施例提供一种半导体结构及其形成方法,其中,所述方法包括:提供基底,基底表面形成有第一绝缘层、以及位于第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层;去除第一抗反射层;将第一掩蔽层的图案倍增,并转移至第一绝缘层中,形成第一图案层,第一图案层至少包括沿第一方向间隔排布的第一侧墙层;在第一图案层的表面形成第二图案层;第二图案层至少包括沿第一方向间隔排布、且沿第三方向延伸的第二侧墙层;将第二侧墙层与第一侧墙层界定的初始图案转移至基底中。
Description
相关申请的交叉引用
本公开基于申请号为202210987111.0、申请日为2022年08月17日、发明名称为“半导体结构及其形成方法”的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本公开作为参考。
本公开涉及半导体技术领域,涉及但不限于一种半导体结构及其形成方法。
半导体结构的制造技术中,通常利用光阻及掩膜层,结合光刻及刻蚀工艺形成所需图案,然而,受到光刻工艺局限性的影响,容易使得形成的所需图案产生偏差,从而影响半导体结构的制备良率。
以动态随机存储器(Dynamic Random Access Memory,DRAM)的制造为例,在动态随机存储器的电容管的形成工艺中,通常采用自对准四重成像技术(Self-Aligned Quadruple Patterning,SAQP)进行图案的转移,由于图案的关键尺寸(Critical Dimension,CD)不断缩小,图案密度越来越大,在刻蚀过程中由于刻蚀负载效应,使得侧墙图案的关键尺寸不能准确控制,且在侧墙图案形成过程中,由于刻蚀选择比的问题使得图案底部呈凹凸状,进而影响后续的图案转移,破坏最终形成电容管结构,例如,使得最后形成的电容孔尺寸均匀性差,且会出现刻蚀不足、刻蚀孔桥接以及孔错位等缺陷。
发明内容
有鉴于此,本公开实施例提供一种半导体结构及其形成方法。
第一方面,本公开实施例提供一种半导体结构的形成方法,所述方法包括:
提供基底,所述基底表面形成有第一绝缘层、以及位于所述第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,所述第一初始间隔层包括第一掩蔽层和位于所述第一掩蔽层表面的第一抗反射层;
去除所述第一抗反射层;
将所述第一掩蔽层的图案倍增,并转移至所述第一绝缘层中,形成第一图案层,所述第一图案层至少包括沿所述第一方向间隔排布的第一侧墙层;
在所述第一图案层的表面形成第二图案层;所述第二图案层至少包括沿所述第一方向间隔排布、且沿第三方向延伸的第二侧墙层;所述第一方向、所述第二方向与所述第三方向为所述基底所在平面内任意三个方向;
将所述第二侧墙层与所述第一侧墙层界定的初始图案转移至所述基底中。
在一些实施例中,所述第一抗反射层与所述基底之间的刻蚀选择比为所述第一绝缘层与所述基底之间的刻蚀选择比的3~10倍。
在一些实施例中,将所述第一掩蔽层的图案倍增,并转移至所述第一绝缘层中,包括:
在所述第一掩蔽层的表面和所述第一绝缘层的表面形成第二初始覆盖层;
去除位于所述第一掩蔽层顶表面和所述第一绝缘层表面的所述第二初始覆盖层,保留的位于所述第一掩蔽层侧壁的所述第二初始覆盖层,构成所述第一侧墙层。
在一些实施例中,所述第一图案层还包括第一牺牲层;在形成所述第一侧墙层之后,半导体结构的形成方法还包括:
在所述第一侧墙层之间的间隙中形成所述第一牺牲层;
其中,所述第一侧墙层与所述第一牺牲层的表面平齐。
在一些实施例中,所述第一初始间隔层通过以下步骤形成:
在所述第一绝缘层表面依次形成第一初始掩膜层和第二初始掩膜层;所述第一初始掩膜层包括所述第一掩蔽层和所述第一抗反射层;
刻蚀所述第二初始掩膜层,形成沿所述第一方向间隔排列的第二初始间隔层;
在所述第二初始间隔层的侧壁形成第一覆盖层;
通过所述第一覆盖层刻蚀所述第一初始掩膜层,形成沿所述第一方向交替排列的所述第一初始间隔层。
在一些实施例中,所述第二初始间隔层通过以下步骤形成:
在所述第二初始掩膜层的表面形成具有第一预设图案的第一光刻胶层;其中,所述第一预设图案包括沿所述第一方向依次排列、且沿所述第二方向延伸的多个第一子图案,所述第一子图案暴露出部分第二初始掩膜层;
去除所述第一子图案暴露出的所述第二初始掩膜层,形成所述第二初始间隔层。
在一些实施例中,所述第二图案层通过以下步骤形成:
在所述第一图案层表面形成第二绝缘层、以及位于所述第二绝缘层表面、沿所述第一方向间隔排列、且沿所述第三方向延伸的第三初始间隔层;所述第三初始间隔层包括第三掩蔽层和位于所述第三掩蔽层表面的第三抗反射层;
去除所述第三抗反射层;其中,所述第三抗反射层与所述基底之间的刻蚀选择比大于所述第二绝缘层与所述基底之间的刻蚀选择比;
将所述第三掩蔽层的图案倍增,并转移至所述第二绝缘层中,形成所述第二图案层。
在一些实施例中,所述第三抗反射层与所述基底之间的刻蚀选择比为所述第二绝缘层与所述基底之间的刻蚀选择比的3~10倍。
在一些实施例中,将所述第三掩蔽层的图案倍增,并转移至所述第二绝缘层中,包括:
在所述第三掩蔽层的表面和所述第二绝缘层的表面形成第四初始覆盖层;
去除位于所述第三掩蔽层顶表面和所述第一绝缘层表面的所述第四初始覆盖层,保留的位于所述第三掩蔽层侧壁的所述第四初始覆盖层,构成所述第二侧墙层。
在一些实施例中,所述第二图案层还包括第二牺牲层;在形成所述第二侧墙层之后,半导体结构的形成方法还包括:
在所述第二侧墙层之间的间隙中形成所述第二牺牲层;
其中,所述第二侧墙层与所述第二牺牲层的底表面平齐。
在一些实施例中,所述第三初始间隔层通过以下步骤形成:
在所述第二绝缘层表面依次形成第三初始掩膜层和第四初始掩膜层;所述第三初始掩膜层包括所述第三掩蔽层和所述第三抗反射层;
刻蚀所述第四初始掩膜层,形成沿所述第一方向间隔排列的第四初始间隔层;
在所述第四初始间隔层的侧壁形成第三覆盖层;
通过所述第三覆盖层刻蚀所述第三初始掩膜层,形成沿所述第一方向交替排列的所述第三初始间隔层。
在一些实施例中,所述第四初始间隔层通过以下步骤形成:
在所述第四初始掩膜层的表面形成具有第二预设图案的第二光刻胶层;其中,所述第二预设图案包括沿所述第一方向依次排列、且沿所述第三方向延伸的多个第二子图案,所述第二子图案暴露出部分第四初始掩膜层;
去除所述第二子图案暴露出的所述第四初始掩膜层,形成所述第四初始间隔层。
在一些实施例中,所述基底包括阵列区域和外围区域,在形成所述第二图案层之后,所述方法还包括:
在所述第二图案层表面具有第三预设图案的第三光刻胶层,其中,所述第三预设图案包括暴露出远离所述外围区域的部分所述阵列区域;
将所述初始图案转移至所述第三预设图案暴露出的所述阵列区域对应的基底中。
在一些实施例中,在形成所述第一图案层之后,且在形成所述第二图案层之前,半导体结构的形成方法还包括:
形成位于所述第一图案层表面的介质层。
在一些实施例中,所述基底包括第四掩膜层;将所述第二侧墙层与所述第一侧墙层界定的初始 图案转移至所述基底中,包括:
以所述第一侧墙层和所述第二侧墙层为掩膜,将所述初始图案转移至所述第四掩膜层中,形成具有初始图案的第四掩膜层;所述初始图案包括多个第三子图案。
在一些实施例中,所述基底还包括衬底,所述第四掩膜层位于所述衬底表面;在形成具有所述初始图案的第四掩膜层之后,所述方法还包括:
去除所述第三子图案暴露的部分所述衬底,以将所述初始图案转移至所述衬底中。
在一些实施例中,所述基底还包括叠层结构,所述第四掩膜层位于所述叠层结构表面;在形成具有所述初始图案的第四掩膜层之后,所述方法还包括:
去除所述第三子图案暴露的部分所述叠层结构,以将所述初始图案转移至所述叠层结构中。
在一些实施例中,所述初始图案包括电容孔图案。
第二方面,本公开实施例提供一种半导体结构,所述半导体结构通过上述权利要求所述的半导体结构的形成方法形成,所述半导体结构包括:
基底;所述基底包括初始图案;所述初始图案通过第一图案层中的第一侧墙层和第二图案层中的第二侧墙层界定;
其中,所述第一图案层位于所述基底的表面,所述第一侧墙层沿所述第一方向间隔排布、且沿第二方向延伸;所述第二图案层位于所述第一图案层的表面,所述第二侧墙层沿所述第一方向间隔排布、且沿第三方向延伸;所述第一方向、所述第二方向与所述第三方向为所述基底所在平面内任意三个方向。
本公开实施例提供的半导体结构及其形成方法,在基底表面形成有第一绝缘层、以及位于第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层,在形成第一图案层的过程中,由于第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,因此,在去除第一抗反射层的过程中不会损伤第一绝缘层,使得第一掩蔽层底部的图案不会出现凹凸结构,减小了第一掩蔽层向下转移过程中的刻蚀负载效应,如此,可以使得第一侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构。
在附图(其不一定是按比例绘制的)中,相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1a~1c为相关技术中半导体结构形成过程中的结构示意图;
图2为本公开实施例提供的半导体结构形成方法的流程示意图;
图3a~图3l、图4a~图4p为本公开实施例提供的半导体结构形成过程中的结构示意图。
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开,而不应被这里阐述的具体实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中,给出了大量的细节以便提供对本公开更为彻底的理解。然而,对于本领域技术人员而言显而易见的是,本公开可以无需一个或多个这些细节而得以实施。在其它的例子中,为了避免与本公开发生混淆,对于本领域公知的一些技术特征未进行描述;即,这里不描述实际实施例的全部特征,不详细描述公知的功能和结构。
在附图中,为了清楚,层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白,当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在……上”、“与……直接相邻”、“直接连接 到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本公开教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时,并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。
相关技术中,在动态随机存储器的电容管的形成工艺中,通常采用SAQP工艺进行图案转移,形成电容孔。图1a~图1c为相关技术中半导体结构形成过程中的结构示意图,如图1a所示,相关技术中的半导体结构被划分为阵列区域(Array Area,AA)和外围区域(Periphery Area,PA),相关技术中的半导体结构包括衬底(图1a和图1b中未示出)、位于衬底10表面的掩膜层100、位于掩膜层100表面的第一图案层A、以及位于第一图案层A表面的第二图案层B。其中,掩膜层100包括依次堆叠的第一硬掩膜层101、第二硬掩膜层102和第三硬掩膜层103、第一图案层A包括沿图1a中X轴方向间隔排列的第一侧墙层111,第二图案层B包括沿X轴方向间隔排列的第二侧墙层112;相关技术中,在形成第一图案层A和第二图案层B之后,会将第一图案层A和第二图案层B界定的电容孔图案依次向下转移,例如,先转移至第三硬掩膜层103中,再通过刻蚀后的第三硬掩膜层转移至第二硬掩膜层102中,形成具有电容孔104的刻蚀后的第二硬掩膜层102a(如图1b所示),最后再通过刻蚀后的第二硬掩膜层102a转移至第一硬掩膜层101和衬底中。
相关技术中,在形成第一侧墙层和第二图案层时,由于图案的关键尺寸不断缩小,图案密度越来越大,在刻蚀过程中由于刻蚀负载效应,使得第一侧墙层111和第二侧墙层112的关键尺寸不能准确控制,且由于刻蚀选择比的问题使得第一图案层A和第二图案层B底部呈凹凸状(如图1a中虚线框所示),进而影响后续的图案转移,破坏最终形成电容管结构,例如,使得最后形成的电容孔尺寸均匀性差(如图1c中的电容孔104-1、电容孔104-2和电容孔104-3所示),且会出现刻蚀不足(如图1b中虚线框所示)、刻蚀孔桥接以及孔错位(如图1c所示)等缺陷。
另外,由于光刻工艺的局限性,使得在阵列区域AA的角落容易产生伪电容孔103(如图1c所示),造成阵列区域AA边缘图案异常,进而影响动态随机存储器的性能和制备良率。
为解决上述技术问题,本公开实施例提供一种新的半导体结构的形成方法,能够精确地控制侧墙图案的关键尺寸,使得侧墙图案底部不会呈凹凸状,进而不会影响后续的图案转移过程,也不会造成最终形成的图案损坏;通过本公开实施例提供的半导体结构的形成方法可以使得最后形成的图案尺寸均匀性好,不会出现刻蚀不足、刻蚀孔桥接以及刻蚀孔错位等缺陷。
在介绍本公开实施例之前,先定义一下以下实施例可能用到的描述立体结构的四个方向。基底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面;在忽略顶表面和底表面的平整度的情况下,定义与基底顶表面和底表面的相交(例如垂直)的方向为第四方向。在基底的顶表面和底表面(即基底所在的平面)方向上,定义三个彼此相交的方向,例如可以定义第一初始间隔层的延伸方向为第二方向,定义第二侧墙层的延伸方向为第三方向,第二方向与第三方向呈锐角或者钝角,第一方向与第二方向和第三方向相交,基于第一方向、第二方向和第三方向可以确定基底的平面方向。本公开实施例中,定义第一方向为X轴方向,定义第二方向为Y1轴方向,定义第三方向为Y2轴方向,定义第四方向为Z轴方向。
本公开实施例提供一种半导体结构的形成方法,图2为本公开实施例提供的半导体结构形成方法的流程示意图,如图2所示,半导体结构的形成方法包括以下步骤:
步骤S201,提供基底,基底表面形成有第一绝缘层、以及位于第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层。
本公开实施例中,基底至少包括衬底,衬底可以包括硅衬底、锗衬底、锗化硅衬底、绝缘体上硅(Silicon-On-Insulator,SOI)衬底或绝缘体上锗(Germanium on Insulator,GOI)衬底等;衬底还可以为包括其他元素半导体或化合物半导体的衬底,例如砷化镓、磷化铟或碳化硅等。在其它实施例中,衬底还可以为进行离子掺杂后的衬底,例如为P型掺杂的衬底或者N型掺杂的衬底。
在一些实施例中,基底还可以包括叠层结构,叠层结构用于形成半导体结构的电容孔,叠层结构包括底部支撑层、底部牺牲层、中间支撑层、顶部牺牲层和顶部支撑层。
在一些实施例中,基底还可以包括位于衬底表面或者叠层结构表面的多层掩膜层,多层掩膜层用于转移将要传递至衬底或者叠层结构表面的图案。
本公开实施例中,第一绝缘层可以作为掩膜层,第一绝缘层可以是旋涂的含硅抗反射涂层(Silicon Anti-Reflection Coating,Si-ARC)。
本公开实施例中,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层,其中,第一掩蔽层可以是旋涂硬掩膜层(Spin On Hardmask,SOH),第一抗反射层可以是氧化硅层或者氮氧化硅层。
在一些实施例中,第一初始间隔层沿第一方向间隔排布、且沿第二方向延伸,其中,第一方向与第二方向可以呈锐角或者钝角。
步骤S202,去除第一抗反射层。
本公开实施例中,可以通过湿法刻蚀技术去除第一抗反射层,例如,采用浓硫酸、氢氟酸、浓硝酸等强酸刻蚀。
本公开实施例中,第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,例如,第一抗反射层与基底之间的刻蚀选择比为第一绝缘层与基底之间的刻蚀选择比的3~10倍。由于第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,因此,在去除第一抗反射层时,不会损伤第一绝缘层。
步骤S203,将第一掩蔽层的图案倍增,并转移至第一绝缘层中,形成第一图案层,第一图案层至少包括沿第一方向间隔排布的第一侧墙层。
本公开实施例中,可以通过自对准双重成像技术(Self-aligned Double Patterning,SADP)实现第一掩蔽层图案的倍增,并将倍增后的图案转移至第一绝缘层中,形成第一侧墙层。
在一些实施例中,在形成第一侧墙层之后,半导体结构的形成方法还包括:在第一侧墙层之间的间隙中形成第一牺牲层;其中,第一侧墙层与第一牺牲层的表面平齐。第一牺牲层可以是SOH或者氮氧化硅层。
需要说明的是,本公开实施例中,第一侧墙层和第一牺牲层的沿第三方向上的顶表面和底表面都是平齐的。
步骤S204,在第一图案层的表面形成第二图案层;第二图案层至少包括沿第一方向间隔排布、且沿第三方向延伸的第二侧墙层。
在一些实施例中,第二侧墙层沿第一方向间隔排布、且沿第三方向延伸,其中,第二方向与第三方向可以呈锐角或者钝角,第一方向与第二方向可以呈直角。
本公开实施例中,第二图案层形成于第一侧墙层和第一牺牲层的表面。第二图案层还包括位于第二侧墙层之间的第二牺牲层,其中,第二侧墙层与第二牺牲层的表面平齐,即第二侧墙层和第二牺牲层的沿第三方向上的顶表面和底表面都是平齐的。第二牺牲层可以是SOH或者氮氧化硅层。
步骤S205,将第二侧墙层与第一侧墙层界定的初始图案转移至基底中。
本公开实施例中,第二方向和第三方向的夹角可以根据初始图案的版图设计确定,例如,第二方向和第三方向之间的夹角可以是20度(°)~90°,例如为20°、40°、70°或者90°。
在一些实施例中,初始图案可以是电容孔图案。
本公开实施例提供的半导体结构的形成方法,在基底表面形成有第一绝缘层、以及位于第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层,在形成第一图案层的过程中,由于第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,因此,在去除第一抗反射层的过程中不会损伤第一绝缘层,使得第一掩蔽层底部的图案不会出现凹凸结构,减小了第一掩蔽层向下转移过程中的刻蚀负载效应,如此,可以使得第一侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构。
图3a~图3l、图4a~图4p为本公开实施例提供的半导体结构形成过程中的结构示意图,下面结合图3a~图3l、图4a~图4p对本公开实施例提供的半导体结构的形成过程进行详细的说明。
首先,执行步骤S201,提供基底,基底表面形成有第一绝缘层、以及位于第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层。
如图3a所示,基底包括第四掩膜层12和位于第四掩膜层12表面的第一绝缘层13;本公开实施 例中,第四掩膜层12包括第一硬掩膜层121、第二硬掩膜层122和第三硬掩膜层123;其中,第一硬掩膜层121可以是多晶硅层,第二硬掩膜层122可以是氧化硅层,第三硬掩膜层123可以是非晶碳层(Amorphous Carbon Layer,ACL)或者多晶硅层;第一绝缘层13可以是氮化硅层或者氮氧化硅层。
在一些实施例中,第四掩膜层12用于传递由第一侧墙层和第二侧墙层界定的初始图案,由于初始图案在转移过程中,每经过一次转移,初始图案的关键尺寸会缩小依次,通过具有多层硬掩膜层的第四掩膜层12来转移初始图案,直至达到所需要的图案尺寸,可以实现工艺节点的不断微缩,提高半导体结构的集成度。因此,本公开实施例中,第四掩膜层12中硬掩膜层的层数可以根据实际需要进行设置,例如,第四掩膜层12还可以由一层硬掩膜层组成或者由五层硬掩膜层组成。
本公开实施例中,第一绝缘层13可以是旋涂的含硅抗反射层。
本公开实施例中,请继续参见图3a,基底包括阵列区域AA和外围区域PA。
在一些实施例中,第一初始间隔层可以通过以下步骤形成:在基底表面依次形成第一初始掩膜层和第二初始掩膜层;第一初始掩膜层包括第一掩蔽层和第一抗反射层;刻蚀第二初始掩膜层,形成沿第一方向间隔排列的第二初始间隔层;在第二初始间隔层的侧壁形成第一覆盖层;通过第一覆盖层刻蚀第一初始掩膜层,形成沿第一方向交替排列的第一初始间隔层。
请继续参见图3a,在第一绝缘层13表面依次形成第一初始掩膜层14和第二初始掩膜层15,第一初始掩膜层14包括第一初始掩蔽层141和第一初始抗反射层142;第二初始掩膜层15包括第二初始掩蔽层151和第二初始抗反射层152。第一初始掩蔽层141和第二初始掩蔽层151可以是旋涂硬掩膜层或者非晶碳层(Amorphous Carbon Layer,ACL);第一初始抗反射层142和第二初始抗反射层152的材料均可以是氮氧化硅。本公开实施例中,可以通过以下任意一种合适的沉积工艺形成第一初始掩膜层和第二初始掩膜层:化学气相沉积(Chemical Vapor Deposition,CVD)工艺、物理气相沉积(Physical Vapor Deposition,PVD)工艺、原子层沉积(Atomic Layer Deposition,ALD)工艺、旋涂工艺或者涂敷工艺。
在其它实施例中,第一初始掩膜层14可以只包括第一初始掩蔽层141,第二初始掩膜层15可以只包括第二初始掩蔽层151。
在一些实施例中,刻蚀第二初始掩膜层,形成沿第一方向间隔排列的第二初始间隔层可以包括以下步骤:在第二初始掩膜层的表面形成具有第一预设图案的第一光刻胶层;其中,第一预设图案包括沿第一方向依次排列、且沿第二方向延伸的多个第一子图案,第一子图案暴露出部分第二初始掩膜层;去除第一子图案暴露出的第二初始掩膜层,形成第二初始间隔层。
请继续参见图3a和图3b,在第二初始掩膜层15的表面形成具有第一预设图案的第一光刻胶层16;其中,第一预设图案包括位于阵列区域AA、且沿X轴方向依次排列的多个第一子图案E,第一子图案E暴露出部分第二初始掩膜层15(即第二初始抗反射层152)。
如图3b和图3c所示,通过第一光刻胶层16刻蚀第二初始掩膜层15,去除第一子图案E暴露出的第二初始掩膜层15(包括第二初始抗反射层152和位于第二初始抗反射层152沿Z轴方向投影区域内的第二初始掩蔽层151),形成第二初始间隔层17。第二初始间隔层17包括第二掩蔽层171和位于第二掩蔽层171表面的第二抗反射层172。
在一些实施例中,请继续参见图3b和图3c,形成第二初始间隔层17之后,半导体结构的形成方法还包括:去除具有第一预设图案的第一光刻胶层16。
在一些实施例中,在第二初始间隔层的侧壁形成第一覆盖层的过程可以包括以下步骤:在第二初始间隔层和第一初始掩膜层的表面形成第一初始覆盖层;去除位于第二初始间隔层顶表面和第一初始掩膜层表面的第一初始覆盖层,保留的位于第二初始间隔层的第一初始覆盖层,构成第一覆盖层。
如图3d所示,在第二初始间隔层17和第一初始掩膜层14的表面形成第一初始覆盖层18,其中,第一初始覆盖层18覆盖第二初始间隔层17侧壁、顶表面以及第一初始掩膜层14的表面。本公开实施例中,可以采用原子层沉积工艺形成第一初始覆盖层18,以提高第一初始覆盖层18的膜层质量。
本公开实施例中,在形成第一初始覆盖层18之后,采用干法刻蚀工艺同时去除第二初始间隔层17顶表面和第一初始掩膜层14表面的第一初始覆盖层18,保留位于第二初始间隔层17侧壁的第一初始覆盖层18,保留的第一初始覆盖层18构成第一覆盖层181(如图3e所示)。
请继续参见图3d和图3e,在形成第一覆盖层181之后,半导体结构的形成方法还包括:去除第二初始间隔层17。在一些实施例中,可以采用湿法刻蚀技术去除第二初始间隔层17,例如,采用浓 硫酸、氢氟酸、浓硝酸等强酸刻蚀。
请继续参见图3e和图3f,通过第一覆盖层181刻蚀第一初始掩膜层14,即去除第一覆盖层181暴露出的部分第一初始掩膜层14(包括第一初始抗反射层142和位于第一初始抗反射层142沿Z轴方向投影区域内的第一初始掩蔽层141),形成第一初始间隔层19,第一初始间隔层19包括第一掩蔽层191和位于第一掩蔽层191表面的第一抗反射层192。
接下来,执行步骤S202,去除第一抗反射层。
如图3f和图3g所示,采用湿法刻蚀技术去除第一抗反射层192,例如可以采用稀释的氢氟酸溶液(水和氢氟酸的体积比为1:200)刻蚀去除第一抗反射层192。
本公开实施例中,由于第一抗反射层192与基底之间的刻蚀选择比大于第一绝缘层13与基底之间的刻蚀选择比(例如,第一抗反射层与基底之间的刻蚀选择比为第一绝缘层与基底之间的刻蚀选择比的3~10倍),因此,在去除第一抗反射层192时,不会损伤第一绝缘层13。
接下来,执行步骤S203,将第一掩蔽层的图案倍增,并转移至第一绝缘层中,形成第一图案层,第一图案层至少包括沿第一方向间隔排布的第一侧墙层。
在一些实施例中,步骤S203可以包括以下步骤:在第一掩蔽层的表面和第一绝缘层的表面形成第二初始覆盖层;去除位于第一掩蔽层顶表面和第一绝缘层表面的第二初始覆盖层,保留的位于第一掩蔽层侧壁的第二初始覆盖层,构成第一侧墙层。
如图3h所示,在第一掩蔽层191和第一绝缘层13的表面形成第二初始覆盖层20;其中,第二初始覆盖层20覆盖第一掩蔽层191的侧壁、顶表面以及第一绝缘层13的表面。本公开实施例中,可采用原子层沉积工艺形成第二初始覆盖层20,以提高第二初始覆盖层20的膜层质量。
如图3h和图3i所示,采用干法刻蚀工艺同时去除第一掩蔽层191顶表面以及第一绝缘层13表面的第二初始覆盖层20,保留位于第一掩蔽层191侧壁的第二初始覆盖层20;通过湿法刻蚀技术去除第一掩蔽层191;通过剩余的第二初始覆盖层20a刻蚀第一绝缘层13,形成第一侧墙层201,第一侧墙层201包括剩余的第二初始覆盖层20a和刻蚀后的第一绝缘层13a。
在一些实施例中,在形成第一侧墙层201之后,半导体结构的形成方法还包括:在第一侧墙层201之间的间隙中形成第一牺牲层。
实施时,可以通过在第一侧墙层之间的空隙中、第一侧墙层的表面、以及第一侧墙层之间空隙的表面形成第一初始牺牲层;回刻第一初始牺牲层,直至暴露出第一侧墙层中的剩余的第二初始牺牲层20a的表面,形成第一牺牲层。
如图3j所示,在第一侧墙层和第一掩蔽层之间的空隙中、第一侧墙层的表面、以及第一掩蔽层之间的空隙表面形成第一初始牺牲层22,旋涂第一牺牲层材料,形成第一初始牺牲层22;第一牺牲层材料可以是SOH或者其它材料。
如图3j和图3k所示,回刻第一初始牺牲层22、直至暴露出第一侧墙层201的表面,剩余的位于第一侧墙层201之间的空隙中的第一初始牺牲层22构成第一牺牲层23。
本公开实施例中,第一侧墙层201与第一牺牲层23的表面平齐,即第一侧墙层201与第一牺牲层23沿Z轴方向的顶表面和底表面均平齐,如此,可以使得后续的图案转移过程更加精准。
本公开实施例提供的半导体结构的形成方法,由于第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,因此,在去除第一抗反射层的过程中不会损伤第一绝缘层,使得第一掩蔽层底部的图案不会出现凹凸结构,减小了第一掩蔽层向下转移过程中的刻蚀负载效应,如此,可以使得第一侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构。
本公开实施例中,在形成第一牺牲层23之后,第一图案层也形成了,图3l为第一图案层的俯视图,为便于理解,图3k中仅示出有限个数的第一侧墙层,且图3l中未示出第一图案层300中的第一牺牲层23。如图3l所示,第一图案层300包括沿X轴方向间隔排布、且沿Y1轴方向延伸的第一侧墙层201。
接下来,执行步骤S204,在第一图案层的表面形成第二图案层;第二图案层至少包括沿第一方向间隔排布、且沿第三方向延伸的第二侧墙层。
在一些实施例中,第二图案层通过以下步骤形成:在第一图案层表面形成第二绝缘层、以及位于第二绝缘层表面、沿第一方向间隔排列、且沿第三方向延伸的第三初始间隔层;第三初始间隔层包括第三掩蔽层和位于第三掩蔽层表面的第三抗反射层;去除第三抗反射层;其中,第三抗反射层与基底之间的刻蚀选择比大于第二绝缘层与基底之间的刻蚀选择比;将第三掩蔽层的图案倍增,并转移至第二绝缘层中,形成第二图案层。
在一些实施例中,第三初始间隔层可以通过以下步骤形成:在第一图案层表面依次形成第三初始掩膜层和第四初始掩膜层;第三初始掩膜层包括第三掩蔽层和第三抗反射层;刻蚀第四初始掩膜层,形成沿第一方向间隔排列的第四初始间隔层;在第四初始间隔层的侧壁形成第三覆盖层;通过第三覆盖层刻蚀第三初始掩膜层,形成沿第一方向交替排列的第三初始间隔层。
在一些实施例中,在形成第二图案层之前,半导体结构的形成方法还包括:形成位于第一图案层300之上的介质层。
如图4a所示,在第一图案层300的表面形成介质层202,介质层202的材料可以是氮化硅或者氮氧化硅。
如图4b所示,在介质层的表面形成第二绝缘层24,第二绝缘层24的材料可以是旋涂的含硅抗反射层。
请继续参见图4b,在第二绝缘层24表面依次形成第三初始掩膜层25和第四初始掩膜层26,第三初始掩膜层25包括第三初始掩蔽层251和第三初始抗反射层252;第四初始掩膜层26包括第四初始掩蔽层261和第四初始抗反射层262。第三初始掩蔽层251和第四初始掩蔽层261可以是旋涂硬掩膜层或者非晶碳层;第三初始抗反射层252和第四初始抗反射层262的材料均可以是氮氧化硅。
本公开实施例中,可以通过任意一种合适的沉积工艺形成第一初始掩膜层和第二初始掩膜层。在其它实施例中,第三初始掩膜层25可以只包括第三初始掩蔽层251,第四初始掩膜层26可以只包括第四初始掩蔽层261。
在一些实施例中,第四初始间隔层可以通过以下步骤形成:在第四初始掩膜层的表面形成具有第二预设图案的第二光刻胶层;其中,第二预设图案包括沿第一方向依次排列的多个第二子图案,第二子图案暴露出部分第四初始掩膜层;第二子图案沿第三方向延伸;去除第二子图案暴露出的第四初始掩膜层,形成第四初始间隔层。
请继续参见图4b和图4c,在第四初始掩膜层26的表面形成具有第二预设图案的第二光刻胶层27;其中,第二预设图案包括位于阵列区域AA、且沿X轴方向依次排列、且沿Y2轴方向延伸的多个第二子图案F,第二子图案F暴露出部分第四初始掩膜层26。
如图4c和图4d所示,通过第二光刻胶层27刻蚀第四初始掩膜层26,去除第二子图案F暴露出的第四初始掩膜层26(包括第四初始抗反射层262和位于第四初始抗反射层262沿Z轴方向投影区域内的第四初始掩蔽层261),形成第四初始间隔层28。第四初始间隔层28包括第四掩蔽层281和位于第四掩蔽层281表面的第四抗反射层282。
在一些实施例中,请继续参见图4c和图4d,形成第四初始间隔层28之后,半导体结构的形成方法还包括:去除具有第二预设图案的第二光刻胶层27。
在一些实施例中,在第四初始间隔层的侧壁形成第三覆盖层可以包括以下步骤:在第四初始间隔层和第三初始掩膜层的表面形成第三初始覆盖层;去除位于第四初始间隔层顶表面和第三初始掩膜层表面的第三初始覆盖层,保留的位于第四初始间隔层侧壁的第三初始覆盖层,构成第三覆盖层。
如图4e所示,在第四初始间隔层28和第三初始掩膜层25的表面形成第三初始覆盖层29,其中,第三初始覆盖层29覆盖第四初始间隔层28侧壁、顶表面以及第三初始掩膜层25的表面。本公开实施例中,可以采用原子层沉积工艺形成第三初始覆盖层29,以提高第三初始覆盖层29的膜层质量。第三初始覆盖层29可以是氧化物层,例如可以是氧化硅层。
本公开实施例中,在形成第三初始覆盖层29之后,采用干法刻蚀工艺同时去除第四初始间隔层28顶表面和第三初始掩膜层25表面的第三初始覆盖层29,保留位于第四初始间隔层28侧壁的第三初始覆盖层29,保留的第三初始覆盖层29构成第三覆盖层291(如图4f所示)。
请继续参见图4e和图4f,在形成第三覆盖层291之后,半导体结构的形成方法还包括:去除第四初始间隔层28。在一些实施例中,可以采用湿法刻蚀技术去除第四初始间隔层28,例如,采用浓硫酸、氢氟酸、浓硝酸等强酸刻蚀。
请继续参见图4f和图4g,通过第三覆盖层291刻蚀第三初始掩膜层25,即去除第三覆盖层291暴露出的部分第三初始掩膜层25(包括第三初始抗反射层252和位于第三初始抗反射层252沿Z轴方向投影区域内的第三初始掩蔽层251),形成第三初始间隔层30。第三初始间隔层30包括第三掩蔽层301和位于第三掩蔽层301表面的第三抗反射层302。
如图4g和图4h所示,采用湿法刻蚀技术去除第三抗反射层302,例如可以采用稀释的氢氟酸溶液(水和氢氟酸的体积比为1:200)刻蚀去除第三抗反射层302。
本公开实施例中,由于第三抗反射层302与基底之间的刻蚀选择比大于第二绝缘层24与基底之间的刻蚀选择比(例如,第三抗反射层302与基底之间的刻蚀选择比为第二绝缘层24与基底之间的 刻蚀选择比的3~10倍),因此,在去除第三抗反射层302时,不会损伤第二绝缘层24。
在一些实施例中,将第三掩蔽层的图案倍增,并转移至第二绝缘层中,包括以下步骤:在第三掩蔽层的表面和第二绝缘层的表面形成第四初始覆盖层;去除位于第三掩蔽层顶表面和第二绝缘层表面的第四初始覆盖层,保留的位于第三掩蔽层侧壁的第四初始覆盖层,构成第二侧墙层。
如图4i所示,在第三掩蔽层301和第二绝缘层24的表面形成第四初始覆盖层31;其中,第四初始覆盖层31覆盖第三掩蔽层301的侧壁、顶表面以及第二绝缘层24的表面。本公开实施例中,可采用原子层沉积工艺形成第四初始覆盖层31,以提高第四初始覆盖层31的膜层质量。
如图4i和图4j所示,在形成第四初始覆盖层31之后,半导体结构的形成方法还包括:采用干法刻蚀工艺同时去除第三掩蔽层301顶表面以及第二绝缘层24表面的第四初始覆盖层31;通过湿法刻蚀技术去除第三掩蔽层301;通过剩余的第四初始覆盖层31a刻蚀第二绝缘层24,形成第二侧墙层311,第二侧墙层311包括剩余的第四初始覆盖层31a和刻蚀后的第二绝缘层24a。
在一些实施例中,如图4k所示,在形成第二侧墙层311之后,半导体结构的形成方法还包括:在第二侧墙层311之间的间隙中形成第二牺牲层34。
需要说明的是,本公开式实施例中,第二牺牲层34的形成过程与第一牺牲层23的形成过程相同,这里不再赘述。
图4l为第二图案层的俯视图,为便于理解,图4l中仅示出有限个数的第二侧墙层,且图4l中未示出第二图案层400中的第二牺牲层34。如图4k所示,第二图案层400包括沿X轴方向间隔排布、且沿Y2轴方向延伸的第二侧墙层311。
本公开实施例提供的半导体结构的形成方法,由于第三抗反射层与基底之间的刻蚀选择比大于第二绝缘层与基底之间的刻蚀选择比,因此,在去除第三抗反射层的过程中不会损伤第二绝缘层,使得第三掩蔽层底部的图案不会出现凹凸结构,减小了第三掩蔽层向下转移过程中的刻蚀负载效应,如此,可以使得第二侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构。
在一些实施例中,在形成第二图案层之后,半导体结构的形成方法还包括:在第二图案层表面形成具有第三预设图案的第三光刻胶层,其中,第三预设图案包括暴露出远离外围区域的部分阵列区域。
如图4l和图4m所示,在第二图案层400表面形成具有第三预设图案的第三光刻胶层36,其中,第三预设图案包括第三子图案。本公开实施例中,通过具有第三预设图案第三光刻胶层36刻蚀去除暴露出的第二图案层400中的第二牺牲层34、位于第二牺牲层34沿Z轴方向投影区域之内的介质层202、以及第一图案层300中的第一牺牲层23,形成如图4n所示的由第一侧墙层201和第二侧墙层311界定初始图案H。
最后,执行步骤S205,将第二侧墙层与第一侧墙层界定的初始图案转移至基底中。
结合图3a、图4o和图4p所示,基底包括第四掩膜层12,第四掩膜层12包括第一硬掩膜层121、第二硬掩膜层122和第三硬掩膜层123,实施时,首先,将初始图案H转移至第四掩膜层中的第三硬掩膜层中,其次,通过具有初始图案H的第三硬掩膜层123刻蚀第二硬掩膜层122,以将初始图案H转移至第二硬掩膜层122中,最后,通过具有初始图案H的第二硬掩膜层刻蚀第一硬掩膜层121,以将初始图案H转移至第一硬掩膜层121中,形成具有初始图案H的第一硬掩膜层121a,以实现将初始图案H转移至基底中。需要说明的是,为便于理解,图4p中仅示出部分初始图案H。
在一些实施例中,初始图案可以是电容孔图案。
本公开实施例提供的半导体结构的形成方法,由于第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,因此,在去除第一抗反射层的过程中不会损伤第一绝缘层,使得第一掩蔽层底部的图案不会出现凹凸结构,减小了第一掩蔽层向下转移过程中的刻蚀负载效应;且由于第三抗反射层与基底之间的刻蚀选择比大于第二绝缘层与基底之间的刻蚀选择比,因此,在去除第三抗反射层的过程中不会损伤第二绝缘层,使得第三掩蔽层底部的图案不会出现凹凸结构,减小了第三掩蔽层向下转移过程中的刻蚀负载效应,如此,可以使得第一侧墙层和第二侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构。
另外,通过本公开实施例提供的半导体结构的形成方法可以使得最后形成的图案尺寸均匀性好,不会出现刻蚀不足、刻蚀孔桥接以及刻蚀孔错位等缺陷,提高了半导体结构的制备良率。
除此之外,本公开实施例还提供一种半导体结构,请继续参考图4m~图4p,半导体结构包括:基底;基底包括初始图案H。
本公开实施例中,请继续参考图4m,基底包括第四掩膜层12,第四掩膜层12包括第一硬掩膜 层121、第二硬掩膜层122和第三硬掩膜层123。
在其它实施例中,基底还包括衬底,以及位于衬底表面的叠层结构。
请继续参考图4m,初始图案H通过第一图案层300中的第一侧墙层201和第二图案层400中的第二侧墙层311界定;第一图案层300包括沿X轴方向交替排列、且沿Y1轴方向(请参考图3i)延伸的第一侧墙层201和第一牺牲层23。
请继续参考图4m,第二图案层400位于第一图案层300的表面,第二图案层400包括沿X轴方向交替排列、且沿Y2轴(请参考图4l)方向延伸的第二侧墙层311和第二牺牲层34。
在一些实施例中,初始图案可以是电容孔图案。
本公开实施例提供的半导体结构与上述实施例中的半导体结构的形成方法类似,对于本公开实施例未详尽披露的技术特征,请参照上述实施例进行理解,这里,不再赘述。
本公开实施例提供的半导体结构包括具有初始图案的基底,初始图案通过第一图案层中的第一侧墙层和第二图案层中的第二侧墙层界定。由于本公开实施例提供的半导体结构通过上述半导体结构的形成方法形成,因此,本公开实施例中的第一侧墙层和第二侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构,因此,本公开实施例中的半导体结构具有较高的制备良率。
在本公开所提供的几个实施例中,应该理解到,所揭露的设备和方法,可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的,例如,单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,如:多个单元或组件可以结合,或可以集成到另一个系统,或一些特征可以忽略,或不执行。另外,所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
本公开所提供的几个方法或设备实施例中所揭露的特征,在不冲突的情况下可以任意组合,得到新的方法实施例或设备实施例。
以上,仅为本公开的一些实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以权利要求的保护范围为准。
本公开实施例提供的半导体结构及其形成方法,在基底表面形成有第一绝缘层、以及位于第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,第一初始间隔层包括第一掩蔽层和位于第一掩蔽层表面的第一抗反射层,在形成第一图案层的过程中,由于第一抗反射层与基底之间的刻蚀选择比大于第一绝缘层与基底之间的刻蚀选择比,因此,在去除第一抗反射层的过程中不会损伤第一绝缘层,使得第一掩蔽层底部的图案不会出现凹凸结构,减小了第一掩蔽层向下转移过程中的刻蚀负载效应,如此,可以使得第一侧墙层的关键尺寸容易控制,不会影响后续的图案转移,进而也不会破坏最终形成半导体结构。
Claims (19)
- 一种半导体结构的形成方法,所述方法包括:提供基底,所述基底表面形成有第一绝缘层、以及位于所述第一绝缘层表面、沿第一方向间隔排布、且沿第二方向延伸的第一初始间隔层,所述第一初始间隔层包括第一掩蔽层和位于所述第一掩蔽层表面的第一抗反射层;去除所述第一抗反射层;将所述第一掩蔽层的图案倍增,并转移至所述第一绝缘层中,形成第一图案层,所述第一图案层至少包括沿所述第一方向间隔排布的第一侧墙层;在所述第一图案层的表面形成第二图案层;所述第二图案层至少包括沿所述第一方向间隔排布、且沿第三方向延伸的第二侧墙层;所述第一方向、所述第二方向与所述第三方向为所述基底所在平面内任意三个方向;将所述第二侧墙层与所述第一侧墙层界定的初始图案转移至所述基底中。
- 根据权利要求1所述的方法,其中,所述第一抗反射层与所述基底之间的刻蚀选择比为所述第一绝缘层与所述基底之间的刻蚀选择比的3~10倍。
- 根据权利要求2所述的方法,其中,将所述第一掩蔽层的图案倍增,并转移至所述第一绝缘层中,包括:在所述第一掩蔽层的表面和所述第一绝缘层的表面形成第二初始覆盖层;去除位于所述第一掩蔽层顶表面和所述第一绝缘层表面的所述第二初始覆盖层,保留的位于所述第一掩蔽层侧壁的所述第二初始覆盖层,构成所述第一侧墙层。
- 根据权利要求3所述的方法,其中,所述第一图案层还包括第一牺牲层;在形成所述第一侧墙层之后,半导体结构的形成方法还包括:在所述第一侧墙层之间的间隙中形成所述第一牺牲层;其中,所述第一侧墙层与所述第一牺牲层的表面平齐。
- 根据权利要求4所述的方法,其中,所述第一初始间隔层通过以下步骤形成:在所述第一绝缘层表面依次形成第一初始掩膜层和第二初始掩膜层;所述第一初始掩膜层包括所述第一掩蔽层和所述第一抗反射层;刻蚀所述第二初始掩膜层,形成沿所述第一方向间隔排列的第二初始间隔层;在所述第二初始间隔层的侧壁形成第一覆盖层;通过所述第一覆盖层刻蚀所述第一初始掩膜层,形成沿所述第一方向交替排列的所述第一初始间隔层。
- 根据权利要求5所述的方法,其中,所述第二初始间隔层通过以下步骤形成:在所述第二初始掩膜层的表面形成具有第一预设图案的第一光刻胶层;其中,所述第一预设图案包括沿所述第一方向依次排列、且沿所述第二方向延伸的多个第一子图案,所述第一子图案暴露出部分第二初始掩膜层;去除所述第一子图案暴露出的所述第二初始掩膜层,形成所述第二初始间隔层。
- 根据权利要求1至6任一项所述的方法,其中,所述第二图案层通过以下步骤形成:在所述第一图案层表面形成第二绝缘层、以及位于所述第二绝缘层表面、沿所述第一方向间隔排列、且沿所述第三方向延伸的第三初始间隔层;所述第三初始间隔层包括第三掩蔽层和位于所述第三掩蔽层表面的第三抗反射层;去除所述第三抗反射层;其中,所述第三抗反射层与所述基底之间的刻蚀选择比大于所述第二绝缘层与所述基底之间的刻蚀选择比;将所述第三掩蔽层的图案倍增,并转移至所述第二绝缘层中,形成所述第二图案层。
- 根据权利要求7所述的方法,其中,所述第三抗反射层与所述基底之间的刻蚀选择比为所述第二绝缘层与所述基底之间的刻蚀选择比的3~10倍。
- 根据权利要求8所述的方法,其中,将所述第三掩蔽层的图案倍增,并转移至所述第二绝缘层中,包括:在所述第三掩蔽层的表面和所述第二绝缘层的表面形成第四初始覆盖层;去除位于所述第三掩蔽层顶表面和所述第一绝缘层表面的所述第四初始覆盖层,保留的位于所 述第三掩蔽层侧壁的所述第四初始覆盖层,构成所述第二侧墙层。
- 根据权利要求9所述的方法,其中,所述第二图案层还包括第二牺牲层;在形成所述第二侧墙层之后,半导体结构的形成方法还包括:在所述第二侧墙层之间的间隙中形成所述第二牺牲层;其中,所述第二侧墙层与所述第二牺牲层的底表面平齐。
- 根据权利要求10所述的方法,其中,所述第三初始间隔层通过以下步骤形成:在所述第二绝缘层表面依次形成第三初始掩膜层和第四初始掩膜层;所述第三初始掩膜层包括所述第三掩蔽层和所述第三抗反射层;刻蚀所述第四初始掩膜层,形成沿所述第一方向间隔排列的第四初始间隔层;在所述第四初始间隔层的侧壁形成第三覆盖层;通过所述第三覆盖层刻蚀所述第三初始掩膜层,形成沿所述第一方向交替排列的所述第三初始间隔层。
- 根据权利要求11所述的方法,其中,所述第四初始间隔层通过以下步骤形成:在所述第四初始掩膜层的表面形成具有第二预设图案的第二光刻胶层;其中,所述第二预设图案包括沿所述第一方向依次排列、且沿所述第三方向延伸的多个第二子图案,所述第二子图案暴露出部分第四初始掩膜层;去除所述第二子图案暴露出的所述第四初始掩膜层,形成所述第四初始间隔层。
- 根据权利要求12所述的方法,其中,所述基底包括阵列区域和外围区域,在形成所述第二图案层之后,所述方法还包括:在所述第二图案层表面具有第三预设图案的第三光刻胶层,其中,所述第三预设图案包括暴露出远离所述外围区域的部分所述阵列区域;将所述初始图案转移至所述第三预设图案暴露出的所述阵列区域对应的基底中。
- 根据权利要求13所述的方法,其中,在形成所述第一图案层之后,且在形成所述第二图案层之前,半导体结构的形成方法还包括:形成位于所述第一图案层表面的介质层。
- 根据权利要求14所述的方法,其中,所述基底包括第四掩膜层;将所述第二侧墙层与所述第一侧墙层界定的初始图案转移至所述基底中,包括:以所述第一侧墙层和所述第二侧墙层为掩膜,将所述初始图案转移至所述第四掩膜层中,形成具有初始图案的第四掩膜层;所述初始图案包括多个第三子图案。
- 根据权利要求15所述的方法,其中,所述基底还包括衬底,所述第四掩膜层位于所述衬底表面;在形成具有所述初始图案的第四掩膜层之后,所述方法还包括:去除所述第三子图案暴露的部分所述衬底,以将所述初始图案转移至所述衬底中。
- 根据权利要求16所述的方法,其中,所述基底还包括叠层结构,所述第四掩膜层位于所述叠层结构表面;在形成具有所述初始图案的第四掩膜层之后,所述方法还包括:去除所述第三子图案暴露的部分所述叠层结构,以将所述初始图案转移至所述叠层结构中。
- 根据权利要求17所述的方法,其中,所述初始图案包括电容孔图案。
- 一种半导体结构,所述半导体结构通过上述权利要求1至18任一项所述的半导体结构的形成方法形成,所述半导体结构包括:基底;所述基底包括初始图案;所述初始图案通过第一图案层中的第一侧墙层和第二图案层中的第二侧墙层界定;其中,所述第一图案层位于所述基底的表面,所述第一侧墙层沿所述第一方向间隔排布、且沿第二方向延伸;所述第二图案层位于所述第一图案层的表面,所述第二侧墙层沿所述第一方向间隔排布、且沿第三方向延伸;所述第一方向、所述第二方向与所述第三方向为所述基底所在平面内任意三个方向。
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WO2022077136A1 (zh) * | 2020-10-16 | 2022-04-21 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
WO2022142180A1 (zh) * | 2020-12-30 | 2022-07-07 | 长鑫存储技术有限公司 | 半导体器件的制造方法及半导体器件 |
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