WO2022077136A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022077136A1
WO2022077136A1 PCT/CN2020/117828 CN2020117828W WO2022077136A1 WO 2022077136 A1 WO2022077136 A1 WO 2022077136A1 CN 2020117828 W CN2020117828 W CN 2020117828W WO 2022077136 A1 WO2022077136 A1 WO 2022077136A1
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layer
spacer
mask
etching
target
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PCT/CN2020/117828
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English (en)
French (fr)
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WO2022077136A9 (zh
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苏博
赵振阳
张海洋
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Application filed by 中芯国际集成电路制造(上海)有限公司, 中芯国际集成电路制造(北京)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to CN202080103573.0A priority Critical patent/CN116508133A/zh
Priority to PCT/CN2020/117828 priority patent/WO2022077136A1/zh
Priority to TW110128224A priority patent/TW202218161A/zh
Publication of WO2022077136A1 publication Critical patent/WO2022077136A1/zh
Priority to US18/128,431 priority patent/US20230238245A1/en
Publication of WO2022077136A9 publication Critical patent/WO2022077136A9/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the distance between the source and the drain of the device is also shortened, so the control ability of the gate structure to the channel becomes worse, and the voltage of the gate structure is pinch-off (Pinch Off) channel becomes more and more difficult, making subthreshold leakage (Subthreshold Leakage) phenomenon, the so-called Short-Channel Effects (SCE) is more likely to occur.
  • SCE Short-Channel Effects
  • FinFET fin field effect transistors
  • the gate structure can control the ultra-thin body (fin) from at least two sides.
  • the gate structure has stronger control of the channel and can well suppress the short-channel effect;
  • FinFET has better compatibility with existing integrated circuit manufacturing.
  • the fin cutting process generally includes a cut first process and a cut last process.
  • the problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to increase the process window for etching the initial pattern layer of the cutting region to form the target pattern layer.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer, the substrate including a target area for forming the target pattern layer and a cutting area corresponding to the cutting position; A discrete mask spacer is formed on the substrate; using the mask spacer as a mask, the target layer is patterned to form a discrete initial pattern layer, the initial pattern layer extending in the lateral direction, and the lateral
  • the vertical direction is the longitudinal direction, and a groove is formed between the adjacent initial pattern layers along the longitudinal direction; a boundary defining groove is formed to penetrate the initial pattern layer located at the junction position of the target area and the cutting area along the transverse direction.
  • the stop layer is to etch the initial pattern layer located in the cutting area, and the remaining initial pattern layer located in the target area is used as a target pattern layer.
  • an embodiment of the present invention further provides a semiconductor structure, comprising: a substrate including a target area and a dicing area, the substrate including a target pattern layer separate from the target area, the target pattern layer extending laterally, and The vertical direction of the transverse direction is the longitudinal direction; the cutting groove is located on the base of the cutting area, the cutting groove extends along the transverse direction, the cutting groove is connected with the target graphic layer along the transverse direction, or the cutting groove Spaced and arranged in parallel with the target graphic layer; a boundary defining groove is located between the cutting groove and the target graphic layer in the lateral direction; a spacer layer is filled between the adjacent target graphic layers and the sidewalls of the adjacent cutting grooves The spacer layer fills the boundary defining grooves between the dicing grooves and the sidewalls of the dicing grooves and the target pattern layer.
  • the technical solution of the embodiment of the present invention has the following advantages: in the method for forming a semiconductor structure provided by the embodiment of the present invention, after the initial pattern layer is formed, a boundary defining groove is formed, which penetrates the target in the lateral direction.
  • the initial graphic layer at the boundary position of the target area and the cutting area, the boundary defining groove is used to define the boundary of the target area, so that the initial graphic layer is disconnected at the boundary position of the target area and the cutting area in the lateral direction, and then the filling is formed
  • the spacer layer of the groove is defined in the groove and the boundary, so that the initial pattern layer is spaced by the spacer layer in the transverse direction at the junction position of the target area and the cutting area, and the adjacent initial pattern layer in the longitudinal direction is also separated by the spacer layer.
  • the spacer layer can define etch stop positions in the lateral and longitudinal directions during the etching of the initial pattern layer located in the cutting region, so that the spacer layer located in the boundary defining groove and the spacer layer located in the groove can be defined.
  • the spacer layers in the grooves correspond to the stop layers along the lateral and longitudinal directions, respectively, and the embodiments of the present invention can accordingly realize self-aligned etching (Self-Aligned) along the lateral and longitudinal directions, which is beneficial to
  • the process window of the initial pattern layer in the etching and cutting area is increased, the process difficulty of forming the target pattern layer is reduced, and the key dimensions and patterns of the target pattern layer can be accurately controlled, thereby improving the cross-sectional topography quality of the target pattern layer. and sidewall topography quality.
  • the target area is an active area, and the cutting area is an isolation area;
  • the initial pattern layer is an initial fin, and the target pattern layer is a fin;
  • the material of the spacer layer is a dielectric material ; in the step of etching the initial pattern layer located in the cutting area, a cutting groove is formed in the spacer layer; after etching the initial pattern layer located in the cutting area, the forming method further includes: in the A filling isolation layer is formed in the cutting groove; the top of the fin is used as a stop position, and the filling isolation layer and the spacer layer are planarized; a part of the thickness of the filling isolation layer and the spacer layer is removed to expose the fins Part of the sidewall, the remaining filled isolation layer and spacer layer are used as isolation structures; the embodiment of the present invention can integrate the fin cutting process with the formation of the isolation structure, which is beneficial to improve process integration and process compatibility, and is also conducive to simplifying Process flow and improve production efficiency.
  • 1 to 4 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure.
  • 5 to 8 are schematic structural diagrams corresponding to each step in another method for forming a semiconductor structure.
  • 9 to 10 are schematic structural diagrams corresponding to each step in another method for forming a semiconductor structure.
  • 11 to 28 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
  • the fin cutting process generally includes fin first cutting (Cut first) process and fin back-cut (Cut last) process.
  • the process window of the current fin cutting process is getting smaller and smaller, and the difficulty of the fin cutting process is also getting higher and higher.
  • FIG. 1 to FIG. 4 schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.
  • a substrate 1 is provided; a plurality of discrete spacers are formed on the substrate 1 , and the spacers include a mask spacer 2 and a dummy mask spacer 3 .
  • the step of removing the dummy mask spacers 3 includes: forming a mask layer 4 on the substrate 1, the mask layer having mask openings 5 exposing the dummy mask spacers 3; using the mask layer 4 as a mask , remove the dummy mask spacer 3 exposed by the mask opening 5 ; remove the mask layer 4 .
  • the substrate 1 is patterned to form the fins 6 .
  • the aspect ratio of the dummy mask spacers 3 is smaller, and the difficulty of removing the dummy mask spacers 3 is relatively low.
  • the above method first removes the dummy mask spacers 3, and after removing the dummy mask spacers 3, the mask spacers 2 have different spacings, and the pattern density of the mask spacers 2 is not uniform.
  • the uneven pattern density of the mask spacers 2 may easily lead to uneven etching rates of the substrate 1 in each region, which in turn leads to a relatively uniform cross-sectional morphology of the formed fins. Difference.
  • FIGS. 5 to 8 are schematic structural diagrams corresponding to each step in another method for forming a semiconductor structure.
  • the fins include device fins 12 and dummy fins 13 .
  • the dummy fins 13 are removed.
  • the step of removing the dummy fins 13 includes: forming a mask layer 14 covering the device fins 12 on the substrate 11, wherein the mask layer 14 is formed with mask openings 15 exposing the dummy fins 13; The layer 14 is a mask, and the dummy fins 13 exposed by the mask opening 15 are removed; the mask layer 14 is removed.
  • the dummy fins 13 are removed, and the fins are formed by using the mask spacers as a mask patterning substrate. Since the spacing between the mask spacers is the same, the pattern density of the mask spacers is The consistency is high, so in the step of patterning the substrate to form the fins, the size consistency and the cross-sectional shape consistency of the fins are also higher.
  • the aspect ratio of the fins is large, which makes it extremely challenging to remove the dummy fins 13 .
  • the mask layer 14 is usually formed by photolithography processes such as exposure and development.
  • the aspect ratio of the dummy fins 13 is large, and the aspect ratio of the mask opening 15 is also large, which leads to a reduction in the process window of the photolithography process for forming the mask layer 14;
  • the etching process has a larger aspect ratio, which makes the etching process more difficult.
  • FIG. 9 to FIG. 10 schematic structural diagrams corresponding to each step in another method for forming a semiconductor structure are shown.
  • a substrate 21 and an initial fin 22 separated from the substrate 21 are provided, the substrate 21 includes an active region (not marked) and an isolation region (not marked); the initial fins are formed on the substrate 21 and filled with Covering layer 23 between parts 22 .
  • the initial fins 22 in the isolation region are removed, and the initial fins 22 in the active region are left as the fins 24 .
  • the capping layer 23 can define a stop position in a direction perpendicular to the extending direction of the initial fins 22 during the process of removing the initial fins 22 located in the isolation regions.
  • the stop position of the etching since the etching objects are all of the same material, it is difficult to control the stop position of the etching, so it is difficult to control the residual amount of the initial fins 22, which not only leads to the formation of the fins 24
  • the quality of the cross-sectional topography and the verticality of the sidewalls are low, and the critical dimension (CD) of the fin portion 24 is likely to fail to meet the design requirements, and the process window of the fin cutting process is small.
  • a boundary defining groove is formed to penetrate the initial pattern layer located at the boundary position of the target area and the cutting area in the lateral direction.
  • the boundary definition groove is used to define the boundary of the target area, so that the initial graphic layer is disconnected at the boundary position of the target area and the cutting area in the lateral direction, and then a spacer layer filled in the groove and the boundary definition groove is formed, Therefore, the initial pattern layer is spaced by the spacer layer at the junction position of the target area and the cutting area in the lateral direction, and the adjacent initial pattern layers in the longitudinal direction are also spaced by the spacer layer.
  • the spacer layer can define the etch stop positions in the lateral and longitudinal directions, so that the spacer layer in the groove and the spacer layer in the groove can be defined by the boundary, corresponding to the lateral and longitudinal directions, respectively.
  • the embodiment of the present invention can realize the etching self-alignment in the lateral and longitudinal directions, which is beneficial to increase the process window of the initial pattern layer in the etching cutting area and reduce the process difficulty of forming the target pattern layer. , and can accurately control the key dimensions and patterns of the target pattern layer, thereby improving the cross-sectional topography quality and sidewall topography quality of the target pattern layer.
  • 11 to 28 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
  • FIG. 11 a schematic cross-sectional view is shown, providing a substrate 200 including a target layer 100 , the substrate 200 including a target area A for forming a target pattern layer and a cutting area B corresponding to a cutting position.
  • the substrate 200 provides a process platform for subsequent processes.
  • the target layer 100 is a film layer to be patterned to form a target pattern layer.
  • the target area A is the area where the subsequent target pattern layer is located, and the area on the substrate 200 other than the target area A is the cutting area B.
  • the target layer 100 is an initial substrate, and the initial substrate is subsequently patterned to form the substrate and the fins protruding from the substrate.
  • the target graphics layer is a fin.
  • the fins are used to form Fin Field Effect Transistors (FinFETs).
  • the target area A is an active area (Active Area, AA)
  • the cutting area B is an isolation area.
  • the material of the initial substrate is silicon.
  • the material of the initial substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the initial substrate can also be a silicon-on-insulator substrate or a silicon-on-insulator substrate.
  • Other types of substrates such as germanium substrates.
  • the target pattern layer may also be a gate structure, a channel stack in a gate all around (GAA) transistor, a pattern transfer layer, or a pattern layer such as a dielectric spacer.
  • the pattern transfer layer may be a film layer such as a hard mask layer
  • the dielectric spacer may be a dielectric layer for isolating the metal interconnection lines in the rear section.
  • the substrate 200 further includes a hard mask material layer 120 on the target layer 100 .
  • the hard mask material layer 120 is patterned using the mask sidewall as a mask to form a hard mask layer. Even if the mask sidewall is lost in the process of patterning the target layer 100, the hard mask layer can continue to be used as the mask.
  • Masking the patterned target layer 100 is beneficial to improve the process stability of the patterned target layer 100 and the accuracy of pattern transfer; moreover, the subsequent process includes multiple etching processes, and the hard mask material layer 120 can also be etched in these
  • the etching stop position is defined in the etching process to avoid etching damage to the film below it.
  • the material of the hard mask material layer 120 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride.
  • the material of the hard mask material layer 120 is silicon nitride.
  • the substrate 200 further includes an adhesive layer 110 located between the target layer 100 and the hard mask material layer 120 .
  • the adhesion layer 110 is used to improve the adhesion between the hard mask material layer 120 and the target layer 100 and reduce the stress generated between the film layers.
  • the material of the adhesion layer 110 is silicon oxide.
  • discrete mask spacers 150 are formed on the substrate 200 .
  • the mask spacer 150 is used as a mask for the patterning target layer 100 .
  • the mask spacer 150 is selected from a material having etching selectivity with the target layer 100 , so as to ensure that the mask spacer 150 can be used as a mask for patterning the target layer 100 .
  • the material of the mask spacers 150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride or titanium oxide, nitrogen-doped tungsten (Nitrogen doped Tungsten) or tungsten doped carbon (Tungsten doped Carbon) and other materials.
  • the mask spacers 150 may be formed by SADP or SAQP process. Specifically, in this embodiment, the steps of forming the mask spacer 150 are described in detail by using the SAQP process to form the mask spacer 150 as an example.
  • a discrete core layer 140 (shown in FIG. 14 ) is formed on the substrate 200 .
  • the core layer 140 is used to provide support for forming the mask spacers.
  • a plurality of adjacent core layers 140 constitute a supporting core layer 140a, and a single core layer 140 constitutes a sacrificial core layer 140b.
  • the steps of forming the core layer 140 include: as shown in FIG. 11 , forming the core material layer 160 on the substrate 200 ; forming a discrete sacrificial layer 170 on the core material layer 160 ; As shown in FIG. 12 , the sacrificial layer 170 is removed; as shown in FIGS. 13 and 14 , using the initial spacer 180 as a mask, the core material layer 160 is patterned to form the core layer 140 .
  • the forming method further includes: forming the first etch stop layer 130 on the substrate 200 .
  • the first etching stop layer 130 is used to define the etching stop position of the subsequent etching process, so as to avoid the problem of etching inconsistency.
  • the forming method further includes: forming a second etch stop layer 165 on the core material layer 160 .
  • the process of forming the sacrificial layer 170 and the initial spacer 180 includes a combination of deposition and etching.
  • the second etch stop layer 165 is used to define the etching process in the etching process of forming the sacrificial layer 170 and forming the initial spacer 180.
  • the initial The wall 180 is a mask to pattern the second etch stop layer 165, and the patterned second etch stop layer 165 can also be used as a mask for the patterned core material layer 160, which is beneficial to improve the process stability and accuracy of pattern transfer .
  • the core layers 140 extend in the transverse direction (as shown in the x direction in FIG. 13 ), and are arranged at intervals along the longitudinal direction (as shown in the y direction in FIG. 13 ), and the transverse direction is perpendicular to the longitudinal direction.
  • the forming method further includes: removing the initial spacer 180 and the second etch stop layer 165 .
  • mask spacers 150 are formed on the sidewalls of the core layer 140 .
  • the steps of forming the mask spacers 150 include: forming a spacer film (not shown) that conformally covers the top surface and sidewalls of the core layer 140 and the top surface of the substrate 200 ; removing the top surface of the core layer 140 and the sidewall film on the top surface of the substrate 200 , and the remaining sidewall film on the sidewall of the core layer 140 is used as the mask sidewall 150 .
  • the forming method further includes: after forming the mask spacers 150 , removing the core layer 140 to expose the substrate 200 thereunder, in preparation for the subsequent patterning of the substrate 200 with the mask spacers 150 .
  • FIG. 13 is a top view
  • FIG. 14 is a cross-sectional view of FIG. 13 at the cc position
  • FIG. 15 is a cross-sectional view based on FIG. 14 .
  • the forming method further includes: forming a core layer 140 Then, before forming the mask spacers 150, the sacrificial core layer 140b located in the cutting region B is removed.
  • the subsequent process of etching the initial pattern layer located in the cutting region B needs to form an etching mask for etching the initial pattern layer located in the cutting region B.
  • an etching mask for etching the initial pattern layer located in the cutting region B.
  • the spacing between the mask spacers The consistency is less affected, which is beneficial to alleviate the problem of the difference in etching rate caused by the consistency difference of pattern density in the process of patterning the target layer 100 with the mask sidewall as the mask, which is correspondingly beneficial to ensure the initial pattern layer.
  • the critical dimensions, cross-section topography and sidewall verticality can meet the design requirements.
  • the aspect ratio of the core layer 140 is small, and it is less difficult to remove a single core layer 140 .
  • the step of removing the sacrificial core layer 140b located in the cutting area B includes: as shown in FIG. 13 and FIG. 14 , forming a first pattern layer 143 on the core layer 140 , and the first pattern layer 143 has a layer located in the cutting area in the first pattern layer 143 .
  • the first pattern layer 143 is a photoresist layer.
  • a first flat layer 141 covering the core layer 140 and a first anti-reflection layer 142 on the flat layer 141 are also formed on the substrate 200 . It should be noted that, for convenience of illustration and description, this embodiment only illustrates the first flat layer 141 and the first anti-reflection layer 142 in FIG. 14 .
  • the sacrificial core layer and the mask spacers located on the sidewalls of the sacrificial core layer form a sacrificial pattern layer; after forming the mask spacers, before patterning the target layer, removing the Sacrificial graphics layer in the dicing area.
  • removing the sacrificial pattern layer located in the cutting area may include: removing the sacrificial pattern layer located in the cutting area after forming the mask spacers and before removing the core layer.
  • a pattern layer used as an etching mask needs to be formed.
  • the pattern layer is formed by a photolithography process.
  • the photolithography process usually requires a calibration process.
  • two film layers are formed on the substrate: the core layer and the mask spacer.
  • removing the sacrificial pattern layer in the cutting area may further include: after removing the core layer and before patterning the target layer, removing the mask spacers in the sacrificial pattern layer in the cutting area.
  • the target layer 100 is patterned to form a separate initial pattern layer 210 .
  • the initial pattern layer 210 extends in the lateral direction (as shown in the x direction in FIG. 13 ), and The vertical direction is the longitudinal direction (as shown in the y direction in FIG. 13 ), and grooves 220 are formed between adjacent initial pattern layers 210 along the longitudinal direction.
  • the initial pattern layer 210 is used to form a target pattern layer through a subsequent cutting (Cut) process.
  • the target pattern layer is a fin
  • the initial pattern layer 210 is correspondingly an initial fin
  • the target layer 100 is patterned to form a substrate 230 and initial fins separated from the substrate 230 .
  • the groove 220 is bounded by the adjacent initial fins and the substrate 230 .
  • the forming method further includes: using the mask spacer 150 as a mask, patterning the hard mask material layer 120 to form a hard mask layer 240.
  • the hard mask layer 240 can protect the initial pattern layer 210 in subsequent processes. Specifically, the subsequent process further includes filling the spacer layer in the groove 220, the formation of the spacer layer includes a process of performing a planarization process, the hard mask layer 240 can be used to define the stop position of the planarization process, and the subsequent etching is located at the cutting position In the process of the initial pattern layer 210 in the area B, the hard mask layer 240 located in the cutting area is also removed, exposing the top of the initial pattern layer 210 in the cutting area B, corresponding to the step of etching the initial pattern layer 210 in the cutting area B Among them, the spacer layer and the remaining hard mask layer 240 can be used as masks for the initial pattern layer 210 in the cutting area B, so as to protect the initial pattern layer 210 in the target area A and reduce the initial pattern layer 210 in the target area A.
  • the pattern layer 210 causes the probability of mis-etching.
  • a boundary defining groove 250 is formed through the initial pattern layer 210 located at the boundary position of the target area A and the dicing area B in the lateral direction.
  • the boundary defining groove 250 is used to define the boundary of the target area A, so that the initial pattern layer 210 is disconnected at the boundary position of the target area A and the cutting area B in the lateral direction, and then the space filled in the groove 220 and the boundary defining groove 250 is formed layer, so that the initial pattern layer 210 in the transverse direction is spaced by the spacer layer at the junction position of the target area A and the cutting area B, and the adjacent initial pattern layers 210 in the longitudinal direction are also spaced by the spacer layer.
  • the spacer layer can define the etching stop positions along the lateral and vertical directions, which is beneficial to increase the process window for forming the target pattern layer and reduce the process difficulty of forming the target pattern layer, and
  • the key dimensions and patterns of the target pattern layer can be precisely controlled, thereby improving the profile topography quality and sidewall topography quality of the target pattern layer.
  • the boundary defining groove 250 also penetrates the hard mask layer 240 located at the boundary between the target area A and the cutting area B in the lateral direction.
  • the opening width of the boundary-defining groove 250 should not be too small, otherwise the process difficulty of etching the initial pattern layer 210 to form the boundary-defining groove 250 will be easily increased, and it is also difficult to control the sidewalls of the remaining initial pattern layer 210 in the target area A to be vertical.
  • the opening width of the groove 250 defined along the lateral boundary should not be too large, otherwise, the etching rates of the initial pattern layers 210 of different types of patterns are likely to be inconsistent, and it is difficult to accurately control the remaining initial pattern layers 210 in the target area A. Therefore, in the actual process, the opening width of the boundary definition groove 250 needs to be reasonably set according to the actual process requirements.
  • the step of forming the boundary defining groove 250 includes: as shown in FIG. 19 , forming a boundary defining mask layer 245 covering the initial pattern layer 210 , and forming the boundary defining mask layer 245 in the target area A in the lateral direction and cutting The boundary definition opening 51 at the boundary position of the region B; as shown in FIG. 20, the boundary definition mask layer 245 is used as a mask, the opening 51 is defined along the boundary, the initial pattern layer 210 is etched, and the boundary definition groove 250 is formed; the boundary definition is removed; Mask layer 245 .
  • the boundary definition mask layer 245 is located on the hard mask layer 240 . Therefore, the boundary definition opening 51 exposes the hard mask layer 240 . Accordingly, openings 51 are defined along the boundary, and the hard mask layer 240 and the initial pattern layer 210 are sequentially etched. In this embodiment, along the longitudinal direction, the boundaries of the boundary-defining openings 51 may be located between the initial pattern layers 210 .
  • the opening 51 is defined along the boundary, and the process of etching the initial pattern layer 210 includes an anisotropic dry etching process.
  • the anisotropic dry etching process has the characteristics of anisotropic etching, which is beneficial to improve the cross-section control and etching accuracy of etching, and is correspondingly beneficial to define the cross-sectional shape and sidewall verticality of the opening 51 on the boundary. and precise control of the opening width.
  • the shape and position of the target area A are indicated by a dotted frame in FIGS. 19 and 20 .
  • the area other than the target area A is the cutting area B.
  • a spacer layer 260 filled in the grooves 220 and the boundary-defining grooves 250 is formed.
  • the spacer layer 260 is filled in the groove 220 and the boundary defining groove 250, so that the initial pattern layer 210 is separated by the spacer layer 260 at the boundary position of the target area A and the cutting area B in the lateral direction, and the adjacent initial pattern layers 210 in the longitudinal direction are separated by the spacer layer 260. Also spaced apart by a spacer layer 260, during the etching of the initial pattern layer 210 located in the dicing region B, the spacer layer 260 can define etch stop locations in the lateral and longitudinal directions.
  • the spacer layer 260 covers the sidewall of the hard mask layer 240 .
  • the material of the spacer layer 260 is a dielectric material.
  • the target pattern layer is a fin.
  • the spacer layer 260 can also be planarized and etched. The remaining spacer layer 260 is used to form an isolation structure to isolate adjacent fins, so that the formation of the spacer layer 260 can be integrated with the fin cutting process and the process of forming the isolation structure, thereby improving process integration and process compatibility It can also simplify the process flow and improve the manufacturing efficiency.
  • the material of the spacer layer 260 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride.
  • the material of the spacer layer 260 is silicon oxide.
  • the spacer layer can be removed later, which is beneficial to improve the flexibility of the selection of the spacer layer material.
  • Carbon, SOC amorphous carbon, organic dielectric layer (Organic Dielectric layer, ODL), silicon-containing anti-reflective layer (Silicon-Anti-reflective Coating, Si-ARC), deep ultraviolet light absorbing oxide layer (Deep UV light absorbing Oxide, DUO), dielectric anti-reflective coating (Dielectric Anti-reflective Coating, DARC) or advanced graphics film (Advanced Patterning Film, APF).
  • the material of the spacer layer is a material that can be easily removed, which is beneficial to reduce the difficulty of subsequent removal of the spacer layer.
  • the step of forming the spacer layer 260 includes: forming a spacer material layer (not shown) that fills the groove 220 and the boundary defining groove 250 and covers the hard mask layer 240 ; the top of the hard mask layer 240 is At the stop position, the spacer material layer is planarized, and the remaining spacer material layer is used as the spacer layer 260 .
  • the process of forming the spacer material layer includes one or more of a flow chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, and a spin-on (Spin-On) process.
  • FCVD flow chemical vapor deposition
  • ALD atomic layer deposition
  • Spin-On spin-on
  • the process of forming the spacer material layer is a process with high gap filling ability, which is beneficial to improve the filling ability of the spacer material layer in the grooves 220 and the boundary definition grooves 250, and correspondingly improve the formation quality of the spacer material layer.
  • the spacer material layer is formed using a flow chemical vapor deposition process.
  • the process of planarizing the spacer material layer includes a chemical mechanical polishing process.
  • the chemical mechanical polishing process is a global planarization technology, which is beneficial to improve the flatness of the top surface of the spacer layer 260 and also to improve the efficiency of planarizing the spacer material layer.
  • the initial pattern located in the cutting region B is etched Layer 210, the remaining initial graphics layer 210 in the target area A is used as the target graphics layer 300 (as shown in FIG. 24).
  • the cutting groove 30 is formed in the spacer layer 260 in the step of etching the initial pattern layer 210 located in the cutting region B.
  • the spacer layer located in the boundary defining groove 250 and the spacer layer 260 located in the groove 220 can be respectively corresponding to the stop layer in the lateral direction and the longitudinal direction, and correspondingly, self-aligning etching in the lateral direction and the longitudinal direction can be realized.
  • Aligned Self-Aligned
  • the target pattern layer 300 is a fin, and the sectional topography quality and sidewall topography quality of the fin are high, and the critical dimension of the fin is precisely controlled, which is beneficial to improve the performance of the FinFET device.
  • the initial fins located in the cutting area B are etched to form the residual dummy fins 320 located in the cutting area B.
  • the residual dummy fins 320 are located between adjacent fins in the subsequent process of forming the isolation structure covering the sidewalls of the fins on the substrate 230, and can play a role of dispersing stress, thereby It is beneficial to improve the probability of bending or tilting of the fins due to different stress on the fins.
  • the height of the residual dummy fins 320 should not be too small, otherwise the effect of stress dispersing of the residual dummy fins 320 will be easily reduced; the height of the residual dummy fins 320 should not be too large, otherwise it is easy to cause the top surface of the isolation structure after the subsequent formation of the isolation structure. If the distance from the remaining dummy fins 320 is too small, it is easy to increase the risk of leakage current. Therefore, in this embodiment, the height of the residual dummy fins 320 is less than or equal to 20% of the height of the fins. As an example, the height of the residual dummy fins 320 is less than or equal to 200 ⁇ .
  • etching the initial pattern layer 210 located in the cutting region B includes the following steps.
  • FIG. 21 is a top view
  • FIG. 22 is a cross-sectional view of FIG. 21 at the cc position
  • a second pattern layer 263 is formed on the spacer layer 260, and the second pattern layer 263 has a cutting area B in the second pattern layer 263. the second opening 61.
  • the second pattern layer 263 covers the initial pattern layer 210 in the target area A, and the second pattern layer 263 has a second opening 61 in the cutting area B, which is used as a mask for etching the initial pattern layer 210 .
  • the second pattern layer 263 is a photoresist layer, and the second pattern layer 263 is formed by a photolithography process such as exposure and development.
  • the spacer layer 260 is used to separate the adjacent initial pattern layers 210 along the longitudinal direction, the spacer layer 260 is used to separate the initial pattern layers 210 of the target area A and the cutting area B along the transverse direction.
  • the edge of the opening 61 may be located between two adjacent initial pattern layers 210 , and the edge of the second opening 61 may be located on the spacer layer 260 in the boundary defining groove 250 in the lateral direction, so as to facilitate the formation of the second opening 61
  • the tolerance of the overlay shift (Overlay Shift) is higher, which is beneficial to improve the process window for forming the second pattern layer 263 .
  • the forming method before forming the second pattern layer 263 , further includes: forming a second flat layer 261 and a second anti-reflection layer 262 on the spacer layer 260 .
  • FIG. 23 is a partial enlarged view based on FIG. 21, and FIG. 24 is a cross-sectional view of FIG. 23 at the position cc.
  • the second pattern layer 263 as a mask, the bottom of the second opening 61 is etched The initial graphics layer 210.
  • the spacer layer 260 can be used as a stop layer in both the lateral and longitudinal directions to define the stop position of the initial pattern layer 210 in the etching cutting region B, which is beneficial to reduce the difficulty of etching the initial pattern layer 210 and improve the
  • the flexibility of the process selection for etching the initial pattern layer 210 for example, the process for etching the initial pattern layer 210 has a higher etching selectivity ratio for the initial pattern layer 210 and the spacer layer 260 .
  • the etching selectivity ratio between the initial pattern layer 210 and the spacer layer 260 is at least 4:1, and the ratio between the initial pattern layer 210 and the spacer layer 260 is at least 4:1.
  • the etching selection between the two is relatively large, which can further improve the effect of the spacer layer 260 in defining the etching stop position.
  • the process of etching the initial pattern layer 210 located in the cutting region B includes an isotropic etching process.
  • the isotropic etching process can reduce damage to other layers.
  • the process of etching the initial pattern layer 210 located in the cutting region B includes a wet etching process or a remote plasma (Remote Plasma) etching process.
  • the wet etching process is easy to achieve isotropic etching, and the wet etching process is simple in operation and low in cost, and the wet etching process can also achieve a larger etching selection ratio.
  • the remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has high etching selectivity, which is beneficial to reduce the loss of other film layers during the etching process.
  • the principle of the remote plasma etching process is to form plasma outside the etching chamber (for example: plasma generated by a remote plasma generator), and then introduce it into the etching chamber and use the plasma and the layer to be etched.
  • the chemical reaction is used for etching, so an isotropic etching effect can be achieved, and because there is no ion bombardment, other film layers will not be damaged.
  • other suitable etching processes can also be used to etch the initial pattern layer located in the cutting area, such as: Inductively Coupled Plasma (ICP) etching or Capacitively Coupled Plasma (CCP) etching and other etching processes .
  • ICP Inductively Coupled Plasma
  • CCP Capacitively Coupled Plasma
  • the forming method further includes: removing the hard mask layer 240 in the cutting region B to expose the initial pattern layer in the cutting region B 210, so that the initial pattern layer 210 of the cutting area B can be etched through the exposed top of the initial pattern layer 210.
  • the target pattern layer 300 is a fin; after etching the initial pattern layer 210 located in the cutting region B, the method for forming the semiconductor structure further includes the following steps.
  • a filling isolation layer 270 is formed in the cutting groove 30 .
  • the filling isolation layer 270 and the spacer layer 260 are subsequently removed with a partial thickness in preparation to form an isolation structure.
  • the material for filling the isolation layer 270 is the same as the material for the spacer layer 260 , which is beneficial to improve process compatibility.
  • the step of forming the filling isolation layer 270 includes: as shown in FIG. 25 , forming a filling isolation material layer 265 filling the cutting groove 30 and covering the spacer layer 260 and the hard mask layer 240 ; as shown in FIG. 26 and As shown in FIG. 27 , FIG. 26 is a top view, and FIG. 27 is a cross-sectional view of FIG. 26 at the cc position, with the top of the fin as the stop position, the filling isolation material layer 265 and the spacer layer 260 are planarized.
  • the filling isolation material layer 265 is formed by a process with strong gap filling capability, so as to improve the filling quality of the filling isolation material layer 265 in the cutting groove 30 .
  • the process of forming the filling isolation layer 270 includes one or both of a flow chemical vapor deposition process and an atomic layer deposition process.
  • the process of planarizing the filling isolation material layer 265 and the spacer layer 260 includes a chemical mechanical polishing process.
  • the filling isolation layer 270 and the spacer layer 260 are partially removed to expose part of the sidewall of the fin, and the remaining filling isolation layer 270 and the spacer layer 260 are used as the isolation structure 330 .
  • the isolation structures 330 are used to isolate adjacent fins.
  • the isolation structures 330 cover the residual dummy fins 320 .
  • the fin cut process is integrated with the process of forming the isolation structure 330 , which is conducive to improving process integration and process compatibility, and is also conducive to simplifying the process flow and improving the manufacturing efficiency. It should be noted that, in this embodiment, part of the spacer layer 260 is reserved to form the isolation structure 330 as an example. In other embodiments, after etching the initial pattern layer located in the cutting region, the forming method may further include: removing the spacer layer.
  • FIG. 26 and FIG. 27 are schematic structural diagrams showing an embodiment of the semiconductor structure of the present invention. 26 is a plan view, and FIG. 27 is a cross-sectional view of FIG. 26 at the cc position.
  • the semiconductor structure includes: a substrate 200 including a target area A and a cutting area B, the substrate 200 includes a target pattern layer 300 separate from the target area A, and the target pattern layer 300 extends in a lateral direction (as shown in the x direction in FIG. 26 ), The direction perpendicular to the transverse direction is the longitudinal direction (as shown in the y direction in FIG. 26 ); the cutting groove 30 (as shown in FIG. 23 and FIG.
  • the cutting groove 30 is located on the substrate 200 of the cutting area B, and the cutting groove 30 is along the transverse direction Extend, the cutting grooves 30 are connected to the target pattern layer 300 in the lateral direction, or the cutting grooves 30 and the target pattern layer 300 are arranged in parallel and spaced apart; the boundary defines the grooves 250 (as shown in FIG. 20 ), and the cutting grooves 250 and the target graphic layer 300 are located in the lateral direction.
  • the spacer layer 260 is filled between the adjacent target pattern layers 300, between the sidewalls of the adjacent cutting grooves 30, and between the sidewalls of the cutting grooves 30 and the target pattern layer 300, and the spacer layer 260 fills the boundary definition Slot 250.
  • the cutting groove 30 is formed by etching the initial pattern layer located in the cutting area B, and the remaining initial pattern layer located in the target area A is used as the target pattern layer 300 .
  • the boundary definition groove 250 is set, and the boundary definition groove 250 is used to define the boundary of the target area A, so that the initial graphic layer is disconnected at the boundary position of the target area A and the cutting area B in the lateral direction, and the spacer layer 260 is correspondingly made. Filled between adjacent target pattern layers 300 , between the sidewalls of adjacent dicing grooves 30 , and between the sidewalls of dicing grooves 30 and the target pattern layer 300 , the initial pattern layer is placed in the target area A along the lateral spacer layer 260 . It is spaced from the boundary position of the cutting area B, and the adjacent initial pattern layers along the longitudinal spacer layer 260 are spaced apart.
  • the spacer layer 260 can define The etching stop positions in the lateral and longitudinal directions, so that the spacer layer 260 located in the boundary definition groove 250 and the spacer layer 260 located between the adjacent initial pattern layers in the longitudinal direction correspond to the stop layers in the lateral direction and the longitudinal direction, respectively,
  • self-alignment in the lateral and vertical directions can be achieved, which is beneficial to increase the process window for forming the target pattern layer 300, reduce the process difficulty of forming the target pattern layer 300, and can improve the target pattern layer 300.
  • the key dimensions and patterns of the target pattern layer 300 are precisely controlled, thereby improving the cross-sectional topography quality and the sidewall topography quality of the target pattern layer 300 .
  • the substrate 200 provides a platform for the process.
  • the target area A is the area where the target pattern layer 300 is located, and the area on the substrate 200 other than the target area A is the cutting area B.
  • the target pattern layer 300 is a fin.
  • the fins are used to form fin field effect transistors.
  • the target area A is an active area
  • the cutting area B is an isolation area.
  • the target pattern layer 300 is a fin. Therefore, the cross-sectional topography and sidewall topography quality of the fin is high, and the critical dimension of the fin is precisely controlled, which is beneficial to improve the performance of the FinFET device.
  • the base 200 further includes a substrate 230 located at the bottom of the fin.
  • the fins protrude from the substrate 230 accordingly.
  • the material of the fins and the substrate 230 is silicon.
  • the target pattern layer may also be a gate structure, a channel stack in a gate all around (GAA) transistor, a pattern transfer layer, or a pattern layer such as a dielectric spacer.
  • the pattern transfer layer may be a film layer structure such as a hard mask layer
  • the dielectric spacer may be a dielectric layer for isolating the metal interconnection lines in the rear section.
  • the cutting groove 30 corresponds to the cutting (Cut) position of the initial pattern layer.
  • the cutting groove 30 is formed by etching the initial pattern layer located in the cutting region B. As shown in FIG. Therefore, the dicing grooves 30 extend in the same direction as the target pattern layer 300 .
  • the semiconductor structure further includes: a residual dummy fin 320 located at the bottom of the cutting groove 30 .
  • the reason why the residual dummy fins 320 remain in the semiconductor structure is that when the original fins located in the dicing region B are etched, part of the original fins remain as the residual dummy fins 320 .
  • the residual dummy fins 320 By arranging the residual dummy fins 320, in the subsequent process of forming the isolation structure covering the sidewalls of the fins on the substrate 230, the residual dummy fins 320 are located between adjacent fins, which can play a role in dispersing stress, thereby It is beneficial to improve the probability of bending or tilting of the fins due to different stress on the fins.
  • the height of the residual dummy fins 320 is less than or equal to 20% of the height of the fins. As an example, the height of the residual dummy fins 320 is less than or equal to 200 ⁇ .
  • the boundary defining groove 250 is used to define the boundary of the target area A, so that the initial pattern layer 210 is laterally disconnected at the boundary position of the target area A and the cutting area B, and the spacer layer 260 fills the boundary defining groove 250, so that the spacer layer 260
  • the initial pattern layer is spaced laterally at the junction of the target area A and the cutting area B.
  • the spacer layer located in the boundary defining groove 250 260 can define the etching stop position along the lateral direction, and can accurately control the key dimensions and patterns of the target pattern layer 300, thereby improving the cross-sectional topography quality and sidewall topography quality of the target pattern layer 300, and increasing the formation of the target pattern. Process window for layer 300 .
  • the spacer layer 260 separates the initial pattern layer in the lateral direction at the junction position of the target area A and the cutting area B, and separates the adjacent initial pattern layers in the longitudinal direction, and the initial pattern layer located in the cutting area B is etched to form During cutting of the grooves 30, the spacer layer 260 can define etch stop positions in the lateral and longitudinal directions.
  • the target pattern layer 300 is a fin; the material of the spacer layer 260 is a dielectric material. In this embodiment, the target pattern layer 300 is a fin.
  • the spacer layer 260 can be etched later, so that the remaining spacer layer 260 can be used to form an isolation structure to By isolating adjacent fins, the formation of the spacer layer 260 can be integrated with the processes of etching the initial fins located in the dicing region B and forming the isolation structure, which improves process integration and process compatibility, and simplifies the process.
  • the material of the spacer layer 260 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon oxycarbide and silicon oxycarbonitride.
  • the material of the spacer layer 260 is silicon oxide.
  • the spacer layer is subsequently removed, which is beneficial to improve the flexibility of the selection of the spacer layer material.
  • the material of the spacer layer may not be a dielectric material, and the material of the spacer layer may include spin-coated carbon, amorphous carbon, organic Dielectric layers, silicon-containing anti-reflection layers, deep UV absorbing oxide layers, dielectric anti-reflection coatings or advanced graphics.
  • the material of the spacer layer is a material that can be easily removed, which is beneficial to reduce the difficulty of removing the spacer layer.
  • the semiconductor structure further includes: a filling isolation layer 270 filled in the cutting groove 30 . Subsequent removal of a partial thickness of the filling isolation layer 270 and the spacer layer 260 forms an isolation structure.
  • the isolation structure is used to isolate adjacent fins, so that the fin cutting process is integrated with the process of forming the isolation structure, which is beneficial to improve process integration and compatibility, as well as simplify the process flow and improve the manufacturing efficiency.
  • the material for filling the isolation layer 270 is the same as the material for the spacer layer 260, which is beneficial to improve process compatibility.
  • the semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods.
  • the specific description of the semiconductor structure in this embodiment reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

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Abstract

一种半导体结构及其形成方法，形成方法包括：提供基底，包括目标层，基底包括用于形成目标图形层的目标区和与切割位置对应的切割区；在基底上形成掩膜侧墙；以掩膜侧墙为掩膜，图形化目标层，形成分立的初始图形层，初始图形层沿横向延伸，与横向垂直的方向为纵向，沿纵向相邻初始图形层之间形成有凹槽；形成边界定义槽，贯穿沿横向位于目标区与切割区的交界位置处的初始图形层；形成填充于凹槽和边界定义槽的间隔层；以位于边界定义槽中的间隔层和位于凹槽中的间隔层，分别对应为沿横向和纵向的停止层，刻蚀位于切割区的初始图形层，位于目标区的剩余初始图形层用于作为目标图形层。本发明实施例有利于增大刻蚀切割区的初始图形层的工艺窗口。

Description

半导体结构及其形成方法 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
 背景技术
在半导体制造中，随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，为了适应更小的特征尺寸，金属-氧化物-半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET）的沟道长度也相应不断缩短。然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，因此栅极结构对沟道的控制能力随之变差，栅极结构电压夹断（Pinch Off）沟道的难度也越来越大，使得亚阈值漏电（Subthreshold Leakage）现象，即所谓的短沟道效应（Short-Channel Effects，SCE）更容易发生。
因此，为了减小短沟道效应的影响，半导体工艺逐渐开始从平面MOSFET向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应晶体管（FinFET）。FinFET中，栅极结构至少可以从两侧对超薄体（鳍部）进行控制，与平面MOSFET相比，栅极结构对沟道的控制能力更强，能够很好地抑制短沟道效应；且FinFET相对于其他器件，与现有集成电路制造具有更好的兼容性。
在半导体领域中，根据工艺要求，通常还需要形成具有不同间距的鳍部，或者，将不需要位置处的伪鳍部去除，以使鳍部的图形层满足设计要求。目前一种做法是通过鳍切（Fin cut）工艺实现以上目的。其中，鳍切工艺一般包括鳍先切（Cut first）工艺和鳍后切（Cut last）工艺。
 技术问题
本发明实施例解决的问题是提供一种半导体结构及其形成方法，有利于增大刻蚀切割区的初始图形层以形成目标图形层的工艺窗口。
 技术解决方案
为解决上述问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底，包括目标层，所述基底包括用于形成目标图形层的目标区和与切割位置对应的切割区；在所述基底上形成分立的掩膜侧墙；以所述掩膜侧墙为掩膜，图形化所述目标层，形成分立的初始图形层，所述初始图形层沿横向延伸，与所述横向垂直的方向为纵向，沿所述纵向相邻所述初始图形层之间形成有凹槽；形成边界定义槽，贯穿沿横向位于所述目标区与所述切割区的交界位置处的初始图形层；形成填充于所述凹槽和所述边界定义槽的间隔层；以位于所述边界定义槽中的间隔层和位于所述凹槽中的间隔层，分别对应为沿所述横向和纵向的停止层，刻蚀位于所述切割区的初始图形层，位于所述目标区的剩余所述初始图形层用于作为目标图形层。
相应的，本发明实施例还提供一种半导体结构，包括：基底，包括目标区和切割区，所述基底包括分立于所述目标区的目标图形层，所述目标图形层沿横向延伸，与所述横向垂直的方向为纵向；切割槽，位于所述切割区的基底上，所述切割槽沿所述横向延伸，所述切割槽沿所述横向与目标图形层相连，或所述切割槽与目标图形层平行间隔排列；边界定义槽，沿横向位于所述切割槽与目标图形层之间；间隔层，填充于相邻所述目标图形层之间、相邻所述切割槽的侧壁之间、以及所述切割槽的侧壁与所述目标图形层之间，所述间隔层填充所述边界定义槽。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例提供的半导体结构的形成方法中，在形成初始图形层之后，形成边界定义槽，贯穿沿横向位于所述目标区和切割区交界位置处的初始图形层，边界定义槽用于定义所述目标区的边界，从而使初始图形层沿横向在所述目标区和切割区的边界位置处断开，之后形成填充于凹槽和边界定义槽的间隔层，从而使初始图形层沿横向在目标区和切割区的交界位置处被间隔层间隔开，沿纵向相邻的初始图形层也被所述间隔层间隔开，在刻蚀位于所述切割区的初始图形层的过程中，所述间隔层能够定义沿横向和纵向的刻蚀停止位置，从而能够以位于所述边界定义槽中的间隔层和位于所述凹槽中的间隔层，分别对应为沿所述横向和纵向的停止层，本发明实施例相应能够实现在沿横向和纵向上的刻蚀自对准（Self-Aligned），从而有利于增大刻蚀切割区的初始图形层的工艺窗口、降低形成目标图形层的工艺难度，且能够对所述目标图形层的关键尺寸和图形进行精确控制，进而提高目标图形层的剖面形貌质量和侧壁形貌质量。
可选方案中，所述目标区为有源区，所述切割区为隔离区；所述初始图形层为初始鳍部，所述目标图形层为鳍部；所述间隔层的材料为介质材料；刻蚀位于所述切割区的初始图形层的步骤中，在所述间隔层中形成有切割槽；刻蚀位于所述切割区的初始图形层之后，所述形成方法还包括：在所述切割槽中形成填充隔离层；以所述鳍部的顶部为停止位置，平坦化所述填充隔离层和间隔层；去除部分厚度的所述填充隔离层和间隔层，暴露出所述鳍部的部分侧壁，剩余所述填充隔离层和间隔层用于作为隔离结构；本发明实施例能够将鳍切工艺与形成隔离结构相整合，有利于提高工艺整合度和工艺兼容性，还有利于简化工艺流程、提高生产制造效率。
 附图说明
图1至图4是一种半导体结构的形成方法中各步骤对应的结构示意图。
图5至图8是另一种半导体结构的形成方法中各步骤对应的结构示意图。
图9至图10是又一种半导体结构的形成方法中各步骤对应的结构示意图。
图11至图28是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
由背景技术可知，通常通过鳍切（Fin cut）工艺形成具有不同间距的鳍部，或者，将不需要位置处的伪鳍部去除，以使鳍部的图形满足设计要求。其中，鳍切工艺一般包括鳍先切（Cut first）工艺和鳍后切（Cut last）工艺。
但是，目前鳍切工艺的工艺窗口越来越小，鳍切工艺的难度也越来越高。
现以鳍先切工艺为例，分析鳍切工艺的工艺窗口越来越小的原因。参考图1至图4，示出了一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1，提供基底1；在基底1上形成多个分立的侧墙，侧墙包括掩膜侧墙2和伪掩膜侧墙3。
参考图2至图3，去除伪掩膜侧墙3。其中，去除伪掩膜侧墙3的步骤包括：在基底1上形成掩膜层4，掩膜层中具有暴露出伪掩膜侧墙3的掩膜开口5；以掩膜层4为掩膜，去除掩膜开口5暴露出的伪掩膜侧墙3；去除掩膜层4。
参考图4，去除伪掩膜侧墙3后，以掩膜侧墙2为掩膜，图形化基底1，形成鳍部6。
与鳍部6的高宽比相比，伪掩膜侧墙3的高宽比更小，去除伪掩膜侧墙3的难度相对较低。但是，上述方法先去除伪掩膜侧墙3，去除伪掩膜侧墙3之后，掩膜侧墙2具有不同的间距，掩膜侧墙2的图形密度不均，在以掩膜侧墙2为掩膜图形化基底1的过程中，掩膜侧墙2的图形密度不均容易导致各个区域的基底1的被刻蚀速率不均，进而导致所形成的鳍部的剖面形貌均一性较差。
另一种方法是鳍后切工艺。图5至图8是另一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图5，提供衬底11以及分立于衬底11上的鳍部，鳍部包括器件鳍部12和伪鳍部13。
结合参考图5至图8，去除伪鳍部13。其中，去除伪鳍部13的步骤包括：在衬底11上形成覆盖器件鳍部12的掩膜层14，掩膜层14中形成有暴露出伪鳍部13的掩膜开口15；以掩膜层14为掩膜，去除掩膜开口15露出的伪鳍部13；去除掩膜层14。
上述方法在形成鳍部之后，再去除伪鳍部13，鳍部通过以掩膜侧墙为掩膜图形化基底而形成，由于掩膜侧墙之间的间距相同，掩膜侧墙的图形密度一致性较高，因此在图形化基底形成鳍部的步骤中，鳍部的尺寸一致性和剖面形貌一致性也较高。
但是，与掩膜侧墙的高宽比相比，鳍部的高宽比较大，导致去除伪鳍部13具有极大的挑战。具体地，掩膜层14通常通过曝光、显影等光刻制程形成。伪鳍部13的高宽比较大，掩膜开口15的深宽比也较大，导致形成掩膜层14的光刻工艺的工艺窗口减小；伪鳍部13的高宽比较大，在去除掩膜开口15露出的伪鳍部13的过程中，刻蚀工艺刻蚀的高宽比也较大，导致刻蚀工艺的难度较高。
还有一些其他方法进行鳍切工艺。参考图9至图10，示出了又一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图9，提供衬底21和分立于衬底21上的初始鳍部22，衬底21包括有源区（未标示）和隔离区（未标示）；在衬底21上形成填充于初始鳍部22之间的覆盖层23。
参考图10，形成覆盖层23后，去除位于隔离区的初始鳍部22，剩余位于有源区的初始鳍部22作为鳍部24。
通过形成覆盖层23，在去除位于隔离区的初始鳍部22的过程中，覆盖层23能够定义沿垂直于初始鳍部22延伸方向上的停止位置。但是，在沿初始鳍部22的延伸方向上，由于刻蚀对象均为同一种材料，难以控制刻蚀的停止位置，从而难以控制初始鳍部22的残余量，这不仅导致形成的鳍部24剖面形貌质量和侧壁垂直度低，还容易导致鳍部24的关键尺寸（CD）不能满足设计要求，鳍切工艺的工艺窗口较小。
因此，亟需一种方法，能够增大鳍部图形化工艺的工艺窗口，减小鳍部图形化工艺的难度。
为了解决所述技术问题，本发明实施例提供的半导体结构的形成方法中，在形成初始图形层之后，形成边界定义槽，贯穿沿横向位于所述目标区和切割区交界位置处的初始图形层，边界定义槽用于定义所述目标区的边界，从而使初始图形层沿横向在所述目标区和切割区的边界位置处断开，之后形成填充于凹槽和边界定义槽的间隔层，从而使初始图形层沿横向在目标区和切割区的交界位置处被所述间隔层间隔开，沿纵向相邻的初始图形层也被所述间隔层间隔开，在刻蚀位于所述切割区的初始图形层的过程中，间隔层能够定义沿横向和纵向的刻蚀停止位置，从而能够以位于边界定义槽中的间隔层和位于凹槽中的间隔层，分别对应为沿横向和纵向的停止层，本发明实施例相应能够实现在沿横向和纵向上的刻蚀自对准，从而有利于增大刻蚀切割区的初始图形层的工艺窗口、降低形成目标图形层的工艺难度，且能够对所述目标图形层的关键尺寸和图形进行精确控制，进而提高目标图形层的剖面形貌质量和侧壁形貌质量。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。图11至图28是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
参考图11，示出了剖面示意图，提供基底200，包括目标层100，所述基底200包括用于形成目标图形层的目标区A和与切割位置对应的切割区B。
基底200为后续工艺制程提供工艺平台。目标层100为待进行图形化以形成目标图形层的膜层。目标区A为后续目标图形层所在的区域，基底200上除目标区A之外的区域为切割区B。
本实施例中，目标层100为初始衬底，后续图形化初始衬底，形成衬底以及凸出于衬底的鳍部。相应地，本实施例中，目标图形层为鳍部。鳍部用于形成鳍式场效应晶体管（FinFET）。相应地，本实施例中，目标区A为有源区（Active Area，AA），切割区B是隔离区。
本实施例中，初始衬底的材料为硅。在其他实施例中，初始衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，初始衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
在其他实施例中，目标图形层还可以为栅极结构、全包围栅极（GAA）晶体管中的沟道叠层、图形传递层或介质隔层等图形层。其中，图形传递层可以为硬掩膜层等膜层，介质隔层可以为用于隔离后段金属互连线的介质层。
本实施例中，基底200还包括位于目标层100上的硬掩膜材料层120。后续先以掩膜侧墙为掩膜图形化硬掩膜材料层120形成硬掩膜层，即使在图形化目标层100的过程中掩膜侧墙发生损耗，也能够继续以硬掩膜层为掩膜图形化目标层100，有利于提高图形化目标层100的工艺稳定性和图形传递的精度；而且，后续制程包括多次进行的刻蚀工艺，硬掩膜材料层120还能够在这些刻蚀工艺中定义刻蚀停止位置，以免对其下方膜层造成刻蚀损伤。硬掩膜材料层120的材料包括氮化硅、氮化钛、碳化钨、氧化硅、碳氧化硅和碳氮氧化硅中的一种或多种。本实施例中，硬掩膜材料层120的材料为氮化硅。
本实施例中，基底200还包括位于目标层100和硬掩膜材料层120之间的黏附层110。黏附层110用于提高硬掩膜材料层120和目标层100之间的黏附性、减小膜层之间产生的应力。本实施例中，黏附层110的材料为氧化硅。
结合参考图11至图17，在基底200上形成分立的掩膜侧墙150（如图17所示）。掩膜侧墙150用于作为图形化目标层100的掩膜。
掩膜侧墙150选用与目标层100具有刻蚀选择性的材料，从而保证掩膜侧墙150能够作为图形化目标层100的掩膜。掩膜侧墙150的材料包括氧化硅、氮化硅、氮氧化硅、硅、氧化铝、氮化钛或氧化钛、氮掺杂钨（Nitrogen doped Tungsten）或钨掺杂的碳（Tungsten doped Carbon）等材料。本实施例中，掩膜侧墙150可以通过SADP或SAQP工艺形成。具体地，本实施例中以利用SAQP工艺形成掩膜侧墙150作为示例，对形成掩膜侧墙150的步骤进行详细说明。
如图11至图14所示，在基底200上形成分立的核心层140（如图14所示）。
核心层140用于为形成掩膜侧墙提供支撑作用。本实施例中，多个相邻的核心层140组成支撑核心层140a，单个核心层140组成牺牲核心层140b。
本实施例中，形成核心层140的步骤包括：如图11所示，在基底200上形成核心材料层160；在核心材料层160上形成分立的牺牲层170；在牺牲层170的侧壁上形成初始侧墙180；如图12所示，去除牺牲层170；如图13和图14所示，以初始侧墙180为掩膜，图形化核心材料层160，形成核心层140。
本实施例中，在提供基底200后，在形成核心材料层160之前，形成方法还包括：在基底200上形成第一刻蚀停止层130。第一刻蚀停止层130用于定义后续刻蚀工艺的刻蚀停止位置，以免引起刻蚀不一致的问题。
本实施例中，在形成核心材料层160后，在形成牺牲层170之前，形成方法还包括：在核心材料层160上形成第二刻蚀停止层165。形成牺牲层170和初始侧墙180的制程均包括沉积和刻蚀相结合的工艺，第二刻蚀停止层165用于在形成牺牲层170和形成初始侧墙180的刻蚀工艺中，定义刻蚀停止的位置，以免对其下方的核心材料层160造成损伤以及防止出现刻蚀不一致的问题，而且，以初始侧墙180为掩膜图形化核心材料层160的过程中，能够先以初始侧墙180为掩膜图形化第二刻蚀停止层165，图形化后的第二刻蚀停止层165也能够作为图形化核心材料层160的掩膜，有利于提高图形传递的工艺稳定性和精度。
本实施例中，核心层140沿横向（如图13中x方向所示）延伸，沿纵向（如图13中y方向所示）间隔排列，横向与纵向相垂直。本实施例中，图形化核心材料层160以形成核心层140后，形成方法还包括：去除初始侧墙180和第二刻蚀停止层165。
如图16所示，在核心层140的侧壁上形成掩膜侧墙150。
本实施例中，形成掩膜侧墙150的步骤包括：形成保形覆盖核心层140的顶面和侧壁以及基底200顶面的侧墙膜（图未示）；去除位于核心层140顶面和基底200顶面的侧墙膜，剩余位于核心层140侧壁的侧墙膜作为掩膜侧墙150。
如图17所示，形成方法还包括：形成掩膜侧墙150后，去除核心层140，暴露出其下方的基底200，为后续以掩膜侧墙150图形化基底200做准备。
结合参考图13至图15，图13为俯视图，图14为图13在cc位置处的剖面图，图15为基于图14的剖面图，本实施例中，形成方法还包括：形成核心层140之后，形成掩膜侧墙150之前，去除位于切割区B的牺牲核心层140b。
后续刻蚀位于切割区B的初始图形层的制程需要形成刻蚀位于切割区B的初始图形层的刻蚀掩膜，通过去除位于切割区B的牺牲核心层140b，有利于减小所述刻蚀掩膜的图形复杂度，从而增大形成所述刻蚀掩膜的工艺窗口（例如：缓解光刻解析度的限制）。而且，单个核心层140组成牺牲核心层140b，去除位于切割区B的牺牲核心层140a对剩余核心层140之间间距的影响小，在形成掩膜侧墙时，掩膜侧墙之间的间距一致性受到的影响小，有利于缓解在以掩膜侧墙为掩膜图形化目标层100的过程中，因图形密度一致性差异而导致刻蚀速率差异的问题，相应有利于保证初始图形层的关键尺寸、剖面形貌以及侧壁垂直度能够满足设计要求。此外，核心层140的高宽比较小，去除单个核心层140的难度较小。
本实施例中，去除位于切割区B的牺牲核心层140b的步骤包括：如图13和图14所示，在核心层140上形成第一图形层143，第一图形层143中具有位于切割区B的牺牲核心层140b上方的第一开口41；如图15所示，以第一图形层143为掩膜，沿第一开口41，刻蚀牺牲核心层140b；去除第一图形层143。
本实施例中，第一图形层143为光刻胶层。本实施例中，在形成第一图形层143之前，还在基底200上形成覆盖核心层140的第一平坦层141、以及位于平坦层141上的第一抗反射层142。需要说明的是，为方便示意和说明，本实施例仅在图14中示意出所述第一平坦层141和第一抗反射层142。
在其他实施例中，形成掩膜侧墙的步骤中，牺牲核心层和位于牺牲核心层侧壁上的掩膜侧墙组成牺牲图形层；形成掩膜侧墙之后，图形化目标层之前，去除位于切割区的牺牲图形层。具体地，去除位于切割区的牺牲图形层可以包括：在形成掩膜侧墙之后，去除核心层之前，去除位于切割区的牺牲图形层。
在去除位于切割区的牺牲图形层的过程中，需要形成用于作为刻蚀掩膜的图形层，图形层通过光刻工艺形成，光刻工艺通常需要进行校准的过程，在形成掩膜侧墙后，基底上形成有两种膜层：核心层和掩膜侧墙，通过在形成掩膜侧墙后且在去除核心层之前，去除位于切割区的牺牲图形层，有利于提高基底上图形的对比度（Contrast），从而为光刻工艺的校准提供更为清晰的对准标记（Alignment Mark），相应有利于提高光刻工艺的校准清晰度和准确度。
在另一些实施例中，去除位于切割区的牺牲图形层还可以包括：在去除核心层后，图形化目标层之前，去除位于切割区的牺牲图形层中的掩膜侧墙。
参考图18，以掩膜侧墙150为掩膜，图形化所述目标层100，形成分立的初始图形层210，初始图形层210沿横向（如图13中x方向所示）延伸，与横向垂直的方向为纵向（如图13中y方向所示），沿纵向相邻初始图形层210之间形成有凹槽220。初始图形层210用于经后续切割（Cut）工艺，形成目标图形层。
本实施例中，目标图形层为鳍部，初始图形层210相应为初始鳍部。
本实施例中，图形化所述目标层100，以形成衬底230和分立于衬底230上的初始鳍部。凹槽220由相邻的初始鳍部与衬底230围成。
本实施例中，在形成掩膜侧墙150后，图形化目标层100之前，形成方法还包括：以掩膜侧墙150为掩膜，图形化硬掩膜材料层120，形成硬掩膜层240。
硬掩膜层240能够在后续制程中对初始图形层210起到保护的作用。具体地，后续制程还包括在凹槽220中填充间隔层，形成间隔层包括进行平坦化工艺的过程，硬掩膜层240能够用于定义平坦化工艺的停止位置，而且，后续刻蚀位于切割区B的初始图形层210的过程中，还去除位于切割区的硬掩膜层240，暴露出切割区B的初始图形层210顶部，相应在刻蚀位于切割区B的初始图形层210的步骤中，间隔层和剩余的硬掩膜层240能够作为切割区B的初始图形层210的掩膜，从而对位于目标区A的初始图形层210起到保护的作用，降低对目标区A的初始图形层210造成误刻蚀的概率。
参考图19至图20，示出了俯视图，形成边界定义槽250，贯穿沿横向位于目标区A与切割区B的交界位置处的初始图形层210。
边界定义槽250用于定义目标区A的边界，从而使初始图形层210沿横向在目标区A和切割区B的边界位置处断开，之后形成填充于凹槽220和边界定义槽250的间隔层，从而使沿所述横向初始图形层210在目标区A和切割区B的交界位置处被间隔层间隔开，沿纵向相邻的初始图形层210也被间隔层间隔开，在刻蚀位于切割区B的初始图形层210的过程中，间隔层能够定义沿横向和纵向的刻蚀停止位置，有利于增大形成目标图形层的工艺窗口、降低形成目标图形层的工艺难度，且能够对目标图形层的关键尺寸和图形进行精确控制，进而提高目标图形层的剖面形貌质量和侧壁形貌质量。
本实施例中，边界定义槽250还贯穿沿横向位于目标区A和切割区B交界位置处的硬掩膜层240。沿横向，边界定义槽250的开口宽度不宜过小，否则容易增加刻蚀初始图形层210以形成边界定义槽250的工艺难度，而且还难以控制目标区A的剩余初始图形层210的侧壁垂直度；沿横向边界定义槽250的开口宽度也不宜过大，否则容易导致不同类型图案的初始图形层210的刻蚀速率不一致，进而难以对目标区A的剩余初始图形层210进行精确控制。因此，在实际工艺中，需根据实际工艺需求，合理设定边界定义槽250的开口宽度。
本实施例中，形成边界定义槽250的步骤包括：如图19所示，形成覆盖初始图形层210的边界定义掩膜层245，边界定义掩膜层245中形成沿横向位于目标区A和切割区B交界位置处的边界定义开口51；如图20所示，以边界定义掩膜层245为掩膜，沿边界定义开口51，刻蚀初始图形层210，形成边界定义槽250；去除边界定义掩膜层245。
本实施例中，边界定义掩膜层245位于硬掩膜层240上。因此，边界定义开口51暴露出硬掩膜层240。相应地，沿边界定义开口51，依次刻蚀硬掩膜层240和初始图形层210。本实施例中，沿纵向，边界定义开口51的边界可以位于初始图形层210之间。
本实施例中，沿边界定义开口51，刻蚀初始图形层210的工艺包括各向异性的干法刻蚀工艺。各向异性的干法刻蚀工艺具有各向异性刻蚀的特性，有利于提高刻蚀的剖面控制性和刻蚀精准度，相应有利于对边界定义开口51的剖面形貌、侧壁垂直度以及开口宽度进行精确控制。
本实施例中，为便于示意和说明，在图19和图20中用虚线框示意出了目标区A的形状和位置。除目标区A之外的区域为切割区B。
参考图21，形成填充于凹槽220和边界定义槽250的间隔层260。
间隔层260填充于凹槽220和边界定义槽250，从而使初始图形层210沿横向在目标区A和切割区B的交界位置处被间隔层260间隔开，沿纵向相邻的初始图形层210也被间隔层260间隔开，在刻蚀位于切割区B的初始图形层210的过程中，间隔层260能够定义沿横向和纵向的刻蚀停止位置。
本实施例中，间隔层260覆盖硬掩膜层240的侧壁。
本实施例中，间隔层260的材料为介质材料。本实施例中，目标图形层为鳍部，通过选用介质材料作为间隔层260的材料，从而在后续刻蚀位于切割区B的初始鳍部后，还能够对间隔层260进行平坦化处理以及刻蚀处理，使剩余的间隔层260用于形成隔离结构，以隔离相邻鳍部，从而能够将形成间隔层260与鳍切工艺以及形成隔离结构的工艺相整合，提高了工艺整合度和工艺兼容性，还能够简化工艺流程、提高生产制造效率。具体地，间隔层260的材料包括氧化硅、氮氧化硅、氮化硅、碳化硅、碳氧化硅和碳氮氧化硅中的一种或多种。作为示例，间隔层260的材料为氧化硅。
其他实施例中，后续还能够去除间隔层，相应有利于提高间隔层材料的选择灵活度，例如：间隔层的材料可以不选用介质材料，间隔层的材料可以包括旋涂碳（Spin-On Carbon，SOC）、无定形碳、有机介电层（Organic Dielectric layer，ODL）、含硅抗反射层（Silicon-Anti-reflective Coating，Si-ARC）、深紫外光吸收氧化层（Deep UV light absorbing Oxide，DUO）、介电抗反射涂层（Dielectric Anti-reflective Coating，DARC）或先进图膜（Advanced Patterning Film，APF）。间隔层的材料为易于被去除的材料，有利于降低后续去除间隔层的难度。
本实施例中，形成间隔层260的步骤包括：形成填充于凹槽220和边界定义槽250且覆盖硬掩膜层240的间隔材料层（图未示）；以硬掩膜层240的顶部为停止位置，平坦化间隔材料层，剩余的间隔材料层用于作为间隔层260。
本实施例中，形成间隔材料层的工艺包括流动式化学气相沉积（FCVD）工艺、原子层沉积（ALD）工艺和旋涂（Spin-On）工艺中的一种或几种。形成间隔材料层的工艺为间隙填充能力较高的工艺，有利于提高间隔材料层在凹槽220和边界定义槽250中的填充能力，相应提高间隔材料层的形成质量。作为一种示例，采用流动式化学气相沉积工艺，形成间隔材料层。
本实施例中，平坦化间隔材料层的工艺包括化学机械研磨工艺。化学机械研磨工艺是一种全局平坦化技术，有利于提高间隔层260的顶面平坦度，还有利于提高平坦化间隔材料层的效率。
结合参考图21至图24，以位于边界定义槽250中的间隔层260和位于凹槽220中的间隔层260，分别对应为沿横向和纵向的停止层，刻蚀位于切割区B的初始图形层210，位于目标区A的剩余初始图形层210用于作为目标图形层300（如图24所示）。本实施例中，刻蚀位于切割区B的初始图形层210的步骤中，在间隔层260中形成切割槽30。
本实施例能够以位于边界定义槽250中的间隔层和位于凹槽220中的间隔层260，分别对应为沿横向和纵向的停止层，相应能够实现在沿横向和纵向上的刻蚀自对准（Self-Aligned），从而增大刻蚀位于切割区B的初始图形层210的工艺窗口、降低形成目标图形层300的工艺难度，且能够对目标图形层300的关键尺寸和图形进行精确控制，进而提高目标图形层300的剖面形貌质量和侧壁形貌质量。本实施例中，目标图形层300为鳍部，鳍部的剖面形貌质量、侧壁形貌质量较高，且鳍部的关键尺寸得到了精确控制，有利于提高FinFET器件的性能。
本实施例中，刻蚀位于切割区B的初始鳍部，形成位于切割区B的残留伪鳍部320。通过形成残留伪鳍部320，后续在衬底230上形成覆盖鳍部部分侧壁的隔离结构的过程中，残留伪鳍部320位于相邻鳍部之间，能够起到分散应力的作用，从而有利于改善由于各鳍部受到的应力不同而导致鳍部发生弯曲或倾斜的概率。
残留伪鳍部320的高度不宜过小，否则容易降低残留伪鳍部320分散应力的效果；残留伪鳍部320的高度也不宜过大，否则容易导致在后续形成隔离结构后，隔离结构顶面与残留伪鳍部320之间的距离过小，容易增加产生漏电流的风险。为此，本实施例中，残留伪鳍部320的高度小于或等于鳍部高度的20%。作为一种示例，残留伪鳍部320的高度小于或等于200Å。
本实施例中，刻蚀位于切割区B的初始图形层210包括以下步骤。
如图21和图22所示，图21为俯视图，图22为图21在cc位置处的剖面图，在间隔层260上形成第二图形层263，第二图形层263中具有位于切割区B的第二开口61。第二图形层263覆盖目标区A的初始图形层210，第二图形层263中具有位于切割区B的第二开口61，用于作为刻蚀初始图形层210的掩膜。
本实施例中，第二图形层263为光刻胶层，第二图形层263通过曝光、显影等光刻工艺形成。本实施例中，由于沿纵向相邻初始图形层210之间被间隔层260间隔，沿横向目标区A和切割区B的初始图形层210之间被间隔层260间隔，因此，沿纵向第二开口61的边缘可以位于相邻两个初始图形层210之间，沿横向，第二开口61的边缘可以位于边界定义槽250中的间隔层260上，从而有利于增大形成第二开口61时的套刻偏移（Overlay Shift）容忍度，进而有利于提高形成第二图形层263的工艺窗口。本实施例中，形成第二图形层263之前，形成方法还包括：在间隔层260上形成第二平坦层261和第二抗反射层262。
如图23和图24所示，图23为基于图21的局部放大图，图24为图23在cc位置处的剖面图，以第二图形层263为掩膜，刻蚀第二开口61下方的初始图形层210。本实施例中，由于沿横向和纵向，间隔层260都能够作为停止层，以定义刻蚀切割区B的初始图形层210的停止位置，从而有利于降低刻蚀初始图形层210的难度、提高刻蚀初始图形层210的工艺选择灵活度，例如：刻蚀初始图形层210的工艺对初始图形层210和间隔层260具有较高的刻蚀选择比。
本实施例中，刻蚀位于切割区B的初始图形层210的步骤中，初始图形层210和间隔层260之间的刻蚀选择比至少为4:1，初始图形层210和间隔层260之间的刻蚀选择比较大，能够进一步提高间隔层260定义刻蚀停止位置的效果。
本实施例中，刻蚀位于切割区B的初始图形层210的工艺包括各向同性的刻蚀工艺。各向同性的刻蚀工艺能够降低对其他膜层的损伤。
作为一种示例，刻蚀位于切割区B的初始图形层210的工艺包括湿法刻蚀工艺或远程等离子体（Remote Plasma）刻蚀工艺。其中，湿法刻蚀工艺易于实现各向同性的刻蚀，且湿法刻蚀工艺操作简单、成本低，湿法刻蚀工艺还能够实现较大的刻蚀选择比。远程等离子体蚀刻工艺具有各向同性的刻蚀特性，而且，远程等离子体刻蚀工艺也具有较高的刻蚀选择性，在刻蚀的过程中，有利于减小对其他膜层的损耗。其中，远程等离子体蚀刻工艺的原理是在刻蚀腔室外部形成等离子体（例如：通过远程等离子体发生器产生等离子体），然后引入刻蚀腔室中并利用等离子体与被刻蚀层的化学反应进行蚀刻，因而可以实现各向同性的刻蚀效果，且因为没有离子轰击，因而不会损伤其他膜层。在其他实施例中，还能够采用其他合适的刻蚀工艺刻蚀位于切割区的初始图形层，例如：电感耦合等离子体（ICP）刻蚀或电容耦合等离子体（CCP）刻蚀等刻蚀工艺。
本实施例中，形成间隔层260之后，刻蚀位于切割区B的初始图形层210之前，形成方法还包括：去除位于切割区B的硬掩膜层240，暴露出切割区B的初始图形层210顶部，以便于通过暴露出的初始图形层210顶部，对切割区B的初始图形层210进行刻蚀。
本实施例中，目标图形层300为鳍部；在刻蚀位于切割区B的初始图形层210之后，半导体结构的形成方法还包括以下步骤。
参考图25至图27，在所述切割槽30中形成填充隔离层270。
通过形成填充隔离层270，为后续去除部分厚度的填充隔离层270和间隔层260以形成隔离结构做准备。本实施例中，填充隔离层270的材料与所述间隔层260的材料相同，从而有利于提高工艺兼容性。
本实施例中，形成填充隔离层270的步骤包括：如图25所示，形成填充于切割槽30且覆盖于间隔层260和硬掩膜层240上的填充隔离材料层265；如图26和图27所示，图26为俯视图，图27为图26在cc位置处的剖面图，以所述鳍部的顶部为停止位置，平坦化填充隔离材料层265和间隔层260。
本实施例中，采用间隙填充能力强的工艺形成填充隔离材料层265，从而提高填充隔离材料层265在切割槽30中的填充质量。具体地，形成填充隔离层270的工艺包括流动式化学气相沉积工艺和原子层沉积工艺中的一种或两种。
本实施例中，平坦化填充隔离材料层265和间隔层260的工艺包括化学机械研磨工艺。
参考图28，去除部分厚度的填充隔离层270和间隔层260，暴露出鳍部的部分侧壁，剩余填充隔离层270和间隔层260用于作为隔离结构330。隔离结构330用于隔离相邻鳍部。隔离结构330覆盖残留伪鳍部320。
本实施例将鳍切（Fin Cut）工艺与形成隔离结构330的工艺相整合，有利于提高工艺整合度和工艺兼容性，还有利于简化工艺流程、提高生产制造效率。需要说明的是，本实施例以保留部分的间隔层260以形成隔离结构330作为一种示例。其他实施例中，在刻蚀位于切割区的初始图形层之后，形成方法还可以包括：去除间隔层。
相应的，本发明还提供一种半导体结构。图26和图27示出了本发明半导体结构一实施例的结构示意图。其中，图26为俯视图，图27为图26在cc位置处的剖面图。
所述半导体结构包括：基底200，包括目标区A和切割区B，基底200包括分立于目标区A的目标图形层300，目标图形层300沿横向（如图26中x方向所示）延伸，与所述横向垂直的方向为纵向（如图26中y方向所示）；切割槽30（如图23和图24所示），位于所述切割区B的基底200上，切割槽30沿横向延伸，切割槽30沿横向与目标图形层300相连，或切割槽30与目标图形层300平行间隔排列；边界定义槽250（如图20所示），沿横向位于切割槽250与目标图形层300之间；间隔层260，填充于相邻目标图形层300之间、相邻切割槽30的侧壁之间、以及切割槽30的侧壁与目标图形层300之间，间隔层260填充边界定义槽250。切割槽30通过在刻蚀位于切割区B的初始图形层形成，剩余位于目标区A的初始图形层用于作为目标图形层300。
本实施例通过设置边界定义槽250，边界定义槽250用于定义目标区A的边界，从而使初始图形层沿横向在目标区A和切割区B的边界位置处断开，相应使间隔层260填充于相邻目标图形层300之间、相邻切割槽30的侧壁之间、以及切割槽30的侧壁与目标图形层300之间，沿横向间隔层260将初始图形层在目标区A和切割区B的交界位置处间隔开，沿纵向间隔层260相邻的初始图形层间隔开，在刻蚀位于切割区B的初始图形层形成切割槽30的过程中，间隔层260能够定义沿横向和纵向的刻蚀停止位置，从而能够以位于边界定义槽250中的间隔层260和沿纵向位于相邻初始图形层之间的间隔层260，分别对应为沿横向和纵向的停止层，相应能够实现在沿横向和纵向上的刻蚀自对准（Self-Aligned），有利于增大形成目标图形层300的工艺窗口、降低形成目标图形层300的工艺难度，且能够对目标图形层300的关键尺寸和图形进行精确控制，进而提高目标图形层300的剖面形貌质量和侧壁形貌质量。
基底200为工艺制程提供平台。目标区A为目标图形层300所在的区域，基底200上除目标区A之外的区域为切割区B。本实施例中，目标图形层300为鳍部。鳍部用于形成鳍式场效应晶体管。相应地，本实施例中，目标区A为有源区，切割区B为隔离区。
本实施例中，目标图形层300为鳍部，因此，鳍部的剖面形貌质量、侧壁形貌质量较高，且鳍部的关键尺寸得到精确控制，有利于提高FinFET器件的性能。
本实施例中，基底200还包括位于鳍部底部的衬底230。鳍部相应凸出于衬底230。本实施例中，鳍部和衬底230的材料为硅。
在其他实施例中，目标图形层还可以为栅极结构、全包围栅极（GAA）晶体管中的沟道叠层、图形传递层或介质隔层等图形层。其中，图形传递层可以为硬掩膜层等膜层结构，介质隔层可以为用于隔离后段金属互连线的介质层。
切割槽30与初始图形层的切割（Cut）位置相对应。切割槽30通过刻蚀位于切割区B的初始图形层形成。因此，切割槽30与目标图形层300的延伸方向相同。
本实施例中，半导体结构还包括：残留伪鳍部320，位于切割槽30的底部。残留伪鳍部320保留于半导体结构中，是由于在刻蚀位于切割区B的初始鳍部时，还保留部分的初始鳍部作为残留伪鳍部320。
通过设置残留伪鳍部320，后续在衬底230上形成覆盖鳍部部分侧壁的隔离结构的过程中，残留伪鳍部320位于相邻鳍部之间，能够起到分散应力的作用，从而有利于改善由于各鳍部受到的应力不同而导致鳍部发生弯曲或倾斜的概率。本实施例中，残留伪鳍部320的高度小于或等于鳍部高度的20%。作为一种示例，残留伪鳍部320的高度小于或等于200Å。
边界定义槽250用于定义目标区A的边界，从而使初始图形层210沿横向在目标区A和切割区B的边界位置处断开，间隔层260填充边界定义槽250，从而使间隔层260将初始图形层沿横向在目标区A和切割区B的交界位置处间隔开，在刻蚀位于切割区B的初始图形层以形成切割槽30的过程中，位于边界定义槽250中的间隔层260能够定义沿横向的刻蚀停止位置，能够对目标图形层300的关键尺寸和图形进行精确控制，进而提高目标图形层300的剖面形貌质量和侧壁形貌质量，增大了形成目标图形层300的工艺窗口。
间隔层260将初始图形层沿横向在目标区A和切割区B的交界位置处隔开，将沿纵向相邻的初始图形层间隔开，在刻蚀位于切割区B的初始图形层以形成切割槽30的过程中，间隔层260能够定义沿横向和纵向的刻蚀停止位置。
本实施例中，目标图形层300为鳍部；间隔层260的材料为介质材料。本实施例中，目标图形层300为鳍部，通过选用介质材料作为间隔层260的材料，从而在后续能够对间隔层260进行刻蚀处理，使剩余的间隔层260用于形成隔离结构，以隔离相邻鳍部，进而能够将形成间隔层260与刻蚀位于切割区B的初始鳍部以及形成隔离结构的工艺相整合，提高了工艺整合度和工艺兼容性，还能够简化工艺。
所述间隔层260的材料包括氧化硅、氮氧化硅、氮化硅、碳化硅、碳氧化硅和碳氮氧化硅中的一种或多种。作为一种示例，间隔层260的材料为氧化硅。
在其他实施例中，后续还去除间隔层，有利于提高间隔层材料的选择灵活度，例如：间隔层的材料可以不选用介质材料，间隔层的材料可以包括旋涂碳、无定形碳、有机介电层、含硅抗反射层、深紫外光吸收氧化层、介电抗反射涂层或先进图膜。间隔层的材料为易于被去除的材料，有利于降低去除间隔层的难度。
本实施例中，所述半导体结构还包括：填充隔离层270，填充于切割槽30内。后续去除部分厚度的填充隔离层270和间隔层260，形成隔离结构。隔离结构用于隔离相邻鳍部，从而将鳍切工艺与形成隔离结构的工艺相整合，有利于提高工艺整合度和兼容性，还有利于简化工艺流程、提高生产制造效率。
本实施例中，填充隔离层270的材料与间隔层260的材料相同，从而有利于提高工艺兼容性。
所述半导体结构可以采用前述实施例所述的形成方法所形成，也可以采用其他形成方法所形成。对本实施例所述半导体结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (1)

  1. 半导体结构及其形成方法
    技术领域
    [0001] 本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
    背景技术
    [0002] 在半导体制造中，随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，为了适应更小的特征尺寸，金属-氧化物-半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET）的沟道长度也相应不断缩短。然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，因此栅极结构对沟道的控制能力随之变差，栅极结构电压夹断（Pinch Off）沟道的难度也越来越大，使得亚阈值漏电（Subthreshold Leakage）现象，即所谓的短沟道效应（Short-Channel Effects，SCE）更容易发生。
    [0003] 因此，为了减小短沟道效应的影响，半导体工艺逐渐开始从平面MOSFET向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应晶体管（FinFET）。FinFET中，栅极结构至少可以从两侧对超薄体（鳍部）进行控制，与平面MOSFET相比，栅极结构对沟道的控制能力更强，能够很好地抑制短沟道效应；且FinFET相对于其他器件，与现有集成电路制造具有更好的兼容性。
    [0004] 在半导体领域中，根据工艺要求，通常还需要形成具有不同间距的鳍部，或者，将不需要位置处的伪鳍部去除，以使鳍部的图形层满足设计要求。目前一种做法是通过鳍切（Fin cut）工艺实现以上目的。其中，鳍切工艺一般包括鳍先切（Cut first）工艺和鳍后切（Cut last）工艺。
    技术问题
    [0005] 本发明实施例解决的问题是提供一种半导体结构及其形成方法，有利于增大刻蚀切割区的初始图形层以形成目标图形层的工艺窗口。
    技术解决方案
    [0006] 为解决上述问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底，包括目标层，所述基底包括用于形成目标图形层的目标区和与切割位置对应的切割区；在所述基底上形成分立的掩膜侧墙；以所述掩膜侧墙为掩膜，图形化所述目标层，形成分立的初始图形层，所述初始图形层沿横向延伸，与所述横向垂直的方向为纵向，沿所述纵向相邻所述初始图形层之间形成有凹槽；形成边界定义槽，贯穿沿横向位于所述目标区与所述切割区的交界位置处的初始图形层；形成填充于所述凹槽和所述边界定义槽的间隔层；以位于所述边界定义槽中的间隔层和位于所述凹槽中的间隔层，分别对应为沿所述横向和纵向的停止层，刻蚀位于所述切割区的初始图形层，位于所述目标区的剩余所述初始图形层用于作为目标图形层。
    [0007] 相应的，本发明实施例还提供一种半导体结构，包括：基底，包括目标区和切割区，所述基底包括分立于所述目标区的目标图形层，所述目标图形层沿横向延伸，与所述横向垂直的方向为纵向；切割槽，位于所述切割区的基底上，所述切割槽沿所述横向延伸，所述切割槽沿所述横向与目标图形层相连，或所述切割槽与目标图形层平行间隔排列；边界定义槽，沿横向位于所述切割槽与目标图形层之间；间隔层，填充于相邻所述目标图形层之间、相邻所述切割槽的侧壁之间、以及所述切割槽的侧壁与所述目标图形层之间，所述间隔层填充所述边界定义槽。
    有益效果
    [0008] 与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例提供的半导体结构的形成方法中，在形成初始图形层之后，形成边界定义槽，贯穿沿横向位于所述目标区和切割区交界位置处的初始图形层，边界定义槽用于定义所述目标区的边界，从而使初始图形层沿横向在所述目标区和切割区的边界位置处断开，之后形成填充于凹槽和边界定义槽的间隔层，从而使初始图形层沿横向在目标区和切割区的交界位置处被间隔层间隔开，沿纵向相邻的初始图形层也被所述间隔层间隔开，在刻蚀位于所述切割区的初始图形层的过程中，所述间隔层能够定义沿横向和纵向的刻蚀停止位置，从而能够以位于所述边界定义槽中的间隔层和位于所述凹槽中的间隔层，分别对应为沿所述横向和纵向的停止层，本发明实施例相应能够实现在沿横向和纵向上的刻蚀自对准（Self-Aligned），从而有利于增大刻蚀切割区的初始图形层的工艺窗口、降低形成目标图形层的工艺难度，且能够对所述目标图形层的关键尺寸和图形进行精确控制，进而提高目标图形层的剖面形貌质量和侧壁形貌质量。
    [0009] 可选方案中，所述目标区为有源区，所述切割区为隔离区；所述初始图形层为初始鳍部，所述目标图形层为鳍部；所述间隔层的材料为介质材料；刻蚀位于所述切割区的初始图形层的步骤中，在所述间隔层中形成有切割槽；刻蚀位于所述切割区的初始图形层之后，所述形成方法还包括：在所述切割槽中形成填充隔离层；以所述鳍部的顶部为停止位置，平坦化所述填充隔离层和间隔层；去除部分厚度的所述填充隔离层和间隔层，暴露出所述鳍部的部分侧壁，剩余所述填充隔离层和间隔层用于作为隔离结构；本发明实施例能够将鳍切工艺与形成隔离结构相整合，有利于提高工艺整合度和工艺兼容性，还有利于简化工艺流程、提高生产制造效率。
    附图说明
    [0010] 图1至图4是一种半导体结构的形成方法中各步骤对应的结构示意图。
    [0011] 图5至图8是另一种半导体结构的形成方法中各步骤对应的结构示意图。
    [0012] 图9至图10是又一种半导体结构的形成方法中各步骤对应的结构示意图。
    [0013] 图11至图28是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
    本发明的实施方式
    [0014] 由背景技术可知，通常通过鳍切（Fin cut）工艺形成具有不同间距的鳍部，或者，将不需要位置处的伪鳍部去除，以使鳍部的图形满足设计要求。其中，鳍切工艺一般包括鳍先切（Cut first）工艺和鳍后切（Cut last）工艺。
    [0015] 但是，目前鳍切工艺的工艺窗口越来越小，鳍切工艺的难度也越来越高。
    [0016] 现以鳍先切工艺为例，分析鳍切工艺的工艺窗口越来越小的原因。参考图1至图4，示出了一种半导体结构的形成方法中各步骤对应的结构示意图。
    [0017] 参考图1，提供基底1；在基底1上形成多个分立的侧墙，侧墙包括掩膜侧墙2和伪掩膜侧墙3。
    [0018] 参考图2至图3，去除伪掩膜侧墙3。其中，去除伪掩膜侧墙3的步骤包括：在基底1上形成掩膜层4，掩膜层中具有暴露出伪掩膜侧墙3的掩膜开口5；以掩膜层4为掩膜，去除掩膜开口5暴露出的伪掩膜侧墙3；去除掩膜层4。
    [0019] 参考图4，去除伪掩膜侧墙3后，以掩膜侧墙2为掩膜，图形化基底1，形成鳍部6。
    [0020] 与鳍部6的高宽比相比，伪掩膜侧墙3的高宽比更小，去除伪掩膜侧墙3的难度相对较低。但是，上述方法先去除伪掩膜侧墙3，去除伪掩膜侧墙3之后，掩膜侧墙2具有不同的间距，掩膜侧墙2的图形密度不均，在以掩膜侧墙2为掩膜图形化基底1的过程中，掩膜侧墙2的图形密度不均容易导致各个区域的基底1的被刻蚀速率不均，进而导致所形成的鳍部的剖面形貌均一性较差。
    [0021] 另一种方法是鳍后切工艺。图5至图8是另一种半导体结构的形成方法中各步骤对应的结构示意图。
    [0022] 参考图5，提供衬底11以及分立于衬底11上的鳍部，鳍部包括器件鳍部12和伪鳍部13。
    [0023] 结合参考图5至图8，去除伪鳍部13。其中，去除伪鳍部13的步骤包括：在衬底11上形成覆盖器件鳍部12的掩膜层14，掩膜层14中形成有暴露出伪鳍部13的掩膜开口15；以掩膜层14为掩膜，去除掩膜开口15露出的伪鳍部13；去除掩膜层14。
    [0024] 上述方法在形成鳍部之后，再去除伪鳍部13，鳍部通过以掩膜侧墙为掩膜图形化基底而形成，由于掩膜侧墙之间的间距相同，掩膜侧墙的图形密度一致性较高，因此在图形化基底形成鳍部的步骤中，鳍部的尺寸一致性和剖面形貌一致性也较高。
    [0025] 但是，与掩膜侧墙的高宽比相比，鳍部的高宽比较大，导致去除伪鳍部13具有极大的挑战。具体地，掩膜层14通常通过曝光、显影等光刻制程形成。伪鳍部13的高宽比较大，掩膜开口15的深宽比也较大，导致形成掩膜层14的光刻工艺的工艺窗口减小；伪鳍部13的高宽比较大，在去除掩膜开口15露出的伪鳍部13的过程中，刻蚀工艺刻蚀的高宽比也较大，导致刻蚀工艺的难度较高。
    [0026] 还有一些其他方法进行鳍切工艺。参考图9至图10，示出了又一种半导体结构的形成方法中各步骤对应的结构示意图。
    [0027] 参考图9，提供衬底21和分立于衬底21上的初始鳍部22，衬底21包括有源区（未标示）和隔离区（未标示）；在衬底21上形成填充于初始鳍部22之间的覆盖层23。
    [0028] 参考图10，形成覆盖层23后，去除位于隔离区的初始鳍部22，剩余位于有源区的初始鳍部22作为鳍部24。
    [0029] 通过形成覆盖层23，在去除位于隔离区的初始鳍部22的过程中，覆盖层23能够定义沿垂直于初始鳍部22延伸方向上的停止位置。但是，在沿初始鳍部22的延伸方向上，由于刻蚀对象均为同一种材料，难以控制刻蚀的停止位置，从而难以控制初始鳍部22的残余量，这不仅导致形成的鳍部24剖面形貌质量和侧壁垂直度低，还容易导致鳍部24的关键尺寸（CD）不能满足设计要求，鳍切工艺的工艺窗口较小。
    [0030] 因此，亟需一种方法，能够增大鳍部图形化工艺的工艺窗口，减小鳍部图形化工艺的难度。
    [0031] 为了解决所述技术问题，本发明实施例提供的半导体结构的形成方法中，在形成初始图形层之后，形成边界定义槽，贯穿沿横向位于所述目标区和切割区交界位置处的初始图形层，边界定义槽用于定义所述目标区的边界，从而使初始图形层沿横向在所述目标区和切割区的边界位置处断开，之后形成填充于凹槽和边界定义槽的间隔层，从而使初始图形层沿横向在目标区和切割区的交界位置处被所述间隔层间隔开，沿纵向相邻的初始图形层也被所述间隔层间隔开，在刻蚀位于所述切割区的初始图形层的过程中，间隔层能够定义沿横向和纵向的刻蚀停止位置，从而能够以位于边界定义槽中的间隔层和位于凹槽中的间隔层，分别对应为沿横向和纵向的停止层，本发明实施例相应能够实现在沿横向和纵向上的刻蚀自对准，从而有利于增大刻蚀切割区的初始图形层的工艺窗口、降低形成目标图形层的工艺难度，且能够对所述目标图形层的关键尺寸和图形进行精确控制，进而提高目标图形层的剖面形貌质量和侧壁形貌质量。
    [0032] 为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。图11至图28是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
    [0033] 参考图11，示出了剖面示意图，提供基底200，包括目标层100，所述基底200包括用于形成目标图形层的目标区A和与切割位置对应的切割区B。
    [0034] 基底200为后续工艺制程提供工艺平台。目标层100为待进行图形化以形成目标图形层的膜层。目标区A为后续目标图形层所在的区域，基底200上除目标区A之外的区域为切割区B。
    [0035] 本实施例中，目标层100为初始衬底，后续图形化初始衬底，形成衬底以及凸出于衬底的鳍部。相应地，本实施例中，目标图形层为鳍部。鳍部用于形成鳍式场效应晶体管（FinFET）。相应地，本实施例中，目标区A为有源区（Active Area，AA），切割区B是隔离区。
    [0036] 本实施例中，初始衬底的材料为硅。在其他实施例中，初始衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，初始衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
    [0037] 在其他实施例中，目标图形层还可以为栅极结构、全包围栅极（GAA）晶体管中的沟道叠层、图形传递层或介质隔层等图形层。其中，图形传递层可以为硬掩膜层等膜层，介质隔层可以为用于隔离后段金属互连线的介质层。
    [0038] 本实施例中，基底200还包括位于目标层100上的硬掩膜材料层120。后续先以掩膜侧墙为掩膜图形化硬掩膜材料层120形成硬掩膜层，即使在图形化目标层100的过程中掩膜侧墙发生损耗，也能够继续以硬掩膜层为掩膜图形化目标层100，有利于提高图形化目标层100的工艺稳定性和图形传递的精度；而且，后续制程包括多次进行的刻蚀工艺，硬掩膜材料层120还能够在这些刻蚀工艺中定义刻蚀停止位置，以免对其下方膜层造成刻蚀损伤。硬掩膜材料层120的材料包括氮化硅、氮化钛、碳化钨、氧化硅、碳氧化硅和碳氮氧化硅中的一种或多种。本实施例中，硬掩膜材料层120的材料为氮化硅。
    [0039] 本实施例中，基底200还包括位于目标层100和硬掩膜材料层120之间的黏附层110。黏附层110用于提高硬掩膜材料层120和目标层100之间的黏附性、减小膜层之间产生的应力。本实施例中，黏附层110的材料为氧化硅。
    [0040] 结合参考图11至图17，在基底200上形成分立的掩膜侧墙150（如图17所示）。掩膜侧墙150用于作为图形化目标层100的掩膜。
    [0041] 掩膜侧墙150选用与目标层100具有刻蚀选择性的材料，从而保证掩膜侧墙150能够作为图形化目标层100的掩膜。掩膜侧墙150的材料包括氧化硅、氮化硅、氮氧化硅、硅、氧化铝、氮化钛或氧化钛、氮掺杂钨（Nitrogen doped Tungsten）或钨掺杂的碳（Tungsten doped Carbon）等材料。本实施例中，掩膜侧墙150可以通过SADP或SAQP工艺形成。具体地，本实施例中以利用SAQP工艺形成掩膜侧墙150作为示例，对形成掩膜侧墙150的步骤进行详细说明。
    [0042] 如图11至图14所示，在基底200上形成分立的核心层140（如图14所示）。
    [0043] 核心层140用于为形成掩膜侧墙提供支撑作用。本实施例中，多个相邻的核心层140组成支撑核心层140a，单个核心层140组成牺牲核心层140b。
    [0044] 本实施例中，形成核心层140的步骤包括：如图11所示，在基底200上形成核心材料层160；在核心材料层160上形成分立的牺牲层170；在牺牲层170的侧壁上形成初始侧墙180；如图12所示，去除牺牲层170；如图13和图14所示，以初始侧墙180为掩膜，图形化核心材料层160，形成核心层140。
    [0045] 本实施例中，在提供基底200后，在形成核心材料层160之前，形成方法还包括：在基底200上形成第一刻蚀停止层130。第一刻蚀停止层130用于定义后续刻蚀工艺的刻蚀停止位置，以免引起刻蚀不一致的问题。
    [0046] 本实施例中，在形成核心材料层160后，在形成牺牲层170之前，形成方法还包括：在核心材料层160上形成第二刻蚀停止层165。形成牺牲层170和初始侧墙180的制程均包括沉积和刻蚀相结合的工艺，第二刻蚀停止层165用于在形成牺牲层170和形成初始侧墙180的刻蚀工艺中，定义刻蚀停止的位置，以免对其下方的核心材料层160造成损伤以及防止出现刻蚀不一致的问题，而且，以初始侧墙180为掩膜图形化核心材料层160的过程中，能够先以初始侧墙180为掩膜图形化第二刻蚀停止层165，图形化后的第二刻蚀停止层165也能够作为图形化核心材料层160的掩膜，有利于提高图形传递的工艺稳定性和精度。
    [0047] 本实施例中，核心层140沿横向（如图13中x方向所示）延伸，沿纵向（如图13中y方向所示）间隔排列，横向与纵向相垂直。本实施例中，图形化核心材料层160以形成核心层140后，形成方法还包括：去除初始侧墙180和第二刻蚀停止层165。
    [0048] 如图16所示，在核心层140的侧壁上形成掩膜侧墙150。
    [0049] 本实施例中，形成掩膜侧墙150的步骤包括：形成保形覆盖核心层140的顶面和侧壁以及基底200顶面的侧墙膜（图未示）；去除位于核心层140顶面和基底200顶面的侧墙膜，剩余位于核心层140侧壁的侧墙膜作为掩膜侧墙150。
    [0050] 如图17所示，形成方法还包括：形成掩膜侧墙150后，去除核心层140，暴露出其下方的基底200，为后续以掩膜侧墙150图形化基底200做准备。
    [0051] 结合参考图13至图15，图13为俯视图，图14为图13在cc位置处的剖面图，图15为基于图14的剖面图，本实施例中，形成方法还包括：形成核心层140之后，形成掩膜侧墙150之前，去除位于切割区B的牺牲核心层140b。
    [0052] 后续刻蚀位于切割区B的初始图形层的制程需要形成刻蚀位于切割区B的初始图形层的刻蚀掩膜，通过去除位于切割区B的牺牲核心层140b，有利于减小所述刻蚀掩膜的图形复杂度，从而增大形成所述刻蚀掩膜的工艺窗口（例如：缓解光刻解析度的限制）。而且，单个核心层140组成牺牲核心层140b，去除位于切割区B的牺牲核心层140a对剩余核心层140之间间距的影响小，在形成掩膜侧墙时，掩膜侧墙之间的间距一致性受到的影响小，有利于缓解在以掩膜侧墙为掩膜图形化目标层100的过程中，因图形密度一致性差异而导致刻蚀速率差异的问题，相应有利于保证初始图形层的关键尺寸、剖面形貌以及侧壁垂直度能够满足设计要求。此外，核心层140的高宽比较小，去除单个核心层140的难度较小。
    [0053] 本实施例中，去除位于切割区B的牺牲核心层140b的步骤包括：如图13和图14所示，在核心层140上形成第一图形层143，第一图形层143中具有位于切割区B的牺牲核心层140b上方的第一开口41；如图15所示，以第一图形层143为掩膜，沿第一开口41，刻蚀牺牲核心层140b；去除第一图形层143。
    [0054] 本实施例中，第一图形层143为光刻胶层。本实施例中，在形成第一图形层143之前，还在基底200上形成覆盖核心层140的第一平坦层141、以及位于平坦层141上的第一抗反射层142。需要说明的是，为方便示意和说明，本实施例仅在图14中示意出所述第一平坦层141和第一抗反射层142。
    [0055] 在其他实施例中，形成掩膜侧墙的步骤中，牺牲核心层和位于牺牲核心层侧壁上的掩膜侧墙组成牺牲图形层；形成掩膜侧墙之后，图形化目标层之前，去除位于切割区的牺牲图形层。具体地，去除位于切割区的牺牲图形层可以包括：在形成掩膜侧墙之后，去除核心层之前，去除位于切割区的牺牲图形层。
    [0056] 在去除位于切割区的牺牲图形层的过程中，需要形成用于作为刻蚀掩膜的图形层，图形层通过光刻工艺形成，光刻工艺通常需要进行校准的过程，在形成掩膜侧墙后，基底上形成有两种膜层：核心层和掩膜侧墙，通过在形成掩膜侧墙后且在去除核心层之前，去除位于切割区的牺牲图形层，有利于提高基底上图形的对比度（Contrast），从而为光刻工艺的校准提供更为清晰的对准标记（Alignment Mark），相应有利于提高光刻工艺的校准清晰度和准确度。
    [0057] 在另一些实施例中，去除位于切割区的牺牲图形层还可以包括：在去除核心层后，图形化目标层之前，去除位于切割区的牺牲图形层中的掩膜侧墙。
    [0058] 参考图18，以掩膜侧墙150为掩膜，图形化所述目标层100，形成分立的初始图形层210，初始图形层210沿横向（如图13中x方向所示）延伸，与横向垂直的方向为纵向（如图13中y方向所示），沿纵向相邻初始图形层210之间形成有凹槽220。初始图形层210用于经后续切割（Cut）工艺，形成目标图形层。
    [0059] 本实施例中，目标图形层为鳍部，初始图形层210相应为初始鳍部。
    [0060] 本实施例中，图形化所述目标层100，以形成衬底230和分立于衬底230上的初始鳍部。凹槽220由相邻的初始鳍部与衬底230围成。
    [0061] 本实施例中，在形成掩膜侧墙150后，图形化目标层100之前，形成方法还包括：以掩膜侧墙150为掩膜，图形化硬掩膜材料层120，形成硬掩膜层240。
    [0062] 硬掩膜层240能够在后续制程中对初始图形层210起到保护的作用。具体地，后续制程还包括在凹槽220中填充间隔层，形成间隔层包括进行平坦化工艺的过程，硬掩膜层240能够用于定义平坦化工艺的停止位置，而且，后续刻蚀位于切割区B的初始图形层210的过程中，还去除位于切割区的硬掩膜层240，暴露出切割区B的初始图形层210顶部，相应在刻蚀位于切割区B的初始图形层210的步骤中，间隔层和剩余的硬掩膜层240能够作为切割区B的初始图形层210的掩膜，从而对位于目标区A的初始图形层210起到保护的作用，降低对目标区A的初始图形层210造成误刻蚀的概率。
    [0063] 参考图19至图20，示出了俯视图，形成边界定义槽250，贯穿沿横向位于目标区A与切割区B的交界位置处的初始图形层210。
    [0064] 边界定义槽250用于定义目标区A的边界，从而使初始图形层210沿横向在目标区A和切割区B的边界位置处断开，之后形成填充于凹槽220和边界定义槽250的间隔层，从而使沿所述横向初始图形层210在目标区A和切割区B的交界位置处被间隔层间隔开，沿纵向相邻的初始图形层210也被间隔层间隔开，在刻蚀位于切割区B的初始图形层210的过程中，间隔层能够定义沿横向和纵向的刻蚀停止位置，有利于增大形成目标图形层的工艺窗口、降低形成目标图形层的工艺难度，且能够对目标图形层的关键尺寸和图形进行精确控制，进而提高目标图形层的剖面形貌质量和侧壁形貌质量。
    [0065] 本实施例中，边界定义槽250还贯穿沿横向位于目标区A和切割区B交界位置处的硬掩膜层240。沿横向，边界定义槽250的开口宽度不宜过小，否则容易增加刻蚀初始图形层210以形成边界定义槽250的工艺难度，而且还难以控制目标区A的剩余初始图形层210的侧壁垂直度；沿横向边界定义槽250的开口宽度也不宜过大，否则容易导致不同类型图案的初始图形层210的刻蚀速率不一致，进而难以对目标区A的剩余初始图形层210进行精确控制。因此，在实际工艺中，需根据实际工艺需求，合理设定边界定义槽250的开口宽度。
    [0066] 本实施例中，形成边界定义槽250的步骤包括：如图19所示，形成覆盖初始图形层210的边界定义掩膜层245，边界定义掩膜层245中形成沿横向位于目标区A和切割区B交界位置处的边界定义开口51；如图20所示，以边界定义掩膜层245为掩膜，沿边界定义开口51，刻蚀初始图形层210，形成边界定义槽250；去除边界定义掩膜层245。
    [0067] 本实施例中，边界定义掩膜层245位于硬掩膜层240上。因此，边界定义开口51暴露出硬掩膜层240。相应地，沿边界定义开口51，依次刻蚀硬掩膜层240和初始图形层210。本实施例中，沿纵向，边界定义开口51的边界可以位于初始图形层210之间。
    [0068] 本实施例中，沿边界定义开口51，刻蚀初始图形层210的工艺包括各向异性的干法刻蚀工艺。各向异性的干法刻蚀工艺具有各向异性刻蚀的特性，有利于提高刻蚀的剖面控制性和刻蚀精准度，相应有利于对边界定义开口51的剖面形貌、侧壁垂直度以及开口宽度进行精确控制。
    [0069] 本实施例中，为便于示意和说明，在图19和图20中用虚线框示意出了目标区A的形状和位置。除目标区A之外的区域为切割区B。
    [0070] 参考图21，形成填充于凹槽220和边界定义槽250的间隔层260。
    [0071] 间隔层260填充于凹槽220和边界定义槽250，从而使初始图形层210沿横向在目标区A和切割区B的交界位置处被间隔层260间隔开，沿纵向相邻的初始图形层210也被间隔层260间隔开，在刻蚀位于切割区B的初始图形层210的过程中，间隔层260能够定义沿横向和纵向的刻蚀停止位置。
    [0072] 本实施例中，间隔层260覆盖硬掩膜层240的侧壁。
    [0073] 本实施例中，间隔层260的材料为介质材料。本实施例中，目标图形层为鳍部，通过选用介质材料作为间隔层260的材料，从而在后续刻蚀位于切割区B的初始鳍部后，还能够对间隔层260进行平坦化处理以及刻蚀处理，使剩余的间隔层260用于形成隔离结构，以隔离相邻鳍部，从而能够将形成间隔层260与鳍切工艺以及形成隔离结构的工艺相整合，提高了工艺整合度和工艺兼容性，还能够简化工艺流程、提高生产制造效率。具体地，间隔层260的材料包括氧化硅、氮氧化硅、氮化硅、碳化硅、碳氧化硅和碳氮氧化硅中的一种或多种。作为示例，间隔层260的材料为氧化硅。
    [0074] 其他实施例中，后续还能够去除间隔层，相应有利于提高间隔层材料的选择灵活度，例如：间隔层的材料可以不选用介质材料，间隔层的材料可以包括旋涂碳（Spin-On Carbon，SOC）、无定形碳、有机介电层（Organic Dielectric layer，ODL）、含硅抗反射层（Silicon-Anti-reflective Coating，Si-ARC）、深紫外光吸收氧化层（Deep UV light absorbing Oxide，DUO）、介电抗反射涂层（Dielectric Anti-reflective Coating，DARC）或先进图膜（Advanced Patterning Film，APF）。间隔层的材料为易于被去除的材料，有利于降低后续去除间隔层的难度。
    [0075] 本实施例中，形成间隔层260的步骤包括：形成填充于凹槽220和边界定义槽250且覆盖硬掩膜层240的间隔材料层（图未示）；以硬掩膜层240的顶部为停止位置，平坦化间隔材料层，剩余的间隔材料层用于作为间隔层260。
    [0076] 本实施例中，形成间隔材料层的工艺包括流动式化学气相沉积（FCVD）工艺、原子层沉积（ALD）工艺和旋涂（Spin-On）工艺中的一种或几种。形成间隔材料层的工艺为间隙填充能力较高的工艺，有利于提高间隔材料层在凹槽220和边界定义槽250中的填充能力，相应提高间隔材料层的形成质量。作为一种示例，采用流动式化学气相沉积工艺，形成间隔材料层。
    [0077] 本实施例中，平坦化间隔材料层的工艺包括化学机械研磨工艺。化学机械研磨工艺是一种全局平坦化技术，有利于提高间隔层260的顶面平坦度，还有利于提高平坦化间隔材料层的效率。
    [0078] 结合参考图21至图24，以位于边界定义槽250中的间隔层260和位于凹槽220中的间隔层260，分别对应为沿横向和纵向的停止层，刻蚀位于切割区B的初始图形层210，位于目标区A的剩余初始图形层210用于作为目标图形层300（如图24所示）。本实施例中，刻蚀位于切割区B的初始图形层210的步骤中，在间隔层260中形成切割槽30。
    [0079] 本实施例能够以位于边界定义槽250中的间隔层和位于凹槽220中的间隔层260，分别对应为沿横向和纵向的停止层，相应能够实现在沿横向和纵向上的刻蚀自对准（Self-Aligned），从而增大刻蚀位于切割区B的初始图形层210的工艺窗口、降低形成目标图形层300的工艺难度，且能够对目标图形层300的关键尺寸和图形进行精确控制，进而提高目标图形层300的剖面形貌质量和侧壁形貌质量。本实施例中，目标图形层300为鳍部，鳍部的剖面形貌质量、侧壁形貌质量较高，且鳍部的关键尺寸得到了精确控制，有利于提高FinFET器件的性能。
    [0080] 本实施例中，刻蚀位于切割区B的初始鳍部，形成位于切割区B的残留伪鳍部320。通过形成残留伪鳍部320，后续在衬底230上形成覆盖鳍部部分侧壁的隔离结构的过程中，残留伪鳍部320位于相邻鳍部之间，能够起到分散应力的作用，从而有利于改善由于各鳍部受到的应力不同而导致鳍部发生弯曲或倾斜的概率。
    [0081] 残留伪鳍部320的高度不宜过小，否则容易降低残留伪鳍部320分散应力的效果；残留伪鳍部320的高度也不宜过大，否则容易导致在后续形成隔离结构后，隔离结构顶面与残留伪鳍部320之间的距离过小，容易增加产生漏电流的风险。为此，本实施例中，残留伪鳍部320的高度小于或等于鳍部高度的20%。作为一种示例，残留伪鳍部320的高度小于或等于200Å。
    [0082] 本实施例中，刻蚀位于切割区B的初始图形层210包括以下步骤。
    [0083] 如图21和图22所示，图21为俯视图，图22为图21在cc位置处的剖面图，在间隔层260上形成第二图形层263，第二图形层263中具有位于切割区B的第二开口61。第二图形层263覆盖目标区A的初始图形层210，第二图形层263中具有位于切割区B的第二开口61，用于作为刻蚀初始图形层210的掩膜。
    [0084] 本实施例中，第二图形层263为光刻胶层，第二图形层263通过曝光、显影等光刻工艺形成。本实施例中，由于沿纵向相邻初始图形层210之间被间隔层260间隔，沿横向目标区A和切割区B的初始图形层210之间被间隔层260间隔，因此，沿纵向第二开口61的边缘可以位于相邻两个初始图形层210之间，沿横向，第二开口61的边缘可以位于边界定义槽250中的间隔层260上，从而有利于增大形成第二开口61时的套刻偏移（Overlay Shift）容忍度，进而有利于提高形成第二图形层263的工艺窗口。本实施例中，形成第二图形层263之前，形成方法还包括：在间隔层260上形成第二平坦层261和第二抗反射层262。
    [0085] 如图23和图24所示，图23为基于图21的局部放大图，图24为图23在cc位置处的剖面图，以第二图形层263为掩膜，刻蚀第二开口61下方的初始图形层210。本实施例中，由于沿横向和纵向，间隔层260都能够作为停止层，以定义刻蚀切割区B的初始图形层210的停止位置，从而有利于降低刻蚀初始图形层210的难度、提高刻蚀初始图形层210的工艺选择灵活度，例如：刻蚀初始图形层210的工艺对初始图形层210和间隔层260具有较高的刻蚀选择比。
    [0086] 本实施例中，刻蚀位于切割区B的初始图形层210的步骤中，初始图形层210和间隔层260之间的刻蚀选择比至少为4:1，初始图形层210和间隔层260之间的刻蚀选择比较大，能够进一步提高间隔层260定义刻蚀停止位置的效果。
    [0087] 本实施例中，刻蚀位于切割区B的初始图形层210的工艺包括各向同性的刻蚀工艺。各向同性的刻蚀工艺能够降低对其他膜层的损伤。
    [0088] 作为一种示例，刻蚀位于切割区B的初始图形层210的工艺包括湿法刻蚀工艺或远程等离子体（Remote Plasma）刻蚀工艺。其中，湿法刻蚀工艺易于实现各向同性的刻蚀，且湿法刻蚀工艺操作简单、成本低，湿法刻蚀工艺还能够实现较大的刻蚀选择比。远程等离子体蚀刻工艺具有各向同性的刻蚀特性，而且，远程等离子体刻蚀工艺也具有较高的刻蚀选择性，在刻蚀的过程中，有利于减小对其他膜层的损耗。其中，远程等离子体蚀刻工艺的原理是在刻蚀腔室外部形成等离子体（例如：通过远程等离子体发生器产生等离子体），然后引入刻蚀腔室中并利用等离子体与被刻蚀层的化学反应进行蚀刻，因而可以实现各向同性的刻蚀效果，且因为没有离子轰击，因而不会损伤其他膜层。在其他实施例中，还能够采用其他合适的刻蚀工艺刻蚀位于切割区的初始图形层，例如：电感耦合等离子体（ICP）刻蚀或电容耦合等离子体（CCP）刻蚀等刻蚀工艺。
    [0089] 本实施例中，形成间隔层260之后，刻蚀位于切割区B的初始图形层210之前，形成方法还包括：去除位于切割区B的硬掩膜层240，暴露出切割区B的初始图形层210顶部，以便于通过暴露出的初始图形层210顶部，对切割区B的初始图形层210进行刻蚀。
    [0090] 本实施例中，目标图形层300为鳍部；在刻蚀位于切割区B的初始图形层210之后，半导体结构的形成方法还包括以下步骤。
    [0091] 参考图25至图27，在所述切割槽30中形成填充隔离层270。
    [0092] 通过形成填充隔离层270，为后续去除部分厚度的填充隔离层270和间隔层260以形成隔离结构做准备。本实施例中，填充隔离层270的材料与所述间隔层260的材料相同，从而有利于提高工艺兼容性。
    [0093] 本实施例中，形成填充隔离层270的步骤包括：如图25所示，形成填充于切割槽30且覆盖于间隔层260和硬掩膜层240上的填充隔离材料层265；如图26和图27所示，图26为俯视图，图27为图26在cc位置处的剖面图，以所述鳍部的顶部为停止位置，平坦化填充隔离材料层265和间隔层260。
    [0094] 本实施例中，采用间隙填充能力强的工艺形成填充隔离材料层265，从而提高填充隔离材料层265在切割槽30中的填充质量。具体地，形成填充隔离层270的工艺包括流动式化学气相沉积工艺和原子层沉积工艺中的一种或两种。
    [0095] 本实施例中，平坦化填充隔离材料层265和间隔层260的工艺包括化学机械研磨工艺。
    [0096] 参考图28，去除部分厚度的填充隔离层270和间隔层260，暴露出鳍部的部分侧壁，剩余填充隔离层270和间隔层260用于作为隔离结构330。隔离结构330用于隔离相邻鳍部。隔离结构330覆盖残留伪鳍部320。
    [0097] 本实施例将鳍切（Fin Cut）工艺与形成隔离结构330的工艺相整合，有利于提高工艺整合度和工艺兼容性，还有利于简化工艺流程、提高生产制造效率。需要说明的是，本实施例以保留部分的间隔层260以形成隔离结构330作为一种示例。其他实施例中，在刻蚀位于切割区的初始图形层之后，形成方法还可以包括：去除间隔层。
    [0098] 相应的，本发明还提供一种半导体结构。图26和图27示出了本发明半导体结构一实施例的结构示意图。其中，图26为俯视图，图27为图26在cc位置处的剖面图。
    [0099] 所述半导体结构包括：基底200，包括目标区A和切割区B，基底200包括分立于目标区A的目标图形层300，目标图形层300沿横向（如图26中x方向所示）延伸，与所述横向垂直的方向为纵向（如图26中y方向所示）；切割槽30（如图23和图24所示），位于所述切割区B的基底200上，切割槽30沿横向延伸，切割槽30沿横向与目标图形层300相连，或切割槽30与目标图形层300平行间隔排列；边界定义槽250（如图20所示），沿横向位于切割槽250与目标图形层300之间；间隔层260，填充于相邻目标图形层300之间、相邻切割槽30的侧壁之间、以及切割槽30的侧壁与目标图形层300之间，间隔层260填充边界定义槽250。切割槽30通过在刻蚀位于切割区B的初始图形层形成，剩余位于目标区A的初始图形层用于作为目标图形层300。
    [0100] 本实施例通过设置边界定义槽250，边界定义槽250用于定义目标区A的边界，从而使初始图形层沿横向在目标区A和切割区B的边界位置处断开，相应使间隔层260填充于相邻目标图形层300之间、相邻切割槽30的侧壁之间、以及切割槽30的侧壁与目标图形层300之间，沿横向间隔层260将初始图形层在目标区A和切割区B的交界位置处间隔开，沿纵向间隔层260相邻的初始图形层间隔开，在刻蚀位于切割区B的初始图形层形成切割槽30的过程中，间隔层260能够定义沿横向和纵向的刻蚀停止位置，从而能够以位于边界定义槽250中的间隔层260和沿纵向位于相邻初始图形层之间的间隔层260，分别对应为沿横向和纵向的停止层，相应能够实现在沿横向和纵向上的刻蚀自对准（Self-Aligned），有利于增大形成目标图形层300的工艺窗口、降低形成目标图形层300的工艺难度，且能够对目标图形层300的关键尺寸和图形进行精确控制，进而提高目标图形层300的剖面形貌质量和侧壁形貌质量。
    [0101] 基底200为工艺制程提供平台。目标区A为目标图形层300所在的区域，基底200上除目标区A之外的区域为切割区B。本实施例中，目标图形层300为鳍部。鳍部用于形成鳍式场效应晶体管。相应地，本实施例中，目标区A为有源区，切割区B为隔离区。
    [0102] 本实施例中，目标图形层300为鳍部，因此，鳍部的剖面形貌质量、侧壁形貌质量较高，且鳍部的关键尺寸得到精确控制，有利于提高FinFET器件的性能。
    [0103] 本实施例中，基底200还包括位于鳍部底部的衬底230。鳍部相应凸出于衬底230。本实施例中，鳍部和衬底230的材料为硅。
    [0104] 在其他实施例中，目标图形层还可以为栅极结构、全包围栅极（GAA）晶体管中的沟道叠层、图形传递层或介质隔层等图形层。其中，图形传递层可以为硬掩膜层等膜层结构，介质隔层可以为用于隔离后段金属互连线的介质层。
    [0105] 切割槽30与初始图形层的切割（Cut）位置相对应。切割槽30通过刻蚀位于切割区B的初始图形层形成。因此，切割槽30与目标图形层300的延伸方向相同。
    [0106] 本实施例中，半导体结构还包括：残留伪鳍部320，位于切割槽30的底部。残留伪鳍部320保留于半导体结构中，是由于在刻蚀位于切割区B的初始鳍部时，还保留部分的初始鳍部作为残留伪鳍部320。
    [0107] 通过设置残留伪鳍部320，后续在衬底230上形成覆盖鳍部部分侧壁的隔离结构的过程中，残留伪鳍部320位于相邻鳍部之间，能够起到分散应力的作用，从而有利于改善由于各鳍部受到的应力不同而导致鳍部发生弯曲或倾斜的概率。本实施例中，残留伪鳍部320的高度小于或等于鳍部高度的20%。作为一种示例，残留伪鳍部320的高度小于或等于200Å。
    [0108] 边界定义槽250用于定义目标区A的边界，从而使初始图形层210沿横向在目标区A和切割区B的边界位置处断开，间隔层260填充边界定义槽250，从而使间隔层260将初始图形层沿横向在目标区A和切割区B的交界位置处间隔开，在刻蚀位于切割区B的初始图形层以形成切割槽30的过程中，位于边界定义槽250中的间隔层260能够定义沿横向的刻蚀停止位置，能够对目标图形层300的关键尺寸和图形进行精确控制，进而提高目标图形层300的剖面形貌质量和侧壁形貌质量，增大了形成目标图形层300的工艺窗口。
    [0109] 间隔层260将初始图形层沿横向在目标区A和切割区B的交界位置处隔开，将沿纵向相邻的初始图形层间隔开，在刻蚀位于切割区B的初始图形层以形成切割槽30的过程中，间隔层260能够定义沿横向和纵向的刻蚀停止位置。
    [0110] 本实施例中，目标图形层300为鳍部；间隔层260的材料为介质材料。本实施例中，目标图形层300为鳍部，通过选用介质材料作为间隔层260的材料，从而在后续能够对间隔层260进行刻蚀处理，使剩余的间隔层260用于形成隔离结构，以隔离相邻鳍部，进而能够将形成间隔层260与刻蚀位于切割区B的初始鳍部以及形成隔离结构的工艺相整合，提高了工艺整合度和工艺兼容性，还能够简化工艺。
    [0111] 所述间隔层260的材料包括氧化硅、氮氧化硅、氮化硅、碳化硅、碳氧化硅和碳氮氧化硅中的一种或多种。作为一种示例，间隔层260的材料为氧化硅。
    [0112] 在其他实施例中，后续还去除间隔层，有利于提高间隔层材料的选择灵活度，例如：间隔层的材料可以不选用介质材料，间隔层的材料可以包括旋涂碳、无定形碳、有机介电层、含硅抗反射层、深紫外光吸收氧化层、介电抗反射涂层或先进图膜。间隔层的材料为易于被去除的材料，有利于降低去除间隔层的难度。
    [0113] 本实施例中，所述半导体结构还包括：填充隔离层270，填充于切割槽30内。后续去除部分厚度的填充隔离层270和间隔层260，形成隔离结构。隔离结构用于隔离相邻鳍部，从而将鳍切工艺与形成隔离结构的工艺相整合，有利于提高工艺整合度和兼容性，还有利于简化工艺流程、提高生产制造效率。
    [0114] 本实施例中，填充隔离层270的材料与间隔层260的材料相同，从而有利于提高工艺兼容性。
    [0115] 所述半导体结构可以采用前述实施例所述的形成方法所形成，也可以采用其他形成方法所形成。对本实施例所述半导体结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
    [0116] 虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。
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