WO2021143718A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示面板 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路、显示面板 Download PDF

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Publication number
WO2021143718A1
WO2021143718A1 PCT/CN2021/071452 CN2021071452W WO2021143718A1 WO 2021143718 A1 WO2021143718 A1 WO 2021143718A1 CN 2021071452 W CN2021071452 W CN 2021071452W WO 2021143718 A1 WO2021143718 A1 WO 2021143718A1
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Prior art keywords
terminal
signal
node
circuit
shift register
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PCT/CN2021/071452
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English (en)
French (fr)
Inventor
胡谦
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/425,431 priority Critical patent/US11488540B2/en
Publication of WO2021143718A1 publication Critical patent/WO2021143718A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present invention relates to the field of display technology, in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display panel.
  • Active matrix organic light-emitting diode displays generally control the light-emitting state of the pixel unit by providing a pixel drive circuit.
  • the pixel drive circuit is generally provided with a drive transistor.
  • the output current of the drive transistor can be controlled by controlling the gate voltage of the drive transistor. Thereby controlling the light-emitting state of the pixel unit.
  • the electrical properties (for example, threshold voltages) of the driving transistors in each pixel driving circuit the uneven light emission of the pixel units may result.
  • the internal compensation pixel driving circuit is usually designed to avoid display abnormalities caused by the electrical difference of the driving transistors.
  • the internal compensation pixel driving circuit requires more driving signals (for example, Reset, Gate, and EM signals) to cooperate with each other.
  • a shift register unit the shift register unit includes a shift register circuit and a data processing circuit, the shift register circuit is used to output a first shift signal to a first output terminal; data processing The circuit is connected to the first output terminal and the second output terminal, and is used for outputting a second shift signal to the second output terminal according to the first shift signal of the first output terminal.
  • the data processing circuit includes an output sub-circuit and a control sub-circuit, and the output sub-circuit is connected to the first output terminal, the second output terminal, the first power terminal, and the second power terminal.
  • the first node used to transmit the signal of the first power terminal to the second output terminal according to the signal of the first output terminal, or used to transmit the signal of the second power terminal according to the signal of the first node
  • the signal is transmitted to the second output terminal
  • the control sub-circuit is connected to the first output terminal, the first clock signal terminal, and the first node, and is used to send the signal to the first output terminal and the first clock signal terminal according to the signals from the first output terminal and the first clock signal terminal.
  • the first node inputs the control signal.
  • the output sub-circuit includes a first switch unit and a second switch unit, the control terminal of the first switch unit is connected to the first output terminal, and the first terminal is connected to the first output terminal.
  • the power terminal, the second terminal is connected to the second output terminal; the control terminal of the second switch unit is connected to the first node, the first terminal is connected to the second power terminal, and the second terminal is connected to the second output terminal.
  • the control sub-circuit includes a third switch unit, a fourth switch unit, and a first capacitor.
  • the control terminal of the third switch unit is connected to the first output terminal, and the first terminal is connected to The first power terminal and the second terminal are connected to the second node;
  • the control terminal of the fourth switch unit is connected to the first clock signal terminal, the first terminal is connected to the second node, and the second terminal is connected to the first node ;
  • the first capacitor is connected between the first clock signal terminal and the second node.
  • the shift register unit is applied to a gate drive circuit of a display panel, and the first shift signal is used as the gate drive signal and the gate drive signal of the pixel drive circuit in the display panel.
  • a reset signal, and the second shift signal is used as an enable signal for a pixel driving circuit in the display panel.
  • the shift register circuit includes: an input circuit, an output circuit, a first pull-up circuit, and a second pull-up circuit.
  • the input circuit is connected to the second power terminal, the second clock signal terminal, the input signal terminal, the third node, and the fourth node, and is used to respond to the signal from the second clock signal terminal to transmit the signal from the second power terminal to the first Four nodes, and used to transmit the signal of the input signal terminal to the third node in response to the signal of the second clock signal terminal;
  • the output circuit is connected to the first power terminal, the fourth node, the third clock signal terminal, The third node and the first output terminal are used to transmit the signal from the first power terminal to the first output terminal in response to the signal from the fourth node, and to transmit the signal from the third node to the first output terminal in response to the signal from the third node.
  • the signal of the third clock signal terminal is transmitted to the first output terminal; the first pull-up circuit is connected to the second clock signal terminal, the third node, and the fourth node, and is used to respond to the signal of the third node to transfer the The signal of the second clock signal terminal is transmitted to the fourth node; the second pull-up circuit is connected to the third node, the fourth node, the first power terminal, and the third clock signal terminal, and is used to respond to the fourth node and the The signal of the third clock signal terminal transmits the signal of the first power terminal to the third node.
  • the shift register circuit further includes an isolation circuit, and the isolation circuit is connected to the second power supply terminal, the third node, and the output circuit, and is configured to respond to the second power supply terminal, the third node, and the output circuit.
  • the signal from the power supply terminal conducts the third node and the output circuit.
  • the input circuit includes a fifth switch unit and a sixth switch unit.
  • the control terminal of the fifth switch unit is connected to the second clock signal terminal, the first terminal is connected to the input signal terminal, and the second terminal is connected to the third node;
  • the control terminal of the sixth switch unit is connected to the second clock signal terminal, and the first terminal is connected to the The second power terminal, the second terminal is connected to the fourth node;
  • the isolation circuit includes a tenth switch unit, the control terminal of the tenth switch unit is connected to the second power terminal, and the first terminal is connected to the third node;
  • the output circuit includes: an eleventh switch unit, a twelfth switch unit, a second capacitor, and a third capacitor.
  • the control end of the eleventh switch unit is connected to the second end of the tenth switch unit, and the first end is connected to the The third clock signal terminal, the second terminal is connected to the first output terminal; the control terminal of the twelfth switch unit is connected to the fourth node, the first terminal is connected to the first power terminal, and the second terminal is connected to the first output terminal.
  • the first pull-up circuit includes a seventh switch unit, the control terminal of the seventh switch unit is connected to the third node, the first terminal is connected to the second clock signal terminal, and the second terminal is connected to the fourth node;
  • the second pull-up circuit includes an eighth switch unit and a ninth switch unit. The control terminal of the eighth switch unit is connected to the fourth node, the first terminal is connected to the first power supply terminal; the control terminal of the ninth switch unit is connected to the third The clock signal terminal, the first terminal is connected to the second terminal of the eighth switch unit.
  • the first clock signal terminal and the third clock signal terminal share the same signal terminal.
  • a shift register unit driving method for driving the above-mentioned shift register unit includes:
  • a data processing circuit is used to output a second shift signal to the second output terminal according to the first shift signal of the first output terminal.
  • the data processing circuit includes an output sub-circuit and a control sub-circuit, and the method further includes:
  • a control sub-circuit is used to input a control signal to the first node according to the signal of the first output terminal.
  • the output sub-circuit includes a first switch unit and a second switch unit
  • the control sub-circuit includes a third switch unit and a fourth switch unit
  • the method further includes:
  • the shift register circuit is used to output an invalid level signal to the first output terminal, and an invalid level signal is input to the first clock signal terminal;
  • the shift register circuit is used to output an invalid level signal to the first output terminal, and an effective level signal is input to the first clock signal terminal.
  • the shift register unit is applied to a gate drive circuit of a display panel, and the second shift signal is used as an enable signal of the pixel drive circuit in the display panel.
  • a gate driving circuit includes a plurality of the above-mentioned shift register units, and a plurality of the shift register units are cascaded.
  • the first output terminal of the shift register unit of the previous stage is connected to the input signal terminal of the shift register unit of the next stage.
  • the gate driving circuit is applied to a display panel
  • the first output terminal in the shift register unit of the nth stage is used to provide a reset signal to the pixel unit of the nth row in the display panel;
  • the second output terminal in the shift register unit of the nth stage is used to provide an enable signal to the pixel unit of the nth row in the display panel;
  • the first output terminal in the shift register unit of the n+1th stage is used to provide a gate driving signal to the pixel unit of the nth row in the display panel;
  • n is a positive integer greater than or equal to 1.
  • the number of stages of the shift register unit is one greater than the number of rows of pixel units in the display panel, and the first output terminal of the shift register unit of the last stage is used To provide a gate drive signal to the pixel unit of the last row.
  • a display panel including the above-mentioned gate driving circuit.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in the related art
  • FIG. 2 is a timing diagram of some nodes in the pixel driving circuit of FIG. 1;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of a shift register unit of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of the shift register unit of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of the shift register unit of the present disclosure.
  • FIG. 6 is a timing diagram of some nodes in the shift register unit of FIG. 5;
  • Figs. 7-10 are state diagrams of the shift register unit in Fig. 5 during different driving periods
  • FIG. 11 is a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another exemplary embodiment of the shift register unit of the present disclosure.
  • FIG. 13 is a timing diagram of some nodes in the shift register unit of FIG. 12;
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in the related art.
  • FIG. 2 is a timing diagram of some nodes in the pixel driving circuit of FIG. 1.
  • FIG. The pixel driving circuit includes first to seventh transistors M1-M7, a capacitor C, and a light-emitting unit OLED, wherein the first to seventh transistors M1-M7 are P-type transistors.
  • the driving method of the pixel driving circuit includes three stages: a reset stage, a compensation stage and a light-emitting stage.
  • the enable signal terminal EM is a high-level signal
  • the reset signal terminal Reset is a low-level signal
  • the gate drive signal terminal Gate is a high-level signal
  • the seventh transistor M7 is turned on
  • the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off
  • the reference voltage terminal Vref inputs a reset signal to the first node N1 and the second node N2.
  • the enable signal terminal EM is a high level signal
  • the reset signal terminal Reset is a high level signal
  • the gate drive signal terminal Gate is a low level signal
  • the transistor M5 and the sixth transistor M6 are turned off
  • the second transistor M2 and the fourth transistor M4 are turned on
  • the signal voltage of Vdata, and Vth is the threshold voltage of the third transistor M3.
  • the enable signal terminal EM is a low-level signal
  • the reset signal terminal Reset is a high-level signal
  • the gate drive signal terminal Gate is a high-level signal
  • the voltage at the first power supply terminal VDD is converted from a low level to High level
  • the first transistor M1, the seventh transistor M7, the second transistor M2, and the fourth transistor M4 are turned off
  • the fifth transistor M5 and the sixth transistor M6 are turned on
  • the light-emitting unit OLED is controlled by the output current of the third transistor M3 Glow.
  • the aforementioned reset signal terminal Reset, gate drive signal terminal Gate, and enable signal terminal EM need to provide corresponding drive signals through corresponding drive circuits and signal lines, respectively.
  • Multiple moving circuits and multiple signal lines increase the power consumption of the display panel, making the wiring layout of the display panel more complicated.
  • this exemplary embodiment first provides a shift register unit, as shown in FIG. 3, which is a schematic structural diagram of an exemplary embodiment of the shift register unit of the present disclosure.
  • the shift register unit includes a shift register circuit. 1 and the data processing circuit 2.
  • the shift register circuit 1 is used to output the first shift signal to the first output terminal OUT1;
  • the data processing circuit 2 is connected to the first output terminal OUT1 and the second output terminal OUT2 for
  • the first shift signal of the first output terminal OUT1 outputs a second shift signal to the second output terminal OUT2.
  • the second shift signal can be used as other driving signals in the pixel driving circuit, for example, EM (enable signal), Reset (reset signal). Therefore, the arrangement of the driving circuit and the signal line corresponding to the driving signal is avoided, and the driving circuit in the display panel is simplified.
  • EM encodeable signal
  • Reset reset signal
  • the shift register unit provided by this exemplary embodiment can be used in a display panel in conjunction with the pixel driving circuit in FIG. 1, and the shift register unit provided by this exemplary embodiment can also be used in conjunction with other pixel driving circuits. It is used in a display panel.
  • the transistor in FIG. 1 may be an N-type transistor, and this exemplary embodiment does not limit the pixel driving circuit.
  • the second shift signal in this exemplary embodiment can also be used as other driving signals in the pixel driving circuit.
  • the shift register circuit 1 in this exemplary embodiment may be any circuit structure capable of generating a shift signal.
  • the data processing circuit may include an output sub-circuit 21 and a control sub-circuit 22.
  • the output sub-circuit The circuit 21 is connected to the first output terminal OUT1, the second output terminal OUT2, the first power terminal VH, the second power terminal VL, and the first node N1, and is used to convert the first output terminal OUT1 according to the signal from the first output terminal OUT1.
  • the signal of a power terminal VH is transmitted to the second output terminal OUT2, or is used to transmit the signal of the second power terminal VL to the second output terminal OUT2 according to the signal of the first node N1;
  • the circuit 22 is connected to the first output terminal OUT1, the first clock signal terminal Clock1, and the first node N1, and is used for inputting to the first node N1 according to the signals of the first output terminal OUT1 and the first clock signal terminal Clock1 control signal.
  • the following exemplary embodiment provides a specific data processing circuit structure, so that the shift register unit can be used in a display panel in cooperation with the pixel driving circuit shown in FIG. 1.
  • a plurality of the shift register units are cascaded to form a gate driving circuit to provide driving signals to the pixel driving circuits of each row.
  • the output sub-circuit 21 may include a first switch unit T1 and a second switch unit T2.
  • the control terminal of the first switch unit T1 is connected to the first output terminal OUT1, the first terminal is connected to the first power terminal VH, and the second terminal is connected to the second output terminal OUT2; the control terminal of the second switch unit T2
  • the first node N1 is connected, the first terminal is connected to the second power terminal VL, and the second terminal is connected to the second output terminal OUT2.
  • the control sub-circuit 22 may include a third switch unit T3, a fourth switch unit T4, and a first capacitor C1.
  • the control terminal of the third switch unit T3 is connected to the first switch unit T3.
  • An output terminal OUT1 the first terminal is connected to the first power terminal VH, the second terminal is connected to the second node N2;
  • the control terminal of the fourth switch unit T4 is connected to the first clock signal terminal Clock1, and the first terminal is connected to the The second node N2, the second terminal is connected to the first node N1;
  • the first capacitor C1 is connected between the first clock signal terminal Clock1 and the second node N2.
  • the first to fourth switching units may be P-type transistors or N-type transistors. As shown in FIG. 5, the first to fourth switching units may be used in this exemplary embodiment. The description is made for a P-type transistor.
  • FIG. 6 it is a timing diagram of some nodes in the shift register unit of FIG. 5.
  • OUT1(n) is the timing diagram of the first output terminal of the nth stage shift register unit
  • OUT1(n+1) is the timing diagram of the first output terminal of the n+1 stage shift register unit
  • OUT2(n) is the first output terminal of the n+1 stage shift register unit.
  • Clock1 is the timing diagram of the first clock signal terminal Clock of the n-th stage shift register unit.
  • This exemplary embodiment takes the n-th stage shift register unit as an example for description, as shown in FIGS.
  • the driving method of the shift register unit includes four stages, wherein the first power terminal constantly outputs a high-level signal, and the second power terminal constantly outputs a low-level signal.
  • the first stage T1 the first output terminal OUT1 outputs a high-level signal
  • the first clock signal terminal Clock1 outputs a high-level signal.
  • the first switch unit to the fourth switch unit are all closed, and the second output The terminal OUT2 maintains the low-level signal of the previous frame.
  • the first output terminal OUT1 outputs a low-level signal
  • the first clock signal terminal Clock1 outputs a low-level signal
  • the first switch unit T1 the third switch unit T3, and the fourth switch
  • the unit T4 is turned on, the second switch unit is turned off, and the second output terminal OUT2 outputs a high-level signal.
  • the first output terminal OUT1 outputs a high-level signal
  • the first clock signal terminal Clock1 outputs a high-level signal
  • the first switch unit to the fourth switch unit are all closed, and the second output The terminal OUT2 maintains a high-level signal
  • the n+1th stage shift register unit outputs a low-level signal.
  • the fourth stage T4 the first output terminal OUT1 outputs a high-level signal
  • the first clock signal terminal Clock1 outputs a low-level signal.
  • the fourth switch unit T4 is turned on, and the first switch unit T1 and the first switch unit T1 are turned on.
  • the three switch unit T3 is turned off.
  • the second switch unit T2 Since the signal at the first clock signal terminal changes from high to low, the potential of the second node N2 changes from high to low under the bootstrap action of the first capacitor C1. Therefore, the second switch unit T2 is turned on, and the second output terminal OUT2 outputs a low-level signal.
  • the exemplary embodiment also provides a gate driving circuit, as shown in FIG. 11, which is a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure.
  • the gate driving circuit includes a plurality of the above-mentioned shift register units cascaded, wherein the first output terminal of the shift register unit of the previous stage can be connected to the input signal terminal of the shift register unit of the next stage.
  • the first output terminal OUT1 in the shift register unit of the nth stage can be connected to the reset signal terminal Reset in the pixel unit of the nth row to provide a reset signal to the pixel drive circuit; the first output terminal OUT1 in the shift register unit of the nth stage
  • the second output terminal OUT2 can be connected to the enable signal terminal EM of the pixel unit in the nth row to provide an enable signal to the pixel driving circuit;
  • the first output terminal OUT1 in the shift register unit of the n+1th stage can be connected to the The gate drive signal terminal Gate of the n rows of pixel units provides a gate drive signal to the pixel drive circuit; where n is a positive integer greater than or equal to 1.
  • the number of stages of the shift register unit is one greater than the number of rows of pixel units in the display panel, and the first output terminal of the shift register unit of the last stage is used to move to the last row.
  • the pixel unit provides a gate drive signal.
  • FIG. 12 it is a schematic structural diagram of another exemplary embodiment of the shift register unit of the present disclosure.
  • the shift register circuit includes: an input circuit 11, an output circuit 12, a first pull-up circuit 13, and a second pull-up circuit 14.
  • the input circuit 11 is connected to the second power supply terminal VL, the second clock signal terminal Clock2, the input signal terminal Gin, the third node N3, the fourth node N4, and is used to respond to the signal of the second clock signal terminal Clock2 to connect the second
  • the signal of the power supply terminal VL is transmitted to the fourth node N4 as shown, and the signal of the input signal terminal Gin is transmitted to the third node N3 in response to the signal of the second clock signal terminal Clock2;
  • the output circuit 12 is connected The first power terminal VH, the fourth node N4, the third clock signal terminal Clock3, the third node N3, and the first output terminal OUT1 are used to respond to the signal of the fourth node N4 to turn the first power terminal VH
  • the signal of the clock signal is transmitted to the first output terminal OUT1, and the signal of the third clock signal terminal Clock3 is transmitted to the first output terminal OUT1 in response to the signal of the third node N3;
  • a first pull-up circuit 13 is connected to the second clock signal terminal
  • the shift register circuit may further include an isolation circuit 15 connected to the second power supply terminal VL, the third node N3, and the output circuit 12 for responding to the The signal from the second power supply terminal VL conducts the third node N3 and the output circuit 12.
  • the input circuit 11 may include a fifth switch unit T5 and a sixth switch unit T6.
  • the control terminal of the fifth switch unit T5 is connected to the second clock signal terminal Clock2, the first terminal is connected to the input signal terminal Gin, and the second terminal is connected to the third node N3;
  • the control terminal of the sixth switch unit T6 is connected to the second clock signal terminal Clock2,
  • the first terminal is connected to the second power terminal VL, and the second terminal is connected to the fourth node N4;
  • the isolation circuit 15 may include a tenth switch unit T10, and the control terminal of the tenth switch unit T10 is connected to the second power terminal VL ,
  • the first end is connected to the third node N3;
  • the output circuit 12 may include an eleventh switch unit T11, a twelfth switch unit T12, a second capacitor C2, a third capacitor C3, and the eleventh switch unit T11
  • the control terminal is connected to the second terminal of the tenth switch unit T10, the first terminal is connected
  • the first pull-up circuit 13 may include a seventh switch unit T7, a seventh switch unit The control terminal of T7 is connected to the third node N3, the first terminal is connected to the second clock signal terminal Clock2, and the second terminal is connected to the fourth node N4;
  • the second pull-up circuit 14 may include an eighth switch unit T8, the ninth switch unit T9, the control terminal of the eighth switch unit T8 is connected to the fourth node N4, the first terminal is connected to the first power terminal VH; the control terminal of the ninth switch unit T9 is connected to the third clock signal terminal Clock3, the first terminal is connected to the second terminal of the eighth switch unit T8.
  • the tenth switch unit T10 is used to isolate the first output terminal OUT1 and the input signal terminal Gin, and is used to reduce the influence of the voltage change of the first output terminal OUT1 on the voltage of the input signal terminal Gin.
  • the fifth switch unit to the twelfth switch unit may be P-type transistors or N-type transistors. As shown in FIG. 5, the fifth switch unit to the twelfth switch unit are used in this exemplary embodiment.
  • the cell can be a P-type transistor for illustration.
  • FIG. 13 it is a timing diagram of some nodes in the shift register unit of FIG. 12. As shown in Figs. 14-17, it is a state diagram of the shift register unit in Fig. 12 during different driving periods.
  • the driving method of the shift register unit includes four stages, wherein the first power terminal constantly outputs a high-level signal, and the second power terminal constantly outputs a low-level signal.
  • the input signal terminal Gin inputs a low level signal
  • the first clock signal terminal Clock1 outputs a high level signal
  • the second clock signal terminal Clock2 inputs a low level signal
  • the third clock signal terminal Clock3 outputs a high level Signals
  • the fifth switch unit T5, the sixth switch unit T6, the seventh switch unit T7, the eighth switch unit T8, the tenth switch unit T10, the eleventh switch unit T11, and the twelfth switch unit T12 is turned on
  • the ninth switch unit is turned off
  • the first output terminal OUT1 outputs a high-level signal.
  • the first switch unit to the fourth switch unit are all turned off, and the second output terminal OUT2 maintains the low level signal of the previous frame.
  • the input signal terminal Gin inputs a high level signal
  • the first clock signal terminal Clock1 outputs a low level signal
  • the second clock signal terminal Clock2 inputs a high level signal
  • the third clock signal terminal Clock3 outputs a low level signal.
  • the fifth switch unit T5, the sixth switch unit T6, the eighth switch unit T8, and the twelfth switch unit T12 are turned off, and the seventh switch unit T7, the ninth switch unit T9, and the tenth switch unit T10 are turned off.
  • the eleventh switch unit T11 is turned on, the first output terminal OUT1 outputs a low-level signal, the first switch unit T1, the third switch unit T3, and the fourth switch unit T4 are turned on, the second switch unit is turned off, and the second switch unit is turned off.
  • the output terminal OUT2 outputs a high-level signal.
  • the third stage T3 the input signal terminal Gin inputs a high level signal, the first clock signal terminal Clock1 outputs a high level signal, the second clock signal terminal Clock2 inputs a low level signal, and the third clock signal terminal Clock3 outputs a high level Signal. As shown in FIG.
  • the fifth switch unit T5, the sixth switch unit T6, the eighth switch unit T8, the twelfth switch unit T12, and the tenth switch unit T10 are turned on, and the seventh switch unit T7 and the ninth switch unit T9 are turned on.
  • the eleventh switch unit T11 is turned off, and the first output terminal OUT1 outputs a high-level signal.
  • the first switch unit to the fourth switch unit are all turned off, and the second output terminal OUT2 maintains a high-level signal.
  • the fourth stage T4 the input signal terminal Gin inputs a high level signal
  • the first clock signal terminal Clock1 outputs a low level signal
  • the second clock signal terminal Clock2 inputs a high level signal
  • the third clock signal terminal Clock3 outputs a low level signal.
  • the fifth switch unit T5, the sixth switch unit T6, the seventh switch unit T7, and the eleventh switch unit T11 are turned off, and the eighth switch unit T8, the ninth switch unit T9, and the tenth switch unit T10 are turned off.
  • the twelfth switch unit T12 is turned on, the first output terminal OUT1 outputs a high level signal, the fourth switch unit T4 is turned on, the first switch unit T1 and the third switch unit T3 are turned off, due to the signal at the first clock signal terminal From high level to low level, under the bootstrap action of the first capacitor C1, the potential of the second node N2 changes from high level to low level, so that the second switch unit T2 is turned on, and the second output terminal OUT2 Output low-level signal.
  • the timings of the first clock signal terminal and the third clock signal terminal are the same. Therefore, the first clock signal terminal and the third clock signal terminal share the same signal terminal.
  • This exemplary embodiment also provides a shift register unit driving method for driving the above-mentioned shift register unit, and the method includes:
  • a data processing circuit is used to output a second shift signal to the second output terminal according to the first shift signal of the first output terminal.
  • the data processing circuit includes an output sub-circuit and a control sub-circuit, and the method further includes:
  • a control sub-circuit is used to input a control signal to the first node according to the signal of the first output terminal.
  • the output sub-circuit includes a first switch unit and a second switch unit
  • the control sub-circuit includes a third switch unit and a fourth switch unit
  • the method further includes:
  • the shift register circuit is used to output an invalid level signal to the first output terminal, and an invalid level signal is input to the first clock signal terminal;
  • the shift register circuit is used to output an invalid level signal to the first output terminal, and an effective level signal is input to the first clock signal terminal.
  • the shift register unit is applied to a gate drive circuit of a display panel, and the second shift signal is used as an enable signal of a pixel drive circuit in the display panel.
  • This exemplary embodiment also provides a display panel including the above-mentioned gate driving circuit.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路、显示面板，移位寄存器单元包括移位寄存电路(1)、数据处理电路(2)。移位寄存电路(1)用于向第一输出端OUT1输出第一移位信号；数据处理电路(2)连接第一输出端OUT1和第二输出端OUT2，用于根据第一输出端OUT1的第一移位信号向第二输出端OUT2输出第二移位信号。第二移位信号能够用作像素驱动电路中的其他驱动信号，从而避免了驱动信号相应驱动电路和信号线的设置。

Description

移位寄存器单元及其驱动方法、栅极驱动电路、显示面板
相关申请的交叉引用
本申请要求于2020年01月16日递交的、名称为《移位寄存器单元及其驱动方法、栅极驱动电路、显示面板》的中国专利申请第202010048515.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法、栅极驱动电路、显示面板。
背景技术
主动式矩阵有机发光二极体显示器一般通过设置有像素驱动电路控制像素单元的发光状态，像素驱动电路中一般设置有驱动晶体管，通过控制驱动晶体管的栅极电压可以控制该驱动晶体管的输出电流，从而控制像素单元的发光状态。然而，由于每个像素驱动电路中驱动晶体管自身电性(例如，阈值电压)存在差异，从而会导致像素单元发光的不均匀。
相关技术中，通常会通过设计内部补偿像素驱动电路的方式避免驱动晶体管电性差异造成的显示异常。相关技术中，内部补偿像素驱动电路需要更多的驱动信号(例如，Reset、Gate、EM信号)相互配合。
然而，为提供上述的驱动信号(例如，Reset、Gate、EM信号)，显示面板上需要设计相应的驱动电路以及信号线。从而会增加显示面板的功耗，同时使得显示面板的布线布图更加复杂。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本发明的一个方面，提供一种移位寄存器单元，该移位寄存器单元包括移位寄存电路和数据处理电路，移位寄存电路用于向第一输出端输出第一移位信号；数据处理电路连接所述第一输出端和第二输出端，用于根据所述第一输出端的第一移位信号向所述第二输出端输出第二移位信号。
本发明的一种示例性实施例中，所述数据处理电路包括输出子电路和控制子电路，输出子电路连接所述第一输出端、第二输出端、第一电源端、第二电源端、第一节点，用于根据所述第一输出端的信号将所述第一电源端的信号传输到所述第二输出端，或用于根据所述第一节点的信号将所述第二电源端的信号传输到所述第二输出端；控制子电路连接所 述第一输出端、第一时钟信号端、第一节点，用于根据所述第一输出端和第一时钟信号端的信号向所述第一节点输入控制信号。
本发明的一种示例性实施例中，所述输出子电路包括第一开关单元和第二开关单元，第一开关单元的控制端连接所述第一输出端，第一端连接所述第一电源端，第二端连接所述第二输出端；第二开关单元的控制端连接所述第一节点，第一端连接所述第二电源端，第二端连接所述第二输出端。
本发明的一种示例性实施例中，所述控制子电路包括第三开关单元、第四开关单元、第一电容，第三开关单元的控制端连接所述第一输出端，第一端连接所述第一电源端，第二端连接第二节点；第四开关单元的控制端连接所述第一时钟信号端，第一端连接所述第二节点，第二端连接所述第一节点；第一电容连接于所述第一时钟信号端和所述第二节点之间。
本发明的一种示例性实施例中，所述移位寄存器单元应用于显示面板的栅极驱动电路，所述第一移位信号用作所述显示面板中像素驱动电路的栅极驱动信号和复位信号，所述第二移位信号用作所述显示面板中像素驱动电路的使能信号。
本发明的一种示例性实施例中，所述移位寄存电路包括：输入电路、输出电路、第一上拉电路、第二上拉电路。输入电路连接第二电源端、第二时钟信号端、输入信号端、第三节点、第四节点，用于响应所述第二时钟信号端的信号将所述第二电源端的信号传输到所示第四节点，以及用于响应所述第二时钟信号端的信号将所述输入信号端的信号传输到所述第三节点；输出电路连接所述第一电源端、第四节点、第三时钟信号端、第三节点、第一输出端，用于响应所述第四节点的信号将所述第一电源端的信号传输到所述第一输出端，以及用于响应所述第三节点的信号将所述第三时钟信号端的信号传输到所述第一输出端；第一上拉电路连接所述第二时钟信号端、第三节点、第四节点，用于响应所述第三节点的信号将所述第二时钟信号端的信号传输到所述第四节点；第二上拉电路连接第三节点、第四节点、第一电源端、第三时钟信号端，用于响应所述第四节点和所述第三时钟信号端的信号将所述第一电源端的信号传输到所述第三节点。
本发明的一种示例性实施例中，所述移位寄存电路还包括隔离电路，隔离电路连接所述第二电源端、所述第三节点、所述输出电路，用于响应所述第二电源端的信号导通所述第三节点和所述输出电路。
本发明的一种示例性实施例中，所述输入电路包括第五开关单元、第六开关单元。第五开关单元的控制端连接第二时钟信号端，第一端连接输入信号端，第二端连接第三节点；第六开关单元的控制端连接第二时钟信号端，第一端连接所述第二电源端，第二端连接第四节点；所述隔离电路包括第十开关单元，第十开关单元的控制端连接所述第二电源端，第一端连接所述第三节点；所述输出电路包括：第十一开关单元、第十二开关单元、第二电容、第三电容，第十一开关单元的控制端连接所述第十开关单元的第二端，第一端连接所述第三时钟信号端，第二端连接所述第一输出端；第十二开关单元的控制端连接所述第 四节点，第一端连接所述第一电源端，第二端连接所述第一输出端；第二电容连接于所述第十开关单元第二端和所述第一输出端之间；第三电容连接于所述第一电源端和所述第四节点之间；所述第一上拉电路包括第七开关单元，第七开关单元的控制端连接所述第三节点，第一端连接所述第二时钟信号端，第二端连接所述第四节点；所述第二上拉电路包括第八开关单元、第九开关单元，第八开关单元的控制端连接所述第四节点，第一端连接所述第一电源端；第九开关单元的控制端连接第三时钟信号端，第一端连接所述第八开关单元的第二端。
本发明的一种示例性实施例中，所述第一时钟信号端与所述第三时钟信号端共用同一信号端。
根据本发明的一个方面，提供一种移位寄存器单元驱动方法，用于驱动上述的移位寄存器单元，该方法包括：
利用移位寄存电路向第一输出端输出第一移位信号；
利用数据处理电路根据所述第一输出端的第一移位信号向所述第二输出端输出第二移位信号。
本发明的一种示例性实施例中，所述数据处理电路包括输出子电路和控制子电路，所述方法还包括：
利用输出子电路根据所述第一输出端的信号将所述第一电源端的信号传输到所述第二输出端，或根据所述第一节点的信号将所述第二电源端的信号传输到所述第二输出端；
利用控制子电路根据所述第一输出端的信号向所述第一节点输入控制信号。
本发明的一种示例性实施例中，所述输出子电路包括第一开关单元和第二开关单元，所述控制子电路包括第三开关单元和第四开关单元，所述方法还包括：
在第一阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入无效电平信号；
在第二阶段，利用所述移位寄存电路向所述第一输出端输出有效电平信号，向所述第一时钟信号端输入有效电平信号；
在第三阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入无效电平信号；
在第四阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入有效电平信号。
本发明的一种示例性实施例中，所述移位寄存器单元应用于显示面板的栅极驱动电路，所述第二移位信号用作所述显示面板中像素驱动电路的使能信号。
根据本发明的一个方面，提供一种栅极驱动电路，该栅极驱动电路包括多个上述的移位寄存器单元，多个所述移位寄存器单元级联。
本发明的一种示例性实施例中，上一级移位寄存器单元的第一输出端连接下一级移位寄存器单元的输入信号端。
本发明的一种示例性实施例中，所述栅极驱动电路应用于显示面板；
第n级所述移位寄存器单元中的第一输出端用于向所述显示面板中的第n行像素单元提供复位信号；
第n级所述移位寄存器单元中的第二输出端用于向所述显示面板中的第n行像素单元提供使能信号；
第n+1级所述移位寄存器单元中的第一输出端用于向所述显示面板中的第n行像素单元提供栅极驱动信号；
其中，n为大于等于1的正整数。
本发明的一种示例性实施例中，所述移位寄存器单元的级数比所述显示面板中像素单元的行数大1，且最后一级所述移位寄存器单元的第一输出端用于向最后一行像素单元提供栅极驱动信号。
根据本发明的一个方面，提供一种显示面板，该显示面板包括上述的栅极驱动电路。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种像素驱动电路的结构示意图；
图2为图1像素驱动电路中部分节点的时序图；
图3为本公开移位寄存器单元一种示例性实施例的结构示意图；
图4为本公开移位寄存器单元另一种示例性实施例的结构示意图；
图5为本公开移位寄存器单元另一种示例性实施例的结构示意图；
图6为图5移位寄存器单元中部分节点的时序图；
图7-10为图5中移位寄存器单元在不同驱动时段的状态图；
图11为本公开栅极驱动电路一种示例性实施例的结构示意图；
图12为本公开移位寄存器单元另一种示例性实施例的结构示意图；
图13为图12移位寄存器单元中部分节点的时序图；
图14-17为图12中移位寄存器单元在不同驱动时段的状态图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施， 且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1、2所示，图1为相关技术中一种像素驱动电路的结构示意图。图2为图1像素驱动电路中部分节点的时序图。该像素驱动电路包括第一到第七晶体管M1-M7、电容C、发光单元OLED，其中，第一到第七晶体管M1-M7为P型晶体管。该像素驱动电路驱动方法包括三个阶段：复位阶段、补偿阶段和发光阶段。如图2所示，在复位阶段T1：使能信号端EM为高电平信号，复位信号端Reset为低电平信号，栅极驱动信号端Gate为高电平信号，第一晶体管M1、第七晶体管M7导通，第二晶体管M2、第四晶体管M4、第五晶体管M5、第六晶体管M6关断，参考电压端Vref向第一节点N1和第二节点N2输入复位信号。在补偿阶段T2：使能信号端EM为高电平信号，复位信号端Reset为高电平信号，栅极驱动信号端Gate为低电平信号，第一晶体管M1、第七晶体管M7、第五晶体管M5、第六晶体管M6关断，第二晶体管M2、第四晶体管M4导通，数据信号端Vdata向第一节点输入补偿电压V，其中，补偿电压V＝Vdata+Vth，Vdata为数据信号端Vdata的信号电压，Vth为第三晶体管M3的阈值电压。在发光阶段：使能信号端EM为低电平信号，复位信号端Reset为高电平信号，栅极驱动信号端Gate为高电平信号，第一电源端VDD的电压由低电平转化为高电平，第一晶体管M1、第七晶体管M7、第二晶体管M2、第四晶体管M4关断，第五晶体管M5、第六晶体管M6导通，发光单元OLED在第三晶体管M3输出电流控制下发光。其中，第三晶体管M3输出端电流I＝w(Vgs-Vth) 2，Vg为第三晶体管M3的栅极电压，Vs为第三晶体管M3的源极电压，Vth为第三晶体管的阈值电压，w为第三晶体管M3的迁移率。则第三晶体管M3输出端电流I＝w(Vgs-Vth) 2＝w(Vdata+Vth-VDD-Vth) 2＝w(Vdata-VDD) 2。由该公式可知，发光单元OLED的发光状态与第三晶体管M3的阈值电压不相关。从而避免了显示面板发光不均匀的现象。然而，上述的复位信号端Reset、栅极驱动信号端Gate、使能信号端EM需要分别通过相应的驱动电路和信号线提供相应的驱动信号。多个动电路和多条信号线会增加显示面板的功耗，使得显示面板的布线布图更加复杂。
基于此，本示例性实施例首先提供一种移位寄存器单元，如图3所示，为本公开移位寄存器单元一种示例性实施例的结构示意图，该移位寄存器单元包括移位寄存电路1和数据处理电路2，移位寄存电路1用于向第一输出端OUT1输出第一移位信号；数据处理电路2连接所述第一输出端OUT1和第二输出端OUT2，用于根据所述第一输出端OUT1的第一移位信号向所述第二输出端OUT2输出第二移位信号。
本示例性实施例中，该第二移位信号能够用作像素驱动电路中的其他驱动信号，例如，EM(使能信号)、Reset(复位信号)。从而避免了该驱动信号相应驱动电路和信号线的设置，简化了显示面板中的驱动电路。
应该理解的是，本示例性实施例提供的移位寄存器单元可以与图1中像素驱动电路配合应用于显示面板中，本示例性实施例提供的移位寄存器单元还可以与其他像素驱动电路配合使用应用于显示面板中，例如，图1中晶体管可以为N型晶体管，本示例性实施例不对像素驱动电路进行限定。同时，本示例性实施例中的第二移位信号还可以用作像素驱动电路中的其他驱动信号。此外，本示例性实施例中的移位寄存电路1可以为能够生成移位信号的任意电路结构。
本示例性实施例中，如图4所示，为本公开移位寄存器单元另一种示例性实施例的结构示意图，所述数据处理电路可以包括输出子电路21和控制子电路22，输出子电路21连接所述第一输出端OUT1、第二输出端OUT2、第一电源端VH、第二电源端VL、第一节点N1，用于根据所述第一输出端OUT1的信号将所述第一电源端VH的信号传输到所述第二输出端OUT2，或用于根据所述第一节点N1的信号将所述第二电源端VL的信号传输到所述第二输出端OUT2；控制子电路22连接所述第一输出端OUT1、第一时钟信号端Clock1、第一节点N1，用于根据所述第一输出端OUT1和第一时钟信号端Clock1的信号向所述第一节点N1输入控制信号。
以下本示例性实施例提供一种具体的数据处理电路结构，以使该移位寄存器单元能够与图1所示出像素驱动电路配合应用于显示面板中。其中，多个该移位寄存器单元级联形成栅极驱动电路以向各行像素驱动电路提供驱动信号。
本示例性实施例中，如图5所示，为本公开移位寄存器单元另一种示例性实施例的结构示意图，所述输出子电路21可以包括第一开关单元T1和第二开关单元T2，第一开关单元T1的控制端连接所述第一输出端OUT1，第一端连接所述第一电源端VH，第二端连接所述第二输出端OUT2；第二开关单元T2的控制端连接所述第一节点N1，第一端连接所述第二电源端VL，第二端连接所述第二输出端OUT2。
本示例性实施例中，如图5所示，所述控制子电路22可以包括第三开关单元T3、第四开关单元T4、第一电容C1，第三开关单元T3的控制端连接所述第一输出端OUT1，第一端连接所述第一电源端VH，第二端连接第二节点N2；第四开关单元T4的控制端连接所述第一时钟信号端Clock1，第一端连接所述第二节点N2，第二端连接所述第一节点N1；第一电容C1连接于所述第一时钟信号端Clock1和所述第二节点N2之间。
本示例性实施例中，第一开关单元到第四开关单元可以为P型晶体管也可以为N型晶体管，如图5所示，本示例性实施例以第一开关单元到第四开关单元可以为P型晶体管进行说明。
以下对上述移位寄存器单元的驱动方法进行说明：
本示例性实施例中，如图6所示，为图5移位寄存器单元中部分节点的时序图。其中，OUT1(n)为第n级移位寄存器单元第一输出端的时序图，OUT1(n+1)为第n+1级移位寄存器单元第一输出端的时序图，OUT2(n)为第n级移位寄存器单元第二输出端的时序图，Clock1为第n级移位寄存器单元第一时钟信号端Clock的时序图。本示例性实施例以第n级移位寄存器单元为例进行说明，如图7-10所示，为图5中移位寄存器单元在不同驱动时段的状态图。该移位寄存器单元的驱动方法包括四个阶段，其中，第一电源端恒输出高电平信号，第二电源端恒输出的低电平信号。在第一阶段T1：第一输出端OUT1输出高电平信号，第一时钟信号端Clock1输出高电平信号，如图7所示，第一开关单元到第四开关单元均关闭，第二输出端OUT2保持上一帧的低电平信号。在第二阶段T2：第一输出端OUT1输出低电平信号，第一时钟信号端Clock1输出低电平信号，如图8所示，第一开关单元T1、第三开关单元T3、第四开关单元T4导通，第二开关单元关断，第二输出端OUT2输出高电平信号。在第三阶段T3：第一输出端OUT1输出高电平信号，第一时钟信号端Clock1输出高电平信号，如图9所示，第一开关单元到第四开关单元均关闭，第二输出端OUT2保持高电平信号，同时在第三阶段T3，第n+1级移位寄存器单元输出低电平信号。在第四阶段T4：第一输出端OUT1输出高电平信号，第一时钟信号端Clock1输出低电平信号，如图10所示，第四开关单元T4导通，第一开关单元T1、第三开关单元T3关断，由于第一时钟信号端的信号由高电平变为低电平，在第一电容C1自举作用下，第二节点N2的电位由高电平变为低电平，从而第二开关单元T2导通，第二输出端OUT2输出低电平信号。
本示例性实施例还提供一种栅极驱动电路，如图11所示，为本公开栅极驱动电路一种示例性实施例的结构示意图。该栅极驱动电路包括级联的多个上述移位寄存器单元，其中，上一级移位寄存器单元的第一输出端可以连接下一级移位寄存器单元的输入信号端。第n级所述移位寄存器单元中的第一输出端OUT1可以连接第n行像素单元中的复位信号端Reset，以向像素驱动电路提供复位信号；第n级所述移位寄存器单元中的第二输出端OUT2可以连接第n行像素单元的使能信号端EM，以向像素驱动电路提供使能信号；第n+1级所述移位寄存器单元中的第一输出端OUT1可以连接第n行像素单元的栅极驱动信号端Gate，以向像素驱动电路提供栅极驱动信号；其中，n为大于等于1的正整数。本示例性实施例中，所述移位寄存器单元的级数比所述显示面板中像素单元的行数大1，且最后一级所述移位寄存器单元的第一输出端用于向最后一行像素单元提供栅极驱动信号。通过将图5中的移位寄存器单元与图1中的像素驱动电路以图11的方式连接，从而能够仅仅通过移位寄存器单元向像素驱动电路同时提供使能信号、栅极驱动信号以及复位信号， 进而避免了与使能信号、复位信号相应的驱动电路和信号线的设置，简化了显示面板中的驱动电路。
本示例性实施例中，如图12所示，为本公开移位寄存器单元另一种示例性实施例的结构示意图。所述移位寄存电路包括：输入电路11、输出电路12、第一上拉电路13、第二上拉电路14。输入电路11连接第二电源端VL、第二时钟信号端Clock2、输入信号端Gin、第三节点N3、第四节点N4，用于响应所述第二时钟信号端Clock2的信号将所述第二电源端VL的信号传输到所示第四节点N4，以及用于响应所述第二时钟信号端Clock2的信号将所述输入信号端Gin的信号传输到所述第三节点N3；输出电路12连接所述第一电源端VH、第四节点N4、第三时钟信号端Clock3、第三节点N3、第一输出端OUT1，用于响应所述第四节点N4的信号将所述第一电源端VH的信号传输到所述第一输出端OUT1，以及用于响应所述第三节点N3的信号将所述第三时钟信号端Clock3的信号传输到所述第一输出端OUT1；第一上拉电路13连接所述第二时钟信号端Clock2、第三节点N3、第四节点N4，用于响应所述第三节点N3的信号将所述第二时钟信号端Clock2的信号传输到所述第四节点N4；第二上拉电路14连接第三节点N3、第四节点N4、第一电源端VH、第三时钟信号端Clock3，用于响应所述第四节点N4和所述第三时钟信号端Clock3的信号将所述第一电源端VH的信号传输到所述第三节点N3。
本示例性实施例中，所述移位寄存电路还可以包括隔离电路15，隔离电路15连接所述第二电源端VL、所述第三节点N3、所述输出电路12，用于响应所述第二电源端VL的信号导通所述第三节点N3和所述输出电路12。
本示例性实施例中，所述输入电路11可以包括第五开关单元T5、第六开关单元T6。第五开关单元T5的控制端连接第二时钟信号端Clock2，第一端连接输入信号端Gin，第二端连接第三节点N3；第六开关单元T6的控制端连接第二时钟信号端Clock2，第一端连接所述第二电源端VL，第二端连接第四节点N4；所述隔离电路15可以包括第十开关单元T10，第十开关单元T10的控制端连接所述第二电源端VL，第一端连接所述第三节点N3；所述输出电路12可以包括第十一开关单元T11、第十二开关单元T12、第二电容C2、第三电容C3，第十一开关单元T11的控制端连接所述第十开关单元T10的第二端，第一端连接所述第三时钟信号端Clock3，第二端连接所述第一输出端OUT1；第十二开关单元T12的控制端连接所述第四节点N4，第一端连接所述第一电源端VH，第二端连接所述第一输出端OUT1；第二电容C2连接于所述第十开关单元第二端和所述第一输出端OUT1之间；第三电容C3连接于所述第一电源端VH和所述第四节点N4之间；所述第一上拉电路13可以包括第七开关单元T7，第七开关单元T7的控制端连接所述第三节点N3，第一端连接所述第二时钟信号端Clock2，第二端连接所述第四节点N4；所述第二上拉电路14可以包括第八开关单元T8、第九开关单元T9，第八开关单元T8的控制端连接所述第四节点N4，第一端连接所述第一电源端VH；第九开关单元T9的控制端连接第三时钟信号端Clock3，第一端连接所述第八开关单元T8的第二端。其中，第十开关单元T10用于隔离 第一输出端OUT1和输入信号端Gin，用于降低第一输出端OUT1电压变化对输入信号端Gin电压的影响。
本示例性实施例中，第五开关单元到第十二开关单元可以为P型晶体管也可以为N型晶体管，如图5所示，本示例性实施例以第五开关单元到第十二开关单元可以为P型晶体管进行说明。
以下结合该移位寄存电路对移位寄存器单元的驱动方法进行详细说明：
如图13所示，为图12移位寄存器单元中部分节点的时序图。如图14-17所示，为图12中移位寄存器单元在不同驱动时段的状态图。该移位寄存器单元的驱动方法包括四个阶段，其中，第一电源端恒输出高电平信号，第二电源端恒输出的低电平信号。在第一阶段T1：输入信号端Gin输入低电平信号，第一时钟信号端Clock1输出高电平信号，第二时钟信号端Clock2输入低电平信号，第三时钟信号端Clock3输出高电平信号，如图14所示，第五开关单元T5、第六开关单元T6、第七开关单元T7、第八开关单元T8、第十开关单元T10、第十一开关单元T11、第十二开关单元T12导通，第九开关单元关断，第一输出端OUT1输出高电平信号。第一开关单元到第四开关单元均关闭，第二输出端OUT2保持上一帧的低电平信号。在第二阶段T2：输入信号端Gin输入高电平信号，第一时钟信号端Clock1输出低电平信号，第二时钟信号端Clock2输入高电平信号，第三时钟信号端Clock3输出低电平信号。如图15所示，第五开关单元T5、第六开关单元T6、第八开关单元T8、第十二开关单元T12关断，第七开关单元T7、第九开关单元T9、第十开关单元T10、第十一开关单元T11导通，第一输出端OUT1输出低电平信号，第一开关单元T1、第三开关单元T3、第四开关单元T4导通，第二开关单元关断，第二输出端OUT2输出高电平信号。在第三阶段T3：输入信号端Gin输入高电平信号，第一时钟信号端Clock1输出高电平信号，第二时钟信号端Clock2输入低电平信号，第三时钟信号端Clock3输出高电平信号。如图16所示，第五开关单元T5、第六开关单元T6、第八开关单元T8、第十二开关单元T12、第十开关单元T10导通，第七开关单元T7、第九开关单元T9、第十一开关单元T11关断，第一输出端OUT1输出高电平信号。第一开关单元到第四开关单元均关断，第二输出端OUT2保持高电平信号。在第四阶段T4：输入信号端Gin输入高电平信号，第一时钟信号端Clock1输出低电平信号，第二时钟信号端Clock2输入高电平信号，第三时钟信号端Clock3输出低电平信号。如图17所示，第五开关单元T5、第六开关单元T6、第七开关单元T7、第十一开关单元T11关断，第八开关单元T8、第九开关单元T9、第十开关单元T10、第十二开关单元T12导通，第一输出端OUT1输出高电平信号，第四开关单元T4导通，第一开关单元T1、第三开关单元T3关断，由于第一时钟信号端的信号由高电平变为低电平，在第一电容C1自举作用下，第二节点N2的电位由高电平变为低电平，从而第二开关单元T2导通，第二输出端OUT2输出低电平信号。
本示例性实施例中，如图13可以看出，第一时钟信号端和第三时钟信号端的时序相同，因此，所述第一时钟信号端与所述第三时钟信号端共用同一信号端。
本示例性实施例还提供一种移位寄存器单元驱动方法，用于驱动上述的移位寄存器单元，该方法包括：
利用移位寄存电路向第一输出端输出第一移位信号；
利用数据处理电路根据所述第一输出端的第一移位信号向所述第二输出端输出第二移位信号。
本示例性实施例中，所述数据处理电路包括输出子电路和控制子电路，所述方法还包括：
利用输出子电路根据所述第一输出端的信号将所述第一电源端的信号传输到所述第二输出端，或根据所述第一节点的信号将所述第二电源端的信号传输到所述第二输出端；
利用控制子电路根据所述第一输出端的信号向所述第一节点输入控制信号。
本示例性实施例中，所述输出子电路包括第一开关单元和第二开关单元，所述控制子电路包括第三开关单元和第四开关单元，所述方法还包括：
在第一阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入无效电平信号；
在第二阶段，利用所述移位寄存电路向所述第一输出端输出有效电平信号，向所述第一时钟信号端输入有效电平信号；
在第三阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入无效电平信号；
在第四阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入有效电平信号。
本示例性实施例中，所述移位寄存器单元应用于显示面板的栅极驱动电路，所述第二移位信号用作所述显示面板中像素驱动电路的使能信号。
本示例性实施例提供的移位寄存器单元驱动方法，上述内容已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种显示面板，该显示面板包括上述的栅极驱动电路。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (15)

  1. 一种移位寄存器单元，其中，包括：
    移位寄存电路，用于向第一输出端输出第一移位信号；
    数据处理电路，连接所述第一输出端和第二输出端，用于根据所述第一输出端的第一移位信号向所述第二输出端输出第二移位信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述数据处理电路包括：
    输出子电路，连接所述第一输出端、所述第二输出端、第一电源端、第二电源端、第一节点，用于根据所述第一输出端的信号将所述第一电源端的信号传输到所述第二输出端，或用于根据所述第一节点的信号将所述第二电源端的信号传输到所述第二输出端；
    控制子电路，连接所述第一输出端、第一时钟信号端、第一节点，用于根据所述第一输出端和所述第一时钟信号端的信号向所述第一节点输入控制信号。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述输出子电路包括：
    第一开关单元，控制端连接所述第一输出端，第一端连接所述第一电源端，第二端连接所述第二输出端；
    第二开关单元，控制端连接所述第一节点，第一端连接所述第二电源端，第二端连接所述第二输出端。
  4. 根据权利要求2所述的移位寄存器单元，其中，所述控制子电路包括：
    第三开关单元，控制端连接所述第一输出端，第一端连接所述第一电源端，第二端连接第二节点；
    第四开关单元，控制端连接所述第一时钟信号端，第一端连接所述第二节点，第二端连接所述第一节点；
    第一电容，连接于所述第一时钟信号端和所述第二节点之间。
  5. 根据权利要求1或2所述的移位寄存器单元，其中，所述移位寄存器单元应用于显示面板的栅极驱动电路，所述第一移位信号用作所述显示面板中像素驱动电路的栅极驱动信号和复位信号，所述第二移位信号用作所述显示面板中像素驱动电路的使能信号。
  6. 根据权利要求2所述的移位寄存器单元，其中，所述移位寄存电路包括：
    输入电路，连接第二电源端、第二时钟信号端、输入信号端、第三节点、第四节点，用于响应所述第二时钟信号端的信号将所述第二电源端的信号传输到所示第四节点，以及用于响应所述第二时钟信号端的信号将所述输入信号端的信号传输到所述第三节点；
    输出电路，连接所述第一电源端、第四节点、第三时钟信号端、第三节点、第一输出端，用于响应所述第四节点的信号将所述第一电源端的信号传输到所述第一输出端，以及用于响应所述第三节点的信号将所述第三时钟信号端的信号传输到所 述第一输出端；
    第一上拉电路，连接所述第二时钟信号端、第三节点、第四节点，用于响应所述第三节点的信号将所述第二时钟信号端的信号传输到所述第四节点；
    第二上拉电路，连接第三节点、第四节点、第一电源端、第三时钟信号端，用于响应所述第四节点和所述第三时钟信号端的信号将所述第一电源端的信号传输到所述第三节点。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述移位寄存电路还包括：
    隔离电路，连接所述第二电源端、所述第三节点、所述输出电路，用于响应所述第二电源端的信号导通所述第三节点和所述输出电路。
  8. 根据权利要求7所述的移位寄存器单元，其中，
    所述输入电路包括：
    第五开关单元，控制端连接第二时钟信号端，第一端连接输入信号端，第二端连接第三节点；
    第六开关单元，控制端连接第二时钟信号端，第一端连接所述第二电源端，第二端连接第四节点；
    所述隔离电路包括：
    第十开关单元，控制端连接所述第二电源端，第一端连接所述第三节点；
    所述输出电路包括：
    第十一开关单元，控制端连接所述第十开关单元的第二端，第一端连接所述第三时钟信号端，第二端连接所述第一输出端；
    第十二开关单元，控制端连接所述第四节点，第一端连接所述第一电源端，第二端连接所述第一输出端；
    第二电容，连接于所述第十开关单元第二端和所述第一输出端之间；
    第三电容，连接于所述第一电源端和所述第四节点之间；
    所述第一上拉电路包括：
    第七开关单元，控制端连接所述第三节点，第一端连接所述第二时钟信号端，第二端连接所述第四节点；
    所述第二上拉电路包括：
    第八开关单元，控制端连接所述第四节点，第一端连接所述第一电源端；
    第九开关单元，控制端连接第三时钟信号端，第一端连接所述第八开关单元的第二端。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第一时钟信号端与所述第三时钟信号端共用同一信号端。
  10. 一种移位寄存器单元驱动方法，用于驱动权利要求1-9任一项所述的移位寄存器单元，其中，包括：
    利用移位寄存电路向第一输出端输出第一移位信号；
    利用数据处理电路根据所述第一输出端的第一移位信号向所述第二输出端输出第二移位信号。
  11. 根据权利要求10所述的移位寄存器单元驱动方法，其中，当所述数据处理电路包括输出子电路、控制子电路时，所述控制子电路连接所述第一输出端、第一时钟信号端、第一节点，所述方法还包括：
    在第一阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入无效电平信号；
    在第二阶段，利用所述移位寄存电路向所述第一输出端输出有效电平信号，向所述第一时钟信号端输入有效电平信号；
    在第三阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入无效电平信号；
    在第四阶段，利用所述移位寄存电路向所述第一输出端输出无效电平信号，向所述第一时钟信号端输入有效电平信号。
  12. 一种栅极驱动电路，其中，包括多个权利要求1-9任一项所述的移位寄存器单元，多个所述移位寄存器单元级联；
    上一级移位寄存器单元的第一输出端连接下一级移位寄存器单元的输入信号端。
  13. 根据权利要求12所述的栅极驱动电路，其中，所述栅极驱动电路应用于显示面板；
    第n级所述移位寄存器单元中的第一输出端用于向所述显示面板中的第n行像素单元提供复位信号；
    第n级所述移位寄存器单元中的第二输出端用于向所述显示面板中的第n行像素单元提供使能信号；
    第n+1级所述移位寄存器单元中的第一输出端用于向所述显示面板中的第n行像素单元提供栅极驱动信号；
    其中，n为大于等于1的正整数。
  14. 根据权利要求13所述的栅极驱动电路，其中，所述移位寄存器单元的级数比所述显示面板中像素单元的行数大1，且最后一级所述移位寄存器单元的第一输出端用于向最后一行像素单元提供栅极驱动信号。
  15. 一种显示面板，其中，包括权利要求12-14任一项所述的栅极驱动电路。
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