WO2018126687A1 - 移位寄存器电路及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器电路及其驱动方法、栅极驱动电路及显示装置 Download PDF

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WO2018126687A1
WO2018126687A1 PCT/CN2017/096787 CN2017096787W WO2018126687A1 WO 2018126687 A1 WO2018126687 A1 WO 2018126687A1 CN 2017096787 W CN2017096787 W CN 2017096787W WO 2018126687 A1 WO2018126687 A1 WO 2018126687A1
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Prior art keywords
node
terminal
reference voltage
signal
shift register
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PCT/CN2017/096787
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English (en)
French (fr)
Inventor
陈沫
刘金良
傅武霞
李环宇
孙松梅
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/746,753 priority Critical patent/US10741132B2/en
Publication of WO2018126687A1 publication Critical patent/WO2018126687A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to a shift register circuit, a driving method thereof, a gate driving circuit, and a display device.
  • the shift register can operate as a gate drive circuit of the display device to sequentially supply gate scan signals to the respective gate lines to turn on transistors in each pixel row, thereby allowing data signals to be written to the respective pixels.
  • the high level of the gate scan signal In order to fully open each transistor, the high level of the gate scan signal generally needs to reach 25V or more. Due to the self-boosting effect of the storage capacitors in the shift register, the voltage at some internal nodes of the shift register is even higher, for example, twice as high as the high level of the gate scan signal (50V or higher) ). Such a high voltage causes a large change in the characteristics of the transistors connected to these internal nodes, resulting in a threshold voltage shift. If the display device is operated for a long time under such conditions, the shift register becomes unstable and a deteriorated gate scan signal is obtained.
  • a shift register circuit comprising: an input control circuit connected to a signal input terminal, a reference voltage terminal, and a first node, the input control circuit being configured to be responsive to the signal An effective pulse signal at the input end sets the first node at a first potential; an output control circuit is coupled to the first node, the first clock signal terminal, and the signal output terminal, the output control circuit being configured to respond Providing a clock signal from the first clock signal terminal to the signal output terminal when the first node is at the first potential, the first potential being less than a potential of the valid pulse signal, and greater than or equal to a potential for maintaining operation of the output control circuit; and a reset circuit coupled to the reset signal terminal, the reference voltage terminal, the first node, and the signal output, the reset circuit being configured to be responsive to a reset signal of the reset signal terminal to provide a reference voltage from the reference voltage terminal to the first node and the Signal output.
  • the input control circuit includes: a first transistor having a gate and a first electrode connected to the signal input, and a second electrode connected to the first node; and a second transistor, A gate connected to the signal input, a first electrode connected to the reference voltage terminal, and a second electrode connected to the first node.
  • the output control circuit includes: a third transistor having a gate connected to the first node, a first electrode connected to the first clock signal end, and a signal output connected to the signal output terminal a second electrode; and a capacitor connected between the first node and the signal output end.
  • the reset circuit includes: a fourth transistor having a gate connected to the reset signal terminal, a first electrode connected to the reference voltage terminal, and a second electrode connected to the first node And a fifth transistor having a gate connected to the reset signal terminal, a first electrode connected to the reference voltage terminal, and a second electrode connected to the signal output terminal.
  • the shift register circuit further includes a pull-down control circuit coupled to the second clock signal terminal, the reference voltage terminal, the first node, and the second node.
  • the pull-down control circuit is configured to provide the reference voltage from the reference voltage terminal to the second node in response to the first node being at the first potential, and responsive to the second node being Providing a clock signal having an effective potential from the second clock signal terminal to supply the reference voltage from the reference voltage terminal to the first node.
  • the pull-down control circuit includes: a sixth transistor having a gate and a first electrode connected to the second clock signal end, and a second electrode connected to the third node; and a seventh transistor having a gate connected to the third node, a first electrode connected to the second clock signal terminal, and a second electrode connected to the second node; an eighth transistor having a connection to the first node a gate, a first electrode connected to the reference voltage terminal, and a second electrode connected to the third node; a ninth transistor having a gate connected to the first node and connected to the reference voltage terminal a first electrode, and a second electrode connected to the second node; and a tenth transistor having a gate connected to the second node, a first electrode connected to the reference voltage terminal, and connected to the The second electrode of the first node.
  • the shift register circuit further includes a first pull down circuit coupled to the second node, the reference voltage terminal, and the signal output.
  • the first pull-down circuit is configured to provide the reference voltage from the reference voltage terminal in response to the second node being provided with the clock signal from the second clock signal terminal having the effective potential Give the signal output.
  • the first pull-down circuit includes an eleventh transistor having a gate connected to the second node, a first electrode connected to the reference voltage terminal, and a signal output connected The second electrode of the end.
  • the shift register circuit further includes a second pull-down circuit coupled to the second clock signal terminal, the reference voltage terminal, and the signal output terminal.
  • the second pull-down circuit is configured to provide the reference voltage from the reference voltage terminal to the signal output terminal in response to the second clock signal having the effective potential from the second clock signal terminal .
  • the second pull-down circuit includes a twelfth transistor having a gate connected to the second clock signal terminal, a first electrode connected to the reference voltage terminal, and a signal output connected thereto The second electrode of the end.
  • a gate drive circuit includes a plurality of cascaded shift register circuits as described above.
  • the signal output terminal of each of the shift register circuits is connected to the signal input terminal of the next stage shift register circuit and shifted by the upper stage Both reset signal terminals of the register circuit.
  • the signal output of the first stage shift register circuit is coupled to the signal input of the second stage shift register circuit.
  • the signal output terminal of the final stage shift register circuit is connected to the reset signal terminal of the shift register circuit of the previous stage.
  • a display device including the gate drive circuit as described above.
  • a method of driving a shift register circuit as described above includes, during a first time period, setting the first node at a first potential in response to the valid pulse signal from the signal input; and in response to the first The node is at the first potential to provide the clock signal from the first clock signal terminal to the signal output terminal; and in a third time period, in response to the reset signal from the reset signal terminal The reference voltage from the reference voltage terminal is provided to the first node and the signal output.
  • the method further includes providing the reference voltage from the reference voltage terminal to the first node in response to the first node being at the first potential for a first time period and a second time period a second node; and in the third time period, providing the reference voltage from the reference voltage terminal to the first in response to the second node being provided with a clock signal having an effective potential from a second clock signal terminal node.
  • the method further comprises, in a third time period, responsive to the second node being provided with the clock signal from the second clock signal terminal having the effective potential
  • the reference voltage of the reference voltage terminal is supplied to the signal output terminal, and the reference voltage from the reference voltage terminal is supplied to the second clock signal having the effective potential from the second clock signal terminal The signal output.
  • FIG. 1 is a block diagram of a shift register circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is an exemplary circuit diagram of the shift register circuit shown in FIG. 1;
  • FIG. 3 is a block diagram of a shift register circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is an exemplary circuit diagram of the shift register circuit shown in FIG. 3;
  • Figure 5 is a timing diagram of the shift register circuit shown in Figure 4.
  • FIG. 6 is a block diagram of a gate driving circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 is a block diagram of a shift register circuit 100 in accordance with an embodiment of the present disclosure.
  • the shift register 100 includes an input control circuit 110, an output control circuit 120, and a reset circuit 130.
  • the input control circuit 110 is connected to the signal input terminal IN, the reference voltage terminal VSS, and the first node N1.
  • the input control circuit 110 is configured to set the first node N1 at a first potential in response to a valid pulse signal from the signal input terminal IN.
  • An effective pulse signal as used herein refers to a signal having such a potential to enable input control circuit 110 to operate.
  • the output control circuit 120 is connected to the first node N1, the first clock signal terminal CLK1, and the signal output terminal G[N].
  • the output control circuit 120 is configured to provide a clock signal from the first clock signal terminal CLK1 to the signal output terminal G[N] in response to the first node N1 being at the first potential.
  • the first potential is less than the valid pulse signal
  • the potential of the number is greater than or equal to the potential used to maintain the output control circuit 120.
  • the reset circuit 130 is connected to the reset signal terminal RST, the reference voltage terminal VSS, the first node N1, and the signal output terminal G[N].
  • the reset circuit 130 is configured to supply a reference voltage from the reference voltage terminal VSS to the first node N1 and the signal output terminal G[N] in response to a reset signal from the reset signal terminal RST.
  • the potential of the internal node N1 is adjusted to be less than the first potential of the potential of the valid pulse signal. Therefore, the potential of the internal node N1 is lowered in operation.
  • This can be advantageous because various problems introduced due to the internal node of the shift register circuit being at a high potential can be avoided, such as the drift of the threshold voltage of the transistor connected to the internal node, the gate generated by the shift register circuit Scan signal instability and the like.
  • FIG. 2 is an exemplary circuit diagram of the shift register circuit 100 shown in FIG. 1.
  • the input control circuit 110 includes a first transistor M1 and a second transistor M2.
  • the first transistor M1 has a gate connected to the signal input terminal IN and a first electrode, and a second electrode connected to the first node N1.
  • the second transistor M2 has a gate connected to the signal input terminal IN, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the first node N1.
  • the turned-on first and second transistors M1, M2 generate a resistor divider effect such that the potential at the first node N1 is pulled low to a first potential (denoted as Vp) which is less than from the signal input IN
  • Vp first potential
  • the output control single channel 120 includes a third transistor M3 and a capacitor C.
  • the third transistor M3 has a gate connected to the first node N1, a first electrode connected to the first clock signal terminal CLK1, and a second electrode connected to the signal output terminal G[N].
  • the capacitor C is connected between the first node N1 and the signal output terminal G[N]. Since the operation of the output control circuit 120 (in this example, the third transistor M3) is controlled by the potential at the first node N1, in order to allow normal operation of the output control circuit 20, the first potential Vp should be greater than or equal to The potential Vo of the output control circuit 20 (third transistor M3) is operated, that is, Vp ⁇ Vo.
  • the third transistor M3 transmits a clock signal from the first clock signal terminal CLK1 to the signal output terminal G[N], and the capacitance C is across the first node N1. It is charged with the voltage of the signal output terminal G[N].
  • the reset circuit 130 includes a fourth transistor M4 and a fifth transistor M5.
  • the fourth transistor M4 has a gate connected to the reset signal terminal RST, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the first node N1.
  • the fifth transistor M5 has a connection A gate connected to the reset signal terminal RST, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the signal output terminal G[N].
  • the fourth transistor M4 transmits a reference voltage from the reference voltage terminal VSS to the first node N1 in response to a reset signal from the reset signal terminal RST, and the fifth transistor M5 is responsive to a reset signal from the reset signal terminal RST
  • the reference voltage from the reference voltage terminal VSS is transmitted to the signal output terminal G[N].
  • FIG. 3 is a block diagram of a shift register circuit 100A in accordance with an embodiment of the present disclosure.
  • the shift register 100A further includes a pull-down control circuit 140, a first pull-down circuit 150, and a second pull-down circuit 160, as compared with the shift register 100 shown in FIG.
  • the configurations of the input control circuit 110, the output control circuit 120, and the reset circuit 130 are similar to those described above with respect to FIG. 1, and thus are not repeated here.
  • the pull-down control circuit 140 is connected to the second clock signal terminal CLK2, the reference voltage terminal VSS, the first node N1, and the second node N2.
  • the pull-down control circuit 140 is configured to provide a reference voltage from the reference voltage terminal VSS to the second node N2 in response to the first node N1 being at the first potential Vp.
  • the pull-down control circuit 140 is also configured to provide a reference voltage from the reference voltage terminal VSS to the first node N1 in response to the second node N2 being supplied with a clock signal potential having an effective potential from the second clock signal terminal CLK2.
  • An effective potential as used herein refers to a potential that enables the pull-down control circuit 140 to operate.
  • the first pull-down circuit 150 is connected to the second node N2, the reference voltage terminal VSS, and the signal output terminal G[N].
  • the first pull-down circuit 150 is configured to provide a reference voltage from the reference voltage terminal VSS to the signal output terminal G[N] in response to the second node N2 being supplied with a clock signal having an effective potential from the second clock signal terminal CLK2. .
  • the signal output from the signal output terminal G[N] can be maintained at a stable reference voltage, thereby improving the stability of the output signal.
  • the second pull-down circuit 160 is connected to the second clock signal terminal CLK2, the reference voltage terminal VSS, and the signal output terminal G[N].
  • the second pull-down circuit 160 is configured to supply a reference voltage from the reference voltage terminal VSS to the signal output terminal G[N] in response to a second clock signal having an effective potential from the second clock signal terminal CLK2.
  • the signal output from the signal output terminal G[N] can be maintained at a stable reference voltage, thereby improving the stability of the output signal.
  • FIG. 4 is an exemplary circuit diagram of the shift register circuit 100A shown in FIG.
  • the configurations of the input control circuit 110, the output control circuit 120, and the reset circuit 130 are similar to those described above with respect to FIG. 2, and thus are not repeated here.
  • the pull-down control circuit 140 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
  • the sixth transistor M6 has a gate connected to the second clock signal terminal CLK2 and a first electrode, and a second electrode connected to the third node N3.
  • the seventh transistor M7 has a gate connected to the third node N3, a first electrode connected to the second clock signal terminal CLK2, and a second electrode connected to the second node N2.
  • the eighth transistor M8 has a gate connected to the first node N1, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the third node N3.
  • the ninth transistor M9 has a gate connected to the first node N1, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the second node N2.
  • the tenth transistor M10 has a gate connected to the second node N2, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the first node N1.
  • the sixth transistor M6 transmits a clock signal from the second clock signal terminal CLK2 to the third node N3 in response to a clock signal having an effective potential from the second clock signal terminal CLK2, the seventh transistor M7 being responsive to the The three node N3 is supplied with a clock signal having an effective potential from the second clock signal terminal CLK2 to transmit a clock signal from the second clock signal terminal CLK2 to the second node N2, and the eighth transistor M8 is in response to the first node N1.
  • a reference voltage from the reference voltage terminal VSS is transmitted to the third node N3 at a potential Vp
  • the ninth transistor M9 transmits the reference voltage from the reference voltage terminal VSS to the second node in response to the first node N1 being at the first potential Vp N2
  • the tenth transistor M10 transmits the reference voltage from the reference voltage terminal VSS to the first node N1 in response to the second node N2 being supplied with the clock signal having the effective potential from the second clock signal terminal CLK2.
  • the first pull-down circuit 150 includes an eleventh transistor M11.
  • the gate of the eleventh transistor M11 is connected to the second node N2, the first electrode is connected to the reference voltage terminal VSS, and the second electrode is connected to the signal output terminal G[N].
  • the eleventh transistor M11 supplies the reference voltage of the reference voltage terminal VSS to the signal output terminal G[N] when the second node N2 is the clock signal potential of the second clock signal terminal CLK2.
  • the second pull-down circuit 160 includes a twelfth transistor M12.
  • the twelfth transistor M12 has a gate connected to the second clock signal terminal CLK2, a first electrode connected to the reference voltage terminal VSS, and a second electrode connected to the signal output terminal G[N].
  • the twelfth transistor M12 supplies a reference voltage from the reference voltage terminal VSS to the signal output terminal G[N] in response to a clock signal having an effective potential from the second clock signal terminal CLK2.
  • FIG. 5 is a timing chart of the shift register circuit shown in FIG. Described in conjunction with Figures 4 and 5 The operation of the shift register circuit. In the following description, a high level is indicated by 1 and a low level is indicated by 0.
  • the signal input terminal IN is supplied with the effective pulse signal Vh
  • the first transistor M1 and the second transistor M2 are turned on. Due to the resistance division effect of the first transistor M1 and the second transistor M2, the potential at the first node N1 is set to the first potential Vp.
  • the first potential Vp is greater than or equal to the potential Vo for maintaining the operation of the output control circuit 20 and is less than the potential Vh of the effective pulse signal, that is, Vh > Vp ⁇ Vo. Since the first node N1 is at the first potential Vp, the ninth transistor M9 is turned on, and the reference voltage from the reference voltage terminal VSS is transferred to the second node N2.
  • the potential Vp+Vh at the first node N1 is now less than 2Vh compared to the prior art in which the potential at the internal node can be twice the output high level (eg, 2Vh). Therefore, in the shift register circuit according to an embodiment of the present disclosure, the potential at the internal node is lowered.
  • the tenth transistor M10 and the eleventh transistor M11 are then turned on, and the reference voltage from the reference voltage terminal VSS is supplied to the first node N1 and the signal output terminal G[N], respectively, to ensure that the first node N1 is at a low level and The signal output terminal G[N] outputs a low level signal.
  • the stages T1-T3 as a whole may be repeated at intervals such that the shift register circuit outputs the gate scan signal at the interval via the signal output terminal G[N].
  • each transistor is illustrated as an N-type transistor, although a P-type transistor is possible.
  • the gate-on voltage has a low level
  • the gate-off voltage has a high level.
  • each transistor may typically be a thin film transistor that is fabricated such that their first and second electrodes are used interchangeably. Other embodiments are also contemplated.
  • FIG. 6 is a block diagram of a gate drive circuit 600 in accordance with an embodiment of the present disclosure.
  • the gate driving circuit 600 includes a plurality of cascaded shift register circuits (SRC). These shift register circuits together form a shift register that operates as a gate drive circuit.
  • SRC cascaded shift register circuits
  • shift registers are shown in FIG. 6, which are the N-2th SRC, the N-1th SRC, the Nth SRC, the N+1th SRC, and the N+2th stage, respectively. SRC.
  • Each of these shift register circuits may be the shift register circuit 100 or 100A described above with reference to Figures 1-4.
  • the signal output terminal of each of the shift register circuits is connected to the signal input terminal of the next stage shift register and The reset signal terminal of the primary shift register.
  • the signal output terminal G[N] of the Nth stage shift register circuit not only inputs a valid pulse signal to the signal input terminal IN of the (N+1)th shift register circuit, but also shifts to the N-1th stage.
  • the reset signal terminal RST of the register inputs a reset signal.
  • the signal output terminal of the first stage shift register is connected to the input end of the second stage shift register, and the signal output end of the final stage shift register is connected to the reset signal end of the previous stage shift register.
  • FIG. 7 is a block diagram of a display device 700 in accordance with an embodiment of the present disclosure.
  • the display device 700 includes a display panel 710, a timing controller 720, a gate driving circuit 730, and a data driving circuit 740.
  • the gate drive circuit 730 can be the gate drive circuit 600 described above with respect to FIG.
  • the display panel 710 is connected to the plurality of gate lines GL and the plurality of data lines DL.
  • the display panel 710 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 710 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and one corresponding one of the data lines DL.
  • the display panel 710 can be a liquid crystal display surface A board, an organic light emitting diode (OLED) display panel or other suitable type of display panel.
  • OLED organic light emitting diode
  • the timing controller 720 controls the operations of the display panel 710, the gate drive circuit 730, and the data drive circuit 740.
  • the timing controller 720 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 720 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the gate drive circuit 730 receives the first control signal CONT1 from the timing controller 720.
  • the gate driving circuit 730 generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1.
  • the gate driving circuit 730 may sequentially apply a plurality of gate signals to the gate lines GL.
  • the data driving circuit 740 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 720.
  • the data driving circuit 740 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driving circuit 740 can apply a plurality of data voltages to the data lines DL.
  • gate drive circuit 730 and/or data drive circuit 740 may be disposed (eg, directly mounted) on display panel 710, or may be by, for example, a Tape Carrier Package (TCP). Connected to display panel 710. In some embodiments, gate drive circuit 730 and/or data drive circuit 740 can be integrated in display panel 710.
  • TCP Tape Carrier Package

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Abstract

一种移位寄存器电路（100，100A），包括：输入控制电路（110），被配置成响应于来自信号输入端（IN）的有效脉冲信号而将第一节点（N1）设定处于第一电位；输出控制电路（120），被配置成响应于第一节点（N1）处于第一电位而将来自第一时钟信号端（CLK1）的时钟信号提供给信号输出端（G[N]），其中第一电位小于有效脉冲信号的电位，且大于或等于用于维持输出控制电路（120）工作的电位；以及复位电路（130），被配置成响应于来自复位信号端（RST）的复位信号而将来自参考电压端（VSS）的参考电压提供给第一节点（N1）和信号输出端（G[N]）。

Description

移位寄存器电路及其驱动方法、栅极驱动电路及显示装置 技术领域
本公开涉及显示技术领域，尤指一种移位寄存器电路、其驱动方法、栅极驱动电路及显示装置。
背景技术
移位寄存器可以操作为显示装置的栅极驱动电路以便向各栅线顺序地提供栅极扫描信号以开启各像素行中的晶体管，从而允许向各像素写入数据信号。
为了能够充分打开各晶体管，栅极扫描信号的高电平一般需要达到25V以上。由于移位寄存器中的存储电容的自举作用(self-boosting effect)，移位寄存器的某些内部节点处的电压甚至会更高，例如高出栅极扫描信号的高电平一倍(50V以上)。如此高的电压导致与这些内部节点相连的晶体管的特性发生较大的变化，产生阈值电压漂移。若显示装置在此种条件下长时间工作，移位寄存器会变得不稳定，得到恶化的栅极扫描信号。
发明内容
提供一种可以缓解、减轻或消除上述问题中的一个或多个的移位寄存器电路和栅极驱动电路将是有利的。
根据本公开的一个方面，提供了一种移位寄存器电路，包括：输入控制电路，连接到信号输入端、参考电压端和第一节点，所述输入控制电路被配置成响应于来自所述信号输入端的有效脉冲信号而将所述第一节点设定处于第一电位；输出控制电路，连接到所述第一节点、第一时钟信号端和信号输出端，所述输出控制电路被配置成响应于所述第一节点处于所述第一电位而将来自所述第一时钟信号端的时钟信号提供给所述信号输出端，所述第一电位小于所述有效脉冲信号的电位，且大于或等于用于维持所述输出控制电路工作的电位；以及复位电路，连接到复位信号端、所述参考电压端、所述第一节点和所述信号输出端，所述复位电路被配置成响应于来自所述复位信号端的复位信号而将来自所述参考电压端的参考电压提供给所述第一节点和所述 信号输出端。
在一些实施例中，所述输入控制电路包括：第一晶体管，具有连接到所述信号输入端的栅极和第一电极、以及连接到所述第一节点的第二电极；以及第二晶体管，具有连接到所述信号输入端的栅极、连接到所述参考电压端的第一电极、以及连接到所述第一节点的第二电极。
在一些实施例中，所述输出控制电路包括：第三晶体管，具有连接到所述第一节点的栅极、连接到所述第一时钟信号端的第一电极、以及连接到所述信号输出端的第二电极；以及电容，连接于所述第一节点与所述信号输出端之间。
在一些实施例中，所述复位电路包括：第四晶体管，具有连接到所述复位信号端的栅极、连接到所述参考电压端的第一电极、以及连接到所述第一节点的第二电极；以及第五晶体管，具有连接到所述复位信号端的栅极、连接到所述参考电压端的第一电极、以及连接到所述信号输出端的第二电极。
在一些实施例中，所述移位寄存器电路还包括连接到第二时钟信号端、所述参考电压端、所述第一节点和第二节点的下拉控制电路。所述下拉控制电路被配置成响应于所述第一节点处于所述第一电位而将来自所述参考电压端的所述参考电压提供给所述第二节点，并且响应于所述第二节点被提供来自所述第二时钟信号端的具有有效电位的时钟信号而将来自所述参考电压端的所述参考电压提供给所述第一节点。
在一些实施例中，所述下拉控制电路包括：第六晶体管，具有连接到所述第二时钟信号端的栅极和第一电极、以及连接到第三节点的第二电极；第七晶体管，具有连接到所述第三节点的栅极、连接到所述第二时钟信号端的第一电极、以及连接到所述第二节点的第二电极；第八晶体管，具有连接到所述第一节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述第三节点的第二电极；第九晶体管，具有连接到所述第一节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述第二节点的第二电极；以及第十晶体管，具有连接到所述第二节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述第一节点的第二电极。
在一些实施例中，所述移位寄存器电路还包括连接到所述第二节点、所述参考电压端和所述信号输出端的第一下拉电路。所述第一下拉电路被配置成响应于所述第二节点被提供来自所述第二时钟信号端的具有所述有效电位的所述时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端。
在一些实施例中，所述第一下拉电路包括第十一晶体管，其具有连接到所述第二节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述信号输出端的第二电极。
在一些实施例中，所述移位寄存器电路还包括连接到所述第二时钟信号端、所述参考电压端和所述信号输出端的第二下拉电路。所述第二下拉电路被配置成响应于来自所述第二时钟信号端的具有所述有效电位的所述第二时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端。
在一些实施例中，所述第二下拉电路包括第十二晶体管，其具有连接到所述第二时钟信号端的栅极、连接到所述参考电压端的第一电极、以及连接到所述信号输出端的第二电极。
根据本公开的另一方面，提供了一种栅极驱动电路，包括级联的多个如上所述的移位寄存器电路。除首级移位寄存器电路和末级移位寄存器电路之外，所述移位寄存器电路中的每一个的信号输出端连接到下一级移位寄存器电路的信号输入端和上一级移位寄存器电路的复位信号端两者。首级移位寄存器电路的信号输出端连接到第二级移位寄存器电路的信号输入端。末级移位寄存器电路的信号输出端连接到上一级移位寄存器电路的复位信号端。
根据本公开的又另一方面，提供了一种显示装置，包括如上所述的栅极驱动电路。
根据本公开的再另一方面，提供了一种驱动如上所述的移位寄存器电路的方法。所述方法包括：在第一时间段，响应于来自所述信号输入端的所述有效脉冲信号而将所述第一节点设定处于第一电位；在第二时间段，响应于所述第一节点处于所述第一电位而将来自所述第一时钟信号端的所述时钟信号提供给所述信号输出端；以及在第三时间段，响应于来自所述复位信号端的所述复位信号而将来自所述参考电压端的所述参考电压提供给所述第一节点和所述信号输出端。
在一些实施例中，所述方法还包括：在第一时间段和第二时间段，响应于所述第一节点处于所述第一电位而将来自所述参考电压端的所述参考电压提供给第二节点；以及在第三时间段，响应于所述第二节点被提供来自第二时钟信号端的具有有效电位的时钟信号而将来自所述参考电压端的所述参考电压提供给所述第一节点。
在一些实施例中，所述方法还包括：在第三时间段，响应于所述第二节点被提供来自所述第二时钟信号端的具有所述有效电位的所述时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端，并且响应于来自所述第二时钟信号端的具有所述有效电位的第二时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1为根据本公开实施例的一种移位寄存器电路的框图；
图2为图1所示的移位寄存器电路的示例性电路图；
图3为根据本公开实施例的一种移位寄存器电路的框图；
图4为图3所示的移位寄存器电路的示例性电路图；
图5为图4所示的移位寄存器电路的时序图；
图6为根据本公开实施例的一种栅极驱动电路的框图；并且
图7为根据本公开实施例的一种显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个元件、部件或部分相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制 本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件或层。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件或层存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图对本公开的实施例进行详细地描述。
图1为根据本公开实施例的一种移位寄存器电路100的框图。参考图1，移位寄存器100包括输入控制电路110、输出控制电路120和复位电路130。
输入控制电路110连接到信号输入端IN、参考电压端VSS和第一节点N1。输入控制电路110被配置成响应于来自信号输入端IN的有效脉冲信号而将第一节点N1设定处于第一电位。如本文所使用的有效脉冲信号是指具有这样的电位以使得输入控制电路110能够工作的信号。
输出控制电路120连接到第一节点N1、第一时钟信号端CLK1和信号输出端G[N]。输出控制电路120被配置成响应于第一节点N1处于所述第一电位而将来自第一时钟信号端CLK1的时钟信号提供给信号输出端G[N]。如下面将描述的，所述第一电位小于所述有效脉冲信 号的电位，且大于或等于用于维持输出控制电路120工作的电位。
复位电路130连接到复位信号端RST、参考电压端VSS、第一节点N1和信号输出端G[N]。复位电路130被配置成响应于来自复位信号端RST的复位信号而将来自参考电压端VSS的参考电压提供给第一节点N1和信号输出端G[N]。
在该实施例中，当移位寄存器电路100在操作中时，内部节点N1的电位被调整为小于有效脉冲信号的电位的第一电位。因此，在操作中内部节点N1的电位被降低。这可以是有利的，因为可以避免由于移位寄存器电路的内部节点处于高电位而引入的各种问题，诸如与该内部节点相连的晶体管的阈值电压的漂移、该移位寄存器电路产生的栅极扫描信号的不稳定性等。
图2为图1所示的移位寄存器电路100的示例性电路图。
输入控制电路110包括第一晶体管M1和第二晶体管M2。第一晶体管M1具有连接到信号输入端IN相连的栅极和第一电极、以及连接到第一节点N1的第二电极。第二晶体管M2具有连接到信号输入端IN的栅极、连接到参考电压端VSS的第一电极、以及连接到第一节点N1的第二电极。在操作中，导通的第一和第二晶体管M1、M2产生电阻分压效应，使得第一节点N1处的电位被拉低至第一电位(记作Vp)，其小于来自信号输入端IN的有效脉冲信号的电位Vh，即，Vh＞Vp。
输出控制单路120包括第三晶体管M3和电容C。第三晶体管M3具有连接到第一节点N1的栅极、连接到第一时钟信号端CLK1的第一电极、以及连接到信号输出端G[N]的第二电极。电容C连接于第一节点N1与信号输出端G[N]之间。由于输出控制电路120(在该示例中，第三晶体管M3)的操作由第一节点N1处的电位控制，因此为了允许输出控制电路20的正常工作，第一电位Vp应当大于或等于用于维持输出控制电路20(第三晶体管M3)工作的电位Vo，即Vp≥Vo。在操作中，当第一节点N1处于第一电位Vp时，第三晶体管M3将来自第一时钟信号端CLK1的时钟信号传送至信号输出端G[N]，并且电容C由跨第一节点N1与信号输出端G[N]的电压充电。
复位电路130包括第四晶体管M4与第五晶体管M5。第四晶体管M4具有连接到复位信号端RST的栅极、连接到参考电压端VSS的第一电极、以及连接到第一节点N1的第二电极。第五晶体管M5具有连 接到复位信号端RST的栅极、连接到参考电压端VSS的第一电极、以及连接到信号输出端G[N]的第二电极。在操作中，第四晶体管M4响应于来自复位信号端RST的复位信号将来自参考电压端VSS的参考电压传送至第一节点N1，并且第五晶体管M5响应于来自复位信号端RST的复位信号将来自参考电压端VSS的参考电压传送至信号输出端G[N]。
图3为根据本公开实施例的一种移位寄存器电路100A的框图。参考图3，与图1所示的移位寄存器100相比，移位寄存器100A还包括下拉控制电路140、第一下拉电路150和第二下拉电路160。输入控制电路110、输出控制电路120和复位电路130的配置与上面关于图1描述的那些类似，并且因此在此不再重复。
下拉控制电路140连接到第二时钟信号端CLK2、参考电压端VSS、第一节点N1和第二节点N2。下拉控制电路140被配置成响应于第一节点N1处于第一电位Vp而将来自参考电压端VSS的参考电压提供给第二节点N2。下拉控制电路140还被配置成响应于第二节点N2被提供来自第二时钟信号端CLK2的具有有效电位的时钟信号电位而将来自参考电压端VSS的参考电压提供给第一节点N1。如本文所使用的有效电位是指使得下拉控制电路140能够工作的电位。
第一下拉电路150连接到第二节点N2、参考电压端VSS和信号输出端G[N]。第一下拉电路150被配置成响应于第二节点N2被提供来自第二时钟信号端CLK2的具有有效电位的时钟信号而将来自参考电压端VSS的参考电压提供给信号输出端G[N]。借助于第一下拉电路150，信号输出端G[N]输出的信号可以被保持处于稳定的参考电压，从而提高输出信号的稳定性。
第二下拉电路160连接到第二时钟信号端CLK2、参考电压端VSS和信号输出端G[N]。第二下拉电路160被配置成响应于来自第二时钟信号端CLK2的具有有效电位的第二时钟信号而将来自参考电压端VSS的参考电压提供给信号输出端G[N]。借助于第二下拉电路160，信号输出端G[N]输出的信号可以被保持处于稳定的参考电压，从而提高输出信号的稳定性。
图4为图3所示的移位寄存器电路100A的示例性电路图。
输入控制电路110、输出控制电路120和复位电路130的配置与上面关于图2描述的那些类似，并且因此在此不再重复。
下拉控制电路140包括第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、以及第十晶体管M10。第六晶体管M6具有连接到第二时钟信号端CLK2的栅极和第一电极、以及连接到第三节点N3的第二电极。第七晶体管M7具有连接到第三节点N3的栅极、连接到第二时钟信号端CLK2的第一电极、以及连接到第二节点N2的第二电极。第八晶体管M8具有连接到第一节点N1的栅极、连接到参考电压端VSS的第一电极、以及连接到第三节点N3的第二电极。第九晶体管M9具有连接到第一节点N1的栅极、连接到参考电压端VSS的第一电极、以及连接到第二节点N2的第二电极。第十晶体管M10具有连接到第二节点N2的栅极、连接到参考电压端VSS的第一电极、以及连接到第一节点N1的第二电极。在操作中，第六晶体管M6响应于来自第二时钟信号端CLK2的具有有效电位的时钟信号而将来自第二时钟信号端CLK2的时钟信号传送至第三节点N3，第七晶体管M7响应于第三节点N3被提供来自第二时钟信号端CLK2的具有有效电位的时钟信号而将来自第二时钟信号端CLK2的时钟信号传送至第二节点N2，第八晶体管M8响应于第一节点N1处于第一电位Vp而将来自参考电压端VSS的参考电压传送至第三节点N3，第九晶体管M9响应于第一节点N1处于第一电位Vp而将来自参考电压端VSS的参考电压传送至第二节点N2，第十晶体管M10响应于第二节点N2被提供来自第二时钟信号端CLK2的具有有效电位的时钟信号而将来自参考电压端VSS的参考电压传送至第一节点N1。
第一下拉电路150包括第十一晶体管M11。第十一晶体管M11的栅极与第二节点N2相连，第一电极与参考电压端VSS相连，第二电极与信号输出端G[N]相连。具体地，第十一晶体管M11在第二节点N2为第二时钟信号端CLK2的时钟信号电位时，将参考电压端VSS的参考电压提供给信号输出端G[N]。
第二下拉电路160包括第十二晶体管M12。第十二晶体管M12具有连接到第二时钟信号端CLK2的栅极、连接到参考电压端VSS的第一电极、以及连接到信号输出端G[N]的第二电极。在操作中，第十二晶体管M12响应于来自第二时钟信号端CLK2的具有有效电位的时钟信号而将来自参考电压端VSS的参考电压提供给信号输出端G[N]。
图5为图4所示的移位寄存器电路的时序图。结合图4和5描述 该移位寄存器电路的操作。在下面的描述中，以1表示高电平，并且以0表示低电平。
在T1阶段，IN＝1，CLK1＝0，CLK2＝1，RST＝0。由于信号输入端IN被提供有效脉冲信号Vh，所以第一晶体管M1和第二晶体管M2打开。由于第一晶体管M1和第二晶体管M2的电阻分压效应，第一节点N1处的电位被设定为第一电位Vp。如上面讨论的，第一电位Vp大于或等于用于维持输出控制电路20工作的电位Vo，且小于有效脉冲信号的电位Vh，即，Vh＞Vp≥Vo。由于第一节点N1处于第一电位Vp，第九晶体管M9打开，并且将来自参考电压端VSS的参考电压传送至第二节点N2。
在T2阶段，IN＝0，CLK1＝1，CLK2＝0，RST＝0。因第一节点N1处于第一电位Vp，所以第三晶体管M3打开，并且将来自第一时钟信号端CLK1的时钟信号(在该示例中，高电平信号Vh)提供给信号输出端G[N]，使得信号输出端G[N]输出高电平信号Vh。同时，因电容C的自举作用，第一节点N1处的电位被拉高至Vp+Vh。由于第一节点N1处于第一电位Vp+Vh，第九晶体管M9打开并且将来自参考电压端VSS的参考电压传送至第二节点N2。与其中内部节点处的电位可以为输出高电平的两倍(例如，2Vh)的现有技术相比，第一节点N1处的电位Vp+Vh现在小于2Vh。因此，在根据本公开的实施例的移位寄存器电路中，内部节点处的电位降低了。
在T3阶段，IN＝0，CLK1＝0，CLK2＝1，RST＝1。由于RST＝1，第四晶体管M4和第五晶体管M5打开，并且将来自参考电压端VSS的参考电压(其在该示例中具有低电平)分别提供给第一节点N1和信号输出端G[N]，使得第一节点N1处的电位被拉低至低电平，并且信号输出端G[N]输出低电平信号。由于CLK2＝1，第六晶体管M6打开，并且将来自第二时钟信号端CLK2的高电平信号提供给第三节点N3，使得第七晶体管M7打开，并且第二节点N2处的电位被拉高。第十晶体管M10和第十一晶体管M11于是被打开，并且将来自参考电压端VSS的参考电压分别提供给第一节点N1和信号输出端G[N]，保证第一节点N1处于低电平并且信号输出端G[N]输出低电平信号。另外，由于CLK2＝1，第十二晶体管M12打开，并且将来自参考电压端VSS的参考电压提供给信号输出端G[N]。
阶段T1-T3作为整体可以以一定的间隔重复，使得该移位寄存器电路经由信号输出端G[N]以该间隔输出栅极扫描信号。
在上面的实施例中，各晶体管被图示为N型晶体管，尽管P型晶体管是可能的。在P型晶体管的情况下，栅极开启电压具有低电平，并且栅极关闭电压具有高电平。在各实施例中，各晶体管可以典型地是薄膜晶体管，其被制作使得它们的第一电极和第二电极可互换地使用。还设想了其他实施例。
图6为根据本公开实施例的一种栅极驱动电路600的框图。参考图6，栅极驱动电路600包括级联的多个移位寄存器电路(SRC)。这些移位寄存器电路一起形成移位寄存器，其可操作为栅极驱动电路。
为了方便说明，图6中仅示出了五个移位寄存器，分别为第N-2级SRC、第N-1级SRC、第N级SRC、第N+1级SRC和第N+2级SRC。这些移位寄存器电路中的每一个可以是上面参考图1-4所述的移位寄存器电路100或100A。
如图6所示，除首级移位寄存器电路和末级移位寄存器电路之外，各移位寄存器电路中的每一个的信号输出端连接到下一级移位寄存器的信号输入端和上一级移位寄存器的复位信号端。在该示例中，第N级移位寄存器电路的信号输出端G[N]不仅向第N+1级移位寄存器电路的信号输入端IN输入有效脉冲信号，还向第N-1级移位寄存器的复位信号端RST输入复位信号。另外，首级移位寄存器的信号输出端连接到第二级移位寄存器的输入端，并且末级移位寄存器的信号输出端连接到上一级移位寄存器的复位信号端。
图7是根据本公开实施例的显示装置700的框图。参考图7，显示装置700包括显示面板710、时序控制器720、栅极驱动电路730和数据驱动电路740。栅极驱动电路730可以是上面关于图6所述的栅极驱动电路600。
显示面板710连接至多个栅极线GL和多个数据线DL。显示面板710基于输出图像数据RGBD’显示具有多个灰度的图像。栅极线GL可在第一方向D1延伸，并且数据线DL可在与第一方向D1交叉(例如，基本垂直)的第二方向D2延伸。显示面板710可包括以矩阵形式排列的多个像素(未示出)。每个像素可电连接至栅极线GL的对应一个栅极线和数据线DL的对应一个数据线。显示面板710可以是液晶显示面 板、有机发光二极管(OLED)显示面板或其他合适类型的显示面板。
时序控制器720控制显示面板710、栅极驱动电路730和数据驱动电路740的操作。时序控制器720从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器720基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。
栅极驱动电路730从时序控制器720接收第一控制信号CONT1。栅极驱动电路730基于第一控制信号CONT1生成用于驱动栅极线GL的多个栅极信号。栅极驱动电路730可顺序地将多个栅极信号施加至栅极线GL。
数据驱动电路740从时序控制器720接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动电路740基于第二控制信号CONT2和输出图像数据RGBD’(例如，数字图像数据)生成多个数据电压(例如，模拟数据电压)。数据驱动电路740可将多个数据电压施加至数据线DL。
在一些示例性实施例中，栅极驱动电路730和/或数据驱动电路740可被设置(例如，直接安装)在显示面板710上，或者可以借助例如带式载体封装(Tape Carrier Package，TCP)连接至显示面板710。在一些实施例中，栅极驱动电路730和/或数据驱动电路740可被集成在显示面板710中。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型落入本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种移位寄存器电路，包括：
    输入控制电路，连接到信号输入端、参考电压端和第一节点，所述输入控制电路被配置成响应于来自所述信号输入端的有效脉冲信号而将所述第一节点设定处于第一电位；
    输出控制电路，连接到所述第一节点、第一时钟信号端和信号输出端，所述输出控制电路被配置成响应于所述第一节点处于所述第一电位而将来自所述第一时钟信号端的时钟信号提供给所述信号输出端，所述第一电位小于所述有效脉冲信号的电位，且大于或等于用于维持所述输出控制电路工作的电位；以及
    复位电路，连接到复位信号端、所述参考电压端、所述第一节点和所述信号输出端，所述复位电路被配置成响应于来自所述复位信号端的复位信号而将来自所述参考电压端的参考电压提供给所述第一节点和所述信号输出端。
  2. 如权利要求1所述的移位寄存器电路，其中所述输入控制电路包括：
    第一晶体管，具有连接到所述信号输入端的栅极和第一电极、以及连接到所述第一节点的第二电极；以及
    第二晶体管，具有连接到所述信号输入端的栅极、连接到所述参考电压端的第一电极、以及连接到所述第一节点的第二电极。
  3. 如权利要求1所述的移位寄存器电路，其中所述输出控制电路包括：
    第三晶体管，具有连接到所述第一节点的栅极、连接到所述第一时钟信号端的第一电极、以及连接到所述信号输出端的第二电极；以及
    电容，连接于所述第一节点与所述信号输出端之间。
  4. 如权利要求1所述的移位寄存器电路，其中所述复位电路包括：
    第四晶体管，具有连接到所述复位信号端的栅极、连接到所述参考电压端的第一电极、以及连接到所述第一节点的第二电极；以及
    第五晶体管，具有连接到所述复位信号端的栅极、连接到所述参考电压端的第一电极、以及连接到所述信号输出端的第二电极。
  5. 如权利要求1-4任一项所述的移位寄存器电路，还包括连接到第二时钟信号端、所述参考电压端、所述第一节点和第二节点的下拉控制电路，其中所述下拉控制电路被配置成响应于所述第一节点处于所述第一电位而将来自所述参考电压端的所述参考电压提供给所述第二节点，并且响应于所述第二节点被提供来自所述第二时钟信号端的具有有效电位的时钟信号而将来自所述参考电压端的所述参考电压提供给所述第一节点。
  6. 如权利要求5所述的移位寄存器电路，其中所述下拉控制电路包括：
    第六晶体管，具有连接到所述第二时钟信号端的栅极和第一电极、以及连接到第三节点的第二电极；
    第七晶体管，具有连接到所述第三节点的栅极、连接到所述第二时钟信号端的第一电极、以及连接到所述第二节点的第二电极；
    第八晶体管，具有连接到所述第一节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述第三节点的第二电极；
    第九晶体管，具有连接到所述第一节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述第二节点的第二电极；以及
    第十晶体管，具有连接到所述第二节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述第一节点的第二电极。
  7. 如权利要求5所述的移位寄存器电路，还包括连接到所述第二节点、所述参考电压端和所述信号输出端的第一下拉电路，其中所述第一下拉电路被配置成响应于所述第二节点被提供来自所述第二时钟信号端的具有所述有效电位的所述时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端。
  8. 如权利要求7所述的移位寄存器电路，其中所述第一下拉电路包括第十一晶体管，其具有连接到所述第二节点的栅极、连接到所述参考电压端的第一电极、以及连接到所述信号输出端的第二电极。
  9. 如权利要求7所述的移位寄存器电路，还包括连接到所述第二时钟信号端、所述参考电压端和所述信号输出端的第二下拉电路，其中所述第二下拉电路被配置成响应于来自所述第二时钟信号端的具有所述有效电位的所述第二时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端。
  10. 如权利要求9所述的移位寄存器电路，其中所述第二下拉电路包括第十二晶体管，其具有连接到所述第二时钟信号端的栅极、连接到所述参考电压端的第一电极、以及连接到所述信号输出端的第二电极。
  11. 一种栅极驱动电路，包括级联的多个如权利要求1-10任一项所述的移位寄存器电路，其中：
    除首级移位寄存器电路和末级移位寄存器电路之外，所述移位寄存器电路中的每一个的信号输出端连接到下一级移位寄存器电路的信号输入端和上一级移位寄存器电路的复位信号端两者；
    首级移位寄存器电路的信号输出端连接到第二级移位寄存器电路的信号输入端；并且
    末级移位寄存器电路的信号输出端连接到上一级移位寄存器电路的复位信号端。
  12. 一种显示装置，包括如权利要求11所述的栅极驱动电路。
  13. 一种驱动如权利要求1-10任一项所述的移位寄存器电路的方法，所述方法包括：
    在第一时间段，响应于来自所述信号输入端的所述有效脉冲信号而将所述第一节点设定处于第一电位；
    在第二时间段，响应于所述第一节点处于所述第一电位而将来自所述第一时钟信号端的所述时钟信号提供给所述信号输出端；以及
    在第三时间段，响应于来自所述复位信号端的所述复位信号而将来自所述参考电压端的所述参考电压提供给所述第一节点和所述信号输出端。
  14. 如权利要求13所述的方法，还包括：
    在第一时间段和第二时间段，响应于所述第一节点处于所述第一电位而将来自所述参考电压端的所述参考电压提供给第二节点；以及
    在第三时间段，响应于所述第二节点被提供来自第二时钟信号端的具有有效电位的时钟信号而将来自所述参考电压端的所述参考电压提供给所述第一节点。
  15. 如权利要求14所述的方法，还包括：
    在第三时间段，响应于所述第二节点被提供来自所述第二时钟信号端的具有所述有效电位的所述时钟信号而将来自所述参考电压端的 所述参考电压提供给所述信号输出端，并且响应于来自所述第二时钟信号端的具有所述有效电位的第二时钟信号而将来自所述参考电压端的所述参考电压提供给所述信号输出端。
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