WO2022160888A1 - 移位寄存器、栅极驱动电路和显示面板 - Google Patents

移位寄存器、栅极驱动电路和显示面板 Download PDF

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Publication number
WO2022160888A1
WO2022160888A1 PCT/CN2021/131986 CN2021131986W WO2022160888A1 WO 2022160888 A1 WO2022160888 A1 WO 2022160888A1 CN 2021131986 W CN2021131986 W CN 2021131986W WO 2022160888 A1 WO2022160888 A1 WO 2022160888A1
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Prior art keywords
signal
potential
transistor
output
node
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PCT/CN2021/131986
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English (en)
French (fr)
Inventor
郭恩卿
盖翠丽
王玲
李俊峰
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云谷（固安）科技有限公司
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Priority to KR1020237019274A priority Critical patent/KR20230098665A/ko
Publication of WO2022160888A1 publication Critical patent/WO2022160888A1/zh
Priority to US18/339,409 priority patent/US11893922B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present application relates to the field of display technology, for example, to a shift register, a gate driving circuit and a display panel.
  • the display panel usually includes a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift registers.
  • the structure of the shift register has problems such as unstable output signal and short pulse width of the output signal, which affects the display of the display panel. Effect.
  • the present application provides a shift register, a gate driving circuit and a display panel, so as to extend the pulse width of an effective signal output by the shift register and improve the stability of the output signal of the shift register.
  • the application provides a shift register, comprising: a first input module, a second input module, a first output module, a second output module, a first output control module and a second output control module;
  • the first input module is set to control the potential of the first node according to the first start signal and the first clock signal;
  • the second input module is set to control the second node according to the second start signal and the first clock signal The potential of the second start signal is opposite to the potential of the first start signal;
  • the first output control module is configured to control the potential of the second node according to the potential of the first node, the first potential signal and the second clock signal; the first output module is configured to control the potential of the second node according to the first node The potential of the second node and the potential of the second node transmit the first potential signal or the second potential signal to the first output terminal of the shift register;
  • the second output control module is configured to control the potential of a third node according to the potential of the first output terminal, the first potential signal and the second clock signal, and the third node is connected to the first node
  • the second output module is configured to transmit the first potential signal or the second potential signal to the second output of the shift register according to the potential of the first output terminal and the potential of the third node end.
  • An embodiment of the present application further provides a gate driving circuit, comprising a plurality of the above shift registers, the plurality of shift registers are connected in cascade;
  • the first start signal input terminal of the first stage shift register is set to be connected to the first start signal
  • the second start signal input terminal of the first stage shift register is set to be connected to the second start signal
  • the The first output end of the first stage shift register is electrically connected to the second start signal input end of the next stage shift register
  • the second output end of the first stage shift register is shifted with the next stage shift register
  • the first start signal input end of the register is electrically connected.
  • the present application further provides a display panel, including the above gate driving circuit, and further comprising: a first clock signal line, a second clock signal line, a first potential signal line and a second potential signal line;
  • the first clock signal line is set to transmit a first clock signal to the shift register; the second clock signal line is set to transmit a second clock signal to the shift register; the first potential signal line is set In order to transmit the first potential signal to the shift register; the second potential signal line is set to transmit the second potential signal to the shift register.
  • the shift register, gate drive circuit and display panel realize the adjustment of the effective signal of the output signal of the first output end and the second output end of the shift register by adjusting the pulse width of the effective signal of the first start signal
  • the pulse width of the effective signal of the first start signal is set to be greater than the pulse width of the effective signal of the first clock signal and the second clock signal
  • the pulse width of the effective signal of the output signal of the shift register is also larger than that of the clock signal
  • the pulse width of the effective signal is increased, and the level loss of the output signal of the shift register can also be reduced through the first output control module and the second output control module.
  • the technical solution of the present application can extend the pulse width of the effective signal output by the shift register, and improve the stability of the output signal of the shift register.
  • the output signal of the shift register is used as the gate driving signal of the transistor for initializing the gate of the driving transistor and the anode of the light-emitting device
  • the initialization time of the gate of the driving transistor and the anode of the light-emitting device can be increased, thereby reducing the problem caused by initialization Problems such as afterimage and abnormal display on the display screen caused by insufficient time will help to improve the display effect.
  • the output signal of the shift register can also be used as the gate driving signal of the light-emitting control transistor, which is also helpful for to improve the display effect.
  • FIG. 1 is a schematic structural diagram of a module of a shift register provided by an embodiment of the present application.
  • FIG. 2 is a driving timing diagram of a shift register provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a module of another shift register provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a module of another shift register provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a module of another shift register provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a module of another shift register provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a shift register provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another shift register provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a module structure of a gate drive circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a shift register in the related art.
  • the structure of the shift register has problems such as unstable output signal and short pulse width of the output signal, which affects the display effect of the display panel.
  • the reason for the above problem is that the display panel includes a light-emitting device and a pixel circuit that drives the light-emitting device to work.
  • the pixel circuit includes a driving transistor, a transistor that initializes the anode of the light-emitting device, and a transistor that initializes the gate of the driving transistor.
  • the gate drive circuit constituted by the bit register can provide gate drive signals to a plurality of transistors in the pixel circuit.
  • the pulse width of the output effective signal of the shift register in the related art usually depends on the pulse width of the input clock signal.
  • the line scanning time for driving the pixel circuit is very short.
  • the clock signal input to the shift register is limited by the line scanning time, so that the pulse width of the clock signal is short, and the output signal of the shift register is also a short pulse signal. Therefore, the pulse of the gate driving signal of the initialization transistor in the pixel circuit is The width is also short, which on the one hand will lead to insufficient initialization time of the light-emitting device, resulting in afterimages on the display screen, and on the other hand will lead to insufficient initialization time of the gate of the driving transistor, resulting in uneven display of the display screen, and even abnormal display. .
  • the output signal of the shift register in the related art is unstable, and there is a problem of level loss, which also affects the display effect of the display panel.
  • FIG. 1 is a schematic diagram of a module structure of a shift register provided by an embodiment of the present application.
  • the shift register includes: a first input module 10 , a second input module 20 , a first output module 30 , and a first input module 10 .
  • Two output modules 40, a first output control module 50 and a second output control module 60 the first input module 10 is configured to control the potential of the first node N1 according to the first start signal IN and the first clock signal CLK1; the second input module 20 is set to control the potential of the second node N2 according to the second start signal INB and the first clock signal CLK1, and the potential of the second start signal INB is opposite to that of the first start signal IN; the first output control module 50 is set to be based on the first output control module 50.
  • the potential of a node N1, the first potential signal VGH and the second clock signal CLK2 control the potential of the second node N2;
  • the first output module 30 is configured to convert the first potential according to the potential of the first node N1 and the potential of the second node N2
  • the signal VGH or the second potential signal VGL is transmitted to the first output terminal O1 of the shift register;
  • the second output control module 60 is configured to control the first output terminal O1 according to the potential of the first output terminal O1, the first potential signal VGH and the second clock signal CLK2.
  • the potential of the three nodes N3, the third node N3 is connected to the first node N1; the second output module 40 is configured to convert the first potential signal VGH or the second potential signal according to the potential of the first output terminal O1 and the potential of the third node N3 VGL is transmitted to the second output terminal O2 of the shift register.
  • the first start signal IN may be a pulse signal with adjustable pulse width.
  • the pulse width of the valid signal of the first start signal IN is larger than the pulse width of the valid signals of the first clock signal CLK1 and the second clock signal CLK2.
  • the potential of the second start signal INB is opposite to that of the first start signal IN.
  • the shift register can generate the inverse signal of the first start signal IN according to the received first start signal IN through its internal structure, so as to obtain the second start signal INB.
  • the shift register may include an inverter, and the shift register
  • the inverse signal of the first start signal IN that is, the second start signal INB, can be obtained through an inverter, and the second start signal INB is input to the second input module 20 .
  • Active level signal among the first clock signal CLK1, the second clock signal CLK2, the potential signal of the first node N1, the potential signal of the second node N2, the potential signal of the third node N3 and the potential signal of the first output terminal O1 It can be a low-level signal or a high-level signal.
  • the potentials of the first potential signal VGH and the second potential signal VGL are opposite, for example, when the first potential signal VGH is a high-level signal, the second potential signal VGL is a low-level signal, or the first potential signal VGH is a low-level signal , the second potential signal VGL is a high level signal.
  • the effective level signal in the potential signals of the output terminal O1 is a low-level signal
  • the first potential signal VGH is a high-level signal
  • the second potential signal VGL is a low-level signal as an example for schematic illustration.
  • the third node N3 is connected to the first node N1, which may be a direct electrical connection or an indirect electrical connection, which is not limited in this embodiment of the present application.
  • the first input module 10 controls the potential of the first node N1 according to the first start signal IN and the first clock signal CLK1, which means that the first input module 10 can change the first start signal in response to the effective level signal of the first clock signal CLK1.
  • IN is transmitted to the first node N1.
  • the second input module 20 controls the potential of the second node N2 according to the second start signal INB and the first clock signal CLK1, which means that the second input module 20 can respond to the effective level signal of the first clock signal CLK1.
  • the start signal INB is transmitted to the second node N2.
  • the first output module 30 transmits the first potential signal VGH or the second potential signal VGL to the first output terminal O1 of the shift register according to the potential of the first node N1 and the potential of the second node N2, which refers to the first output module 30
  • the first potential signal VGH can be transmitted to the first output terminal O1 in response to the active level signal of the first node N1
  • the second potential signal VGL can be transmitted to the first output terminal in response to the active level signal of the second node N2 O1.
  • the first input module 10 can control the potential of the first node N1 according to the first start signal IN and the first clock signal CLK1, the potential of the first node N1 affects the duration of the first output terminal O1 to output the first potential signal VGH, so it can be
  • the pulse width of the first potential signal VGH output by the first output terminal O1 is adjusted by adjusting the pulse width of the first start signal IN and in combination with the control of the first clock signal CLK1.
  • the second input module 20 controls the potential of the second node N2 according to the second start signal INB and the first clock signal CLK1
  • the potential of the second node N2 affects the time period during which the first output terminal O1 outputs the second potential signal VGL, so it can be
  • the pulse width of the second potential signal VGL output by the first output terminal O1 is adjusted by adjusting the pulse width of the second start signal INB and in combination with the control of the first clock signal CLK1.
  • the pulse width of the second start signal INB depends on the pulse width of the first start signal IN. Therefore, the solution of this embodiment can adjust the pulse width of the effective signal of the first start signal IN to adjust the first start signal of the shift register.
  • the pulse width of the valid signal of the output signal of the output terminal O1 when the pulse width of the valid signal of the first start signal IN is set to be larger than the pulse width of the valid signal of the first clock signal CLK1 and the second clock signal CLK2, the first output The pulse width of the valid signal of the output signal of the terminal O1 is also larger than the pulse width of the valid signal of the first clock signal CLK1 and the second clock signal CLK2.
  • the first output control module 50 controls the potential of the second node N2 according to the potential of the first node N1, the first potential signal VGH and the second clock signal CLK2, which means that the first output control module 50 can control the potential of the second clock signal CLK2
  • the potential of the second node N2 is controlled according to the potential of the first node N1, the first potential signal VGH and the second clock signal CLK2.
  • the first output control module 50 can pull down the potential of the second node N2 to a relative level. a lower potential corresponding to the second potential signal VGL.
  • the first output module 30 can transmit the second potential signal VGL to the first output terminal O1 in response to a valid level signal (eg, a low level signal) of the second node N2, if the potential of the second node N2 is not low enough ( That is, when the absolute value of the difference between the potential of the second node N2 and the second potential signal VGL is greater than the set threshold), the second potential signal VGL transmitted from the first output module 30 to the first output terminal O1 will experience a level loss .
  • the first output control module 50 can be used to control the voltage of the second node N2.
  • the potential is pulled down to be lower than the potential of the second potential signal VGL, so that the potential of the second node N2 can reach a sufficiently low potential (the sufficiently low potential satisfies: the difference between the potential of the second node N2 and the second potential signal VGL
  • the absolute value of is less than the set threshold), thereby reducing the level loss of the low-level signal output by the first output terminal O1.
  • the first output module 30 includes a transistor whose gate is connected to the second node N2, the first electrode is connected to the second potential signal VGL, and the second electrode is connected to the first output terminal O1, the set threshold may be equal to the threshold voltage of the transistor.
  • the second output module 40 transmits the first potential signal VGH or the second potential signal VGL to the second output terminal O2 of the shift register according to the potential of the first output terminal O1 and the potential of the third node N3, which refers to the second output module 40 can transmit the first potential signal VGH to the second output terminal O2 in response to the active level signal of the first output terminal O1, and transmit the second potential signal VGL to the second potential signal VGL in response to the active level signal of the third node N3 Output O2.
  • the potential of the first output terminal O1 affects the duration of the second output terminal O2 outputting the first potential signal VGH
  • the potential of the first output terminal O1 is controlled by the first start signal IN, so by adjusting the effective value of the first start signal IN
  • the pulse width of the effective signal of the output signal of the first output terminal O1 is adjusted according to the pulse width of the signal
  • the pulse width of the first potential signal VGH output by the second output terminal O2 can also be adjusted.
  • the potential of the third node N3 affects the duration of the second output terminal O2 outputting the second potential signal VGL
  • the potential of the third node N3 is the same as the potential of the first node N1, and the first input module 10 can respond to the first start signal IN according to the potential of the third node N3.
  • the solution of this embodiment can adjust the pulse width of the effective signal of the output signal of the second output terminal O2 of the shift register by adjusting the pulse width of the effective signal of the first start signal IN.
  • the pulse width of the effective signal is greater than that of the first clock signal CLK1 and the second clock signal CLK2
  • the pulse width of the effective signal of the output signal of the second output terminal O2 is also greater than that of the first clock signal CLK1 and the second clock signal CLK1.
  • the second output control module 60 controls the potential of the third node N3 according to the potential of the first output terminal O1, the first potential signal VGH and the second clock signal CLK2, which means that the second output control module 60 can control the potential of the second clock signal CLK2
  • the potential of the third node N3 is controlled according to the potential of the first output terminal O1, the first potential signal VGH and the second clock signal CLK2.
  • the second output control module 60 can pull down the potential of the third node N3 to a potential lower than the potential corresponding to the second potential signal VGL.
  • the second output module 40 can transmit the second potential signal VGL to the second output terminal O2 in response to a valid level signal (eg, a low level signal) of the third node N3, if the potential of the third node N3 is not low enough ( That is, when the absolute value of the difference between the potential of the third node N3 and the second potential signal VGL is greater than the set threshold), the second potential signal VGL transmitted from the second output module 40 to the second output terminal O2 will experience a level loss .
  • the second output control module 60 can be used to control the output voltage of the third node N3.
  • the potential is pulled down to be lower than the potential of the second potential signal VGL, so that the potential of the third node N3 can reach a sufficiently low potential (the sufficiently low potential satisfies: the difference between the potential of the third node N3 and the second potential signal VGL
  • the absolute value of is less than the set threshold), thereby reducing the level loss of the low-level signal output by the second output terminal O2.
  • the second output module 40 includes a transistor whose gate is connected to the third node N3, the first electrode is connected to the second potential signal VGL, and the second electrode is connected to the second output terminal O2, the set threshold may be equal to the threshold voltage of the transistor.
  • the technical solution of the embodiment of the present application realizes that the pulse width of the effective signal of the output signal of the first output terminal and the output signal of the second output terminal can be adjusted by adjusting the pulse width of the effective signal of the first starting signal.
  • the pulse width of the signal is greater than the pulse width of the effective signal of the first clock signal and the second clock signal
  • the pulse width of the effective signal of the output signal of the first output terminal and the second output terminal of the shift register is also larger than the effective signal of the clock signal.
  • the first output control module and the second output control module can also reduce the level loss of the output signal of the shift register.
  • the pulse width of the output signal of the shift register in the related art depends on the pulse width of the clock signal. The stability of the output signal of the bit register.
  • the shift register provided by the embodiments of the present application can be applied to a gate drive circuit of a display panel, and a gate drive signal is provided to a transistor in a pixel circuit of the display panel through the shift register, for example, the output of the second output end of the shift register
  • the signal can be used as a gate drive signal.
  • the output signal of the shift register is used as the gate driving signal of the transistor for initializing the gate of the driving transistor and the anode of the light-emitting device in the pixel circuit
  • the initialization time of the gate of the driving transistor and the anode of the light-emitting device can be increased, thereby increasing the initialization time of the gate of the driving transistor and the anode of the light-emitting device.
  • the pixel circuit also includes a light-emitting control transistor that controls the light-emitting stage of the light-emitting device. Since the effective signal pulse width of the output signal of the shift register of this scheme is wide, and the stability of the output signal is good, the shift register The output signal of the register can also be used as the gate driving signal of the light-emitting control transistor, which also helps to improve the display effect.
  • FIG. 2 is a driving timing diagram of a shift register provided by an embodiment of the present application.
  • the driving timing can be used to drive the shift register shown in FIG. 1 .
  • the working principle of the bit register is explained.
  • the working process of the shift register includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5 and a sixth stage t6.
  • the pulse width of the first start signal IN is larger than the pulse widths of the first clock signal CLK1 and the second clock signal CLK2.
  • the first clock signal CLK1 is at a low level
  • the second clock signal CLK2 is at a high level
  • the first start signal IN is at a high level
  • the second start signal INB is at a low level.
  • the first input module 10 transmits the first start signal IN to the first node N1 in response to the low level signal of the first clock signal CLK1, so that the potential of the first node N1 is high.
  • the second input module 20 transmits the second start signal INB to the second node N2 in response to the low level signal of the first clock signal CLK1, so that the potential of the second node N2 is low.
  • the first output module 30 transmits the second potential signal VGL to the first output terminal O1 in response to the low-level signal of the second node N2, so that the first output signal OUTB is a low-level signal.
  • the potential of the third node N3 is the same as the potential of the first node N1 and is at a high level.
  • the second output module 40 transmits the first potential signal VGH to the second output terminal O2 in response to the low-level signal of the first output terminal O1, so that the second output signal OUT is a high-level signal.
  • the first output signal OUTB is consistent with the second start signal INB
  • the second output signal OUT is consistent with the first start signal IN.
  • the first clock signal CLK1 is at a high level
  • the second clock signal CLK2 jumps from a high level to a low level
  • the first start signal IN is at a low level
  • the second start signal INB is at a high level flat.
  • the first input module 10 stops transmitting the first start signal IN, and the potential of the first node N1 remains at the high level of the previous stage.
  • the second input module 20 stops transmitting the second start signal INB, and the potential of the second node N2 remains at the low level of the previous stage.
  • the first output control module 50 pulls down the potential of the second node N2 to a lower level than the low level according to the potential of the first node N1, the first potential signal VGH and the second clock signal CLK2
  • the signal potential ensures that the first output module 30 continues to transmit the second potential signal VGL to the first output terminal O1 in response to the low level signal of the second node N2, so that the first output signal OUTB is still a low level signal.
  • the potential of the third node N3 is the same as the potential of the first node N1 and is at a high level.
  • the second output module 40 continues to transmit the first potential signal VGH to the second output terminal O2 in response to the low-level signal of the first output terminal O1, so that the second output signal OUT is a high-level signal.
  • the first output signal OUTB is still consistent with the second start signal INB, and the second output signal OUT is still consistent with the first start signal IN.
  • the first clock signal CLK1 is at a low level
  • the second clock signal CLK2 is at a high level
  • the first start signal IN is at a low level
  • the second start signal INB is at a high level.
  • the first input module 10 transmits the first start signal IN to the first node N1 so that the potential of the first node N1 is low.
  • the second input module 20 transmits the second start signal INB to the second node N2 so that the potential of the second node N2 is at a high potential.
  • the first output module 30 transmits the first potential signal VGH to the first output terminal O1 in response to the low-level signal of the first node N1, so that the first output signal OUTB is a high-level signal.
  • the potential of the third node N3 is the same as the potential of the first node N1 and is at a low level.
  • the second output module 40 transmits the second potential signal VGL to the second output terminal O2 in response to the low-level signal of the third node N3, so that the second output signal OUT is a low-level signal.
  • the first output signal OUTB is inverted, which is consistent with the inverted second start signal INB, and the second output signal OUT is inverted, which is consistent with the inverted first start signal IN .
  • the first start signal IN is kept at a low level
  • the second start signal INB is kept at a high level.
  • the first input module 10 stops transmitting For the first start signal IN, the potential of the first node N1 remains at the low level of the previous stage.
  • the second input module 20 stops transmitting the second start signal INB, and the potential of the second node N2 remains at the high level of the previous stage.
  • the potential of the third node N3 is the same as the potential of the first node N1 and is at a low level.
  • the first output module 30 continues to transmit the first potential signal VGH to the first output terminal O1, so that the first output signal OUTB is a high-level signal.
  • the second output control module 60 pulls down the potential of the third node N3 to be lower than the potential of the first output terminal O1, the first potential signal VGH and the second clock signal CLK2 according to the potential of the first output terminal O1 The potential of the low-level signal (as shown in FIG.
  • the potential of the third node N3 becomes lower when entering the fourth stage t4 from the third stage t3 ) to ensure that the second output module 40 continues to respond to the third node
  • the low-level signal of N3 transmits the second potential signal VGL to the second output terminal O2, so that the second output signal OUT is a low-level signal, so as to reduce the level loss of the low-level signal output by the second output terminal O2.
  • the first output signal OUTB remains a high-level signal
  • the second output signal OUT remains a low-level signal.
  • the first clock signal CLK1 is at a low level
  • the second clock signal CLK2 is at a high level
  • the first start signal IN is at a high level
  • the second start signal INB is at a low level.
  • the first input module 10 transmits the first start signal IN to the first node N1 so that the potential of the first node N1 is high.
  • the second input module 20 transmits the second start signal INB to the second node N2, so that the potential of the second node N2 is low.
  • the first output module 30 transmits the second potential signal VGL to the first output terminal O1 in response to the low-level signal of the second node N2, so that the first output signal OUTB is a low-level signal.
  • the potential of the third node N3 is the same as the potential of the first node N1 and is at a high level.
  • the second output module 40 transmits the first potential signal VGH to the second output terminal O2 in response to the low-level signal of the first output terminal O1, so that the second output signal OUT is a high-level signal.
  • the first output signal OUTB is inverted, which is consistent with the inverted second start signal INB, and the second output signal OUT is inverted, which is consistent with the inverted first start signal IN .
  • the first start signal IN is kept at a high level
  • the second start signal INB is kept at a low level.
  • the first input module 10 stops transmitting For the first start signal IN, the potential of the first node N1 remains at the high level of the previous stage.
  • the second input module 20 stops transmitting the second start signal INB, and the potential of the second node N2 remains at the low level of the previous stage.
  • the first output control module 50 pulls down the potential of the second node N2 to a lower level than the low level according to the potential of the first node N1, the first potential signal VGH and the second clock signal CLK2
  • the potential of the signal (as shown in FIG. 2, the potential of the second node N2 becomes lower when entering the sixth stage t6 from the fifth stage t5) to ensure that the first output module 30 continues to respond to the low level of the second node N2
  • the level signal transmits the second potential signal VGL to the first output terminal O1, so that the first output signal OUTB is still a low level signal, so as to reduce the level loss of the low level signal output by the first output terminal O1.
  • the potential of the third node N3 is the same as the potential of the first node N1 and is at a high level.
  • the second output module 40 continues to transmit the first potential signal VGH to the second output terminal O2 in response to the low-level signal of the first output terminal O1, so that the second output signal OUT is a high-level signal.
  • the first output signal OUTB is kept consistent with the second start signal INB, and the second output signal OUT is kept consistent with the first start signal IN.
  • the pulse width of the low-level signal of the first start signal IN is set to be greater than the pulse width of the low-level signals of the first clock signal CLK1 and the second clock signal CLK2, it is possible to realize the transition through the shift register.
  • the first starting signal IN is shifted and outputted to obtain the second output signal OUT
  • the second starting signal INB is shifted and outputted to obtain the first output signal OUTB.
  • the pulse width of the low level signal of the first output signal OUTB and the second output signal OUT of the shift register is larger than the pulse width of the low level signal of the clock signal, and is reduced by the first output control module 50.
  • the low-level loss of the first output signal OUTB of the shift register is reduced, and the low-level loss of the second output signal OUT of the shift register is reduced by the second output control module 60, which is beneficial to prolong the output signal of the shift register.
  • Low level time and when the output signal of the shift register is used as the gate driving signal of the initialization transistor in the pixel circuit, it is beneficial to prolong the initialization time of the gate of the driving transistor and the anode of the light-emitting device, thereby reducing the initialization time caused by Problems such as afterimage and abnormal display caused by insufficient display screen will help to improve the display effect.
  • the gate driving circuit in the display panel usually includes a plurality of shift registers connected in cascade, and the shift register in this embodiment can realize the shift output of the first start signal IN to obtain the second output signal OUT , shift and output the second start signal INB to obtain the first output signal OUTB.
  • the second output signal OUT output by the shift register at this stage can also be used as the lower
  • the first start signal IN input by the first stage shift register, and the first output signal OUTB output by the current stage shift register can also be used as the second start signal INB input by the next stage shift register, which is helpful for the current stage shift register.
  • the output signal of the bit register is passed to the next stage shift register.
  • the low-level loss of the output signal of the shift register can also be reduced, thereby reducing the level of the signal transmitted from the shift register of the current stage to the shift register of the next stage. loss.
  • FIG. 3 is a schematic diagram of a module structure of another shift register provided by an embodiment of the present application.
  • the first output control module 50 is set to the potential of the first node N1 and the first potential signal VGH is the first potential, and when the second clock signal CLK2 jumps from the first potential to the second potential, the potential of the second node N2 is pulled down to a potential lower than the second potential signal VGL.
  • the first output control module 50 includes: a first transistor M1, a second transistor M2 and a first capacitor C1; the gate of the first transistor M1 is connected to the second node N2 and the second end of the first capacitor C1; The first pole is input with the second clock signal CLK2, the second pole of the first transistor M1 is connected to the first end of the first capacitor C1 and the second pole of the second transistor M2; the gate of the second transistor M2 is connected to the first node N1, A first potential signal VGH is input to the first electrode of the second transistor M2.
  • the driving timing diagram of the shift register shown in FIG. 2 can also be used to drive the shift register shown in FIG. 3 to work.
  • the first potential of the second clock signal CLK2 may be A high-level potential
  • the second potential can be a low-level potential
  • the first output control module 50 can pull down the potential of the second node N2 to a potential lower than the second potential signal VGL according to the potential of the first node N1, the first potential signal VGH and the second clock signal CLK2, that is, lower than the potential of the second potential signal VGL.
  • the potential of the low-level signal ensures that the first output module 30 continues to transmit the second potential signal VGL to the first output terminal O1 in response to the low-level signal of the second node N2, so that the first output signal OUTB is still at a low level level signal, so as to reduce the level loss of the low level signal output by the first output terminal O1.
  • the first transistor M1 and the second transistor M2 in the first output control module 50 may be P-type transistors or N-type transistors. In this embodiment and the following embodiments, multiple transistors in the shift register are used. A P-type transistor is used as an example for schematic illustration.
  • the first transistor M1 is turned on in response to the low level signal of the second node N2, and when turned on, transmits the second clock signal CLK2 to the fourth node N4 between the first transistor M1 and the second transistor M2.
  • the second transistor M2 is turned on in response to the low-level signal of the first node N1, and transmits the first potential signal VGH to the fourth node N4 when turned on.
  • the potential of the first node N1 is at a high potential
  • the potential of the second node N2 is at a low potential
  • the second transistor M2 is turned off
  • the first transistor M1 is turned on
  • the The second clock signal CLK2 is transmitted to the fourth node N4, so that the potential of the fourth node N4 is high, the two ends of the first capacitor C1 form a potential difference, and the first capacitor C1 is charged.
  • the second clock signal CLK2 jumps from the first potential to the second potential, the potential of the second node N2 is close to the low potential, the first transistor M1 continues to be turned on, and turns The second clock signal CLK2 is transmitted to the fourth node N4, so that the potential of the fourth node N4 changes from a high potential to a low potential.
  • the first capacitor C1 can couple the potential of the second node N2 to The extremely low level lower than the low level ensures that the first output module 30 continues to transmit the second level signal VGL to the first output terminal O1 in response to the low level signal of the second node N2, so that the first output signal OUTB is still A low-level signal to reduce the level loss of the low-level signal output by the first output terminal O1.
  • FIG. 4 is a schematic structural diagram of a module of another shift register provided by an embodiment of the present application.
  • the second output control module 60 is set to the potential of the first output terminal O1 and the first potential
  • the signals VGH are both at the first potential, and when the second clock signal CLK2 jumps from the first potential to the second potential, the potential of the third node N3 is pulled down to a potential lower than the second potential signal VGL;
  • the second output control module 60 includes: a third transistor M3, a fourth transistor M4, and a second capacitor C2; the gate of the third transistor M3 is connected to the third node N3 and the second end of the second capacitor C2, and the first pole of the third transistor M3 is input to the second capacitor C2.
  • the drive timing diagram of the shift register shown in FIG. 2 can also be used to drive the shift register shown in FIG. 4 to work.
  • the second output control module 60 can be based on the potential of the first output terminal O1, the first potential signal VGH and the second clock signal CLK2 pulls down the potential of the third node N3 to be lower than the potential of the second potential signal VGL, that is, lower than the potential of the low-level signal, so as to ensure that the second output module 40 continues to respond to the low-level signal of the third node N3.
  • the second potential signal VGL is transmitted to the second output terminal O2, so that the second output signal OUT is a low-level signal, so as to reduce the level loss of the low-level signal output by the second output terminal O2.
  • the third transistor M3 is turned on in response to the low level signal of the third node N3, and transmits the second clock signal CLK2 to the fifth node N5 between the third transistor M3 and the fourth transistor M4 when turned on.
  • the fourth transistor M4 is turned on in response to the low level signal of the first output terminal O1, and transmits the first potential signal VGH to the fifth node N5 when turned on.
  • the potential of the third node N3 is at a low potential
  • the potential of the first output terminal O1 is at a high potential
  • the fourth transistor M4 is turned off
  • the third transistor M3 is turned on
  • the The second clock signal CLK2 is transmitted to the fifth node N5, so that the potential of the fifth node N5 is at a high potential, the two ends of the second capacitor C2 form a potential difference, and the second capacitor C2 is charged.
  • the second clock signal CLK2 jumps from the first potential to the second potential, the potential of the third node N3 is close to the low potential, the third transistor M3 continues to be turned on, and turns the The second clock signal CLK2 is transmitted to the fifth node N5, so that the potential of the fifth node N5 changes from a high potential to a low potential.
  • the second capacitor C2 can couple the potential of the third node N3 to a low potential
  • the extremely low level of the low level ensures that the second output module 40 continues to transmit the second level signal VGL to the second output terminal O2 in response to the low level signal of the third node N3, so that the second output signal OUT is low level level signal, so as to reduce the level loss of the low level signal output by the second output terminal O2.
  • FIG. 5 is a schematic structural diagram of a module of another shift register provided by an embodiment of the present application.
  • the first input module 10 is set to include a fifth transistor M5, and the gate of the fifth transistor M5 is input The first clock signal CLK1, the first pole of the fifth transistor M5 is input with the first start signal IN, and the second pole of the fifth transistor M5 is connected to the first node N1;
  • the second input module 20 includes a sixth transistor M6, the sixth transistor M6
  • the gate of the sixth transistor M6 is input with the first clock signal CLK1, the first electrode of the sixth transistor M6 is input with the second start signal INB, and the second electrode of the sixth transistor M6 is connected to the second node N2.
  • the fifth transistor M5 can be turned on in response to the low level signal of the first clock signal CLK1, and when turned on, transmits the first start signal IN to the first node N1, so that the potential of the first node N1 is the same as that of the first start signal.
  • the potential of the signal IN is the same, and the signal output by the first output terminal O1 of the first output module 30 is controlled by controlling the potential of the first node N1.
  • the sixth transistor M6 can be turned on in response to the low level signal of the first clock signal CLK1, and when turned on, transmits the second start signal INB to the second node N2, so that the potential of the second node N2 is the same as that of the second node N2.
  • the potential of the start signal INB is the same, and the signal output by the first output terminal O1 of the first output module 30 is controlled by controlling the potential of the second node N2.
  • FIG. 6 is a schematic diagram of a module structure of another shift register provided by an embodiment of the present application.
  • the first output module 30 is set to include a first output unit 31 and a second output unit 32;
  • An output unit 31 is configured to be turned on or off according to the potential of the first node N1, and transmits the first potential signal VGH to the first output terminal O1 when it is turned on;
  • the second output unit 32 is configured to be turned on or off according to the second node
  • the potential of N2 is turned on or off, and when it is turned on, the second potential signal VGL is transmitted to the first output terminal O1 of the shift register.
  • the first output unit 31 may be turned on in response to the low-level signal of the first node N1, and transmit the first potential signal VGH to the first output terminal O1 when turned on.
  • the second output unit 32 can be turned on in response to the low-level signal of the second node N2, and transmits the second potential signal VGL to the first output terminal O1 when turned on.
  • the advantage of this setting is that the potential of the first node N1 can be controlled by adjusting the pulse width of the first start signal IN in combination with the first clock signal CLK1, thereby adjusting the pulse width of the first potential signal VGH output by the first output terminal O1 , and the pulse width of the second start signal INB depends on the pulse width of the first start signal IN.
  • this scheme can also control the second node N2 by adjusting the pulse width of the first start signal IN and combining with the first clock signal CLK1. and adjust the pulse width of the second potential signal VGL output by the first output terminal O1, so that the output signal of the first output terminal O1 of the shift register is a pulse signal with adjustable pulse width.
  • the first output unit 31 is set to include a seventh transistor M7, the gate of the seventh transistor M7 is connected to the first node N1, the first electrode of the seventh transistor M7 is input with the first potential signal VGH, and the seventh transistor M7 is connected to the first potential signal VGH.
  • the second pole of the transistor M7 is connected to the first output terminal O1;
  • the second output unit 32 includes an eighth transistor M8, the gate of the eighth transistor M8 is connected to the second node N2, and the first pole of the eighth transistor M8 is input with the second potential signal VGL, the second pole of the eighth transistor M8 is connected to the first output terminal O1.
  • the seventh transistor M7 may be turned on in response to the low-level signal of the first node N1, and transmit the first potential signal VGH to the first output terminal O1 when turned on.
  • the eighth transistor M8 may be turned on in response to the low-level signal of the second node N2, and transmit the second potential signal VGL to the first output terminal O1 when turned on.
  • the first potential signal VGH and the second potential signal VGL are alternately transmitted to the first output terminal O1, so that the first output of the shift register
  • the output signal of the terminal O1 forms a pulse signal with an adjustable pulse width.
  • FIG. 7 is a schematic structural diagram of a shift register provided by an embodiment of the present application
  • FIG. 8 is a schematic structural diagram of another shift register provided by an embodiment of the present application.
  • the second output module 40 is set to include a third output unit 41 and a fourth output unit 42; the third output unit 41 is set to be turned on or off according to the potential of the third node N3, and when it is turned on, the second potential signal VGL is transmitted to the second output terminal O2; the fourth output unit 42 is set to be turned on or off according to the potential of the first output terminal O1, and transmits the first potential signal VGH to the second output terminal of the shift register when it is turned on.
  • Output O2 is a schematic structural diagram of a shift register provided by an embodiment of the present application
  • the second output module 40 is set to include a third output unit 41 and a fourth output unit 42; the third output unit 41 is set to be turned on or off according to the potential of the third node N3, and when it is turned on, the second potential signal VGL is
  • the third output unit 41 may be turned on in response to the low-level signal of the third node N3, and transmit the second potential signal VGL to the second output terminal O2 when turned on.
  • the fourth output unit 42 can be turned on in response to the low-level signal of the first output terminal O1, and transmits the first potential signal VGH to the second output terminal O2 of the shift register when it is turned on.
  • the advantage of this setting is that the pulse width of the output signal of the first output terminal O1 can be adjusted by adjusting the pulse width of the first start signal IN, and then the pulse width of the first potential signal VGH output by the second output terminal O2 can be adjusted.
  • the potential of the third node N3 is the same as the potential of the first node N1.
  • the potential of the third node N3 can be controlled, thereby adjusting the output of the second output terminal O2.
  • the pulse width of the second potential signal VGL, so that the output signal of the second output terminal O2 of the shift register is a pulse signal with an adjustable pulse width.
  • the third output unit 41 is set to include a ninth transistor M9, the gate of the ninth transistor M9 is connected to the third node N3, and the first electrode of the ninth transistor M9 is input with the second potential signal VGL , the second pole of the ninth transistor M9 is connected to the second output terminal O2;
  • the fourth output unit 42 includes a tenth transistor M10, the gate of the tenth transistor M10 is connected to the first output terminal O1, and the first pole of the tenth transistor M10 is input For the first potential signal VGH, the second pole of the tenth transistor M10 is connected to the second output terminal O2.
  • the ninth transistor M9 may be turned on in response to the low level signal of the third node N3, and transmit the second potential signal VGL to the second output terminal O2 when turned on.
  • the tenth transistor M10 may be turned on in response to the low-level signal of the first output terminal O1, and transmit the first potential signal VGH to the second output terminal O2 when turned on.
  • the first potential signal VGH and the second potential signal VGL are alternately transmitted to the second output terminal O2, so that the second output of the shift register
  • the output signal of the terminal O2 forms a pulse signal with an adjustable pulse width.
  • the fourth output unit 42 is configured to further include a third capacitor C3, the first end of the third capacitor C3 is connected to the first pole of the tenth transistor M10, and the second end of the third capacitor C3 is connected to the tenth transistor M10 gate of transistor M10.
  • the third capacitor C3 can play the role of maintaining the gate potential of the tenth transistor M10, for example, during the period when the second output terminal O2 of the shift register outputs a high-level signal, the gate potential of the tenth transistor M10 is maintained as A low potential is used to ensure that the tenth transistor M10 transmits the first potential signal VGH to the second output terminal O2 when it is turned on.
  • the set shift register further includes an eleventh transistor M11, the eleventh transistor M11 is connected between the first node N1 and the third node N3, and the gate of the eleventh transistor M11 is The second potential signal VGL is input to the pole.
  • the eleventh transistor M11 may be in a normally-on state in response to the second potential signal VGL.
  • the eleventh transistor M11 when entering the fourth stage t4 from the third stage t3 , the second clock signal CLK2 jumps from the first potential to the first potential Two potentials, the second output control module 60 can couple the potential of the third node N3 to a very low potential lower than the low potential.
  • the eleventh transistor M11 is provided to help block the extremely low potential of the third node N3. The electric potential of the third node N3 is prevented from being transmitted to the first node N1, thereby affecting the normal operation of the shift register.
  • the driving timing diagram of the shift register shown in FIG. 2 can also be used to drive the shift registers shown in FIG. 7 and FIG. 8 to work.
  • the working principle of the shift register provided by the embodiment of the present application will be described below with reference to FIG. 2 , FIG. 7 , and FIG. 8 .
  • the working process of the shift register includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5 and a sixth stage t6.
  • the first clock signal CLK1 is at a low level
  • the second clock signal CLK2 is at a high level
  • the first start signal IN is at a high level
  • the second start signal INB is at a low level.
  • the fifth transistor M5 and the sixth transistor M6 are turned on, the eleventh transistor M11 is always turned on, and the fifth transistor M5 transmits the first start signal IN to the first node N1, so that the potential of the first node N1 is a high potential
  • the first The potential of the three nodes N3 is the same as that of the first node N1, and the sixth transistor M6 transmits the second start signal INB to the second node N2, so that the potential of the second node N2 is low.
  • the second transistor M2, the seventh transistor M7, the third transistor M3 and the ninth transistor M9 are turned off, and the first transistor M1 and the eighth transistor M8 are turned on.
  • the first transistor M1 transmits the second clock signal CLK2 to the fourth node N4 so that the potential of the fourth node N4 is a high potential.
  • the two ends of the first capacitor C1 form a potential difference, and the first capacitor C1 is charged.
  • the eighth transistor M8 transmits the second potential signal VGL to the first output terminal O1, so that the first output signal OUTB is a low level signal.
  • the fourth transistor M4 and the tenth transistor M10 are turned on, the fourth transistor M4 transmits the first potential signal VGH to the fifth node N5, so that the potential of the fifth node N5 is at a high potential, and the tenth transistor M10 transmits the first potential signal VGH to the fifth node N5.
  • VGH is transmitted to the second output terminal O2, so that the second output signal OUT is a high level signal.
  • the first output signal OUTB is consistent with the second start signal INB
  • the second output signal OUT is consistent with the first start signal IN.
  • the first clock signal CLK1 is at a high level
  • the second clock signal CLK2 jumps from a high level to a low level
  • the first start signal IN is at a low level
  • the second start signal INB is at a high level flat.
  • the fifth transistor M5 and the sixth transistor M6 are turned off, the potential of the first node N1 is high
  • the potential of the third node N3 is the same as that of the first node N1, and the potential of the second node N2 is low.
  • the second transistor M2, the seventh transistor M7, the third transistor M3 and the ninth transistor M9 are turned off, and the first transistor M1 and the eighth transistor M8 are turned on.
  • the first transistor M1 transmits the second clock signal CLK2 to the fourth node N4, so that the potential of the fourth node N4 changes from a high potential to a low potential. Due to the coupling effect of the first capacitor C1, the first capacitor C1 can connect the second node.
  • the potential of N2 is coupled to a very low potential lower than the low potential, so as to increase the degree of conduction of the eighth transistor M8, so that the eighth transistor M8 is fully turned on, so as to ensure that the eighth transistor M8 transmits the second potential signal VGL to the first
  • the output terminal O1 makes the first output signal OUTB a low level signal.
  • the fourth transistor M4 and the tenth transistor M10 are turned on, the fourth transistor M4 transmits the first potential signal VGH to the fifth node N5, so that the potential of the fifth node N5 is at a high potential, and the tenth transistor M10 transmits the first potential signal VGH to the fifth node N5.
  • VGH is transmitted to the second output terminal O2, so that the second output signal OUT is a high level signal.
  • the first output signal OUTB is still consistent with the second start signal INB
  • the second output signal OUT is still consistent with the first start signal IN.
  • the first clock signal CLK1 is at a low level
  • the second clock signal CLK2 is at a high level
  • the first start signal IN is at a low level
  • the second start signal INB is at a high level.
  • the fifth transistor M5 and the sixth transistor M6 are turned on, and the fifth transistor M5 transmits the first start signal IN to the first node N1, so that the potential of the first node N1 is a low potential
  • the potential of the third node N3 is the same as that of the first node N1.
  • the potential of N1 is the same
  • the sixth transistor M6 transmits the second start signal INB to the second node N2, so that the potential of the second node N2 is a high potential.
  • the first transistor M1 and the eighth transistor M8 are turned off, and the second transistor M2, the seventh transistor M7, the third transistor M3 and the ninth transistor M9 are turned on.
  • the seventh transistor M7 transmits the first potential signal VGH to the first output terminal O1, so that the first output signal OUTB is a high level signal, and the fourth transistor M4 and the tenth transistor M10 are turned off.
  • the third transistor M3 transmits the second clock signal CLK2 to the fifth node N5 so that the potential of the fifth node N5 is a high potential.
  • the two ends of the second capacitor C2 form a potential difference, and the second capacitor C2 is charged.
  • the ninth transistor M9 transmits the second potential signal VGL to the second output terminal O2, so that the second output signal OUT is a low level signal.
  • the first output signal OUTB is inverted, which is consistent with the inverted second start signal INB, and the second output signal OUT is inverted, which is consistent with the inverted first start signal IN .
  • the first start signal IN is kept at a low level
  • the second start signal INB is kept at a high level.
  • the fifth transistor M5 and the sixth The transistor M6 is turned off, the potential of the first node N1 is a low potential, the potential of the third node N3 is the same as that of the first node N1, and the potential of the second node N2 is a high potential.
  • the first transistor M1 and the eighth transistor M8 are turned off, and the second transistor M2, the seventh transistor M7, the third transistor M3 and the ninth transistor M9 are turned on.
  • the seventh transistor M7 continues to transmit the first potential signal VGH to the first output terminal O1, so that the first output signal OUTB is a high level signal, and the fourth transistor M4 and the tenth transistor M10 are turned off.
  • the third transistor M3 transmits the second clock signal CLK2 to the fifth node N5, so that the potential of the fifth node N5 jumps from a high potential to a low potential.
  • the second capacitor C2 can couple the potential of the third node N3 to a very low potential lower than the low potential, so as to increase the degree of conduction of the ninth transistor M9 and make the ninth transistor M9 fully is turned on, thereby ensuring that the ninth transistor M9 transmits the second potential signal VGL to the second output terminal O2, so that the second output signal OUT is a low-level signal.
  • the low-level signal output by the second output terminal O2 becomes lower.
  • the third transistor M3, the fourth transistor M4 and the The second output control module 60 formed by the second capacitor C2 can reduce the level loss of the low-level signal output by the second output terminal O2 in the third stage t3, which is beneficial to prolong the low level of the output signal of the shift register. time.
  • the first output signal OUTB remains a high-level signal
  • the second output signal OUT remains a low-level signal.
  • the first clock signal CLK1 is at a low level
  • the second clock signal CLK2 is at a high level
  • the first start signal IN is at a high level
  • the second start signal INB is at a low level.
  • the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the remaining transistors are turned off.
  • the potentials of the first node N1 and the third node N3 are high potentials
  • the potentials of the second node N2 are low potentials
  • the potentials of the fourth node N4 are high potentials.
  • the two ends of the first capacitor C1 form a potential difference, and the first capacitor C1 is charged.
  • the eighth transistor M8 transmits the second potential signal VGL to the first output terminal O1, so that the first output signal OUTB is a low level signal.
  • the tenth transistor M10 transmits the first potential signal VGH to the second output terminal O2, so that the second output signal OUT is a high-level signal.
  • the first output signal OUTB is inverted, which is consistent with the inverted second start signal INB, and the second output signal OUT is inverted, which is consistent with the inverted first start signal IN .
  • the first start signal IN is kept at a high level
  • the second start signal INB is kept at a low level.
  • the fifth transistor M5 and the sixth The transistor M6 is turned off, the potential of the first node N1 is high, the potential of the third node N3 is the same as the potential of the first node N1, and the potential of the second node N2 is low.
  • the second transistor M2, the seventh transistor M7, the third transistor M3 and the ninth transistor M9 are turned off, and the first transistor M1 and the eighth transistor M8 are turned on.
  • the first transistor M1 transmits the second clock signal CLK2 to the fourth node N4, so that the potential of the fourth node N4 changes from a high potential to a low potential.
  • the first capacitor C1 can connect the second node
  • the potential of N2 is coupled to a very low potential lower than the low potential, so as to increase the degree of conduction of the eighth transistor M8, so that the eighth transistor M8 is fully turned on, thereby ensuring that the eighth transistor M8 transmits the second potential signal VGL to the first
  • the output terminal O1 makes the first output signal OUTB a low level signal. As shown in FIG. 2, after entering the sixth stage t6 from the fifth stage t5, the low-level signal output by the first output terminal O1 becomes lower.
  • the first transistor M1, the second transistor M2 and the The first output control module 50 formed by the first capacitor C1 can reduce the level loss of the low-level signal output by the first output terminal O1 in the fifth stage t5, which is beneficial to prolong the low level of the output signal of the shift register. time.
  • the fourth transistor M4 and the tenth transistor M10 are turned on, the fourth transistor M4 transmits the first potential signal VGH to the fifth node N5, so that the potential of the fifth node N5 is high, and the tenth transistor M4 transmits the first potential signal VGH to the fifth node N5.
  • M10 transmits the first potential signal VGH to the second output terminal O2, so that the second output signal OUT is a high-level signal.
  • the first output signal OUTB is kept consistent with the second start signal INB
  • the second output signal OUT is kept consistent with the first start signal IN.
  • Five transistors M5, the sixth transistor M6 in the second input module 20, the seventh transistor M7 in the first output unit 31, the eighth transistor M8 in the second output unit 32, the ninth transistor in the third output unit 41 M9, the tenth transistor M10 and the eleventh transistor M11 in the fourth output unit 42 can all be thin film transistors
  • the display panel further includes a pixel circuit composed of thin film transistors, and a plurality of transistors in the shift register can be combined with the pixel circuit
  • the transistors in the device are fabricated in the same process flow, which helps to simplify the fabrication process of the display panel.
  • FIG. 9 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present application.
  • the gate drive circuit includes a plurality of shift registers 100 connected in cascade; the first stage shift register 100
  • the first start signal input terminal I1 of the An output terminal O1 is electrically connected to the second start signal input terminal I2 of the shift register 100 of the next stage, and the second output terminal O2 of the shift register 100 of the first stage is electrically connected to the first start signal of the shift register 100 of the next stage.
  • the input terminal I1 is electrically connected.
  • the gate driving circuit includes a plurality of shift registers 100 connected in cascade, and the shift register in this embodiment can realize the shift output of the first start signal IN to obtain the second output signal OUT , shift and output the second start signal INB to obtain the first output signal OUTB. Therefore, when the shift register is applied to the gate drive circuit, the second output signal OUT output by the shift register at this stage can also be used as the lower
  • the first start signal IN input by the first stage shift register, and the first output signal OUTB output by the current stage shift register can also be used as the second start signal INB input by the next stage shift register, which is helpful for the current stage shift register.
  • the output signal of the bit register is passed to the next stage shift register. And through the first output control module 50 and the second output control module 60 in the shift register, the low level loss of the output signal of the shift register can also be reduced, thereby reducing the transfer of the current stage shift register to the next stage shift register. level loss of the valid signal.
  • the gate driving circuit provided by the embodiment of the present application includes the shift register provided by any of the above-mentioned embodiments of the present application. Therefore, the gate driving circuit has corresponding functional modules and effects of the shift register, which will not be repeated here.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 200 includes the gate driving circuit provided by the above embodiment. , and also includes: a first clock signal line 210, a second clock signal line 220, a first potential signal line 230 and a second potential signal line 240; the first clock signal line 210 is configured to transmit the first clock signal to the shift register 100 CLK1; the second clock signal line 220 is set to transmit the second clock signal CLK2 to the shift register 100; the first potential signal line 230 is set to transmit the first potential signal VGH to the shift register 100; the second potential signal line 240 is set to The second potential signal VGL is transmitted to the shift register 100 .
  • the display panel may be, for example, an organic light emitting diode display panel or a liquid crystal display panel or the like.
  • the display panel may further include a first start signal line configured to transmit the first start signal IN to the first stage shift register 100 in the gate driving circuit, and the shift register may also receive the signal through its internal structure according to the received signal.
  • the first start signal IN of the first start signal IN generates the inverse signal of the first start signal IN to obtain the second start signal INB, and the second start signal INB is input to the second start signal input terminal of the first stage shift register 100 i2.
  • the first stage shift register can shift and output the first start signal IN and the second start signal INB to the next stage shift register.
  • the signal output by the first stage of the shift register is shifted and output, and the output signal of the second output terminal O2 of each stage of the shift register can be used as the gate driving signal of the transistor of the pixel circuit in the display panel. Therefore, the display panel provided by the embodiments of the present application realizes the function of outputting the gate driving signal row by row (for example, the gate driving signal may be a scanning signal or a light-emitting control signal), and the pulse of the gate driving signal output by the multi-stage shift register is The width is adjustable and the stability is good.
  • the display panel provided by the embodiment of the present application includes the gate driving circuit and the shift register in the gate driving circuit provided by any of the above-mentioned embodiments of the present application. Therefore, the display panel has the gate driving circuit and the shift register in the gate driving circuit. The corresponding functional modules and effects of the bit register will not be repeated here.
  • FIG. 11 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application, and FIG. 11 schematically shows a situation where the pixel circuit includes seven thin film transistors and one storage capacitor.
  • the display panel 200 further includes a light-emitting control signal line 250 , the second output end O2 of the shift register 100 is connected to the light-emitting control signal line 250 , and the second output end O2 of the shift register 100 outputs The signal is used as the light-emitting control signal EM.
  • the pixel circuit in the display panel is connected to the light-emitting device D1, and the pixel circuit may include a storage capacitor Cst, a driving transistor DT, a first initialization transistor T1 configured to transmit an initialization signal Vref to the gate G of the driving transistor DT, and a first initialization transistor T1 configured to transmit the initialization signal Vref to the gate G of the driving transistor DT.
  • the anode of the device D1 transmits the second initialization transistor T2 of the initialization signal Vref, the data write transistor T3 set to write the data voltage Vdata into the storage capacitor Cst, the threshold compensation transistor T4 set to perform threshold voltage compensation on the drive transistor DT, and the set
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to control the light-emitting stage of the light-emitting device D1.
  • the light emission control signal line 250 is arranged to transmit the light emission control signal EM to the gates of the first light emission control transistor T5 and the second light emission control transistor T6. 1 , 10 and 11 , when the pulse width of the first start signal IN of the shift register is set to be greater than the pulse width of the first clock signal CLK1 and the second clock signal CLK2 , the shift register can The start signal IN is shifted and output to obtain the second output signal OUT, and the second start signal INB is shifted and output to obtain the first output signal OUTB.
  • the pulse widths of the first output signal OUTB and the second output signal OUT of the shift register are larger than the pulse width of the clock signal, and the first output signal output by the shift register is reduced by the first output control module 50 .
  • the low-level loss of OUTB reduces the low-level loss of the second output signal OUT output by the shift register through the second output control module 60, which is beneficial to prolong the low-level time of the output signal of the shift register and improve the shift register.
  • the stability of the output signal of the bit register When the output signal of the shift register is used as the gate driving signal of the light-emitting control transistor in the pixel circuit, it is also helpful to improve the display effect.
  • FIG. 12 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the display panel 200 further includes a scan line 260 , and the second output end O2 of the shift register 100 is connected to the scan line 260 .
  • Line 260, the signal output by the second output terminal O2 of the shift register 100 is used as a scan signal.
  • the scan line 260 is arranged to provide scan signals to gates of transistors in the pixel circuit, for example, to the gates of the first initialization transistor T1 and the second initialization transistor T2.
  • the display panel 200 includes a pixel circuit
  • the pixel circuit includes a driving transistor DT, a light-emitting device D1, a first initialization transistor T1 and a second initialization transistor T2, the first initialization transistor T1 is set to drive The potential of the gate G of the transistor DT is initialized, and the second initializing transistor T2 is set to initialize the anode of the light emitting device D1; the scan line 260 is connected to the gates of the first initializing transistor T1 and/or the second initializing transistor T2.
  • the pulse width of the first start signal IN of the shift register is set to be greater than the pulse width of the first clock signal CLK1 and the second clock signal CLK2, compared with the related art, the first output of the shift register provided by the embodiment of the present application
  • the pulse widths of the signal OUTB and the second output signal OUT are larger than that of the clock signal, and can also reduce the low level loss of the output signal of the shift register, which is beneficial to prolong the low level time of the output signal of the shift register.
  • the signal output by the second output terminal O2 of the shift register is used as the scanning signal for driving the first initialization transistor T1 and the second initialization transistor T2
  • FIG. 13 is a schematic structural diagram of a shift register in the related art.
  • the gate driving circuit in the display panel is configured to include the multiple methods provided in any of the above-mentioned embodiments of the present application.
  • the cascade-connected shift registers 100 may also include a shift register 300 in the related art.
  • the second output terminal O2 of the shift register 100 and the output terminal Gout of the shift register 300 can both be connected to the scan line 260, the shift register 100 is connected to the first scan line 261, and the first scan line 261 can be connected to the pixel circuit in the pixel circuit.
  • the gate of the first initialization transistor T1 transmits the first scan signal Scan1, or the third scan signal Scan3 may also be transmitted to the gate of the second initialization transistor T2 in the pixel circuit.
  • the output terminal Gout of the shift register 300 is connected to the second scan line 262, and the second scan line 262 can transmit the second scan signal Scan2 to the gates of the data writing transistor T3 and the threshold compensation transistor T4 in the pixel circuit.
  • the shift register 300 includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M18.
  • the shift register 300 has one input signal SIN and one output second scan signal Scan2.
  • the effective signal pulse width output by the output terminal Gout of the shift register 300 in the related art generally depends on the effective signal pulse width of the first clock signal CLK1 and the second clock signal CLK2.
  • the effective signal pulse width of the first clock signal CLK1 and the second clock signal CLK2 After setting the first start signal IN of the shift register 100 When the effective signal pulse width is greater than the effective signal pulse width of the first clock signal CLK1 and the second clock signal CLK2, the effective signal pulse width output by the second output end O2 of the shift register 100 is greater than that output by the output end Gout of the shift register 300 Therefore, the effective pulse width of the output signal of the shift register 100 is no longer limited by the line scanning time of the display panel.
  • the shift register 100 When driving the pixel circuit in the display panel to work, the shift register 100 provided in the embodiment of the present application can be used in conjunction with the shift register 300 in the related art, so that the signal output by the second output end O2 of the shift register 100 is used as the driving signal
  • the first scan signal Scan1 for the first initialization transistor T1 to work, and/or the third scan signal 263 for driving the second initialization transistor T2 to work, and the signal output from the output terminal Gout of the shift register 300 is used as the driving data to write the transistor T3 and the second scan signal Scan2 for the threshold compensation transistor T4 to work.
  • the advantage of this setting is that, on the one hand, the shift register 300 can drive the data writing transistor T3 and the threshold compensation transistor T4 to work normally; on the other hand, since the pulse width of the output signal of the shift register 100 is adjustable,
  • the signal output by the second output terminal O2 of the register 100 is used as the first scan signal Scan1 and/or the third scan signal Scan3, which is beneficial to prolong the initialization time of the gate of the driving transistor and the anode of the light-emitting device, thereby reducing the problem of insufficient initialization time.
  • the resulting display screen has problems such as afterimage and abnormal display, which helps to improve the display effect.
  • the scan line 260 connected to the second output terminal O2 of the shift register 100 can be simultaneously connected to the initialization transistors (including the first initialization transistor T1 and/or the second initialization transistor T2) in the pixel circuits of multiple rows, so that the display panel can Simultaneously initialize several rows of pixel circuits without causing logic errors, and the wide pulse signal output by the second output terminal O2 of the shift register 100 is no longer limited by the row scanning time of the pixel circuits.

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Abstract

一种移位寄存器、栅极驱动电路和显示面板，移位寄存器包括：第一输入模块（10）、第二输入模块（20）、第一输出模块（30）、第二输出模块（40）、第一输出控制模块（50）和第二输出控制模块（60）；第一输入模块（10）设置为根据第一起始信号（IN）和第一时钟信号（CLK1）控制第一节点（N1）的电位；第二输入模块（20）设置为根据第二起始信号（INB）和第一时钟信号（CLK1）控制第二节点（N2）的电位；第一输出控制模块（50）设置为控制第二节点（N2）的电位；第一输出模块（30）设置为根据第一节点（N1）的电位和第二节点（N2）的电位将第一电位信号（VGH）或第二电位信号（VGL）传输至移位寄存器的第一输出端（O1）；第二输出控制模块（60）设置为控制第三节点（N3）的电位；第二输出模块（40）设置为根据第一输出端（O1）的电位和第三节点（N3）的电位将第一电位信号（VGH）或第二电位信号（VGL）传输至移位寄存器的第二输出端（O2）。

Description

移位寄存器、栅极驱动电路和显示面板
本申请要求在2021年01月29日提交中国专利局、申请号为202110127280.2的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种移位寄存器、栅极驱动电路和显示面板。
背景技术
随着显示技术的发展，人们对于显示面板的性能要求越来越高。
显示面板通常包括栅极驱动电路，栅极驱动电路包括多个级联的移位寄存器，移位寄存器的结构存在输出信号不稳定以及输出信号的脉宽较短等问题，影响了显示面板的显示效果。
发明内容
本申请提供一种移位寄存器、栅极驱动电路和显示面板，以实现延长移位寄存器输出的有效信号的脉宽，并提升移位寄存器的输出信号的稳定性。
本申请提供了一种移位寄存器，包括：第一输入模块、第二输入模块、第一输出模块、第二输出模块、第一输出控制模块和第二输出控制模块；
所述第一输入模块设置为根据第一起始信号和第一时钟信号控制第一节点的电位；所述第二输入模块设置为根据第二起始信号和所述第一时钟信号控制第二节点的电位，所述第二起始信号与所述第一起始信号的电位相反；
所述第一输出控制模块设置为根据所述第一节点的电位、第一电位信号和第二时钟信号控制所述第二节点的电位；所述第一输出模块设置为根据所述第一节点的电位和所述第二节点的电位将所述第一电位信号或第二电位信号传输至所述移位寄存器的第一输出端；
所述第二输出控制模块设置为根据所述第一输出端的电位、所述第一电位信号和所述第二时钟信号控制第三节点的电位，所述第三节点与所述第一节点连接；所述第二输出模块设置为根据所述第一输出端的电位和所述第三节点的电位将所述第一电位信号或所述第二电位信号传输至所述移位寄存器的第二输出端。
本申请实施例还提供了一种栅极驱动电路，包括多个上述的移位寄存器，所述多个移位寄存器级联连接；
第一级移位寄存器的第一起始信号输入端设置为接入第一起始信号，所述第一级移位寄存器的第二起始信号输入端设置为接入第二起始信号，所述第一级移位寄存器的第一输出端与下一级移位寄存器的第二起始信号输入端电连接，所述第一级移位寄存器的第二输出端与所述下一级移位寄存器的第一起始信号输入端电连接。
本申请还提供一种显示面板，包括上述的栅极驱动电路，还包括：第一时钟信号线、第二时钟信号线、第一电位信号线和第二电位信号线；
所述第一时钟信号线设置为向所述移位寄存器传输第一时钟信号；所述第二时钟信号线设置为向所述移位寄存器传输第二时钟信号；所述第一电位信号线设置为向所述移位寄存器传输第一电位信号；所述第二电位信号线设置为向所述移位寄存器传输第二电位信号。
本申请提供的移位寄存器、栅极驱动电路和显示面板，实现了通过调整第一起始信号的有效信号的脉宽来调整移位寄存器的第一输出端和第二输出端的输出信号的有效信号的脉宽，在设置第一起始信号的有效信号的脉宽大于第一时钟信号和第二时钟信号的有效信号的脉宽时，移位寄存器的输出信号的有效信号的脉宽也大于时钟信号的有效信号的脉宽，并且通过第一输出控制模块和第二输出控制模块还能减少移位寄存器的输出信号的电平损失。与现有技术相比，本申请的技术方案能够延长移位寄存器输出的有效信号的脉宽，并提升移位寄存器的输出信号的稳定性。当移位寄存器的输出信号作为对驱动晶体管的栅极和发光器件的阳极进行初始化的晶体管的栅极驱动信号时，能够增加驱动晶体管的栅极和发光器件的阳极的初始化时间，从而减轻由初始化时间不充足带来的显示画面出现残影及显示异常等问题，有助于提升显示效果。另外，由于该移位寄存器的输出信号的有效信号的脉宽较宽，并且输出信号的稳定性较好，该移位寄存器的输出信号还可作为发光控制晶体管的栅极驱动信号，同样有助于提升显示效果。
附图说明
图1是本申请实施例提供的一种移位寄存器的模块结构示意图；
图2是本申请实施例提供的一种移位寄存器的驱动时序图；
图3是本申请实施例提供的另一种移位寄存器的模块结构示意图；
图4是本申请实施例提供的另一种移位寄存器的模块结构示意图；
图5是本申请实施例提供的另一种移位寄存器的模块结构示意图；
图6是本申请实施例提供的另一种移位寄存器的模块结构示意图；
图7是本申请实施例提供的一种移位寄存器的结构示意图；
图8是本申请实施例提供的另一种移位寄存器的结构示意图；
图9是本申请实施例提供的一种栅极驱动电路的模块结构示意图；
图10是本申请实施例提供的一种显示面板的结构示意图；
图11是本申请实施例提供的一种像素电路的结构示意图；
图12是本申请实施例提供的另一种显示面板的结构示意图；
图13是相关技术中的一种移位寄存器的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。
正如背景技术所述，移位寄存器的结构存在输出信号不稳定以及输出信号的脉宽较短等问题，影响了显示面板的显示效果。出现上述问题的原因在于：显示面板包括发光器件和驱动发光器件工作的像素电路，像素电路包括驱动晶体管、对发光器件的阳极进行初始化的晶体管以及对驱动晶体管的栅极进行初始化的晶体管，由移位寄存器构成的栅极驱动电路能够向像素电路中的多个晶体管提供栅极驱动信号。相关技术中的移位寄存器的输出有效信号的脉宽通常取决于其输入的时钟信号的脉宽，显示面板工作在高刷新频率的工况下时，驱动像素电路工作的行扫描时间非常短，移位寄存器输入的时钟信号受限于行扫描时间，使得时钟信号的脉宽较短，进而导致移位寄存器的输出信号也是短脉冲信号，因此像素电路中的初始化晶体管的栅极驱动信号的脉宽也较短，这样一方面会导致发光器件的初始化时间不足，使显示画面出现残影，另一方面会导致驱动晶体管栅极的初始化时间不足，从而引起显示画面显示不均，甚至出现显示异常。并且，相关技术中的移位寄存器的输出信号不稳定，存在电平损失问题，同样会影响显示面板的显示效果。
本申请实施例提供了一种移位寄存器。图1是本申请实施例提供的一种移位寄存器的模块结构示意图，如图1所示，该移位寄存器包括：第一输入模块10、第二输入模块20、第一输出模块30、第二输出模块40、第一输出控制模块50和第二输出控制模块60；第一输入模块10设置为根据第一起始信号IN和第一时钟信号CLK1控制第一节点N1的电位；第二输入模块20设置为根据第二起始信号INB和第一时钟信号CLK1控制第二节点N2的电位，第二起始信号 INB与第一起始信号IN的电位相反；第一输出控制模块50设置为根据第一节点N1的电位、第一电位信号VGH和第二时钟信号CLK2控制第二节点N2的电位；第一输出模块30设置为根据第一节点N1的电位和第二节点N2的电位将第一电位信号VGH或第二电位信号VGL传输至移位寄存器的第一输出端O1；第二输出控制模块60设置为根据第一输出端O1的电位、第一电位信号VGH和第二时钟信号CLK2控制第三节点N3的电位，第三节点N3与第一节点N1连接；第二输出模块40设置为根据第一输出端O1的电位和第三节点N3的电位将第一电位信号VGH或第二电位信号VGL传输至移位寄存器的第二输出端O2。
第一起始信号IN可以是脉宽可调的脉冲信号，例如第一起始信号IN的有效信号的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的有效信号的脉宽。第二起始信号INB与第一起始信号IN的电位相反，例如第一起始信号IN为低电平时，第二起始信号INB为高电平，或者，第一起始信号IN为高电平时，第二起始信号INB为低电平。移位寄存器可通过其内部结构根据接收到的第一起始信号IN生成第一起始信号IN的反信号，以得到第二起始信号INB，例如移位寄存器中可包括反相器，移位寄存器可通过反相器得到第一起始信号IN的反信号，即第二起始信号INB，并将第二起始信号INB输入至第二输入模块20。
第一时钟信号CLK1、第二时钟信号CLK2、第一节点N1的电位信号、第二节点N2的电位信号、第三节点N3的电位信号和第一输出端O1的电位信号中的有效电平信号可以是低电平信号，也可以是高电平信号。第一电位信号VGH与第二电位信号VGL的电位相反，例如第一电位信号VGH为高电平信号时，第二电位信号VGL为低电平信号，或者第一电位信号VGH为低电平信号时，第二电位信号VGL为高电平信号。本实施例及下文的实施例中，均以第一时钟信号CLK1、第二时钟信号CLK2、第一节点N1的电位信号、第二节点N2的电位信号、第三节点N3的电位信号和第一输出端O1的电位信号中的有效电平信号为低电平信号，第一电位信号VGH为高电平信号，第二电位信号VGL为低电平信号为例进行示意性说明。
第三节点N3与第一节点N1连接，可以是直接电连接，也可以是间接电连接，本申请实施例在此不做限定。
第一输入模块10根据第一起始信号IN和第一时钟信号CLK1控制第一节点N1的电位，是指第一输入模块10能够响应于第一时钟信号CLK1的有效电平信号将第一起始信号IN传输至第一节点N1。第二输入模块20根据第二起始信号INB和第一时钟信号CLK1控制第二节点N2的电位，是指第二输入模块20能够响应于第一时钟信号CLK1的有效电平信号将第二起始信号INB传输至第二节点N2。
第一输出模块30根据第一节点N1的电位和第二节点N2的电位将第一电位信号VGH或第二电位信号VGL传输至移位寄存器的第一输出端O1，是指第一输出模块30能够响应于第一节点N1的有效电平信号将第一电位信号VGH传输至第一输出端O1，并响应于第二节点N2的有效电平信号将第二电位信号VGL传输至第一输出端O1。由于第一输入模块10能够根据第一起始信号IN和第一时钟信号CLK1控制第一节点N1的电位，第一节点N1的电位影响第一输出端O1输出第一电位信号VGH的时长，因此可通过调整第一起始信号IN的脉宽并结合第一时钟信号CLK1的控制来调整第一输出端O1输出的第一电位信号VGH的脉宽。由于第二输入模块20根据第二起始信号INB和第一时钟信号CLK1控制第二节点N2的电位，第二节点N2的电位影响第一输出端O1输出第二电位信号VGL的时长，因此可通过调整第二起始信号INB的脉宽并结合第一时钟信号CLK1的控制来调整第一输出端O1输出的第二电位信号VGL的脉宽。而第二起始信号INB的脉宽取决于第一起始信号IN的脉宽，因此，本实施例的方案能够通过调整第一起始信号IN的有效信号的脉宽来实现调整移位寄存器的第一输出端O1的输出信号的有效信号的脉宽，当设置第一起始信号IN的有效信号的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的有效信号的脉宽时，第一输出端O1的输出信号的有效信号的脉宽也大于第一时钟信号CLK1和第二时钟信号CLK2的有效信号的脉宽。
第一输出控制模块50根据第一节点N1的电位、第一电位信号VGH和第二时钟信号CLK2控制第二节点N2的电位，是指第一输出控制模块50能够在第二时钟信号CLK2的电位发生跳变时，根据第一节点N1的电位、第一电位信号VGH和第二时钟信号CLK2控制第二节点N2的电位，例如第一输出控制模块50能够将第二节点N2的电位下拉至相对于第二电位信号VGL所对应电位更低的电位。由于第一输出模块30可响应于第二节点N2的有效电平信号(如低电平信号)将第二电位信号VGL传输至第一输出端O1，若第二节点N2的电位不够低时(即第二节点N2的电位与第二电位信号VGL的差值的绝对值大于设定阈值时)，则第一输出模块30向第一输出端O1传输的第二电位信号VGL会出现电平损失。本实施例可通过设置第一输出模块30响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1时，利用第一输出控制模块50将第二节点N2的电位下拉至低于第二电位信号VGL的电位，以使第二节点N2的电位能够达到足够低的电位(该足够低的电位满足：第二节点N2的电位与第二电位信号VGL的差值的绝对值小于设定阈值)，从而减少第一输出端O1输出的低电平信号的电平损失。当第一输出模块30包括栅极连接第二节点N2、第一极接入第二电位信号VGL，第二极连接第一输出端O1的晶体管时，设定阈值可以等于该晶体管的阈值电压。
第二输出模块40根据第一输出端O1的电位和第三节点N3的电位将第一电位信号VGH或第二电位信号VGL传输至移位寄存器的第二输出端O2，是指第二输出模块40能够响应于第一输出端O1的有效电平信号将第一电位信号VGH传输至第二输出端O2，并响应于第三节点N3的有效电平信号将第二电位信号VGL传输至第二输出端O2。由于第一输出端O1的电位影响第二输出端O2输出第一电位信号VGH的时长，第一输出端O1的电位受到第一起始信号IN的控制，因此在通过调整第一起始信号IN的有效信号的脉宽来调整第一输出端O1的输出信号的有效信号的脉宽时，也能够调整第二输出端O2输出的第一电位信号VGH的脉宽。由于第三节点N3的电位影响第二输出端O2输出第二电位信号VGL的时长，第三节点N3的电位与第一节点N1的电位相同，且第一输入模块10能够根据第一起始信号IN和第一时钟信号CLK1控制第一节点N1的电位，因此在调整第一起始信号IN的脉宽时，也能够调整第二输出端O2输出的第二电位信号VGL的脉宽。因此，本实施例的方案能够通过调整第一起始信号IN的有效信号的脉宽来实现调整移位寄存器的第二输出端O2的输出信号的有效信号的脉宽，当设置第一起始信号IN的有效信号的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的有效信号的脉宽时，第二输出端O2的输出信号的有效信号的脉宽也大于第一时钟信号CLK1和第二时钟信号CLK2的有效信号的脉宽。
第二输出控制模块60根据第一输出端O1的电位、第一电位信号VGH和第二时钟信号CLK2控制第三节点N3的电位，是指第二输出控制模块60能够在第二时钟信号CLK2的电位发生跳变时，根据第一输出端O1的电位、第一电位信号VGH和第二时钟信号CLK2控制第三节点N3的电位，例如第二输出控制模块60能够将第三节点N3的电位下拉至相对于第二电位信号VGL所对应电位更低的电位。由于第二输出模块40可响应于第三节点N3的有效电平信号(如低电平信号)将第二电位信号VGL传输至第二输出端O2，若第三节点N3的电位不够低时(即第三节点N3的电位与第二电位信号VGL的差值的绝对值大于设定阈值时)，则第二输出模块40向第二输出端O2传输的第二电位信号VGL会出现电平损失。本实施例可通过设置第二输出模块40响应于第三节点N3的低电平信号将第二电位信号VGL传输至第二输出端O2时，利用第二输出控制模块60将第三节点N3的电位下拉至低于第二电位信号VGL的电位，以使第三节点N3的电位能够达到足够低的电位(该足够低的电位满足：第三节点N3的电位与第二电位信号VGL的差值的绝对值小于设定阈值)，从而减少第二输出端O2输出的低电平信号的电平损失。当第二输出模块40包括栅极连接第三节点N3、第一极接入第二电位信号VGL，第二极连接第二输出端O2的晶体管时，设定阈值可以等于该晶体管的阈值电压。
本申请实施例的技术方案，实现了通过调整第一起始信号的有效信号的脉宽来调整第一输出端和第二输出端的输出信号的有效信号的脉宽，在设置第一起始信号的有效信号的脉宽大于第一时钟信号和第二时钟信号的有效信号的脉宽时，移位寄存器的第一输出端和第二输出端的输出信号的有效信号的脉宽也大于时钟信号的有效信号的脉宽，并且通过第一输出控制模块和第二输出控制模块还能减少移位寄存器的输出信号的电平损失。相关技术中的移位寄存器的输出信号的脉宽取决于时钟信号的脉宽，与相关技术相比，本申请实施例的技术方案能够延长移位寄存器输出的有效信号的脉宽，并提升移位寄存器的输出信号的稳定性。本申请实施例提供的移位寄存器可应用于显示面板的栅极驱动电路中，通过移位寄存器向显示面板的像素电路中的晶体管提供栅极驱动信号，例如移位寄存器的第二输出端的输出信号可作为栅极驱动信号。当移位寄存器的输出信号作为像素电路中对驱动晶体管的栅极和发光器件的阳极进行初始化的晶体管的栅极驱动信号时，能够增加驱动晶体管的栅极和发光器件的阳极的初始化时间，从而减轻由初始化时间不充足带来的显示画面出现残影及显示异常等问题，有助于提升显示效果。另外，像素电路还包括对发光器件的发光阶段进行控制的发光控制晶体管，由于本方案的移位寄存器的输出信号的有效信号的脉宽较宽，并且输出信号的稳定性较好，该移位寄存器的输出信号还可作为发光控制晶体管的栅极驱动信号，同样有助于提升显示效果。
图2是本申请实施例提供的一种移位寄存器的驱动时序图，该驱动时序可用于驱动图1所示的移位寄存器，下面将结合图1和图2，对本申请实施例提供的移位寄存器的工作原理进行说明。示例性地，该移位寄存器的工作过程包括第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4、第五阶段t5和第六阶段t6。可选地，第一起始信号IN的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的脉宽。
在第一阶段t1，第一时钟信号CLK1为低电平，第二时钟信号CLK2为高电平，第一起始信号IN为高电平，第二起始信号INB为低电平。第一输入模块10响应于第一时钟信号CLK1的低电平信号将第一起始信号IN传输至第一节点N1，使得第一节点N1的电位为高电位。第二输入模块20响应于第一时钟信号CLK1的低电平信号将第二起始信号INB传输至第二节点N2，使得第二节点N2的电位为低电位。第一输出模块30响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB为低电平信号。第三节点N3的电位与第一节点N1的电位相同，为高电平。第二输出模块40响应于第一输出端O1的低电平信号将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第一阶段t1，第一输出信号OUTB与第二起始信号INB一致，第二输出信号OUT与第一起始信号IN一致。
在第二阶段t2，第一时钟信号CLK1为高电平，第二时钟信号CLK2由高电平跳变为低电平，第一起始信号IN为低电平，第二起始信号INB高电平。第一输入模块10停止传输第一起始信号IN，第一节点N1的电位保持为上一阶段的高电平。第二输入模块20停止传输第二起始信号INB，第二节点N2的电位保持为上一阶段的低电平。第一输出控制模块50在第二时钟信号CLK2发生跳变时，根据第一节点N1的电位、第一电位信号VGH和第二时钟信号CLK2将第二节点N2的电位下拉至低于低电平信号的电位，以保证第一输出模块30继续响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB仍为低电平信号。第三节点N3的电位与第一节点N1的电位相同，为高电平。第二输出模块40继续响应于第一输出端O1的低电平信号将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第二阶段t2，第一输出信号OUTB仍然与第二起始信号INB一致，第二输出信号OUT仍然与第一起始信号IN一致。
在第三阶段t3，第一时钟信号CLK1为低电平，第二时钟信号CLK2为高电平，第一起始信号IN为低电平，第二起始信号INB高电平。第一输入模块10将第一起始信号IN传输至第一节点N1，使得第一节点N1的电位为低电位。第二输入模块20将第二起始信号INB传输至第二节点N2，使得第二节点N2的电位为高电位。第一输出模块30响应于第一节点N1的低电平信号将第一电位信号VGH传输至第一输出端O1，使得第一输出信号OUTB为高电平信号。第三节点N3的电位与第一节点N1的电位相同，为低电平。第二输出模块40响应于第三节点N3的低电平信号将第二电位信号VGL传输至第二输出端O2，使得第二输出信号OUT为低电平信号。在第三阶段t3，第一输出信号OUTB发生反转，与已经反转后的第二起始信号INB一致，第二输出信号OUT发生反转，与已经反转后的第一起始信号IN一致。
在第四阶段t4，第一起始信号IN保持为低电平，第二起始信号INB保持为高电平。在第一时钟信号CLK1由第三阶段t3的低电平跳变为高电平，第二时钟信号CLK2由第三阶段t3的高电平跳变为低电平时，第一输入模块10停止传输第一起始信号IN，第一节点N1的电位保持为上一阶段的低电平。第二输入模块20停止传输第二起始信号INB，第二节点N2的电位保持为上一阶段的高电平。第三节点N3的电位与第一节点N1的电位相同，为低电平。第一输出模块30继续将第一电位信号VGH传输至第一输出端O1，使得第一输出信号OUTB为高电平信号。第二输出控制模块60在第二时钟信号CLK2的电位发生跳变时，根据第一输出端O1的电位、第一电位信号VGH和第二时钟信号CLK2将第三节点N3的电位下拉至低于低电平信号的电位(如图2所示，第三节点N3的电位在由第三阶段t3进入第四阶段t4时变得更低)，以保证第二输出模块40继 续响应于第三节点N3的低电平信号将第二电位信号VGL传输至第二输出端O2，使得第二输出信号OUT为低电平信号，以减少第二输出端O2输出的低电平信号的电平损失。在第四阶段t4，第一输出信号OUTB保持为高电平信号，第二输出信号OUT保持为低电平信号。
在第五阶段t5，第一时钟信号CLK1为低电平，第二时钟信号CLK2为高电平，第一起始信号IN为高电平，第二起始信号INB低电平。第一输入模块10将第一起始信号IN传输至第一节点N1，使得第一节点N1的电位为高电位。第二输入模块20将第二起始信号INB传输至第二节点N2，使得第二节点N2的电位为低电位。第一输出模块30响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB为低电平信号。第三节点N3的电位与第一节点N1的电位相同，为高电平。第二输出模块40响应于第一输出端O1的低电平信号将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第五阶段t5，第一输出信号OUTB发生反转，与已经反转后的第二起始信号INB一致，第二输出信号OUT发生反转，与已经反转后的第一起始信号IN一致。
在第六阶段t6，第一起始信号IN保持为高电平，第二起始信号INB保持为低电平。在第一时钟信号CLK1由第五阶段t5的低电平跳变为高电平，第二时钟信号CLK2由第五阶段t5的高电平跳变为低电平时，第一输入模块10停止传输第一起始信号IN，第一节点N1的电位保持为上一阶段的高电平。第二输入模块20停止传输第二起始信号INB，第二节点N2的电位保持为上一阶段的低电平。第一输出控制模块50在第二时钟信号CLK2发生跳变时，根据第一节点N1的电位、第一电位信号VGH和第二时钟信号CLK2将第二节点N2的电位下拉至低于低电平信号的电位(如图2所示，第二节点N2的电位在由第五阶段t5进入第六阶段t6时变得更低)，以保证第一输出模块30继续响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB仍为低电平信号，以减少第一输出端O1输出的低电平信号的电平损失。第三节点N3的电位与第一节点N1的电位相同，为高电平。第二输出模块40继续响应于第一输出端O1的低电平信号将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第六阶段t6，第一输出信号OUTB维持与第二起始信号INB一致，第二输出信号OUT维持与第一起始信号IN一致。
本实施例的技术方案，在设置第一起始信号IN的低电平信号的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的低电平信号的脉宽时，可实现通过移位寄存器将第一起始信号IN移位输出，得到第二输出信号OUT，将第二起始信号INB移位输出，得到第一输出信号OUTB。与相关技术相比，移位寄存器 的第一输出信号OUTB和第二输出信号OUT的低电平信号的脉宽大于时钟信号的低电平信号的脉宽，并且通过第一输出控制模块50减少了移位寄存器的第一输出信号OUTB的低电平损失，通过第二输出控制模块60减少了移位寄存器的第二输出信号OUT的低电平损失，有利于延长移位寄存器的输出信号的低电平时间，并且在将移位寄存器的输出信号作为像素电路中的初始化晶体管的栅极驱动信号时，有利于延长驱动晶体管的栅极和发光器件的阳极的初始化时间，从而减轻由初始化时间不充足带来的显示画面出现残影及显示异常等问题，有助于提升显示效果。在将移位寄存器的输出信号作为像素电路中的发光控制晶体管的栅极驱动信号时，同样有助于提升显示效果。另外，由于显示面板中的栅极驱动电路通常包括多个级联连接的移位寄存器，且本实施例中的移位寄存器能够实现将第一起始信号IN移位输出，得到第二输出信号OUT，将第二起始信号INB移位输出，得到第一输出信号OUTB，因此，将该移位寄存器应用于栅极驱动电路时，本级移位寄存器输出的第二输出信号OUT还可作为下一级移位寄存器输入的第一起始信号IN，本级移位寄存器输出的第一输出信号OUTB还可作为下一级移位寄存器输入的第二起始信号INB，这样有助于本级移位寄存器的输出信号向下一级移位寄存器传递。并且通过第一输出控制模块50和第二输出控制模块60还能减少移位寄存器的输出信号的低电平损失，进而减少本级移位寄存器传递至下一级移位寄存器的信号的电平损失。
图3是本申请实施例提供的另一种移位寄存器的模块结构示意图，如图3所示，可选地，第一输出控制模块50设置为在第一节点N1的电位和第一电位信号VGH均为第一电位，且第二时钟信号CLK2由第一电位跳变至第二电位时，将第二节点N2的电位下拉至低于第二电位信号VGL的电位。第一输出控制模块50包括：第一晶体管M1、第二晶体管M2和第一电容C1；第一晶体管M1的栅极连接第二节点N2和第一电容C1的第二端，第一晶体管M1的第一极输入第二时钟信号CLK2，第一晶体管M1的第二极连接第一电容C1的第一端和第二晶体管M2的第二极；第二晶体管M2的栅极连接第一节点N1，第二晶体管M2的第一极输入第一电位信号VGH。
图2所示的移位寄存器的驱动时序图，同样能够用于驱动图3所示的移位寄存器工作，结合图2和图3，示例性地，第二时钟信号CLK2的第一电位可以是高电平的电位，第二电位可以是低电平的电位，在移位寄存器的驱动时序由第五阶段t5进入第六阶段t6时，第二时钟信号CLK2由第一电位跳变至第二电位，第一输出控制模块50可根据第一节点N1的电位、第一电位信号VGH和第二时钟信号CLK2将第二节点N2的电位下拉至低于第二电位信号VGL的电位，即低于低电平信号的电位，以保证第一输出模块30继续响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1，使得第一输出信号 OUTB仍为低电平信号，以减少第一输出端O1输出的低电平信号的电平损失。
第一输出控制模块50中的第一晶体管M1和第二晶体管M2可以是P型晶体管，也可以是N型晶体管，本实施例及下文的实施例中，以移位寄存器中的多个晶体管均是P型晶体管为例进行示意性说明。
第一晶体管M1响应于第二节点N2的低电平信号导通，并在导通时将第二时钟信号CLK2传输至第一晶体管M1和第二晶体管M2之间的第四节点N4。第二晶体管M2响应于第一节点N1的低电平信号导通，并在导通时将第一电位信号VGH传输至第四节点N4。结合图2和图3，在第五阶段t5，第一节点N1的电位为高电位，第二节点N2的电位为低电位，第二晶体管M2关断，第一晶体管M1导通，并将第二时钟信号CLK2传输至第四节点N4，使第四节点N4的电位为高电位，第一电容C1的两端形成电位差，第一电容C1被充电。在由第五阶段t5进入至第六阶段t6时，第二时钟信号CLK2由第一电位跳变至第二电位，第二节点N2的电位接近低电位，第一晶体管M1继续导通，并将第二时钟信号CLK2传输至第四节点N4，使第四节点N4的电位由高电位变为低电位，由于第一电容C1的耦合作用，第一电容C1能够将第二节点N2的电位耦合至低于低电位的极低电位，以保证第一输出模块30继续响应于第二节点N2的低电平信号将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB仍为低电平信号，以减少第一输出端O1输出的低电平信号的电平损失。
图4是本申请实施例提供的另一种移位寄存器的模块结构示意图，如图4所示，可选地，第二输出控制模块60设置为在第一输出端O1的电位和第一电位信号VGH均为第一电位，且第二时钟信号CLK2由第一电位跳变至第二电位时，将第三节点N3的电位下拉至低于第二电位信号VGL的电位；第二输出控制模块60包括：第三晶体管M3、第四晶体管M4和第二电容C2；第三晶体管M3的栅极连接第三节点N3和第二电容C2的第二端，第三晶体管M3的第一极输入第二时钟信号CLK2，第三晶体管M3的第二极连接第二电容C2的第一端和第四晶体管M4的第二极；第四晶体管M4的栅极连接第一输出端O1，第四晶体管M4的第一极输入第一电位信号VGH。
图2所示的移位寄存器的驱动时序图，同样能够用于驱动图4所示的移位寄存器工作，结合图2和图4，示例性地，在移位寄存器的驱动时序由第三阶段t3进入第四阶段t4时，第二时钟信号CLK2由第一电位跳变至第二电位，第二输出控制模块60可根据第一输出端O1的电位、第一电位信号VGH和第二时钟信号CLK2将第三节点N3的电位下拉至低于第二电位信号VGL的电位，即低于低电平信号的电位，以保证第二输出模块40继续响应于第三节点N3的低电平信号将第二电位信号VGL传输至第二输出端O2，使得第二输出信号OUT为 低电平信号，以减少第二输出端O2输出的低电平信号的电平损失。
第三晶体管M3响应于第三节点N3的低电平信号导通，并在导通时将第二时钟信号CLK2传输至第三晶体管M3和第四晶体管M4之间的第五节点N5。第四晶体管M4响应于第一输出端O1的低电平信号导通，并在导通时将第一电位信号VGH传输至第五节点N5。结合图2和图4，在第三阶段t3，第三节点N3的电位为低电位，第一输出端O1的电位为高电位，第四晶体管M4关断，第三晶体管M3导通，并将第二时钟信号CLK2传输至第五节点N5，使第五节点N5的电位为高电位，第二电容C2的两端形成电位差，第二电容C2被充电。在由第三阶段t3进入第四阶段t4时，第二时钟信号CLK2由第一电位跳变至第二电位，第三节点N3的电位接近低电位，第三晶体管M3继续导通，并将第二时钟信号CLK2传输至第五节点N5，使第五节点N5的电位由高电位变为低电位，由于第二电容C2的耦合作用，第二电容C2能够将第三节点N3的电位耦合至低于低电位的极低电位，以保证第二输出模块40继续响应于第三节点N3的低电平信号将第二电位信号VGL传输至第二输出端O2，使得第二输出信号OUT为低电平信号，以减少第二输出端O2输出的低电平信号的电平损失。
图5是本申请实施例提供的另一种移位寄存器的模块结构示意图，如图5所示，可选地，设置第一输入模块10包括第五晶体管M5，第五晶体管M5的栅极输入第一时钟信号CLK1，第五晶体管M5的第一极输入第一起始信号IN，第五晶体管M5的第二极连接第一节点N1；第二输入模块20包括第六晶体管M6，第六晶体管M6的栅极输入第一时钟信号CLK1，第六晶体管M6的第一极输入第二起始信号INB，第六晶体管M6的第二极连接第二节点N2。
第五晶体管M5可响应于第一时钟信号CLK1的低电平信号导通，并在导通时将第一起始信号IN传输至第一节点N1，以使第一节点N1的电位与第一起始信号IN的电位相同，进而通过控制第一节点N1的电位来控制第一输出模块30的第一输出端O1输出的信号。第六晶体管M6可响应于第一时钟信号CLK1的低电平信号导通，并在导通时将第二起始信号INB传输至第二节点N2，以使第二节点N2的电位与第二起始信号INB的电位相同，进而通过控制第二节点N2的电位来控制第一输出模块30的第一输出端O1输出的信号。
图6是本申请实施例提供的另一种移位寄存器的模块结构示意图，如图6所示，可选地，设置第一输出模块30包括第一输出单元31和第二输出单元32；第一输出单元31设置为根据第一节点N1的电位导通或关断，并在自身导通时将第一电位信号VGH传输至第一输出端O1；第二输出单元32设置为根据第二节点N2的电位导通或关断，并在自身导通时将第二电位信号VGL传输至移位寄存器的第一输出端O1。
示例性地，第一输出单元31可响应于第一节点N1的低电平信号而导通，并在导通时将第一电位信号VGH传输至第一输出端O1。第二输出单元32可响应于第二节点N2的低电平信号而导通，并在导通时将第二电位信号VGL传输至第一输出端O1。这样设置的好处在于，能够通过调整第一起始信号IN的脉宽并结合第一时钟信号CLK1来控制第一节点N1的电位，进而调整第一输出端O1输出的第一电位信号VGH的脉宽，而第二起始信号INB的脉宽取决于第一起始信号IN的脉宽，因此，本方案通过调整第一起始信号IN的脉宽并结合第一时钟信号CLK1还能控制第二节点N2的电位，进而调整第一输出端O1输出的第二电位信号VGL的脉宽，以使移位寄存器的第一输出端O1的输出信号为脉宽可调的脉冲信号。
参见图6，可选地，设置第一输出单元31包括第七晶体管M7，第七晶体管M7的栅极连接第一节点N1，第七晶体管M7的第一极输入第一电位信号VGH，第七晶体管M7的第二极连接第一输出端O1；第二输出单元32包括第八晶体管M8，第八晶体管M8的栅极连接第二节点N2，第八晶体管M8的第一极输入第二电位信号VGL，第八晶体管M8的第二极连接第一输出端O1。
第七晶体管M7可响应于第一节点N1的低电平信号导通，并在导通时将第一电位信号VGH传输至第一输出端O1。第八晶体管M8可响应于第二节点N2的低电平信号导通，并在导通时将第二电位信号VGL传输至第一输出端O1。本实施例可通过控制第七晶体管M7和第八晶体管M8的导通时序，将第一电位信号VGH和第二电位信号VGL交替传输至第一输出端O1，以使移位寄存器的第一输出端O1的输出信号形成脉宽可调的脉冲信号。
图7是本申请实施例提供的一种移位寄存器的结构示意图，图8是本申请实施例提供的另一种移位寄存器的结构示意图，如图7和图8所示，可选地，设置第二输出模块40包括第三输出单元41和第四输出单元42；第三输出单元41设置为根据第三节点N3的电位导通或关断，并在自身导通时将第二电位信号VGL传输至第二输出端O2；第四输出单元42设置为根据第一输出端O1的电位导通或关断，并在自身导通时将第一电位信号VGH传输至移位寄存器的第二输出端O2。
示例性地，第三输出单元41可响应于第三节点N3的低电平信号导通，并在导通时将第二电位信号VGL传输至第二输出端O2。第四输出单元42可响应于第一输出端O1的低电平信号导通，并在导通时将第一电位信号VGH传输至移位寄存器的第二输出端O2。这样设置的好处在于，能够通过调整第一起始信号IN的脉宽来调整第一输出端O1的输出信号的脉宽，进而调整第二输出端O2输出的第一电位信号VGH的脉宽，由于第三节点N3的电位与第一节点N1的 电位相同，在调整第一起始信号IN的脉宽并结合第一时钟信号CLK1还能控制第三节点N3的电位，进而调整第二输出端O2输出的第二电位信号VGL的脉宽，以使移位寄存器的第二输出端O2的输出信号为脉宽可调的脉冲信号。
参见图7和图8，可选地，设置第三输出单元41包括第九晶体管M9，第九晶体管M9的栅极连接第三节点N3，第九晶体管M9的第一极输入第二电位信号VGL，第九晶体管M9的第二极连接第二输出端O2；第四输出单元42包括第十晶体管M10，第十晶体管M10的栅极连接第一输出端O1，第十晶体管M10的第一极输入第一电位信号VGH，第十晶体管M10的第二极连接第二输出端O2。
第九晶体管M9可响应于第三节点N3的低电平信号导通，并在导通时将第二电位信号VGL传输至第二输出端O2。第十晶体管M10可响应于第一输出端O1的低电平信号导通，并在导通时将第一电位信号VGH传输至第二输出端O2。本实施例可通过控制第九晶体管M9和第十晶体管M10的导通时序，将第一电位信号VGH和第二电位信号VGL交替传输至第二输出端O2，以使移位寄存器的第二输出端O2的输出信号形成脉宽可调的脉冲信号。
参见图8，可选地，设置第四输出单元42还包括第三电容C3，第三电容C3的第一端连接第十晶体管M10的第一极，第三电容C3的第二端连接第十晶体管M10的栅极。第三电容C3能够起到对第十晶体管M10的栅极电位进行保持的作用，例如使得移位寄存器的第二输出端O2在输出高电平信号期间，保持第十晶体管M10的栅极电位为低电位，以保证第十晶体管M10在导通时将第一电位信号VGH传输至第二输出端O2。
继续参见图7和图8，可选地，设置移位寄存器还包括第十一晶体管M11，第十一晶体管M11连接于第一节点N1与第三节点N3之间，第十一晶体管M11的栅极输入第二电位信号VGL。第十一晶体管M11可响应于第二电位信号VGL而处于常导通状态，参见图2，在由第三阶段t3进入第四阶段t4时，第二时钟信号CLK2由第一电位跳变至第二电位，第二输出控制模块60能够将第三节点N3的电位耦合至低于低电位的极低电位，本实施例设置第十一晶体管M11，有助于隔断第三节点N3出现的极低电位，避免第三节点N3的极低电位传输至第一节点N1，从而影响移位寄存器的正常工作。
图2所示的移位寄存器的驱动时序图，同样能够用于驱动图7和图8所示的移位寄存器工作。下面将结合图2和图7和图8，对本申请实施例提供的移位寄存器的工作原理进行说明。示例性地，该移位寄存器的工作过程包括第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4、第五阶段t5和第六阶段t6。
在第一阶段t1，第一时钟信号CLK1为低电平，第二时钟信号CLK2为高 电平，第一起始信号IN为高电平，第二起始信号INB为低电平。第五晶体管M5和第六晶体管M6导通，第十一晶体管M11常导通，第五晶体管M5将第一起始信号IN传输至第一节点N1，使得第一节点N1的电位为高电位，第三节点N3的电位与第一节点N1的电位相同，第六晶体管M6将第二起始信号INB传输至第二节点N2，使得第二节点N2的电位为低电位。第二晶体管M2、第七晶体管M7、第三晶体管M3和第九晶体管M9关断，第一晶体管M1和第八晶体管M8导通。第一晶体管M1将第二时钟信号CLK2传输至第四节点N4，使得第四节点N4的电位为高电位。第一电容C1的两端形成电位差，第一电容C1被充电。第八晶体管M8将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB为低电平信号。第四晶体管M4和第十晶体管M10导通，第四晶体管M4将第一电位信号VGH传输至第五节点N5，以使第五节点N5的电位为高电位，第十晶体管M10将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第一阶段t1，第一输出信号OUTB与第二起始信号INB一致，第二输出信号OUT与第一起始信号IN一致。
在第二阶段t2，第一时钟信号CLK1为高电平，第二时钟信号CLK2由高电平跳变为低电平，第一起始信号IN为低电平，第二起始信号INB高电平。第五晶体管M5和第六晶体管M6关断，第一节点N1的电位为高电位，第三节点N3的电位与第一节点N1的电位相同，第二节点N2的电位为低电位。第二晶体管M2、第七晶体管M7、第三晶体管M3和第九晶体管M9关断，第一晶体管M1和第八晶体管M8导通。第一晶体管M1将第二时钟信号CLK2传输至第四节点N4，使得第四节点N4的电位由高电位变为低电位，由于第一电容C1的耦合作用，第一电容C1能够将第二节点N2的电位耦合至低于低电位的极低电位，以增大第八晶体管M8的导通程度，使第八晶体管M8全开，以保证第八晶体管M8将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB为低电平信号。第四晶体管M4和第十晶体管M10导通，第四晶体管M4将第一电位信号VGH传输至第五节点N5，以使第五节点N5的电位为高电位，第十晶体管M10将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第二阶段t2，第一输出信号OUTB仍然与第二起始信号INB一致，第二输出信号OUT仍然与第一起始信号IN一致。
在第三阶段t3，第一时钟信号CLK1为低电平，第二时钟信号CLK2为高电平，第一起始信号IN为低电平，第二起始信号INB高电平。第五晶体管M5和第六晶体管M6导通，第五晶体管M5将第一起始信号IN传输至第一节点N1，使得第一节点N1的电位为低电位，第三节点N3的电位与第一节点N1的电位相同，第六晶体管M6将第二起始信号INB传输至第二节点N2，使得第二节点N2的电位为高电位。第一晶体管M1和第八晶体管M8关断，第二晶体管M2、 第七晶体管M7、第三晶体管M3和第九晶体管M9导通。第七晶体管M7将第一电位信号VGH传输至第一输出端O1，使得第一输出信号OUTB为高电平信号，第四晶体管M4和第十晶体管M10关断。第三晶体管M3将第二时钟信号CLK2传输至第五节点N5，使得第五节点N5的电位为高电位。第二电容C2的两端形成电位差，第二电容C2被充电。第九晶体管M9将第二电位信号VGL传输至第二输出端O2，使得第二输出信号OUT为低电平信号。在第三阶段t3，第一输出信号OUTB发生反转，与已经反转后的第二起始信号INB一致，第二输出信号OUT发生反转，与已经反转后的第一起始信号IN一致。
在第四阶段t4，第一起始信号IN保持为低电平，第二起始信号INB保持为高电平。在第一时钟信号CLK1由第三阶段t3的低电平跳变为高电平，第二时钟信号CLK2由第三阶段t3的高电平跳变为低电平时，第五晶体管M5和第六晶体管M6关断，第一节点N1的电位为低电位，第三节点N3的电位与第一节点N1的电位相同，第二节点N2的电位为高电位。第一晶体管M1和第八晶体管M8关断，第二晶体管M2、第七晶体管M7、第三晶体管M3和第九晶体管M9导通。第七晶体管M7继续将第一电位信号VGH传输至第一输出端O1，使得第一输出信号OUTB为高电平信号，第四晶体管M4和第十晶体管M10关断。第三晶体管M3将第二时钟信号CLK2传输至第五节点N5，使得第五节点N5的电位由高电位跳变为低电位。由于第二电容C2的耦合作用，第二电容C2能够将第三节点N3的电位耦合至低于低电位的极低电位，以增大第九晶体管M9的导通程度，使第九晶体管M9全开，进而保证第九晶体管M9将第二电位信号VGL传输至第二输出端O2，使得第二输出信号OUT为低电平信号。如图2所示，由第三阶段t3进入第四阶段t4之后，第二输出端O2输出的低电平信号变得更低，因此本方案通过设置由第三晶体管M3、第四晶体管M4和第二电容C2构成的第二输出控制模块60，实现了减少第二输出端O2输出的低电平信号在第三阶段t3的电平损失，有利于延长移位寄存器的输出信号的低电平时间。在第四阶段t4，第一输出信号OUTB保持为高电平信号，第二输出信号OUT保持为低电平信号。
在第五阶段t5，第一时钟信号CLK1为低电平，第二时钟信号CLK2为高电平，第一起始信号IN为高电平，第二起始信号INB低电平。第一晶体管M1、第四晶体管M4、第五晶体管M5、第六晶体管M6、第八晶体管M8、第十晶体管M10和第十一晶体管M11导通，其余晶体管关断。第一节点N1和第三节点N3的电位为高电位，第二节点N2的电位为低电位，第四节点N4的电位为高电位。第一电容C1的两端形成电位差，第一电容C1被充电。第八晶体管M8将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB为低电平信号。第十晶体管M10将第一电位信号VGH传输至第二输出端O2，使得第二 输出信号OUT为高电平信号。在第五阶段t5，第一输出信号OUTB发生反转，与已经反转后的第二起始信号INB一致，第二输出信号OUT发生反转，与已经反转后的第一起始信号IN一致。
在第六阶段t6，第一起始信号IN保持为高电平，第二起始信号INB保持为低电平。在第一时钟信号CLK1由第五阶段t5的低电平跳变为高电平，第二时钟信号CLK2由第五阶段t5的高电平跳变为低电平时，第五晶体管M5和第六晶体管M6关断，第一节点N1的电位为高电位，第三节点N3的电位与第一节点N1的电位相同，第二节点N2的电位为低电位。第二晶体管M2、第七晶体管M7、第三晶体管M3和第九晶体管M9关断，第一晶体管M1和第八晶体管M8导通。第一晶体管M1将第二时钟信号CLK2传输至第四节点N4，使得第四节点N4的电位由高电位变为低电位，由于第一电容C1的耦合作用，第一电容C1能够将第二节点N2的电位耦合至低于低电位的极低电位，以增大第八晶体管M8的导通程度，使第八晶体管M8全开，进而保证第八晶体管M8将第二电位信号VGL传输至第一输出端O1，使得第一输出信号OUTB为低电平信号。如图2所示，由第五阶段t5进入第六阶段t6之后，第一输出端O1输出的低电平信号变得更低，因此本方案通过设置由第一晶体管M1、第二晶体管M2和第一电容C1构成的第一输出控制模块50，实现了减少第一输出端O1输出的低电平信号在第五阶段t5的电平损失，有利于延长移位寄存器的输出信号的低电平时间。在第六阶段t6，第四晶体管M4和第十晶体管M10导通，第四晶体管M4将第一电位信号VGH传输至第五节点N5，以使第五节点N5的电位为高电位，第十晶体管M10将第一电位信号VGH传输至第二输出端O2，使得第二输出信号OUT为高电平信号。在第六阶段t6，第一输出信号OUTB维持与第二起始信号INB一致，第二输出信号OUT维持与第一起始信号IN一致。
本申请实施例中，第一输出控制模块50中的第一晶体管M1和第二晶体管M2、第二输出控制模块60中的第三晶体管M3和第四晶体管M4、第一输入模块10中的第五晶体管M5、第二输入模块20中的第六晶体管M6、第一输出单元31中的第七晶体管M7、第二输出单元32中的第八晶体管M8、第三输出单元41中的第九晶体管M9、第四输出单元42中的第十晶体管M10以及第十一晶体管M11均可以是薄膜晶体管，显示面板中还包括由薄膜晶体管构成的像素电路，移位寄存器中的多个晶体管可以与像素电路中的晶体管在同一道工艺流程中制作，这样有助于简化显示面板的制作工艺。
本申请实施例还提供了一种栅极驱动电路，本申请实施例提供的栅极驱动电路，包括本申请上述任意实施例提供的移位寄存器。图9是本申请实施例提供的一种栅极驱动电路的模块结构示意图，如图9所示，该栅极驱动电路包括多个级联连接的移位寄存器100；第一级移位寄存器100的第一起始信号输入端 I1接入第一起始信号IN，第一级移位寄存器100的第二起始信号输入端I2接入第二起始信号INB，第一级移位寄存器100的第一输出端O1与下一级移位寄存器100的第二起始信号输入端I2电连接，第一级移位寄存器100的第二输出端O2与下一级移位寄存器100的第一起始信号输入端I1电连接。
结合图1和图9，栅极驱动电路包括多个级联连接的移位寄存器100，且本实施例中的移位寄存器能够实现将第一起始信号IN移位输出，得到第二输出信号OUT，将第二起始信号INB移位输出，得到第一输出信号OUTB，因此，将该移位寄存器应用于栅极驱动电路时，本级移位寄存器输出的第二输出信号OUT还可作为下一级移位寄存器输入的第一起始信号IN，本级移位寄存器输出的第一输出信号OUTB还可作为下一级移位寄存器输入的第二起始信号INB，这样有助于本级移位寄存器的输出信号向下一级移位寄存器传递。并且通过移位寄存器中的第一输出控制模块50和第二输出控制模块60还能减少移位寄存器的输出信号的低电平损失，进而减少本级移位寄存器传递至下一级移位寄存器的有效信号的电平损失。
本申请实施例提供的栅极驱动电路，包括本申请上述任意实施例提供的移位寄存器，因此该栅极驱动电路具有移位寄存器相应的功能模块和效果，这里不再赘述。
本申请实施例还提供了一种显示面板，图10是本申请实施例提供的一种显示面板的结构示意图，结合图1和图10，该显示面板200包括上述实施例提供的栅极驱动电路，还包括：第一时钟信号线210、第二时钟信号线220、第一电位信号线230和第二电位信号线240；第一时钟信号线210设置为向移位寄存器100传输第一时钟信号CLK1；第二时钟信号线220设置为向移位寄存器100传输第二时钟信号CLK2；第一电位信号线230设置为向移位寄存器100传输第一电位信号VGH；第二电位信号线240设置为向移位寄存器100传输第二电位信号VGL。
该显示面板例如可以为有机发光二极管显示面板或液晶显示面板等。可选地，显示面板还可以包括设置为向栅极驱动电路中的第一级移位寄存器100传输第一起始信号IN的第一起始信号线，移位寄存器还可通过其内部结构根据接收到的第一起始信号IN生成第一起始信号IN的反信号，以得到第二起始信号INB，并将第二起始信号INB输入至第一级移位寄存器100的第二起始信号输入端I2。第一级移位寄存器能够将第一起始信号IN和第二起始信号INB移位输出至下一级移位寄存器，相邻的两级移位寄存器中，后一级移位寄存器能够将前一级移位寄存器输出的信号进行移位并输出，且每一级移位寄存器的第二输出端O2的输出信号可作为显示面板中像素电路的晶体管的栅极驱动信号。因此， 本申请实施例提供的显示面板实现了逐行输出栅极驱动信号(例如栅极驱动信号可以是扫描信号或发光控制信号)的功能，多级移位寄存器输出的栅极驱动信号的脉宽可调，且稳定性良好。
本申请实施例提供的显示面板，包括本申请上述任意实施例提供的栅极驱动电路及栅极驱动电路中的移位寄存器，因此该显示面板具有栅极驱动电路及栅极驱动电路中的移位寄存器相应的功能模块和效果，这里不再赘述。
图11是本申请实施例提供的一种像素电路的结构示意图，图11示意性地示出了该像素电路包括七个薄膜晶体管和一个存储电容的情况。结合图10和图11，可选地，显示面板200还包括发光控制信号线250，移位寄存器100的第二输出端O2连接发光控制信号线250，移位寄存器100的第二输出端O2输出的信号作为发光控制信号EM。
显示面板中的像素电路与发光器件D1连接，该像素电路可包括存储电容Cst、驱动晶体管DT、设置为向驱动晶体管DT的栅极G传输初始化信号Vref的第一初始化晶体管T1、设置为向发光器件D1的阳极传输初始化信号Vref的第二初始化晶体管T2、设置为将数据电压Vdata写入存储电容Cst的数据写入晶体管T3、设置为对驱动晶体管DT进行阈值电压补偿的阈值补偿晶体管T4以及设置为控制发光器件D1的发光阶段的第一发光控制晶体管T5和第二发光控制晶体管T6。
发光控制信号线250设置为向第一发光控制晶体管T5和第二发光控制晶体管T6的栅极传输发光控制信号EM。结合图1、图10和图11，当设置移位寄存器的第一起始信号IN的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的脉宽时，可实现通过移位寄存器将第一起始信号IN移位输出，得到第二输出信号OUT，将第二起始信号INB移位输出，得到第一输出信号OUTB。与相关技术相比，移位寄存器的第一输出信号OUTB和第二输出信号OUT的脉宽大于时钟信号的脉宽，并且通过第一输出控制模块50减少了移位寄存器输出的第一输出信号OUTB的低电平损失，通过第二输出控制模块60减少了移位寄存器输出的第二输出信号OUT的低电平损失，有利于延长移位寄存器的输出信号的低电平时间，并提升移位寄存器的输出信号的稳定性。在将移位寄存器的输出信号作为像素电路中的发光控制晶体管的栅极驱动信号时，同样有助于提升显示效果。
图12是本申请实施例提供的另一种显示面板的结构示意图，结合图11和图12，可选地，显示面板200还包括扫描线260，移位寄存器100的第二输出端O2连接扫描线260，移位寄存器100的第二输出端O2输出的信号作为扫描信号。扫描线260设置为向像素电路中的晶体管的栅极提供扫描信号，例如向 第一初始化晶体管T1和第二初始化晶体管T2的栅极提供扫描信号。
结合图11和图12，可选地，显示面板200包括像素电路，像素电路包括驱动晶体管DT、发光器件D1、第一初始化晶体管T1和第二初始化晶体管T2，第一初始化晶体管T1设置为对驱动晶体管DT的栅极G的电位进行初始化，第二初始化晶体管T2设置为对发光器件D1的阳极进行初始化；扫描线260连接第一初始化晶体管T1和/或第二初始化晶体管T2的栅极。当设置移位寄存器的第一起始信号IN的脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的脉宽时，与相关技术相比，本申请实施例提供的移位寄存器的第一输出信号OUTB和第二输出信号OUT的脉宽大于时钟信号的脉宽，并且还能够减少移位寄存器的输出信号的低电平损失，有利于延长移位寄存器的输出信号的低电平时间。在将移位寄存器的第二输出端O2输出的信号作为驱动第一初始化晶体管T1和第二初始化晶体管T2的扫描信号时，有利于延长驱动晶体管的栅极和发光器件的阳极的初始化时间，从而减轻由初始化时间不充足带来的显示画面出现残影及显示异常等问题，有助于提升显示效果。
图13是相关技术中的一种移位寄存器的结构示意图，结合图1、图11至图13，可选地，设置显示面板中的栅极驱动电路包括本申请上述任意实施例所提供的多个级联连接的移位寄存器100，还可以包括相关技术中的移位寄存器300。其中，移位寄存器100的第二输出端O2和移位寄存器300的输出端Gout均可连接扫描线260，移位寄存器100连接第一扫描线261，第一扫描线261可以向像素电路中的第一初始化晶体管T1的栅极传输第一扫描信号Scan1，或者也可以向像素电路中的第二初始化晶体管T2的栅极传输第三扫描信号Scan3。移位寄存器300的输出端Gout连接第二扫描线262，第二扫描线262可以向像素电路中的数据写入晶体管T3和阈值补偿晶体管T4的栅极传输第二扫描信号Scan2。
移位寄存器300包括第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第十六晶体管M16、第十七晶体管M17、第十八晶体管M18、第十九晶体管M19、第四电容C4以及第五电容C5。移位寄存器300具有一路输入信号SIN和一路输出的第二扫描信号Scan2。相关技术中的移位寄存器300的输出端Gout输出的有效信号脉宽通常取决于第一时钟信号CLK1和第二时钟信号CLK2的有效信号脉宽，在设置移位寄存器100的第一起始信号IN的有效信号脉宽大于第一时钟信号CLK1和第二时钟信号CLK2的有效信号脉宽时，移位寄存器100的第二输出端O2输出的有效信号脉宽大于移位寄存器300的输出端Gout输出的有效信号脉宽，因此，移位寄存器100的输出信号的有效脉冲宽度不再受到显示面板的行扫描时间的限制。
在驱动显示面板中像素电路工作时，可将本申请实施例提供的移位寄存器 100和相关技术中的移位寄存器300配合使用，使移位寄存器100的第二输出端O2输出的信号作为驱动第一初始化晶体管T1工作的第一扫描信号Scan1，和/或作为驱动第二初始化晶体管T2工作的第三扫描信号263，并使移位寄存器300的输出端Gout输出的信号作为驱动数据写入晶体管T3和阈值补偿晶体管T4工作的第二扫描信号Scan2。这样设置的好处在于，一方面，能够通过移位寄存器300驱动数据写入晶体管T3和阈值补偿晶体管T4正常工作，另一方面，由于移位寄存器100的输出信号的脉冲宽度可调，将移位寄存器100的第二输出端O2输出的信号作为第一扫描信号Scan1和/或第三扫描信号Scan3，有利于延长驱动晶体管的栅极和发光器件的阳极的初始化时间，从而减轻由初始化时间不充足带来的显示画面出现残影及显示异常等问题，有助于提升显示效果。并且，移位寄存器100的第二输出端O2连接的扫描线260可同时连接多行像素电路中的初始化晶体管(包括第一初始化晶体管T1和/或第二初始化晶体管T2)，以使显示面板能够同时对数行像素电路进行初始化，同时又不会引起逻辑错误，移位寄存器100的第二输出端O2输出的宽脉冲信号，不再受到像素电路的行扫描时间的限制。

Claims (17)

  1. 一种移位寄存器，包括：第一输入模块、第二输入模块、第一输出模块、第二输出模块、第一输出控制模块和第二输出控制模块；
    所述第一输入模块设置为根据第一起始信号和第一时钟信号控制第一节点的电位；所述第二输入模块设置为根据第二起始信号和所述第一时钟信号控制第二节点的电位，所述第二起始信号与所述第一起始信号的电位相反；
    所述第一输出控制模块设置为根据所述第一节点的电位、第一电位信号和第二时钟信号控制所述第二节点的电位；所述第一输出模块设置为根据所述第一节点的电位和所述第二节点的电位将所述第一电位信号或第二电位信号传输至所述移位寄存器的第一输出端；
    所述第二输出控制模块设置为根据所述第一输出端的电位、所述第一电位信号和所述第二时钟信号控制第三节点的电位，所述第三节点与所述第一节点连接；所述第二输出模块设置为根据所述第一输出端的电位和所述第三节点的电位将所述第一电位信号或所述第二电位信号传输至所述移位寄存器的第二输出端。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一输出控制模块设置为在所述第一节点的电位和所述第一电位信号均为第一电位，且所述第二时钟信号由所述第一电位跳变至第二电位的情况下，将所述第二节点的电位下拉至低于所述第二电位信号的电位；
    所述第一输出控制模块包括：第一晶体管、第二晶体管和第一电容；
    所述第一晶体管的栅极连接所述第二节点和所述第一电容的第二端，所述第一晶体管的第一极设置为输入所述第二时钟信号，所述第一晶体管的第二极连接所述第一电容的第一端和所述第二晶体管的第二极；所述第二晶体管的栅极连接所述第一节点，所述第二晶体管的第一极设置为输入所述第一电位信号。
  3. 根据权利要求1所述的移位寄存器，其中，所述第二输出控制模块设置为在所述第一输出端的电位和所述第一电位信号均为第一电位，且所述第二时钟信号由所述第一电位跳变至第二电位的情况下，将所述第三节点的电位下拉至低于所述第二电位信号的电位；
    所述第二输出控制模块包括：第三晶体管、第四晶体管和第二电容；
    所述第三晶体管的栅极连接所述第三节点和所述第二电容的第二端，所述第三晶体管的第一极设置为输入所述第二时钟信号，所述第三晶体管的第二极连接所述第二电容的第一端和所述第四晶体管的第二极；所述第四晶体管的栅极连接所述第一输出端，所述第四晶体管的第一极设置为输入所述第一电位信号。
  4. 根据权利要求1所述的移位寄存器，其中，所述第一输入模块包括第五晶体管，所述第五晶体管的栅极设置为输入所述第一时钟信号，所述第五晶体管的第一极设置为输入所述第一起始信号，所述第五晶体管的第二极连接所述第一节点；
    所述第二输入模块包括第六晶体管，所述第六晶体管的栅极设置为输入所述第一时钟信号，所述第六晶体管的第一极设置为输入所述第二起始信号，所述第六晶体管的第二极连接所述第二节点。
  5. 根据权利要求1所述的移位寄存器，其中，所述第一输出模块包括第一输出单元和第二输出单元；
    所述第一输出单元设置为根据所述第一节点的电位导通或关断，并在自身导通的情况下将所述第一电位信号传输至所述第一输出端；所述第二输出单元设置为根据所述第二节点的电位导通或关断，并在自身导通的情况下将所述第二电位信号传输至所述移位寄存器的第一输出端。
  6. 根据权利要求5所述的移位寄存器，其中，所述第一输出单元包括第七晶体管，所述第七晶体管的栅极连接所述第一节点，所述第七晶体管的第一极设置为输入所述第一电位信号，所述第七晶体管的第二极连接所述第一输出端。
  7. 根据权利要求5所述的移位寄存器，其中，所述第二输出单元包括第八晶体管，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一极设置为输入所述第二电位信号，所述第八晶体管的第二极连接所述第一输出端。
  8. 根据权利要求1所述的移位寄存器，其中，所述第二输出模块包括第三输出单元和第四输出单元；
    所述第三输出单元设置为根据所述第三节点的电位导通或关断，并在自身导通的情况下将所述第二电位信号传输至所述第二输出端；所述第四输出单元设置为根据所述第一输出端的电位导通或关断，并在自身导通的情况下将所述第一电位信号传输至所述移位寄存器的第二输出端。
  9. 根据权利要求8所述的移位寄存器，其中，所述第三输出单元包括第九晶体管，所述第九晶体管的栅极连接所述第三节点，所述第九晶体管的第一极设置为输入所述第二电位信号，所述第九晶体管的第二极连接所述第二输出端。
  10. 根据权利要求8所述的移位寄存器，其中，所述第四输出单元包括第十晶体管，所述第十晶体管的栅极连接所述第一输出端，所述第十晶体管的第一极设置为输入所述第一电位信号，所述第十晶体管的第二极连接所述第二输出端。
  11. 根据权利要求10所述的移位寄存器，其中，所述第四输出单元还包括 第三电容，所述第三电容的第一端连接所述第十晶体管的第一极，所述第三电容的第二端连接所述第十晶体管的栅极。
  12. 根据权利要求1所述的移位寄存器，还包括第十一晶体管，所述第十一晶体管连接于所述第一节点与所述第三节点之间，所述第十一晶体管的栅极设置为输入所述第二电位信号。
  13. 一种栅极驱动电路，包括多个如权利要求1-12中任一项所述的移位寄存器，所述多个移位寄存器级联连接；
    第一级移位寄存器的第一起始信号输入端设置为接入所述第一起始信号，所述第一级移位寄存器的第二起始信号输入端设置为接入所述第二起始信号，所述第一级移位寄存器的第一输出端与下一级移位寄存器的第二起始信号输入端电连接，所述第一级移位寄存器的第二输出端与所述下一级移位寄存器的第一起始信号输入端电连接。
  14. 一种显示面板，包括权利要求13所述的栅极驱动电路，还包括：第一时钟信号线、第二时钟信号线、第一电位信号线和第二电位信号线；
    所述第一时钟信号线设置为向所述移位寄存器传输第一时钟信号；所述第二时钟信号线设置为向所述移位寄存器传输第二时钟信号；所述第一电位信号线设置为向所述移位寄存器传输第一电位信号；所述第二电位信号线设置为向所述移位寄存器传输第二电位信号。
  15. 根据权利要求14所述的显示面板，还包括发光控制信号线，所述移位寄存器的第二输出端连接所述发光控制信号线，所述发光控制信号线设置为将所述移位寄存器的第二输出端输出的信号作为发光控制信号。
  16. 根据权利要求14所述的显示面板，还包括扫描线，所述移位寄存器的第二输出端连接所述扫描线，所述扫描线设置为将所述移位寄存器的第二输出端输出的信号作为扫描信号。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括像素电路，所述像素电路包括驱动晶体管、发光器件、第一初始化晶体管和第二初始化晶体管，所述第一初始化晶体管设置为对所述驱动晶体管的栅极电位进行初始化，所述第二初始化晶体管设置为对所述发光器件的阳极进行初始化；所述扫描线连接所述第一初始化晶体管和所述第二初始化晶体管的栅极中的至少之一。
PCT/CN2021/131986 2021-01-29 2021-11-22 移位寄存器、栅极驱动电路和显示面板 WO2022160888A1 (zh)

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