WO2023178621A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2023178621A1
WO2023178621A1 PCT/CN2022/082864 CN2022082864W WO2023178621A1 WO 2023178621 A1 WO2023178621 A1 WO 2023178621A1 CN 2022082864 W CN2022082864 W CN 2022082864W WO 2023178621 A1 WO2023178621 A1 WO 2023178621A1
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Prior art keywords
node
terminal
signal
circuit
gate
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PCT/CN2022/082864
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
吴刘
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/082864 priority Critical patent/WO2023178621A1/zh
Priority to CN202280000536.6A priority patent/CN117136402A/zh
Publication of WO2023178621A1 publication Critical patent/WO2023178621A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a driving method thereof, and a display device.
  • a pixel driving circuit usually includes a switching transistor connected between a power supply terminal and a driving transistor.
  • the display panel can adjust the sub-pixel where the pixel driving circuit is located by controlling the duty cycle of the gate pulse width modulation signal of the switching transistor.
  • brightness since the switching transistor is in a conductive state for a long time, the threshold value of the switching transistor drifts seriously, thereby affecting normal display.
  • a display panel includes: a plurality of pixel driving circuits, the plurality of pixel driving circuits are array-distributed along a first direction and a second direction, and the first direction Intersecting with the second direction, a plurality of the pixel driving circuits form a plurality of pixel driving circuit groups, each of the pixel driving circuit groups includes a plurality of pixel driving circuit rows, and the pixel driving circuit rows include a plurality of pixel driving circuit rows along the first direction.
  • the pixel drive circuit is distributed, and the pixel drive circuit includes: a drive circuit, a first switch unit, the drive circuit is connected to the first node, the second node, and the third node, and is used to respond to the signal of the first node passing through all the The second node inputs a driving current to the third node; the first end of the first switch unit is connected to the first power end, and the second end is connected to the second node for responding to a pulse width modulation signal to connect the The first power terminal and the second node; wherein, in the same pixel driving circuit group, the second terminal of any first switching unit is connected to at least one first switching unit in each other pixel driving circuit row. The second end of the connection.
  • the driving circuit includes: a driving transistor, a first electrode of the driving transistor is connected to the second node, a second electrode is connected to the third node, and a gate electrode is connected to the first node.
  • the first switch unit includes: a first transistor, a first electrode of the first transistor is connected to the first power supply terminal, a second electrode is connected to the second node, and a gate electrode is connected to the pulse width modulation signal terminal.
  • the pixel driving circuit also includes: a second transistor, a third transistor, and a capacitor.
  • the first electrode of the second transistor is connected to the data signal terminal, the second electrode is connected to the first node, and the gate electrode is connected to the first gate drive signal terminal.
  • the first electrode of the third transistor is connected to the third node, the second electrode is connected to the sensing signal terminal, and the gate is connected to the second gate drive signal terminal; the capacitor is connected between the first node and the third node between.
  • the display panel further includes: a gate driving circuit, the gate driving circuit includes a plurality of output terminals, the output terminals are arranged corresponding to the rows of the pixel driving circuits, and the The output terminal is used to provide the pulse width modulation signal to the control terminal of the first switch unit in the corresponding pixel driving circuit row; the gate driving circuit is used to drive the same pixel in the same frame.
  • a subset of pixel drive circuits in the circuit group provides the pulse width modulation signal, part of the pixel drive circuit rows in the pixel drive circuit group forms the pixel drive circuit subset, and the gate drive circuit is used to operate at least
  • the pulse width modulation signal is provided to different pixel driving circuit subgroups in the same pixel driving circuit group in some different frames.
  • the pixel driving circuit group includes a plurality of pixel driving circuit rows adjacent in the second direction. In the same pixel driving circuit group, in the second direction The second ends of the first switch units distributed on the plurality of pixel driving circuits are connected to each other.
  • the pixel driving circuit subgroup includes one pixel driving circuit row, and the pixel driving circuit group includes odd pixel driving circuit rows located in odd rows and even pixel driving circuits located in even rows. circuit rows, and two pixel driving circuit rows in the pixel driving circuit group are arranged adjacently in the second direction; the gate driving circuit is used to drive odd-numbered pixel driving circuit rows or even-numbered pixels in the same frame.
  • the circuit row selectively provides the pulse width modulated signal
  • the gate drive circuit is configured to provide the pulse width modulated signal to odd numbered pixel drive circuit rows in at least part of the frame, and to provide the pulse width modulated signal to even numbered pixel drive circuit rows in at least part of the frame. Rows of pixel drive circuits provide the pulse width modulated signals.
  • the gate drive circuit includes: a first gate drive circuit and a second gate drive circuit.
  • the first gate drive circuit is connected to a first signal input line and a first clock signal line. , a second clock signal line, used to provide the pulse width modulation signal to odd-numbered pixel driving circuit rows in response to the signals of the first signal input line, the first clock signal line, and the second clock signal line;
  • the second gate driver The circuit is connected to the second signal input line, the first clock signal line, and the second clock signal line, and is used to drive circuit rows of even-numbered pixels in response to signals from the second signal input line, the first clock signal line, and the second clock signal line.
  • the pulse width modulated signal is provided.
  • the first gate driving circuit includes a plurality of cascaded shift register units
  • the second gate driving circuit includes a plurality of cascaded shift register units
  • the shift register unit includes: a first input circuit, a second input circuit, a pull-up circuit, a pull-down circuit, a first output circuit, and a second output circuit.
  • the first input circuit is connected to the signal input terminal, the first clock signal terminal, and the fourth node, used to respond to the signal of the first clock signal terminal and transmit the signal of the signal input terminal to the fourth node;
  • the second input circuit is connected to the second power terminal, the second clock signal terminal, the fifth node, and the signal input terminal, for transmitting the signal of the second power terminal to the fifth node in response to the signal of the second clock signal terminal, and for transmitting the signal of the second clock signal terminal to the signal of the second clock signal terminal in response to the signal of the signal input terminal.
  • the fifth node a pull-up circuit is connected to the first clock signal terminal, the fifth node, and the sixth node, and is used to respond to the signals of the fifth node and the first clock signal terminal to convert the signal of the first clock signal terminal.
  • a pull-down circuit is connected to the fourth node, the third power terminal, and the sixth node, and is used to transmit the signal of the third power terminal to the sixth node in response to the signal of the fourth node.
  • a first output circuit is connected to the fourth node, the first output terminal, and the second power terminal, and is used to transmit the signal of the second power terminal to the first output terminal in response to the signal of the fourth node;
  • the second output circuit is connected to the sixth node, the third power terminal, and the first output terminal, and is used to transmit the signal of the third power terminal to the first output terminal in response to the signal of the sixth node.
  • the first input circuit includes: a fourth transistor and a fifth transistor.
  • the first electrode of the fourth transistor is connected to the signal input terminal, the second electrode is connected to the seventh node, and the gate electrode
  • the first clock signal terminal is connected; the first electrode of the fifth transistor is connected to the seventh node, the second electrode is connected to the fourth node, and the gate electrode is connected to the first clock signal terminal.
  • the second input circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor.
  • the first electrode of the seventh transistor is connected to the second power terminal, the second electrode is connected to the fifth node, and the gate electrode is connected to the the second clock signal terminal;
  • the first pole of the eighth transistor is connected to the fifth node, the second pole is connected to the eighth node, and the gate is connected to the signal input terminal;
  • the first pole of the ninth transistor is connected to the eighth node , the second pole is connected to the second clock signal terminal, and the gate is connected to the signal input terminal.
  • the shift register unit further includes: a first isolation circuit and a second isolation circuit.
  • the first isolation circuit is connected to the second power terminal, the fourth node, and the seventh node.
  • the signal of the second power terminal is transmitted to the seventh node;
  • the second isolation circuit is connected to the eighth node, the second power terminal, and the fifth node, and is used in response to the The signal of the fifth node transmits the signal of the second power terminal to the eighth node.
  • the first isolation circuit includes: a sixth transistor, a first electrode of the sixth transistor is connected to the seventh node, a second electrode is connected to the second power supply terminal, and a gate electrode is connected to The fourth node;
  • the second isolation circuit includes: a tenth transistor, a first electrode of the tenth transistor is connected to the second power terminal, a second electrode is connected to the eighth node, and a gate electrode is connected to the fifth node.
  • the pull-up circuit includes: an eleventh transistor, a twelfth transistor, and a first capacitor.
  • the first pole of the eleventh transistor is connected to the first clock signal terminal, and the second
  • the first electrode of the twelfth transistor is connected to the ninth node, the gate electrode is connected to the fifth node;
  • the first electrode of the twelfth transistor is connected to the ninth node, the second electrode is connected to the sixth node, and the gate electrode is connected to the first clock signal terminal.
  • the first capacitor is connected to the fifth node.
  • the pull-down circuit includes: a thirteenth transistor, a first electrode of the thirteenth transistor is connected to the third power terminal, a second electrode is connected to the sixth node, and a gate electrode is connected to the fourth node.
  • the first output circuit is further connected to a second output terminal for transmitting the signal of the second power terminal to the second output terminal in response to the signal of the fourth node;
  • the second output circuit is also connected to a second output terminal and a fourth power terminal, and is used to transmit the signal of the fourth power terminal to the second output terminal in response to the signal of the sixth node.
  • the first output The terminal or the second output terminal forms the output terminal of the gate drive circuit.
  • the effective driving levels of the first input circuit, the second input circuit, the pull-up circuit, the first output circuit, and the second output circuit are high levels;
  • the second power supply The terminal is a high-level signal terminal, the fourth power terminal and the third power terminal are both low-level signal terminals, and the voltage of the third power terminal is smaller than the voltage of the fourth power terminal.
  • the first output circuit includes: a fourteenth transistor, a fifteenth transistor, and a second capacitor.
  • the first pole of the fourteenth transistor is connected to the second power terminal, and the second
  • the first electrode of the fifteenth transistor is connected to the second power terminal, the second electrode is connected to the second output terminal, and the gate is connected to the fourth node.
  • the fourth node; the second capacitor is connected to the fourth node.
  • the second output circuit includes: a sixteenth transistor, a seventeenth transistor, and a third capacitor.
  • the first electrode of the sixteenth transistor is connected to the third power supply terminal, the second electrode is connected to the first output terminal, and the gate
  • the first electrode of the seventeenth transistor is connected to the fourth power supply terminal, the second electrode is connected to the second output terminal, and the gate electrode is connected to the sixth node; the third capacitor is connected to the Describe the sixth node.
  • the second output circuit includes: a sixteenth transistor and a twenty-fifth transistor.
  • the first pole of the sixteenth transistor is connected to the seventh node, and the second pole is connected to the seventh node.
  • the first output terminal, the gate electrode is connected to the sixth node;
  • the first electrode of the twenty-fifth transistor is connected to the seventh node, the second electrode is connected to the third power supply terminal, and the gate electrode is connected to the sixth node;
  • the third capacitor is connected to the sixth node.
  • the shift register unit further includes: a reset circuit connected to the fourth node, the first clock signal terminal, the reset signal terminal, the second power supply terminal, and the sixth node, for transmitting the signal of the first clock signal terminal to the fourth node in response to the signal of the reset signal terminal, and for transmitting the signal of the second power supply terminal to the sixth node in response to the signal of the reset signal terminal. node.
  • the first input circuit includes: a fourth transistor and a fifth transistor.
  • the first electrode of the fourth transistor is connected to the signal input terminal, the second electrode is connected to the seventh node, and the gate electrode Connect the first clock signal terminal;
  • the first electrode of the fifth transistor is connected to the seventh node, the second electrode is connected to the fourth node, and the gate electrode is connected to the first clock signal terminal;
  • the shift register unit It also includes: a first isolation circuit, the first isolation circuit is connected to the second power terminal, the fourth node, and the seventh node, and is used to transmit the signal of the second power terminal to the signal of the fourth node in response to the signal of the fourth node.
  • the seventh node; the reset circuit includes: an eighteenth transistor, a nineteenth transistor, and a twentieth transistor.
  • the first electrode of the eighteenth transistor is connected to the fourth node, the second electrode is connected to the tenth node, and the gate electrode Connect the reset signal terminal;
  • the first pole of the nineteenth transistor is connected to the tenth node, the second pole is connected to the first clock signal terminal, and the gate is connected to the reset signal terminal;
  • the first pole of the twentieth transistor is connected to the reset signal terminal.
  • the first pole is connected to the second power terminal, the second pole is connected to the sixth node, and the gate is connected to the reset signal terminal; wherein the seventh node is connected to the tenth node.
  • the first output terminal of the shift register unit of this stage is connected to the signal input terminal of the adjacent next-stage shift register unit;
  • a signal input line is connected to the signal input end of the first stage shift register unit in the first gate drive circuit;
  • the first clock signal line is connected to the third stage of the odd-stage shift register unit in the first gate drive circuit.
  • the second clock signal line is connected to the first clock signal terminal of the even-numbered shift register unit and the odd-numbered stage in the first gate drive circuit.
  • the second clock signal terminal of the shift register unit is connected to the first clock signal terminal of the even-numbered shift register unit and the odd-numbered stage in the first gate drive circuit.
  • the first output end of the shift register unit of this level is connected to the signal input end of the adjacent next-level shift register unit; the second signal input line is connected to the second gate The signal input end of the first-stage shift register unit in the gate drive circuit; the first clock signal line is connected to the first clock signal end of the odd-stage shift register unit in the second gate drive circuit and the even-stage shift register.
  • the second clock signal terminal of the unit, the second clock signal line is connected to the first clock signal terminal of the even-numbered shift register unit and the second clock signal terminal of the odd-stage shift register unit in the second gate drive circuit .
  • the gate driving circuit includes: a plurality of cascaded shift register units and a plurality of output control circuits, and the shift register units are arranged corresponding to the pixel driving circuit group,
  • the shift register unit is used to output the pulse width modulation signal through an output terminal;
  • the output control circuit is set correspondingly to the shift register unit, and the output control circuit is connected to the corresponding shift register unit.
  • the output control circuit is used to respond to the signal of the first control signal terminal to control the shifter.
  • the pulse width modulation signal at the output terminal of the bit register unit is transmitted to the third output terminal, and the signal from the fifth power supply terminal is transmitted to the fourth output terminal in response to the signal from the first control signal terminal.
  • the output control circuit It is also used to transmit the pulse width modulation signal of the output terminal of the shift register unit to the fourth output terminal in response to the signal of the second control signal terminal, and to transmit the pulse width modulation signal of the fifth power supply in response to the signal of the second control signal terminal.
  • the signal from the terminal is transmitted to the third output terminal; wherein the third output terminal and the fourth output terminal form the output terminal of the gate drive circuit, and the third output terminal is used to control the output to the
  • the odd-numbered pixel driving circuit rows corresponding to the circuit provide the pulse-width modulation signal
  • the fourth output terminal is used to provide the pulse-width modulation signal to the even-numbered pixel driving circuit rows corresponding to the output control circuit.
  • the output control circuit includes: a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, the first electrode of the twenty-first transistor Connected to the output end of the corresponding shift register unit, the second electrode is connected to the third output end, and the gate is connected to the first control signal end; the first electrode of the twenty-second transistor is connected to the corresponding shift register unit.
  • the second electrode is connected to the fourth output end, and the gate electrode is connected to the second control signal end;
  • the first electrode of the twenty-third transistor is connected to the fifth power supply end, and the second electrode is connected to the third Output terminal, the gate electrode is connected to the second control signal terminal;
  • the first electrode of the twenty-fourth transistor is connected to the fifth power supply terminal, the second electrode is connected to the fourth output terminal, and the gate electrode is connected to the first control signal terminal.
  • a display panel driving method is provided.
  • the display panel driving method is used to drive the above-mentioned display panel.
  • the display panel driving method includes:
  • the pulse width modulated signal is provided to different subsets of the pixel drive circuits within the same group of pixel drive circuits in at least partially different frames.
  • a display device wherein the display device includes the above-mentioned display panel.
  • Figure 1 is a schematic structural diagram of a pixel driving circuit in the related art
  • Figure 2 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure
  • Figure 3 is a complete structural diagram of area A in Figure 2;
  • Figure 4 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of the gate drive circuit GOA in Figure 2;
  • Figure 6a is a schematic structural diagram of an exemplary embodiment of the shift register unit in Figure 5;
  • Figure 6b is a schematic structural diagram of another exemplary embodiment of the shift register unit in Figure 5;
  • Figure 7 is a timing diagram of each node in a driving method of the shift register unit shown in Figure 6a;
  • Figure 8 is a timing diagram of each signal line in a driving method of the display panel shown in Figure 5;
  • Figure 9 is a schematic structural diagram of another exemplary embodiment of a gate driving circuit in a display panel of the present disclosure.
  • FIG. 10 is a timing diagram of each node in a driving method of the shift register unit shown in FIG. 9 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include a driving circuit 74, a first switching unit 71, a second switching unit 72, a third switching unit 73, and a capacitor C.
  • the driving circuit is connected to the first node N1, the second node N2, and the third node N3, and is used to input a driving current to the third node N3 through the second node N2 in response to the signal of the first node N1;
  • the first switch The first end of the unit 71 is connected to the first power supply terminal VDD, the second end is connected to the second node N2, and the control end is connected to the pulse width modulation signal terminal PWM for responding to the pulse width modulation signal of the pulse width modulation signal terminal PWM to connect
  • the second switch unit 72 is connected to the data signal terminal Da, the first node N1, and the first gate drive signal terminal G1 for responding to the first gate drive
  • the signal of the signal terminal G1 is connected to the first node N1 and the data signal terminal Da;
  • the third switch unit 73 is connected to the third node N3, the sensing signal terminal Sense, and the second gate drive signal terminal G2 for responding to the second gate
  • the driving circuit 74 may include: a driving transistor DT, a first electrode of the driving transistor DT is connected to the second node N2, a second electrode is connected to the third node N3, and a gate electrode is connected to the third node N3.
  • a node N1; the first switch unit 71 may include: a first transistor T1, the first electrode of the first transistor T1 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate electrode is connected to The pulse width modulation signal terminal PWM.
  • the second switch unit 72 may include: a second transistor T2, a first electrode of the second transistor T2 is connected to the data signal terminal Da, a second electrode is connected to the first node N1, and a gate electrode is connected to the first gate drive signal terminal G1.
  • the third switching unit 73 may include a third transistor T3, a first electrode of the third transistor T3 is connected to the third node N3, a second electrode is connected to the sensing signal terminal Sense, and a gate is connected to the second gate drive signal terminal G2.
  • the first transistor T1, the second transistor T2, and the third transistor T3 may all be N-type transistors.
  • the first power terminal VDD may be a high-level power terminal
  • the sixth power terminal VSS may be a low-level power terminal.
  • the pixel driving circuit can turn on the second transistor T2 during the data writing phase and write a data signal to the first node N1 through the data signal terminal Da; during the light-emitting phase, through the pulse width modulation signal terminal PWM
  • the pulse width modulation signal turns on the first transistor T1 to connect the first power terminal VDD and the second node.
  • the driving transistor DT provides a driving current to the third node N3 according to the voltage of the first node N1 to drive the light-emitting unit OLED to emit light.
  • the display panel can adjust the brightness of the light-emitting unit OLED by adjusting the duty cycle of the pulse width modulation signal.
  • the threshold value of the first transistor T1 will drift seriously, thereby affecting the display effect.
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure.
  • Figure 3 is the complete structure of area A in Figure 2.
  • the display panel may include: a plurality of pixel driving circuits Pix, and the pixel driving circuit Pix may be as shown in FIG. 1 , wherein FIG. 2 shows the first switch unit 71 in the pixel driving circuit and other pixel driving circuits.
  • Circuit structure P A plurality of the pixel driving circuits Pix are distributed in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect.
  • the first direction X may be a row direction
  • the second direction Y may is the column direction.
  • a plurality of the pixel driving circuits Pix may form a plurality of pixel driving circuit groups Pz
  • the pixel driving circuit group Pz may include odd-numbered pixel driving circuit rows located in odd-numbered rows and even-numbered pixel driving circuit rows located in even-numbered rows
  • the Two pixel driving circuit rows in the pixel driving circuit group Pz may be arranged adjacently in the second direction Y.
  • the pixel driving circuit row includes a plurality of the pixel driving circuits Pix distributed along the first direction. As shown in FIGS. 2 and 3 , in the same pixel driving circuit group Pz, the second ends of the first switch units 71 in the two pixel driving circuits distributed in the second direction Y are connected to each other.
  • the display panel can selectively provide the pulse width modulation signal to two pixel driving circuits in the same pixel driving circuit group in the same frame, and provide the pulse width modulation signal to the same pixel driving circuit in at least part of different frames.
  • Different pixel driving circuit rows in the pixel driving circuit group provide the pulse width modulation signal.
  • the display panel can provide a pulse width modulation signal to the odd-numbered pixel driving circuit rows in the first driving period.
  • the first switch unit 71 in the odd-numbered pixel driving circuit rows is turned on, and the first power terminal VDD passes through the odd-numbered pixel driving circuit rows.
  • the first switch unit 71 in the pixel driving circuit row provides power supply voltage to the second node N2 in the odd pixel driving circuit row and the second node N2 in the even pixel driving circuit row respectively, thereby realizing the odd pixel driving circuit row and the even pixel
  • the driving circuit rows enter the light-emitting stage at the same time.
  • the display panel can provide a pulse width modulation signal to the even-numbered pixel driving circuit rows in the second driving period.
  • the first switch unit 71 in the even-numbered pixel driving circuit rows is turned on, and the first power terminal VDD is driven by the even-numbered pixels.
  • the first switch unit 71 in the circuit row provides power supply voltage to the second node N2 in the odd pixel driving circuit row and the second node N2 in the even pixel driving circuit row respectively, thereby realizing the odd pixel driving circuit row and the even pixel driving circuit.
  • the rows enter the glowing stage at the same time.
  • the first switch unit in the even-numbered pixel driving circuit row is not conductive, and the first switching unit in the even-numbered pixel driving circuit row can perform threshold recovery during this period.
  • the first switch unit in the odd-numbered pixel driving circuit row is not conductive, and the first switching unit in the odd-numbered pixel driving circuit row can perform threshold recovery during this period. Therefore, the display panel can improve the above-mentioned threshold drift problem of the first switch unit.
  • the first driving period and the second driving period may include one frame or multiple frames.
  • the display panel may also include: a gate drive circuit GOA1 and a gate drive circuit GOA2.
  • the gate drive circuit GOA1 may be used to provide the first gate drive signal terminal G1 in the pixel drive circuit row by row. gate drive signal.
  • the gate driving circuit GOA2 may be used to provide gate driving signals row by row to the second gate driving signal terminal G2 in the pixel driving circuit.
  • the display panel may further include a gate driving circuit GOA.
  • the gate driving circuit GOA may include multiple output terminals. The output terminals are arranged corresponding to the rows of the pixel driving circuits, and the output terminals are used to provide signals to the rows of the pixel driving circuits.
  • the control end of the first switch unit 71 in the corresponding pixel driving circuit row provides the pulse width modulation signal.
  • the gate driving circuit GOA may be used to provide the pulse width modulation signal to either an odd pixel driving circuit row or an even pixel driving circuit row in the same frame, and the gate driving circuit is used to provide the pulse width modulation signal to an odd pixel driving circuit row or an even pixel driving circuit row in at least part of the frame. providing the pulse width modulated signal to odd numbered pixel drive circuit rows, and for providing the pulse width modulated signal to even numbered pixel drive circuit rows for at least part of the frame.
  • the second end of the first switch unit 71 in the same pixel driving circuit row may be connected through the first connection line L1.
  • the second ends of the first switch units in two pixel driving circuits adjacently distributed in the second direction Y may be connected through the second connection line L2.
  • the first connection line L1 and the second connection line L2 intersect to form a grid structure, thereby reducing the potential difference between the second nodes in different pixel driving circuits.
  • the display panel may also be provided with only the second connection line L2.
  • the second end of any first switching unit may be connected to the second end of the first switching unit in the pixel driving circuit at any position in another pixel driving circuit row. end.
  • the second end of the first switch unit in the pixel drive circuit of the first column in the odd-numbered pixel drive circuit row can be connected to the first switch unit of the second column pixel drive circuit in the even-numbered pixel drive circuit row. Second end.
  • the pixel driving circuit group Pz may also include other numbers of pixel driving circuit rows, and multiple pixel driving circuit rows in the same pixel driving circuit group Pz may be arranged adjacently.
  • FIG. 4 it is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • the pixel driving circuit group Pz may include four pixel driving circuit rows.
  • the second end of any first switch unit 71 is connected to at least one of the other pixel driving circuit rows.
  • the second end of a switch unit 71 is connected.
  • the gate driving circuit GOA may be used to provide the pulse width modulation signal to a subset of pixel driving circuits in the same pixel driving circuit group in the same frame, and some of the pixel driving circuit rows in the pixel driving circuit group form the The pixel driving circuit subset is provided, and the gate driving circuit is configured to provide the pulse width modulation signal to different pixel driving circuit subsets in the same pixel driving circuit group in at least part of different frames.
  • the pixel driving circuit subgroup may include one or more pixel driving circuit rows. For example, when the pixel driving circuit subgroup includes one pixel driving circuit row, the display panel can provide pulse width modulation signals to each pixel driving circuit row in the same pixel driving circuit group during different driving periods to achieve different pixel driving.
  • the circuit row turns on the first switch unit in time intervals to provide sufficient recovery time for the first switch unit.
  • the driving period may include one frame or multiple frames.
  • different pixel driving circuit subgroups may have different combinations of pixel driving circuit rows.
  • the same pixel driving circuit group may be supplied to the same pixel driving circuit group during the first driving period.
  • the pixel driving circuit row located in the first row and the pixel driving circuit row located in the second row provide pulse width modulation signals, which can be used in the second driving period to provide the pixel driving circuit row located in the second row and the pixel driving circuit row located in the same pixel driving circuit group.
  • the pixel driving circuit row located in the third row provides a pulse width modulation signal, which can provide pulse width modulation signals to the pixel driving circuit row located in the third row and the pixel driving circuit row located in the fourth row in the same pixel driving circuit group.
  • this setting can also reserve sufficient recovery time for the first switch unit.
  • the pixel driving circuit in the display panel of the present disclosure can also have other structures, as long as the pixel driving circuit includes a first switch unit connected between the driving transistor and the high-level power terminal, and the pixel driving circuit The circuit can improve the threshold drift of the first switch unit through the above settings.
  • FIG. 5 it is a schematic structural diagram of the gate driving circuit GOA in FIG. 2 .
  • the gate driving circuit may include: a first gate driving circuit 81 and a second gate driving circuit 82.
  • the first gate driving circuit 81 is connected to the first signal input line STUA, the first clock signal line LC1, and the second clock signal line STUA.
  • the signal line LC2 is used to provide the pulse width modulation signal to the odd-numbered pixel driving circuit rows in response to the signals of the first signal input line STUA, the first clock signal line LC1, and the second clock signal line LC2; the second gate driver
  • the circuit 82 is connected to the second signal input line STUB, the first clock signal line LC1 and the second clock signal line LC2, and is used to respond to the second signal input line STUB, the first clock signal line LC1 and the second clock signal line LC2.
  • signal provides the pulse width modulated signal to even rows of pixel drive circuits.
  • the first gate driving circuit 81 may include multiple cascaded shift register units PWM
  • the second gate driving circuit 82 may include multiple cascaded shift register units PWM.
  • shift register unit PWM As shown in Figure 6a, it is a schematic structural diagram of an exemplary embodiment of the shift register unit in Figure 5.
  • the shift register unit may include: a first input circuit 11 , a second input circuit 12 , a pull-up circuit 3 , a pull-down circuit 4 , a first output circuit 21 , and a second output circuit 22 .
  • the first input circuit 11 is connected to the signal input terminal In, the first clock signal terminal CK1 and the fourth node N4, and is used to transmit the signal of the signal input terminal In to the third node N4 in response to the signal of the first clock signal terminal CK1.
  • the second input circuit 12 is connected to the second power terminal VGH, the second clock signal terminal CK2, the fifth node N5, and the signal input terminal In, and is used to respond to the signal of the second clock signal terminal CK2 to convert the third
  • the signal of the second power terminal VGH is transmitted to the fifth node N5, and the signal of the second clock signal terminal CK2 is transmitted to the fifth node N5 in response to the signal of the signal input terminal In;
  • a pull-up circuit 3 is connected to the first clock signal terminal CK1, the fifth node N5, and the sixth node N6, for responding to the signals of the fifth node N5 and the first clock signal terminal CK1 to convert the signal of the first clock signal terminal CK1 is transmitted to the sixth node N6; the pull
  • the signal of the second power terminal VGH is transmitted to the first output terminal Out1; the second output circuit 22 is connected to the sixth node N6, the third power terminal LVGL and the first output terminal Out1 for responding to the sixth node
  • the signal of N6 transmits the signal of the third power terminal LVGL to the first output terminal Out1.
  • the second power supply terminal VGH may be a valid level terminal
  • the third power supply terminal LVGL may be an inactive level terminal.
  • the shift register cell driving method may include seven stages. In the first stage, the shift register unit may input a valid level to the first clock signal terminal Ck1 and input an invalid level to the second clock signal terminal CK2 and the signal input terminal In. Among them, the effective level is the potential that can drive the target circuit to operate normally. In the first stage, the first input circuit 11 transmits the invalid level of the signal input terminal In to the fourth clock signal terminal In under the action of the first clock signal terminal CK1. Node N4.
  • the fifth node N5 maintains the effective level of the previous stage, and the pull-up circuit 3 transmits the effective level of the first clock signal terminal CK1 to the effective level of the first clock signal terminal CK1 under the action of the fifth node N5 and the effective level of the first clock signal terminal CK1.
  • the second output circuit 22 transmits the inactive level of the third power terminal LVGL to the first output terminal Out1 under the action of the active level of the sixth node N6. In the second stage, a valid level can be input to the second clock signal terminal CK2, and an invalid level can be input to the first clock signal terminal CK1 and the signal input terminal In.
  • the second input circuit 12 can transmit the effective level of the second power terminal VGH to the fifth node N5 under the action of the second clock signal terminal CK2.
  • the fourth node N4 maintains the inactive level of the previous stage
  • the sixth node N6 maintains At the effective level of the previous stage
  • the second output circuit 22 transmits the inactive level of the third power supply terminal LVGL to the first output terminal Out1 under the action of the effective level of the sixth node N6.
  • a valid level is input to the first clock signal terminal CK1
  • an invalid level is input to the second clock signal terminal CK2 and the signal input terminal In.
  • the first input circuit 11 transmits the inactive level of the signal input terminal In to the fourth node N4 under the action of the first clock signal terminal CK1.
  • the fifth node N5 maintains the effective level of the previous stage, and the pull-up circuit 3 transmits the effective level of the first clock signal terminal CK1 to the effective level of the first clock signal terminal CK1 under the action of the fifth node N5 and the effective level of the first clock signal terminal CK1.
  • the second output circuit 22 transmits the inactive level of the third power terminal LVGL to the first output terminal Out1 under the action of the active level of the sixth node N6.
  • an inactive level is input to the first clock signal terminal CK1
  • a valid level is input to the second clock signal terminal CK2 and the signal input terminal In.
  • the second input circuit 12 can transmit the effective levels of the second clock signal terminal CK2 and the second power terminal VGH to the fifth node N5 under the action of the signal input terminal In and the second clock signal terminal CK2, and the fourth node N4 maintains
  • the sixth node N6 maintains the inactive level of the previous stage, and the second output circuit 22 transmits the inactive level of the third power terminal LVGL to the inactive level of the third power terminal LVGL under the action of the effective level of the sixth node N6.
  • One output terminal Out1 In the fifth stage, an inactive level is input to the second clock signal terminal CK2, and a valid level is input to the first clock signal terminal Ck1 and the signal input terminal In.
  • the first input circuit 11 transmits the effective level of the signal input terminal In to the fourth node N4 under the action of the first clock signal terminal CK1.
  • the pull-down circuit 4 transmits the inactive level of the third power terminal LVGL to the sixth node N6 under the action of the fourth node N4.
  • the first output circuit 21 transmits the effective level of the second power terminal VGH to the first output terminal Out1 under the action of the fourth node N4.
  • an inactive level is input to the first clock signal terminal CK1 and the signal input terminal In, and a valid level is input to the second clock signal terminal CK2.
  • the second input circuit 12 can transmit the effective level of the second power terminal VGH to the fifth node N5 under the action of the second clock signal terminal CK2.
  • the sixth node N6 maintains the inactive level of the previous stage, and the fourth node N4 maintains the effective level of the previous stage.
  • the first output circuit 21 transmits the effective level of the second power terminal VGH to the first output terminal Out1 under the action of the fourth node N4.
  • an inactive level is input to the second clock signal terminal CK2 and the signal input terminal In, and a valid level is input to the first clock signal terminal CK1.
  • the first input circuit 11 transmits the inactive level of the signal input terminal In to the fourth node N4 under the action of the first clock signal terminal CK1.
  • the pull-up circuit 3 transmits the effective level of the first clock signal terminal CK1 to the sixth node N6 under the action of the fifth node N5 and the first clock signal terminal CK1.
  • the second output circuit 22 transmits the effective level of the sixth node N6 to The inactive level of the third power terminal LVGL is transmitted to the first output terminal Out1 under the action of the voltage level.
  • the shift register unit can realize the shift output of the signal.
  • the first input circuit 11 may include: a fourth transistor T4 and a fifth transistor T5.
  • the first pole of the fourth transistor T4 is connected to the signal input terminal In.
  • the second electrode is connected to the seventh node N7, and the gate is connected to the first clock signal terminal CK1;
  • the first electrode of the fifth transistor T5 is connected to the seventh node N7, the second electrode is connected to the fourth node N4, and the gate is connected to The first clock signal terminal CK1.
  • the second input circuit 12 includes: a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the first electrode of the seventh transistor T7 is connected to the second power supply terminal VGH, and the second electrode is connected to the fifth node.
  • the gate is connected to the second clock signal terminal CK2; the first electrode of the eighth transistor T8 is connected to the fifth node N5, the second electrode is connected to the eighth node N8, and the gate is connected to the signal input terminal In; The first pole of the nine-transistor T9 is connected to the eighth node N8, the second pole is connected to the second clock signal terminal CK2, and the gate is connected to the signal input terminal In.
  • the shift register unit further includes: a first isolation circuit 51 and a second isolation circuit 52.
  • the first isolation circuit 51 is connected to the second power terminal VGH and the fourth power terminal VGH.
  • Node N4 and seventh node N7 are used to transmit the signal of the second power terminal VGH to the seventh node N7 in response to the signal of the fourth node N4;
  • the second isolation circuit 52 is connected to the eighth node N8 , the second power terminal VGH and the fifth node N5, for transmitting the signal of the second power terminal VGH to the eighth node N8 in response to the signal of the fifth node N5.
  • the first isolation circuit 51 may include: a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the seventh node N7, and a second pole is connected to the seventh node N7.
  • the gate of the second power terminal VGH is connected to the fourth node N4;
  • the second isolation circuit 52 may include: a tenth transistor T10, the first pole of the tenth transistor T10 is connected to the second power terminal VGH, and the second The gate electrode is connected to the eighth node N8, and the gate electrode is connected to the fifth node N5.
  • the pull-up circuit 3 may include: an eleventh transistor T11, a twelfth transistor T12, and a first capacitor C1.
  • the first pole of the eleventh transistor T11 is connected to
  • the first clock signal terminal CK1 has a second electrode connected to the ninth node N9 and a gate connected to the fifth node N5; the first electrode of the twelfth transistor T12 is connected to the ninth node N9 and the second electrode is connected to the The gate of the sixth node N6 is connected to the first clock signal terminal CK1; the first capacitor C1 may be connected between the fifth node N5 and the ninth node.
  • the pull-down circuit 4 may include: a thirteenth transistor T13, a first electrode of the thirteenth transistor T13 is connected to the third power terminal LVGL, a second electrode is connected to the sixth node N6, and a gate is connected to the fourth Node N4.
  • the first capacitor C1 may also be connected between the fifth node N5 and other signal terminals.
  • the first output circuit 21 may also be connected to a second output terminal Out2 for converting the signal of the second power terminal VGH in response to the signal of the fourth node N4. transmitted to the second output terminal Out2; the second output circuit 22 can also be connected to the second output terminal Out2 and the fourth power supply terminal VGL, for responding to the signal of the sixth node N6 to switch the fourth power supply terminal
  • the VGL signal is transmitted to the second output terminal Out2.
  • the first output circuit 21 may include: a fourteenth transistor T14, a fifteenth transistor T15, a second capacitor C2, and the first pole of the fourteenth transistor T14 is connected
  • the second power terminal VGH has a second pole connected to the first output terminal Out1 and a gate connected to the fourth node N4; the first pole of the fifteenth transistor T15 is connected to the second power terminal VGH and the second The electrode is connected to the second output terminal Out2, and the gate is connected to the fourth node N4; the second capacitor C2 can be connected between the fourth node N4 and the first output terminal Out1.
  • the second output circuit 22 may include: a sixteenth transistor T16, a seventeenth transistor T17, and a third capacitor C3.
  • the first pole of the sixteenth transistor T16 is connected to the third power supply terminal LVGL, and the second pole is connected to the third power supply terminal LVGL.
  • the first output terminal Out1 the gate is connected to the sixth node N6;
  • the first electrode of the seventeenth transistor T17 is connected to the fourth power supply terminal VGL, the second electrode is connected to the second output terminal Out2, and the gate is connected
  • the third capacitor C3 may be connected between the sixth node N6 and the third power terminal LVGL.
  • the second capacitor C2 may also be connected between the fourth node N4 and other signal terminals, and the third capacitor C3 may also be connected between the sixth node N6 and other signal terminals.
  • the shift register unit may also include: a reset circuit 6.
  • the reset circuit 6 may be connected to the fourth node N4, the first clock signal terminal CK1, and the reset signal terminal TRS. , the second power terminal VGH, the sixth node, used for transmitting the signal of the first clock signal terminal CK1 to the fourth node N4 in response to the signal of the reset signal terminal TRS, and for responding to the reset signal
  • the signal of the terminal TRS transmits the signal of the second power terminal VGH to the sixth node N6.
  • the reset circuit 6 may include: an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20.
  • the first pole of the eighteenth transistor T18 is connected to The fourth node N4 has a second electrode connected to the tenth node N10 and a gate connected to the reset signal terminal TRS; a first electrode of the nineteenth transistor T19 is connected to the tenth node N10 and a second electrode connected to the first
  • the gate of the clock signal terminal CK1 is connected to the reset signal terminal TRS;
  • the first pole of the twentieth transistor T20 is connected to the second power terminal VGH, the second pole is connected to the sixth node N6, and the gate is connected to the reset Signal terminal TRS; wherein the seventh node N7 is connected to the tenth node N10.
  • the fourth to twentieth transistors T4 to T20 may all be N-type transistors.
  • the effective driving levels of the first input circuit 11, the second input circuit 12, the pull-up circuit 3, the first output circuit 21, and the second output circuit 22 are high levels, that is, the first input circuit 11.
  • the second input circuit 12, the pull-up circuit 3, the first output circuit 21, and the second output circuit 22 can be turned on under the action of a high level.
  • the second power terminal VGH may be a high-level signal terminal
  • the fourth power terminal VGL and the third power terminal LVGL may be low-level signal terminals.
  • the second output circuit 22 in the shift register unit shown in FIG. 6b may further include a twenty-fifth transistor T25.
  • the first electrode of the sixteenth transistor T16 is connected to the seventh node N7
  • the second electrode is connected to the first output terminal Out1
  • the gate is connected to the sixth node N6
  • the first electrode of the twenty-fifth transistor T25 is connected to the first output terminal Out1.
  • the first pole is connected to the seventh node N7
  • the second pole is connected to the third power terminal LVGL
  • the gate is connected to the sixth node N6.
  • the first output terminal Out1 outputs a high level
  • the fourth node N4 outputs a high level
  • the sixth transistor T6 transmits the high level signal of the second power terminal VGH to the seventh node under the action of the fourth node N4.
  • N7, the first output terminal Out1 and the seventh node N7 have a small voltage difference, so this setting can reduce the leakage current of the first output terminal Out1 through the sixteenth transistor T16.
  • FIG 7 it is a timing diagram of each node in a driving method of the shift register unit shown in Figure 6a.
  • In is the timing diagram of the input signal input terminal
  • CK1 is the timing diagram of the first clock signal terminal
  • CK2 is the timing diagram of the second clock signal terminal
  • N5 is the timing diagram of the fifth node
  • N4 is the timing diagram of the fourth node
  • N6 is the timing diagram of the sixth node
  • Out1 is the timing diagram of the first output terminal
  • Out2 is the timing diagram of the second output terminal.
  • the driving method of the shift register unit may include seven stages. As shown in Figure 7, in the first stage t1, a valid level is input to the first clock signal terminal Ck1, and an invalid level is input to the second clock signal terminal CK2 and the signal input terminal In.
  • the effective level is a potential that can drive the target circuit to operate normally. In this exemplary embodiment, the effective level is a high level, and correspondingly, the ineffective level is a low level.
  • the fourth transistor T4 and the fifth transistor T5 are turned on under the action of the first clock signal terminal CK1, and the signal input terminal In inputs a low level signal to the fourth node.
  • the fifth node N5 maintains the high-level signal of the previous stage, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the first clock signal terminal CK1 inputs a high-level signal to the sixth node N6, and the sixteenth transistor T16 It is turned on under the action of the sixth node N6, the third power terminal LVGL inputs a low level signal to the first output terminal Out1, the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power terminal VGL supplies the second The output terminal Out2 inputs a low level signal.
  • the threshold drift of the eighth transistor T8 and the voltage change of the signal input terminal In due to the rise of the voltage of the third power supply terminal LVGL can cause the turn-off leakage current of the eighth transistor T8 to increase.
  • the tenth transistor T10 is turned on under the action of the fifth node N5, and the second power terminal VGH inputs a high-level signal to the eighth node N8. This setting can reduce the voltages of the fifth node N5 and the eighth node N8. difference, thereby reducing the leakage current of the fifth node N5 through the eighth transistor T8.
  • the first output terminal Out1 can be cascaded with the signal input terminal In of the adjacent next-level shift register unit, and the second output terminal Out2 can provide a pulse to the corresponding row of pixel driving circuits. wide modulated signal.
  • the voltage of the third power supply terminal LVGL may be smaller than the voltage of the fourth power supply terminal VGL.
  • the smaller third power supply terminal LVGL can effectively turn off the third power supply terminal in the next stage shift register unit. eight transistors, thereby reducing the leakage current of the fifth node.
  • the third power terminal LVGL may also be shared as the fourth power terminal VGL.
  • a valid level can be input to the second clock signal terminal CK2, and an invalid level can be input to the first clock signal terminal CK1 and the signal input terminal In.
  • the seventh transistor T7 is turned on under the action of the second clock signal terminal CK2, the second power terminal VGH inputs a high level signal to the fifth node N5, the fourth node N4 maintains the low level signal of the previous stage, and the sixth node N6 maintains the high level signal of the previous stage, the sixteenth transistor T16 is turned on under the action of the sixth node N6, the third power supply terminal LVGL inputs a low level signal to the first output terminal Out1, and the seventeenth transistor T17 The six nodes N6 are turned on, and the fourth power supply terminal VGL inputs a low level signal to the second output terminal Out2.
  • a valid level is input to the first clock signal terminal CK1
  • an invalid level is input to the second clock signal terminal CK2 and the signal input terminal In.
  • the fourth transistor T4 and the fifth transistor T5 are turned on under the action of the first clock signal terminal CK1, and the signal input terminal In inputs a low level signal to the fourth node.
  • the fifth node N5 maintains the high-level signal of the previous stage, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the first clock signal terminal CK1 inputs a high-level signal to the sixth node N6, and the sixteenth transistor T16 It is turned on under the action of the sixth node N6, the third power terminal LVGL inputs a low level signal to the first output terminal Out1, the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power terminal VGL supplies the second The output terminal Out2 inputs a low level signal.
  • an inactive level is input to the first clock signal terminal CK1, and a valid level is input to the second clock signal terminal CK2 and the signal input terminal In.
  • the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, the second power terminal VGH and the second clock signal terminal CK2 both input high-level signals to the fifth node N5, and the fourth node N4 maintains the previous stage.
  • the sixth node N6 maintains the high level signal of the previous stage
  • the sixteenth transistor T16 is turned on under the action of the sixth node N6, and the third power supply terminal LVGL inputs a low level signal to the first output terminal Out1
  • the seventeenth transistor T17 is turned on under the action of the sixth node N6, and the fourth power supply terminal VGL inputs a low level signal to the second output terminal Out2.
  • an inactive level is input to the second clock signal terminal CK2, and a valid level is input to the first clock signal terminal Ck1 and the signal input terminal In.
  • the fourth transistor T4 and the fifth transistor T5 are turned on under the action of the first clock signal terminal CK1, the signal input terminal In inputs a high level signal to the fourth node N4, and the fourteenth transistor T14 is turned on under the action of the fourth node N4 , the second power supply terminal VGH inputs a high-level signal to the first output terminal Out1, the fifteenth transistor T15 is turned on under the action of the fourth node N4, and the second power supply terminal VGH inputs a high-level signal to the second output terminal Out2.
  • the thirteenth transistor T13 is turned on under the action of the fourth node N4, the third power terminal LVGL inputs a low level signal to the sixth node N6, and the sixteenth transistor T16 and the seventeenth transistor T17 act on the sixth node N6 down shutdown.
  • the eighth transistor T8 and the ninth transistor T9 are turned on under the action of the signal input terminal In, and the second clock signal terminal CK2 inputs a low level signal to the fifth node N5.
  • the sixth transistor T6 is turned on under the action of the fourth node N4, and the second power terminal VGH inputs a high level signal to the seventh node N7 and the tenth node N10.
  • This setting can reduce the voltage of the fourth node N4 and the seventh node N7.
  • the voltage difference between the fourth node N4 and the tenth node N10 can be reduced, thereby reducing the leakage current of the fourth node N4 through the fifth transistor T5 and the eighteenth transistor T18.
  • an inactive level is input to the first clock signal terminal CK1 and the signal input terminal In, and a valid level is input to the second clock signal terminal CK2.
  • the seventh transistor T7 is turned on under the action of the second clock signal terminal CK2, the second power terminal VGH inputs a high level signal to the fifth node N5, the sixth node N6 maintains the low level signal of the previous stage, and the fourth node N4 maintains the high level signal of the previous stage.
  • the fourteenth transistor T14 is turned on under the action of the fourth node N4, the second power supply terminal VGH inputs a high level signal to the first output terminal Out1, the fifteenth transistor T15 is turned on under the action of the fourth node N4, the second power supply terminal The terminal VGH inputs a high level signal to the second output terminal Out2.
  • an inactive level is input to the second clock signal terminal CK2 and the signal input terminal In, and a valid level is input to the first clock signal terminal CK1.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the signal input terminal In inputs a low-level signal to the fourth node N4.
  • the eleventh transistor T11 is turned on under the action of the fifth node N5, and the twelfth transistor T12 is turned on under the action of the first clock signal terminal CK1.
  • the first clock signal terminal CK1 provides a high level signal to the sixth node N6.
  • the sixteenth transistor T16 is turned on under the action of the sixth node N6.
  • the third power supply terminal LVGL inputs a low level signal to the first output terminal Out1.
  • the seventeenth transistor T17 is turned on under the action of the sixth node N6.
  • the fourth power supply terminal T16 is turned on under the action of the sixth node N6.
  • the terminal VGL inputs a low level signal to the second output
  • the duration of the high-level pulse output by the signal input terminal In can be adjusted according to actual needs.
  • the first clock signal terminal CK1 outputs at least one high-level pulse signal
  • the second clock signal terminal CK2 outputs at least one high-level pulse signal
  • the first clock signal terminal CK1 outputs at least one high-level pulse signal.
  • the second clock signal terminal CK2 outputs a low-level signal.
  • the first clock signal terminal CK1 outputs a low-level signal. That is, as shown in FIG. 7 , within a single high-level pulse period output from the signal input terminal In, the shift register unit driving method includes at least a fourth phase t4 and a fifth phase t5 .
  • the first output terminal Out1 of the shift register unit of this stage is connected to the signal input of the adjacent shift register unit of the next stage. terminal In; the first signal input line STUA is connected to the signal input terminal In of the first stage shift register unit in the first gate driving circuit; the first clock signal line LC1 is connected to the first gate driving circuit The first clock signal terminal CK1 of the odd-numbered stage shift register unit and the second clock signal terminal CK2 of the even-numbered shift register unit, the second clock signal line LC2 is connected to the even-numbered shift register unit of the first gate driving circuit. The first clock signal terminal CK1 of the bit register unit and the second clock signal terminal CK2 of the odd-stage shift register unit.
  • the first output terminal Out1 of the shift register unit of this stage is connected to the signal input terminal In of the adjacent next-stage shift register unit;
  • the second signal input line STUB is connected to the The signal input terminal In of the first-stage shift register unit in the second gate drive circuit;
  • the first clock signal line LC1 is connected to the first clock signal terminal of the odd-stage shift register unit in the second gate drive circuit.
  • the second clock signal line LC2 connects the first clock signal terminal CK1 and the odd-numbered stage shift register unit in the second gate drive circuit.
  • the display panel may also include a reset signal line LTRS, which is connected to the reset signal terminals of all shift register units.
  • FIG. 8 it is a timing diagram of each signal line in a driving method of the display panel shown in FIG. 5 .
  • SUTA is the timing diagram of the first signal input line
  • STUB is the timing diagram of the second signal input line
  • LC1 is the timing diagram of the first clock signal line LC1
  • LC2 is the timing diagram of the second clock signal line
  • LTRS is the reset Timing diagram of signal lines.
  • the first signal input line STUA outputs a high-level pulse signal
  • the shift register unit in the first gate driving circuit 81 outputs a pulse width modulation signal step by step to provide pulses to the odd pixel driving circuit rows row by row. wide modulated signal.
  • the second signal input line STUB continues to output a low level signal, and each shift register unit in the second gate driving circuit 82 continues to output a low level. It should be understood that in other frames, the second signal input line STUB can output a high-level pulse signal, and the shift register unit in the second gate driving circuit 82 outputs a pulse width modulation signal step by step to drive the even pixels.
  • the circuit provides a pulse width modulated signal row by row.
  • the first signal input line STUA can continuously output a low level signal, and each shift register unit in the first gate driving circuit 81 continues to output a low level.
  • the display panel can realize time-sharing conduction of the first transistor in the odd-numbered pixel driving circuit rows and the first transistor in the even-numbered pixel driving circuit rows, thereby improving the threshold shift problem of the first transistor.
  • the first gate driving circuit 81 and the second gate driving circuit 82 alternately output pulse width modulation signals. This arrangement can also ensure that the fourteenth transistor T14, the sixteenth transistor T16 and other transistors in the shift register unit are fully supplied. threshold recovery time. For example, when the first gate driving circuit 81 outputs a pulse width modulation signal, the gate of the fourteenth transistor T14 in the first gate driving circuit is at a high level for a long time, and the gate of the sixteenth transistor T16 The gate is at a low level for a long time.
  • the gate of the fourteenth transistor T14 in the first gate driving circuit is at a low level for a long time.
  • the sixteenth transistor The gate of T16 is high for a long time. This setting can improve the stability of the gate drive circuit.
  • one frame F includes a blank period F1 and a scan period F2.
  • the reset signal line LTRS can output a high-level signal in the blank period F1 of the first frame to turn on the eighteenth transistor in all shift register units. T18, the nineteenth transistor T19, and the twentieth transistor T20, thereby resetting the sixth node N6 through the second power supply terminal VGH, and resetting the fourth node N4 through the first clock signal terminal CK1.
  • the signal of the first clock signal terminal CK1 may be a low-level signal.
  • the black dot area in Figure 8 is an omitted area of the timing diagram.
  • FIG. 9 it is a schematic structural diagram of another exemplary embodiment of a gate driving circuit in a display panel of the present disclosure.
  • the gate drive circuit may also include: a plurality of cascaded shift register units PWM and a plurality of output control circuits 9.
  • the shift register unit PWM is arranged corresponding to the pixel drive circuit group Pz.
  • the register unit PWM is used to output the pulse width modulation signal through the output terminal; the output control circuit 9 is set correspondingly to the shift register unit PWM, and the output control circuit 9 is connected to the corresponding shift register unit PWM
  • the output terminal, the fifth power terminal VGL5, the first control signal terminal VDDA, the second control signal terminal VDDB, the third output terminal Out3, and the fourth output terminal Out4, the output control circuit 9 is used to respond to the first control
  • the signal of the signal terminal VDDA transmits the pulse width modulation signal of the output terminal of the shift register unit to the third output terminal Out3, and in response to the signal of the first control signal terminal VDDA, the signal of the fifth power supply terminal VGL5 is transmitted to The fourth output terminal Out4, the output control circuit 9 is also used to transmit the pulse width modulation signal of the output terminal of the shift register unit to the fourth output terminal Out4 in response to the signal of the second control signal terminal VDDB, and in response to the The signal of the second control signal terminal VDDB transmits the signal of the fifth power
  • the third output terminal Out3 is used to provide the pulse width modulation signal to the odd-numbered pixel driving circuit rows corresponding to the output control circuit, and the fourth output terminal Out4 is used to drive the even-numbered pixels corresponding to the output control circuit.
  • Rows of circuits provide the pulse width modulated signal.
  • the output control circuit 9 and the pixel driving circuit row corresponding to the same shift register unit correspond to each other.
  • the output control circuit 9 may include: a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fourth transistor T24.
  • the first electrode of the twenty-first transistor T21 is connected to the output terminal of the corresponding shift register unit, the second electrode is connected to the third output terminal Out3, and the gate electrode is connected to the first control signal terminal VDDA;
  • the first electrode of the twelve transistors T22 is connected to the output terminal of the corresponding shift register unit, the second electrode is connected to the fourth output terminal Out4, and the gate is connected to the second control signal terminal VDDB;
  • the twenty-third transistor T23 The first pole is connected to the fifth power terminal VGL5, the second pole is connected to the third output terminal Out3, and the gate is connected to the second control signal terminal VDDB;
  • the first pole of the twenty-fourth transistor T24 is connected to the The fifth power terminal VGL5 has a second electrode connected to the fourth output terminal Out4 and a gate connected to the first
  • the twenty-first to twenty-fourth transistors T21 to T24 may all be N-type transistors, and the fifth power supply terminal VGL5 may be a low-level signal terminal.
  • the shift register unit in the gate drive circuit can be shown in Figure 6a.
  • FIG. 10 it is a timing diagram of each node in a driving method of the shift register unit shown in Figure 9.
  • VDDA is the timing diagram of the first control signal terminal
  • VDDB is the timing diagram of the second control signal terminal.
  • the shift register unit driving method may include two driving periods: a first driving period t1 and a second driving period t2. Among them, during the first driving period t1, a low-level signal is input to the first control signal terminal VDDA, a high-level signal is input to the second control signal terminal VDDB, and the twenty-first transistor T21 and the twenty-fourth transistor T24 are turned on.
  • the twenty-second transistor T22 and the twenty-third transistor T23 are turned off, and the plurality of output control circuits 9 transmit the pulse width modulation signals output by the shift register unit to the odd-numbered pixel driving circuit rows.
  • a high-level signal is input to the first control signal terminal VDDA and a low-level signal is input to the second control signal terminal VDDB.
  • the twenty-first transistor T21 and the twenty-fourth transistor T24 are turned off.
  • the twenty-second transistor T22 and the twenty-third transistor T23 are turned on, and the plurality of output control circuits 9 transmit the pulse width modulation signal output by the shift register unit to the even-numbered pixel driving circuit rows.
  • the display panel can realize time-sharing conduction of the first transistor in the odd-numbered pixel driving circuit rows and the first transistor in the even-numbered pixel driving circuit rows, thereby improving the threshold shift problem of the first transistor.
  • the above-mentioned first driving period t1 and second driving period t2 may include one frame or multiple frames.
  • the voltage of the first control signal terminal VDDA and the second control signal terminal VDDB in the high-level stage may be equal to the voltage of the second power supply terminal VGH in the shift register unit, and the first control signal terminal VDDA and the second control signal terminal VDDB are in the low-level stage.
  • the voltage of the stage may be equal to the voltage of the third power supply terminal LVGL in the shift register unit.
  • This exemplary embodiment also provides a display panel driving method, which is used to drive the above-mentioned display panel.
  • the display panel driving method includes:
  • the pulse width modulated signal is provided to different subsets of the pixel drive circuits within the same group of pixel drive circuits in at least partially different frames.
  • This exemplary embodiment also provides a display device, wherein the display device may include the above-mentioned display panel.
  • the display device can be a display device of a mobile phone, a tablet computer, or a television.

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Abstract

一种显示面板及其驱动方法、显示装置。显示面板包括：多个像素驱动电路(Pix)，多个像素驱动电路(Pix)沿第一方向(X)和第二方向(Y)阵列分布，第一方向(X)和第二方向(Y)相交，多个像素驱动电路(Pix)形成多个像素驱动电路组(Pz)，每个像素驱动电路组(Pz)包括多个像素驱动电路行，像素驱动电路行包括多个沿第一方向(X)分布的像素驱动电路(Pix)，像素驱动电路(Pix)包括：驱动电路(74)、第一开关单元(71)，驱动电路(74)连接第一节点(N1)、第二节点(N2)、第三节点(N3)，用于响应第一节点(N1)的信号通过第二节点(N2)向第三节点(N3)输入驱动电流；第一开关单元(71)的第一端连接第一电源端(VDD)，第二端连接第二节点(N2)，用于响应一脉宽调制信号以连接第一电源端(VDD)和第二节点(N2)；其中，在同一像素驱动电路组(Pz)中，任一第一开关单元(71)的第二端与其他每一像素驱动电路行中至少一个第一开关单元(71)的第二端连接。可以改善第一开关单元(71)阈值偏移的问题。

Description

显示面板及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其驱动方法、显示装置。
背景技术
相关技术中，像素驱动电路通常包括有连接于电源端和驱动晶体管之间的开关晶体管，显示面板可以通过控制该开关晶体管栅极脉宽调制信号的占空比调节该像素驱动电路所在子像素的亮度。然而，由于该开关晶体管长时间处于导通状态，从而导致该开关晶体管阈值漂移严重，进而影响正常显示。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括：多个像素驱动电路，多个所述像素驱动电路沿第一方向和第二方向阵列分布，所述第一方向和第二方向相交，多个所述像素驱动电路形成多个像素驱动电路组，每个所述像素驱动电路组包括多个像素驱动电路行，所述像素驱动电路行包括多个沿第一方向分布的所述像素驱动电路，所述像素驱动电路包括：驱动电路、第一开关单元，驱动电路连接第一节点、第二节点、第三节点，用于响应所述第一节点的信号通过所述第二节点向所述第三节点输入驱动电流；第一开关单元的第一端连接第一电源端，第二端连接所述第二节点，用于响应一脉宽调制信号以连接所述第一电源端和所述第二节点；其中，在同一所述像素驱动电路组中，任一第一开关单元的第二端与其他每一像素驱动电路行中至少一个所述第一开关单元的第二端连接。
本公开一种示例性实施例中，所述驱动电路包括：驱动晶体管，驱动晶体管的第一极连接所述第二节点，第二极连接所述第三节点，栅极连接所述第一节点；所述第一开关单元包括：第一晶体管，第一晶体管的第一极连接所述第一电源端，第二极连接所述第二节点，栅极连接所述脉宽调制信号端。所述像素驱动电路还包括：第二晶体管、第三晶体管、电容，第二晶体管的第一极连接数据信号端，第二极连接所述第一节点，栅极连接第一栅极驱动信号端；第三晶体管的第一极连接所述第三节点，第二极连接感测信号端，栅极连接第二栅极驱动信号端；电容连接于所述第一节点和所述第三节点之间。
本公开一种示例性实施例中，所述显示面板还包括：栅极驱动电路，所述栅极驱动电路包括多个输出端，所述输出端与所述像素驱动电路行对应设置，所述输出端用于向与其对应的所述像素驱动电路行中所述第一开关单元的控制端提供所述脉宽调制信号；所述栅极驱动电路用于在同一帧中向同一所述像素驱动电路组中的像素驱动电路子组提供所述脉宽调制信号，所述像素驱动电路组中的部分像素驱动电路行形成所述像素驱动电路子组，且所述栅极驱动电路用于在至少部分不同帧中向同一所述像素驱动电路组中不同的所述像素驱动电路子组提供所述脉宽调制信号。
本公开一种示例性实施例中，所述像素驱动电路组包括在所述第二方向上相邻的多个像素驱动电路行，在同一所述像素驱动电路组中，在所述第二方向上分布的多个所述像素驱动电路中的第一开关单元的第二端相互连接。
本公开一种示例性实施例中，所述像素驱动电路子组包括一个所述像素驱动电路行，所述像素驱动电路组包括位于奇数行的奇数像素驱动电路行和位于偶数行的偶数像素驱动电路行，且所述像素驱动电路组中的两像素驱动电路行在所述第二方向上相邻设置；所述栅极驱动电路用于在同一帧中向奇数像素驱动电路行或偶数像素驱动电路行择一提供所述脉宽调制信号，且所述栅极驱动电路用于在至少部分帧中向奇数像素驱动电路行提供所述脉宽调制信号，以及用于在至少部分帧中向偶数像素驱动电路行提供所述脉宽调制信号。
本公开一种示例性实施例中，所述栅极驱动电路包括：第一栅极驱动 电路、第二栅极驱动电路，第一栅极驱动电路连接第一信号输入线、第一时钟信号线、第二时钟信号线，用于响应所述第一信号输入线、第一时钟信号线、第二时钟信号线的信号向奇数像素驱动电路行提供所述脉宽调制信号；第二栅极驱动电路连接第二信号输入线、第一时钟信号线、第二时钟信号线，用于响应所述第二信号输入线、第一时钟信号线、第二时钟信号线的信号向偶数像素驱动电路行提供所述脉宽调制信号。
本公开一种示例性实施例中，所述第一栅极驱动电路包括多个级联的移位寄存器单元，所述第二栅极驱动电路包括多个级联的移位寄存器单元；所述移位寄存器单元包括：第一输入电路、第二输入电路、上拉电路、下拉电路、第一输出电路、第二输出电路，第一输入电路连接信号输入端、第一时钟信号端、第四节点，用于响应所述第一时钟信号端的信号将所述信号输入端的信号传输到所述第四节点；第二输入电路连接第二电源端，第二时钟信号端、第五节点、信号输入端，用于响应所述第二时钟信号端的信号将所述第二电源端的信号传输到所述第五节点，以及用于响应所述信号输入端的信号将所述第二时钟信号端的信号传输到所述第五节点；上拉电路连接所述第一时钟信号端、第五节点、第六节点，用于响应所述第五节点和第一时钟信号端的信号将所述第一时钟信号端的信号传输到所述第六节点；下拉电路连接所述第四节点、第三电源端、第六节点，用于响应所述第四节点的信号将所述第三电源端的信号传输到所述第六节点；第一输出电路连接所述第四节点、第一输出端、第二电源端，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第一输出端；第二输出电路连接所述第六节点、第三电源端、第一输出端，用于响应所述第六节点的信号将所述第三电源端的信号传输到所述第一输出端。
本公开一种示例性实施例中，所述第一输入电路包括：第四晶体管、第五晶体管，第四晶体管的第一极连接所述信号输入端，第二极连接第七节点，栅极连接所述第一时钟信号端；第五晶体管的第一极连接所述第七节点，第二极连接所述第四节点，栅极连接所述第一时钟信号端。所述第二输入电路包括：第七晶体管、第八晶体管、第九晶体管，第七晶体管的第一极连接所述第二电源端，第二极连接所述第五节点，栅极连接所述第二时钟信号端；第八晶体管的第一极连接所述第五节点，第二极连接第八 节点，栅极连接所述信号输入端；第九晶体管的第一极连接所述第八节点，第二极连接所述第二时钟信号端，栅极连接所述信号输入端。
本公开一种示例性实施例中，所述移位寄存器单元还包括：第一隔离电路、第二隔离电路，第一隔离电路连接所述第二电源端、第四节点、第七节点，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第七节点；第二隔离电路连接所述第八节点、第二电源端、第五节点，用于响应所述第五节点的信号将所述第二电源端的信号传输到所述第八节点。
本公开一种示例性实施例中，所述第一隔离电路包括：第六晶体管，第六晶体管的第一极连接所述第七节点，第二极连接所述第二电源端，栅极连接所述第四节点；所述第二隔离电路包括：第十晶体管，第十晶体管的第一极连接所述第二电源端，第二极连接所述第八节点，栅极连接所述第五节点。
本公开一种示例性实施例中，所述上拉电路包括：第十一晶体管、第十二晶体管、第一电容，第十一晶体管的第一极连接所述第一时钟信号端，第二极连接第九节点，栅极连接所述第五节点；第十二晶体管的第一极连接所述第九节点，第二极连接所述第六节点，栅极连接所述第一时钟信号端；第一电容连接于所述第五节点。所述下拉电路包括：第十三晶体管，第十三晶体管的第一极连接所述第三电源端，第二极连接所述第六节点，栅极连接所述第四节点。
本公开一种示例性实施例中，所述第一输出电路还连接第二输出端，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第二输出端；所述第二输出电路还连接第二输出端、第四电源端，用于响应所述第六节点的信号将所述第四电源端的信号传输到所述第二输出端，所述第一输出端或所述第二输出端形成所述栅极驱动电路的输出端。
本公开一种示例性实施例中，所述第一输入电路、第二输入电路、上拉电路、第一输出电路、第二输出电路的有效驱动电平为高电平；所述第二电源端为高电平信号端，所述第四电源端和所述第三电源端同为低电平信号端，且所述第三电源端的电压小于所述第四电源端的电压。
本公开一种示例性实施例中，所述第一输出电路包括：第十四晶体管、 第十五晶体管、第二电容，第十四晶体管的第一极连接所述第二电源端，第二极连接所述第一输出端，栅极连接所述第四节点；第十五晶体管的第一极连接所述第二电源端，第二极连接所述第二输出端，栅极连接所述第四节点；第二电容连接于所述第四节点。所述第二输出电路包括：第十六晶体管、第十七晶体管、第三电容，第十六晶体管的第一极连接所述第三电源端，第二极连接所述第一输出端，栅极连接所述第六节点；第十七晶体管的第一极连接所述第四电源端，第二极连接所述第二输出端，栅极连接所述第六节点；第三电容连接于所述第六节点。
本公开一种示例性实施例中，所述第二输出电路包括：第十六晶体管、第二十五晶体管，第十六晶体管的第一极连接所述第七节点，第二极连接所述第一输出端，栅极连接所述第六节点；第二十五晶体管的第一极连接所述第七节点，第二极连接所述第三电源端，栅极连接所述第六节点；第三电容连接于所述第六节点。
本公开一种示例性实施例中，所述移位寄存器单元还包括：复位电路，复位电路连接所述第四节点、第一时钟信号端、复位信号端、第二电源端、第六节点，用于响应所述复位信号端的信号将所述第一时钟信号端的信号传输到所述第四节点，以及用于响应所述复位信号端的信号将所述第二电源端的信号传输到所述第六节点。
本公开一种示例性实施例中，所述第一输入电路包括：第四晶体管、第五晶体管，第四晶体管的第一极连接所述信号输入端，第二极连接第七节点，栅极连接所述第一时钟信号端；第五晶体管的第一极连接所述第七节点，第二极连接所述第四节点，栅极连接所述第一时钟信号端；所述移位寄存器单元还包括：第一隔离电路，第一隔离电路连接所述第二电源端、第四节点、第七节点，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第七节点；所述复位电路包括：第十八晶体管、第十九晶体管、第二十晶体管，第十八晶体管的第一极连接所述第四节点，第二极连接第十节点，栅极连接所述复位信号端；第十九晶体管的第一极连接所述第十节点，第二极连接所述第一时钟信号端，栅极连接所述复位信号端；第二十晶体管的第一极连接所述第二电源端，第二极连接所述第六节点，栅极连接所述复位信号端；其中，所述第七节点连接所述第十节点。
本公开一种示例性实施例中，在所述第一栅极驱动电路中：本级移位寄存器单元的第一输出端连接相邻下一级移位寄存器单元的信号输入端；所述第一信号输入线连接所述第一栅极驱动电路中首级移位寄存器单元的信号输入端；所述第一时钟信号线连接所述第一栅极驱动电路中奇数级移位寄存器单元的第一时钟信号端和偶数级移位寄存器单元的第二时钟信号端，所述第二时钟信号线连接所述第一栅极驱动电路中偶数级移位寄存器单元的第一时钟信号端和奇数级移位寄存器单元的第二时钟信号端。在所述第二栅极驱动电路中：本级移位寄存器单元的第一输出端连接相邻下一级移位寄存器单元的信号输入端；所述第二信号输入线连接所述第二栅极驱动电路中首级移位寄存器单元的信号输入端；所述第一时钟信号线连接所述第二栅极驱动电路中奇数级移位寄存器单元的第一时钟信号端和偶数级移位寄存器单元的第二时钟信号端，所述第二时钟信号线连接所述第二栅极驱动电路中偶数级移位寄存器单元的第一时钟信号端和奇数级移位寄存器单元的第二时钟信号端。
本公开一种示例性实施例中，所述栅极驱动电路包括：多个级联的移位寄存器单元、多个输出控制电路，所述移位寄存器单元与所述像素驱动电路组对应设置，所述移位寄存器单元用于通过输出端输出所述脉宽调制信号；所述输出控制电路与所述移位寄存器单元对应设置，所述输出控制电路连接与其对应的所述移位寄存器单元的输出端、第五电源端、第一控制信号端、第二控制信号端、第三输出端、第四输出端，所述输出控制电路用于响应所述第一控制信号端的信号将所述移位寄存器单元输出端的脉宽调制信号传输到所述第三输出端，以及响应所述第一控制信号端的信号将所述第五电源端的信号传输到所述第四输出端，所述输出控制电路还用于响应所述第二控制信号端的信号将所述移位寄存器单元输出端的脉宽调制信号传输到所述第四输出端，以及响应所述第二控制信号端的信号将所述第五电源端的信号传输到所述第三输出端；其中，所述第三输出端和所述第四输出端形成所述栅极驱动电路的输出端，所述第三输出端用于向所述输出控制电路对应的奇数像素驱动电路行提供所述脉宽调制信号，所述第四输出端用于向所述输出控制电路对应的偶数像素驱动电路行提供所述脉宽调制信号。
本公开一种示例性实施例中，所述输出控制电路包括：第二十一晶体管、第二十二晶体管、第二十三晶体管、第二十四晶体管，第二十一晶体管的第一极连接与其对应的所述移位寄存器单元的输出端，第二极连接第三输出端，栅极连接所述第一控制信号端；第二十二晶体管的第一极连接与其对应的所述移位寄存器单元的输出端，第二极连接第四输出端，栅极连接所述第二控制信号端；第二十三晶体管的第一极连接所述第五电源端，第二极连接第三输出端，栅极连接所述第二控制信号端；第二十四晶体管的第一极连接所述第五电源端，第二极连接第四输出端，栅极连接所述第一控制信号端。
根据本公开的一个方面，提供一种显示面板驱动方法，所述显示面板驱动方法用于驱动上述的显示面板，所述显示面板驱动方法包括：
在同一帧中向同一所述像素驱动电路组中的像素驱动电路子组提供所述脉宽调制信号，所述像素驱动电路组中的部分像素驱动电路行形成所述像素驱动电路子组，且在至少部分不同帧中向同一所述像素驱动电路组中不同的所述像素驱动电路子组提供所述脉宽调制信号。
根据本公开的一个方面，提供一种显示装置，其中，所述显示装置包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种像素驱动电路的结构示意图；
图2为本公开显示面板一种示例性实施例的结构示意图；
图3为图2中区域A的完整结构示意图；
图4为本公开显示面板另一种示例性实施例中的结构示意图；
图5为图2中栅极驱动电路GOA的结构示意图；
图6a为图5中移位寄存器单元一种示例性实施例的结构示意图；
图6b为为图5中移位寄存器单元另一种示例性实施例的结构示意图；
图7为图6a所示移位寄存器单元一种驱动方法中各节点的时序图；
图8为图5所示显示面板一种驱动方法中各信号线的时序图；
图9为本公开显示面板中栅极驱动电路另一种示例性实施例的结构示意图；
图10为图9所示移位寄存器单元一种驱动方法中各节点的时序图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中一种像素驱动电路的结构示意图。该像素驱动电路可以包括驱动电路74、第一开关单元71、第二开关单元72、第三开关单元73、电容C。驱动电路连接第一节点N1、第二节点N2、第三节点N3，用于响应所述第一节点N1的信号通过所述第二节点N2向所述第三节点N3输入驱动电流；第一开关单元71的第一端连接第一电源端VDD，第二端连接所述第二节点N2，控制端连接脉宽调制信号端PWM，用于响应脉宽调制信号端PWM的脉宽调制信号以连接所述第一电源端VDD和所述第二节点N2；第二开关单元72连接数据信号端Da、第一节点N1、第一栅极驱动信号端G1，用于响应所述第一栅极驱动信号端G1的信号以连接第一节点N1和数据信号端Da；第三开关单元73连接第三节点N3、感测信号端Sense、第二栅极驱动信号端G2，用于响应第二栅极驱动信号端G2的信号以连接第三节点N3和感测信号端Sense；电容C连接于所述第一节点N1和所述第三节点N3之间。第三节点N3用于连接一发光单元OLED的第一电极，发光单元OLED的另一电极可以连接于 第六电源端VSS。
如图1所示，所述驱动电路74可以包括：驱动晶体管DT，驱动晶体管DT的第一极连接所述第二节点N2，第二极连接所述第三节点N3，栅极连接所述第一节点N1；所述第一开关单元71可以包括：第一晶体管T1，第一晶体管T1的第一极连接所述第一电源端VDD，第二极连接所述第二节点N2，栅极连接所述脉宽调制信号端PWM。第二开关单元72可以包括：第二晶体管T2，第二晶体管T2的第一极连接数据信号端Da，第二极连接所述第一节点N1，栅极连接第一栅极驱动信号端G1。第三开关单元73可以包括第三晶体管T3，第三晶体管T3的第一极连接所述第三节点N3，第二极连接感测信号端Sense，栅极连接第二栅极驱动信号端G2。其中，第一晶体管T1、第二晶体管T2、第三晶体管T3均可以为N型晶体管。第一电源端VDD可以为高电平电源端，第六电源端VSS可以为低电平电源端。
如图1所示，该像素驱动电路可以在数据写入阶段，导通第二晶体管T2，通过数据信号端Da向第一节点N1写入数据信号；在发光阶段，通过脉宽调制信号端PWM的脉宽调制信号导通第一晶体管T1，以连接第一电源端VDD和第二节点，驱动晶体管DT根据第一节点N1的电压向第三节点N3提供驱动电流，以驱动发光单元OLED发光。其中，该显示面板可以通过调节脉宽调制信号的占空比调节发光单元OLED的亮度。然而，由于第一晶体管T1长期处于导通状态，从而会导致第一晶体管T1阈值漂移严重，进而影响显示效果。
基于此，本示例性实施例提供一种显示面板，如图2、3所示，图2为本公开显示面板一种示例性实施例的结构示意图，图3为图2中区域A的完整结构示意图。所述显示面板可以包括：多个像素驱动电路Pix，该像素驱动电路Pix可以如图1所示，其中，图2示出了像素驱动电路中的第一开关单元71和像素驱动电路中的其他电路结构P。多个所述像素驱动电路Pix沿第一方向X和第二方向Y阵列分布，所述第一方向X和第二方向Y相交，例如，第一方向X可以为行方向，第二方向Y可以为列方向。多个所述像素驱动电路Pix可以形成多个像素驱动电路组Pz，所述像素驱动电路组Pz可以包括位于奇数行的奇数像素驱动电路行和位于偶 数行的偶数像素驱动电路行，且所述像素驱动电路组Pz中的两像素驱动电路行可以在所述第二方向Y上相邻设置。其中，所述像素驱动电路行包括多个沿第一方向分布的所述像素驱动电路Pix。如图2、3所示，在同一所述像素驱动电路组Pz中，在所述第二方向Y上分布的两个所述像素驱动电路中的第一开关单元71的第二端相互连接。
本示例性实施例中，该显示面板可以在同一帧中向同一所述像素驱动电路组中的两像素驱动电路行择一提供所述脉宽调制信号，且在至少部分不同帧中向同一所述像素驱动电路组中不同的像素驱动电路行提供所述脉宽调制信号。例如，该显示面板可以在第一驱动时段中，向奇数像素驱动电路行提供脉宽调制信号，此时，奇数像素驱动电路行中的第一开关单元71导通，第一电源端VDD通过奇数像素驱动电路行中的第一开关单元71分别向奇数像素驱动电路行中的第二节点N2和偶数像素驱动电路行中的第二节点N2提供电源电压，从而实现奇数像素驱动电路行和偶数像素驱动电路行同时进入发光阶段。该显示面板可以在第二驱动时段中，向偶数像素驱动电路行提供脉宽调制信号，此时，偶数像素驱动电路行中的第一开关单元71导通，第一电源端VDD通过偶数像素驱动电路行中的第一开关单元71分别向奇数像素驱动电路行中的第二节点N2和偶数像素驱动电路行中的第二节点N2提供电源电压，从而实现奇数像素驱动电路行和偶数像素驱动电路行同时进入发光阶段。本示例性实施例中，在第一驱动时段中，偶数像素驱动电路行中的第一开关单元不导通，偶数像素驱动电路行中的第一开关单元可以在该时段进行阈值恢复，在第二驱动时段中，奇数像素驱动电路行中的第一开关单元不导通，奇数像素驱动电路行中的第一开关单元可以在该时段进行阈值恢复。从而该显示面板可以改善上述的第一开关单元阈值漂移的问题。其中，第一驱动时段和第二驱动时段可以包括一帧或多帧。
如图2所示，该显示面板还可以包括：栅极驱动电路GOA1、栅极驱动电路GOA2，栅极驱动电路GOA1可以用于向像素驱动电路中的第一栅极驱动信号端G1逐行提供栅极驱动信号。栅极驱动电路GOA2可以用于向像素驱动电路中的第二栅极驱动信号端G2逐行提供栅极驱动信号。
如图2所示，该显示面板还可以包括栅极驱动电路GOA，栅极驱动 电路GOA可以包括多个输出端，输出端与所述像素驱动电路行对应设置，所述输出端用于向与其对应的所述像素驱动电路行中第一开关单元71的控制端提供所述脉宽调制信号。所述栅极驱动电路GOA可以用于在同一帧中向奇数像素驱动电路行或偶数像素驱动电路行择一提供所述脉宽调制信号，且所述栅极驱动电路用于在至少部分帧中向奇数像素驱动电路行提供所述脉宽调制信号，以及用于在至少部分帧中向偶数像素驱动电路行提供所述脉宽调制信号。
本示例性实施例中，如图2所示，同一像素驱动电路行中第一开关单元71的第二端可以通过第一连接线L1连接。同一像素驱动电路组中，在第二方向Y上相邻分布的两像素驱动电路中第一开关单元的第二端可以通过第二连接线L2连接。第一连接线L1和第二连接线L2相交形成网格结构，从而可以降低不同像素驱动电路中第二节点的电位差。应该理解的是，在其他示例性实施例中，该显示面板也可以仅设置第二连接线L2。此外，在其他示例性实施例中，同一像素驱动电路组中，任一第一开关单元的第二端可以连接另一像素驱动电路行中任一位置像素驱动电路中第一开关单元的第二端。例如，同一像素驱动电路组中，奇数像素驱动电路行中第一列像素驱动电路中第一开关单元的第二端可以连接偶数像素驱动电路行中第二列像素驱动电路中第一开关单元的第二端。
在其他示例性实施例中，像素驱动电路组Pz中还可以包括其他数量的像素驱动电路行，且同一像素驱动电路组Pz中的多个像素驱动电路行可以相邻设置。如图4所示，为本公开显示面板另一种示例性实施例中的结构示意图。其中，像素驱动电路组Pz可以包括四个像素驱动电路行，在同一像素驱动电路组Pz中，任一第一开关单元71的第二端与其他每一像素驱动电路行中至少一个所述第一开关单元71的第二端连接。栅极驱动电路GOA可以用于在同一帧中向同一所述像素驱动电路组中的像素驱动电路子组提供所述脉宽调制信号，所述像素驱动电路组中的部分像素驱动电路行形成所述像素驱动电路子组，且所述栅极驱动电路用于在至少部分不同帧中向同一所述像素驱动电路组中不同的所述像素驱动电路子组提供所述脉宽调制信号。其中，像素驱动电路子组可以包括一个或多个像素驱动电路行。例如，当像素驱动电路子组包括一个像素驱动电路行时， 该显示面板可以在不同驱动时段分别向同一像素驱动电路组中的每一像素驱动电路行提供脉宽调制信号，以实现不同像素驱动电路行分时段打开其中的第一开关单元，从而给第一开关单元提供充足的恢复时间，上述驱动时段可以包括一帧或多帧。当像素驱动电路子组包括多个像素驱动电路行时，不同的所述像素驱动电路子组可以具有不同的像素驱动电路行的组合，例如，可以在第一驱动时段，向同一像素驱动电路组中位于第一行的像素驱动电路行和位于第二行的像素驱动电路行提供脉宽调制信号，可以在第二驱动时段，向同一像素驱动电路组中位于第二行的像素驱动电路行和位于第三行的像素驱动电路行提供脉宽调制信号，可以在第三驱动时段，向同一像素驱动电路组中位于第三行的像素驱动电路行和位于第四行的像素驱动电路行提供脉宽调制信号，该设置同样可以给第一开关单元预留充足的恢复时间。此外，在其他示例性实施例中，本公开显示面板中像素驱动电路还可以为其他结构，只要像素驱动电路包括连接于驱动晶体管和高电平电源端之间的第一开关单元，该像素驱动电路均可以通过上述设置改善第一开关单元的阈值漂移。
本示例性实施例中，如图5所示，为图2中栅极驱动电路GOA的结构示意图。所述栅极驱动电路可以包括：第一栅极驱动电路81、第二栅极驱动电路82，第一栅极驱动电路81连接第一信号输入线STUA、第一时钟信号线LC1、第二时钟信号线LC2，用于响应所述第一信号输入线STUA、第一时钟信号线LC1、第二时钟信号线LC2的信号向奇数像素驱动电路行提供所述脉宽调制信号；第二栅极驱动电路82连接第二信号输入线STUB、第一时钟信号线LC1、第二时钟信号线LC2，用于响应所述第二信号输入线STUB、第一时钟信号线LC1、第二时钟信号线LC2的信号向偶数像素驱动电路行提供所述脉宽调制信号。
本示例性实施例中，如图5所示，所述第一栅极驱动电路81可以包括多个级联的移位寄存器单元PWM，所述第二栅极驱动电路82可以包括多个级联的移位寄存器单元PWM。如图6a所示，为图5中移位寄存器单元一种示例性实施例的结构示意图。所述移位寄存器单元可以包括：第一输入电路11、第二输入电路12、上拉电路3、下拉电路4、第一输出电路21、第二输出电路22。第一输入电路11连接信号输入端In、第一时钟信 号端CK1、第四节点N4，用于响应所述第一时钟信号端CK1的信号将所述信号输入端In的信号传输到所述第四节点N4；第二输入电路12连接第二电源端VGH，第二时钟信号端CK2、第五节点N5、信号输入端In，用于响应所述第二时钟信号端CK2的信号将所述第二电源端VGH的信号传输到所述第五节点N5，以及用于响应所述信号输入端In的信号将所述第二时钟信号端CK2的信号传输到所述第五节点N5；上拉电路3连接所述第一时钟信号端CK1、第五节点N5、第六节点N6，用于响应所述第五节点N5和第一时钟信号端CK1的信号将所述第一时钟信号端CK1的信号传输到所述第六节点N6；下拉电路4连接所述第四节点N4、第三电源端LVGL、第六节点N6，用于响应所述第四节点N4的信号将所述第三电源端LVGL的信号传输到所述第六节点N6；第一输出电路21连接所述第四节点N4、第一输出端Out1、第二电源端VGH，用于响应所述第四节点N4的信号将所述第二电源端VGH的信号传输到所述第一输出端Out1；第二输出电路22连接所述第六节点N6、第三电源端LVGL、第一输出端Out1，用于响应所述第六节点N6的信号将所述第三电源端LVGL的信号传输到所述第一输出端Out1。
本示例性实施例中，第二电源端VGH可以为有效电平端，第三电源端LVGL可以为无效电平端。该移位寄存器单元驱动方法可以包括七个阶段。该移位寄存器单元可以在第一阶段，向第一时钟信号端Ck1输入有效电平、向第二时钟信号端CK2、信号输入端In输入无效电平。其中，有效电平即为能够驱动目标电路正常工作的电位，在第一阶段中，第一输入电路11在第一时钟信号端CK1的作用下将信号输入端In的无效电平传输到第四节点N4。第五节点N5维持上一阶段的有效电平，上拉电路3在第五节点N5和第一时钟信号端CK1的有效电平作用下，将第一时钟信号端CK1的有效电平传输到第六节点N6。第二输出电路22在第六节点N6的有效电平作用下将第三电源端LVGL的无效电平传输到第一输出端Out1。在第二阶段，可以向第二时钟信号端CK2输入有效电平、向第一时钟信号端CK1、信号输入端In输入无效电平。第二输入电路12可以在第二时钟信号端CK2作用下将第二电源端VGH的有效电平传输到第五节点N5，第四节点N4维持上一阶段的无效电平，第六节点N6维持上一阶段的有 效电平，第二输出电路22在第六节点N6的有效电平作用下将第三电源端LVGL的无效电平传输到第一输出端Out1。在第三阶段，向第一时钟信号端CK1输入有效电平、向第二时钟信号端CK2、信号输入端In输入无效电平。第一输入电路11在第一时钟信号端CK1的作用下将信号输入端In的无效电平传输到第四节点N4。第五节点N5维持上一阶段的有效电平，上拉电路3在第五节点N5和第一时钟信号端CK1的有效电平作用下，将第一时钟信号端CK1的有效电平传输到第六节点N6。第二输出电路22在第六节点N6的有效电平作用下将第三电源端LVGL的无效电平传输到第一输出端Out1。在第四阶段，向第一时钟信号端CK1输入无效电平、向第二时钟信号端CK2、信号输入端In输入有效电平。第二输入电路12可以在信号输入端In和第二时钟信号端CK2的作用下将第二时钟信号端CK2和第二电源端VGH的有效电平传输到第五节点N5，第四节点N4维持上一阶段的无效电平，第六节点N6维持上一阶段的有效电平，第二输出电路22在第六节点N6的有效电平作用下将第三电源端LVGL的无效电平传输到第一输出端Out1。在第五阶段，向第二时钟信号端CK2输入无效电平、向第一时钟信号端Ck1、信号输入端In输入有效电平。第一输入电路11在第一时钟信号端CK1的作用下将信号输入端In的有效电平传输到第四节点N4。下拉电路4在第四节点N4的作用下将第三电源端LVGL的无效电平传输到第六节点N6。第一输出电路21在第四节点N4作用下将第二电源端VGH的有效电平传输到第一输出端Out1。在第六阶段，向第一时钟信号端CK1、信号输入端In输入无效电平、向第二时钟信号端CK2输入有效电平。第二输入电路12可以在第二时钟信号端CK2作用下将第二电源端VGH的有效电平传输到第五节点N5。第六节点N6维持上一阶段的无效电平，第四节点N4维持上一阶段的有效电平。第一输出电路21在第四节点N4作用下将第二电源端VGH的有效电平传输到第一输出端Out1。在第七阶段，向第二时钟信号端CK2、信号输入端In输入无效电平、向第一时钟信号端CK1输入有效电平。第一输入电路11在第一时钟信号端CK1的作用下将信号输入端In的无效电平传输到第四节点N4。上拉电路3在第五节点N5和第一时钟信号端CK1的作用下将第一时钟信号端CK1的有效电平传输到第六节点N6，第二输出电路22在第六节点 N6的有效电平作用下将第三电源端LVGL的无效电平传输到第一输出端Out1。该移位寄存器单元可以实现信号的移位输出。
本示例性实施例中，如图6a所示，所述第一输入电路11可以包括：第四晶体管T4、第五晶体管T5，第四晶体管T4的第一极连接所述信号输入端In，第二极连接第七节点N7，栅极连接所述第一时钟信号端CK1；第五晶体管T5的第一极连接所述第七节点N7，第二极连接所述第四节点N4，栅极连接所述第一时钟信号端CK1。所述第二输入电路12包括：第七晶体管T7、第八晶体管T8、第九晶体管T9，第七晶体管T7的第一极连接所述第二电源端VGH，第二极连接所述第五节点N5，栅极连接所述第二时钟信号端CK2；第八晶体管T8的第一极连接所述第五节点N5，第二极连接第八节点N8，栅极连接所述信号输入端In；第九晶体管T9的第一极连接所述第八节点N8，第二极连接所述第二时钟信号端CK2，栅极连接所述信号输入端In。
本示例性实施例中，如图6a所示，所述移位寄存器单元还包括：第一隔离电路51、第二隔离电路52，第一隔离电路51连接所述第二电源端VGH、第四节点N4、第七节点N7，用于响应所述第四节点N4的信号将所述第二电源端VGH的信号传输到所述第七节点N7；第二隔离电路52连接所述第八节点N8、第二电源端VGH、第五节点N5，用于响应所述第五节点N5的信号将所述第二电源端VGH的信号传输到所述第八节点N8。
本示例性实施例中，如图6a所示，所述第一隔离电路51可以包括：第六晶体管T6，第六晶体管T6的第一极连接所述第七节点N7，第二极连接所述第二电源端VGH，栅极连接所述第四节点N4；所述第二隔离电路52可以包括：第十晶体管T10，第十晶体管T10的第一极连接所述第二电源端VGH，第二极连接所述第八节点N8，栅极连接所述第五节点N5。
本示例性实施例中，如图6a所示，所述上拉电路3可以包括：第十一晶体管T11、第十二晶体管T12、第一电容C1，第十一晶体管T11的第一极连接所述第一时钟信号端CK1，第二极连接第九节点N9，栅极连接所述第五节点N5；第十二晶体管T12的第一极连接所述第九节点N9，第 二极连接所述第六节点N6，栅极连接所述第一时钟信号端CK1；第一电容C1可以连接于所述第五节点N5和第九节点之间。所述下拉电路4可以包括：第十三晶体管T13，第十三晶体管T13的第一极连接所述第三电源端LVGL，第二极连接所述第六节点N6，栅极连接所述第四节点N4。第一电容C1还可以连接于所述第五节点N5和其他信号端之间。
本示例性实施例中，如图6a所示，所述第一输出电路21还可以连接第二输出端Out2，用于响应所述第四节点N4的信号将所述第二电源端VGH的信号传输到所述第二输出端Out2；所述第二输出电路22还可以连接第二输出端Out2、第四电源端VGL，用于响应所述第六节点N6的信号将所述第四电源端VGL的信号传输到所述第二输出端Out2。
本示例性实施例中，如图6a所示，所述第一输出电路21可以包括：第十四晶体管T14、第十五晶体管T15、第二电容C2，第十四晶体管T14的第一极连接所述第二电源端VGH，第二极连接所述第一输出端Out1，栅极连接所述第四节点N4；第十五晶体管T15的第一极连接所述第二电源端VGH，第二极连接所述第二输出端Out2，栅极连接所述第四节点N4；第二电容C2可以连接于所述第四节点N4和第一输出端Out1之间。所述第二输出电路22可以包括：第十六晶体管T16、第十七晶体管T17、第三电容C3，第十六晶体管T16的第一极连接所述第三电源端LVGL，第二极连接所述第一输出端Out1，栅极连接所述第六节点N6；第十七晶体管T17的第一极连接所述第四电源端VGL，第二极连接所述第二输出端Out2，栅极连接所述第六节点N6；第三电容C3可以连接于所述第六节点N6和第三电源端LVGL之间。在其他示例性实施例中，第二电容C2还可以连接于所述第四节点N4和其他信号端之间，第三电容C3还可以连接于所述第六节点N6和其他信号端之间。
本示例性实施例中，如图6a所示，所述移位寄存器单元还可以包括：复位电路6，复位电路6可以连接所述第四节点N4、第一时钟信号端CK1、复位信号端TRS、第二电源端VGH、第六节点，用于响应所述复位信号端TRS的信号将所述第一时钟信号端CK1的信号传输到所述第四节点N4，以及用于响应所述复位信号端TRS的信号将所述第二电源端VGH的信号传输到所述第六节点N6。
本示例性实施例中，如图6a所示，所述复位电路6可以包括：第十八晶体管T18、第十九晶体管T19、第二十晶体管T20，第十八晶体管T18的第一极连接所述第四节点N4，第二极连接第十节点N10，栅极连接所述复位信号端TRS；第十九晶体管T19的第一极连接所述第十节点N10，第二极连接所述第一时钟信号端CK1，栅极连接所述复位信号端TRS；第二十晶体管T20的第一极连接所述第二电源端VGH，第二极连接所述第六节点N6，栅极连接所述复位信号端TRS；其中，所述第七节点N7连接所述第十节点N10。
本示例性实施例中，如图6a所示，第四晶体管T4到第二十晶体管T20可以均为N型晶体管。相应的，所述第一输入电路11、第二输入电路12、上拉电路3、第一输出电路21、第二输出电路22的有效驱动电平为高电平，即所述第一输入电路11、第二输入电路12、上拉电路3、第一输出电路21、第二输出电路22可以在高电平作用下导通。本示例性实施例中，所述第二电源端VGH可以为高电平信号端，所述第四电源端VGL和所述第三电源端LVGL可以为低电平信号端。
如图6b所示，为为图5中移位寄存器单元另一种示例性实施例的结构示意图。图6b所示移位寄存器单元和图6a所示移位寄存器单元相比，图6b所示移位寄存器单元中的第二输出电路22还可以包括第二十五晶体管T25。其中，第十六晶体管T16的第一极连接所述第七节点N7，第二极连接所述第一输出端Out1，栅极连接所述第六节点N6；第二十五晶体管T25的第一极连接所述第七节点N7，第二极连接所述第三电源端LVGL，栅极连接所述第六节点N6。当第一输出端Out1输出高电平时，相应的，第四节点N4输出高电平，第六晶体管T6在第四节点N4作用下将第二电源端VGH的高电平信号传输到第七节点N7，第一输出端Out1和第七节点N7具有较小的电压差，从而该设置可以降低第一输出端Out1通过第十六晶体管T16的漏电流。
如图7所示，为图6a所示移位寄存器单元一种驱动方法中各节点的时序图。其中，In为输入信号输入端的时序图，CK1为第一时钟信号端的时序图，CK2为第二时钟信号端的时序图，N5为第五节点的时序图，N4为第四节点的时序图，N6为第六节点的时序图，Out1为第一输出端的时 序图，Out2为第二输出端的时序图。
该移位寄存器单元的驱动方法可以包括七个阶段。其中，如图7所示，在第一阶段t1，向第一时钟信号端Ck1输入有效电平、向第二时钟信号端CK2、信号输入端In输入无效电平。其中，有效电平为能够驱动目标电路正常工作的电位，本示例性实施例中，有效电平为高电平，相应的，无效电平为低电平。在第一阶段t1中，第四晶体管T4、第五晶体管T5在第一时钟信号端CK1的作用下导通，信号输入端In向第四节点输入低电平信号。第五节点N5维持上一阶段的高电平信号，第十一晶体管T11、第十二晶体管T12导通，第一时钟信号端CK1向第六节点N6输入高电平信号，第十六晶体管T16在第六节点N6作用下导通，第三电源端LVGL向第一输出端Out1输入低电平信号，第十七晶体管T17在第六节点N6作用下导通，第四电源端VGL向第二输出端Out2输入低电平信号。此外，第八晶体管T8的阈值漂移，以及信号输入端In由于第三电源端LVGL电压抬升而发生的电压变化均可以造成第八晶体管T8的关断漏电流增加，本示例性实施例中，在第一阶段t1，第十晶体管T10在第五节点N5作用下导通，第二电源端VGH向第八节点N8输入高电平信号，该设置可以降低第五节点N5和第八节点N8的电压差，从而降低第五节点N5通过第八晶体管T8的漏电流。
需要说明的是，如图5所示，第一输出端Out1可以级联相邻下一级移位寄存器单元的信号输入端In，第二输出端Out2可以向与其对应的像素驱动电路行提供脉宽调制信号。本示例性实施例中，所述第三电源端LVGL的电压可以小于所述第四电源端VGL的电压，较小的第三电源端LVGL可以有效关断下一级移位寄存器单元中的第八晶体管，从而降低第五节点的漏电流。应该理解的是，在其他示例性实施例中，第三电源端LVGL也可以共用为第四电源端VGL。
在第二阶段t2，可以向第二时钟信号端CK2输入有效电平、向第一时钟信号端CK1、信号输入端In输入无效电平。第七晶体管T7在第二时钟信号端CK2的作用下导通，第二电源端VGH向第五节点N5输入高电平信号，第四节点N4维持上一阶段的低电平信号，第六节点N6维持上一阶段的高电平信号，第十六晶体管T16在第六节点N6作用下导通，第 三电源端LVGL向第一输出端Out1输入低电平信号，第十七晶体管T17在第六节点N6作用下导通，第四电源端VGL向第二输出端Out2输入低电平信号。
在第三阶段t3，向第一时钟信号端CK1输入有效电平、向第二时钟信号端CK2、信号输入端In输入无效电平。第四晶体管T4、第五晶体管T5在第一时钟信号端CK1的作用下导通，信号输入端In向第四节点输入低电平信号。第五节点N5维持上一阶段的高电平信号，第十一晶体管T11、第十二晶体管T12导通，第一时钟信号端CK1向第六节点N6输入高电平信号，第十六晶体管T16在第六节点N6作用下导通，第三电源端LVGL向第一输出端Out1输入低电平信号，第十七晶体管T17在第六节点N6作用下导通，第四电源端VGL向第二输出端Out2输入低电平信号。
在第四阶段t4，向第一时钟信号端CK1输入无效电平、向第二时钟信号端CK2、信号输入端In输入有效电平。第七晶体管T7、第八晶体管T8、第九晶体管T9导通，第二电源端VGH和第二时钟信号端CK2均向第五节点N5输入高电平信号，第四节点N4维持上一阶段的低电平信号，第六节点N6维持上一阶段的高电平信号，第十六晶体管T16在第六节点N6作用下导通，第三电源端LVGL向第一输出端Out1输入低电平信号，第十七晶体管T17在第六节点N6作用下导通，第四电源端VGL向第二输出端Out2输入低电平信号。
在第五阶段t5，向第二时钟信号端CK2输入无效电平、向第一时钟信号端Ck1、信号输入端In输入有效电平。第四晶体管T4、第五晶体管T5在第一时钟信号端CK1作用下导通，信号输入端In向第四节点N4输入高电平信号，第十四晶体管T14在第四节点N4作用下导通，第二电源端VGH向第一输出端Out1输入高电平信号，第十五晶体管T15在第四节点N4作用下导通，第二电源端VGH向第二输出端Out2输入高电平信号。同时，第十三晶体管T13在第四节点N4作用下导通，第三电源端LVGL向第六节点N6输入低电平信号，第十六晶体管T16、第十七晶体管T17在第六节点N6作用下关断。第八晶体管T8、第九晶体管T9在信号输入端In作用下导通，第二时钟信号端CK2向第五节点N5输入低电平信号。此外，第六晶体管T6在第四节点N4作用下导通，第二电源端VGH向第 七节点N7和第十节点N10输入高电平信号，该设置可以降低第四节点N4和第七节点N7的电压差，以及可以降低第四节点N4和第十节点N10的电压差，从而降低第四节点N4通过第五晶体管T5和第十八晶体管T18的漏电流。
在第六阶段t6，向第一时钟信号端CK1、信号输入端In输入无效电平、向第二时钟信号端CK2输入有效电平。第七晶体管T7在第二时钟信号端CK2的作用下导通，第二电源端VGH向第五节点N5输入高电平信号，第六节点N6维持上一阶段的低电平信号，第四节点N4维持上一阶段的高电平信号。第十四晶体管T14在第四节点N4作用下导通，第二电源端VGH向第一输出端Out1输入高电平信号，第十五晶体管T15在第四节点N4作用下导通，第二电源端VGH向第二输出端Out2输入高电平信号。
在第七阶段t7，向第二时钟信号端CK2、信号输入端In输入无效电平、向第一时钟信号端CK1输入有效电平。第四晶体管T4、第五晶体管T5导通，信号输入端In向第四节点N4输入低电平信号。第十一晶体管T11在第五节点N5作用下导通，第十二晶体管T12在第一时钟信号端CK1作用下导通，第一时钟信号端CK1向第六节点N6提供高电平信号。第十六晶体管T16在第六节点N6作用下导通，第三电源端LVGL向第一输出端Out1输入低电平信号，第十七晶体管T17在第六节点N6作用下导通，第四电源端VGL向第二输出端Out2输入低电平信号。
需要说明的是，本示例性实施例中，信号输入端In输出高电平脉冲的时长可以根据实际需求调节。其中，在信号输入端In输出的单个高电平脉冲时段内，第一时钟信号端CK1至少输出一个高电平脉冲信号，第二时钟信号端CK2至少输出一个高电平脉冲信号，且第一时钟信号端CK1输出高电平脉冲信号时，第二时钟信号端CK2输出低电平信号，第二时钟信号端CK2输出高电平脉冲信号时，第一时钟信号端CK1输出低电平信号。即如图7所示，在信号输入端In输出的单个高电平脉冲时段内，该移位寄存器单元驱动方法至少包括第四阶段t4和第五阶段t5。
本示例性实施例中，如图5所示，在所述第一栅极驱动电路81中：本级移位寄存器单元的第一输出端Out1连接相邻下一级移位寄存器单元 的信号输入端In；所述第一信号输入线STUA连接所述第一栅极驱动电路中首级移位寄存器单元的信号输入端In；所述第一时钟信号线LC1连接所述第一栅极驱动电路中奇数级移位寄存器单元的第一时钟信号端CK1和偶数级移位寄存器单元的第二时钟信号端CK2，所述第二时钟信号线LC2连接所述第一栅极驱动电路中偶数级移位寄存器单元的第一时钟信号端CK1和奇数级移位寄存器单元的第二时钟信号端CK2。在所述第二栅极驱动电路82中：本级移位寄存器单元的第一输出端Out1连接相邻下一级移位寄存器单元的信号输入端In；所述第二信号输入线STUB连接所述第二栅极驱动电路中首级移位寄存器单元的信号输入端In；所述第一时钟信号线LC1连接所述第二栅极驱动电路中奇数级移位寄存器单元的第一时钟信号端CK1和偶数级移位寄存器单元的第二时钟信号端CK2，所述第二时钟信号线LC2连接所述第二栅极驱动电路中偶数级移位寄存器单元的第一时钟信号端CK1和奇数级移位寄存器单元的第二时钟信号端CK2。此外，该显示面板还可以包括复位信号线LTRS，复位信号线LTRS连接所有移位寄存器单元的复位信号端。
如图8所示，为图5所示显示面板一种驱动方法中各信号线的时序图。其中，SUTA为第一信号输入线的时序图，STUB为第二信号输入线的时序图，LC1为第一时钟信号线LC1的时序图，LC2为第二时钟信号线的时序图，LTRS为复位信号线的时序图。在该帧中，第一信号输入线STUA输出高电平脉冲信号，第一栅极驱动电路81中的移位寄存器单元逐级输出脉宽调制信号，以向奇数像素驱动电路行逐行提供脉宽调制信号。第二信号输入线STUB持续输出低电平信号，第二栅极驱动电路82中的各移位寄存器单元持续输出低电平。应该理解的是，在其他帧中，第二信号输入线STUB可以输出高电平脉冲信号，第二栅极驱动电路82中的移位寄存器单元逐级输出脉宽调制信号，以向偶数像素驱动电路行逐行提供脉宽调制信号。第一信号输入线STUA可以持续输出低电平信号，第一栅极驱动电路81中的各移位寄存器单元持续输出低电平。从而该显示面板可以实现奇数像素驱动电路行中第一晶体管和偶数像素驱动电路行中第一晶体管的分时导通，进而改善第一晶体管的阈值偏移问题。此外，第一栅极驱动电路81和第二栅极驱动电路82交替输出脉宽调制信号，该设置还可 以使得移位寄存器单元中的第十四晶体管T14、第十六晶体管T16等晶体管得到充足的阈值恢复时间，例如，当第一栅极驱动电路81输出脉宽调制信号时，第一栅极驱动电路中第十四晶体管T14的栅极长时间处于高电平，第十六晶体管T16的栅极长时间处于低电平，当第二栅极驱动电路82输出脉宽调制信号时，第一栅极驱动电路中第十四晶体管T14的栅极长时间处于低电平，第十六晶体管T16的栅极长时间处于高电平。该设置可以提高栅极驱动电路的稳定性。
如图8所示，一帧F包括空白时段F1和扫描时段F2，复位信号线LTRS可以在首帧的空白时段F1输出高电平信号，以导通所有移位寄存器单元中的第十八晶体管T18、第十九晶体管T19、第二十晶体管T20，从而通过第二电源端VGH对第六节点N6进行复位，通过第一时钟信号端CK1对第四节点N4进行复位。该阶段，第一时钟信号端CK1的信号可以为低电平信号。此外，图8中带黑点区域为时序图的省略区域。
本示例性实施例中，如图9所示，为本公开显示面板中栅极驱动电路另一种示例性实施例的结构示意图。所述栅极驱动电路还可以包括：多个级联的移位寄存器单元PWM、多个输出控制电路9，所述移位寄存器单元PWM与所述像素驱动电路组Pz对应设置，所述移位寄存器单元PWM用于通过输出端输出所述脉宽调制信号；所述输出控制电路9与所述移位寄存器单元PWM对应设置，所述输出控制电路9连接与其对应的所述移位寄存器单元PWM的输出端、第五电源端VGL5、第一控制信号端VDDA、第二控制信号端VDDB、第三输出端Out3、第四输出端Out4，所述输出控制电路9用于响应所述第一控制信号端VDDA的信号将所述移位寄存器单元输出端的脉宽调制信号传输到第三输出端Out3，以及响应所述第一控制信号端VDDA的信号将所述第五电源端VGL5的信号传输到第四输出端Out4，所述输出控制电路9还用于响应所述第二控制信号端VDDB的信号将所述移位寄存器单元输出端的脉宽调制信号传输到第四输出端Out4，以及响应所述第二控制信号端VDDB的信号将所述第五电源端VGL5的信号传输到第三输出端Out3。所述第三输出端Out3用于向所述输出控制电路对应的奇数像素驱动电路行提供所述脉宽调制信号，所述第四输出端Out4用于向所述输出控制电路对应的偶数像素驱动电路行提供 所述脉宽调制信号。其中，与同一移位寄存器单元对应的输出控制电路9和像素驱动电路行相互对应。
本示例性实施例中，如图9所示，所述输出控制电路9可以包括：第二十一晶体管T21、第二十二晶体管T22、第二十三晶体管T23、第二十四晶体管T24，第二十一晶体管T21的第一极连接与其对应的所述移位寄存器单元的输出端，第二极连接所述第三输出端Out3，栅极连接所述第一控制信号端VDDA；第二十二晶体管T22的第一极连接与其对应的所述移位寄存器单元的输出端，第二极连接第四输出端Out4，栅极连接所述第二控制信号端VDDB；第二十三晶体管T23的第一极连接所述第五电源端VGL5，第二极连接所述第三输出端Out3，栅极连接所述第二控制信号端VDDB；第二十四晶体管T24的第一极连接所述第五电源端VGL5，第二极连接第四输出端Out4，栅极连接所述第一控制信号端VDDA。
本示例性实施例中，第二十一晶体管T21到第二十四晶体管T24可以均为N型晶体管，第五电源端VGL5可以低电平信号端。该栅极驱动电路中的移位寄出器单元可以如图6a所示。
如图10所示，为图9所示移位寄存器单元一种驱动方法中各节点的时序图。其中，VDDA为第一控制信号端的时序图，VDDB为第二控制信号端的时序图。该移位寄存器单元驱动方法可以包括二个驱动时段：第一驱动时段t1、第二驱动时段t2。其中，在第一驱动时段t1，向第一控制信号端VDDA输入低电平信号，向第二控制信号端VDDB输入高电平信号，第二十一晶体管T21、第二十四晶体管T24导通，第二十二晶体管T22、第二十三晶体管T23关断，多个输出控制电路9将移位寄存器单元输出的脉宽调制信号传输到奇数像素驱动电路行。在第二驱动时段t2，向第一控制信号端VDDA输入高电平信号，向第二控制信号端VDDB输入低电平信号，第二十一晶体管T21、第二十四晶体管T24关断，第二十二晶体管T22、第二十三晶体管T23导通，多个输出控制电路9将移位寄存器单元输出的脉宽调制信号传输到偶数像素驱动电路行。从而该显示面板可以实现奇数像素驱动电路行中第一晶体管和偶数像素驱动电路行中第一晶体管分时导通，进而改善第一晶体管的阈值偏移问题。上述的第一驱动时段t1、第二驱动时段t2可以包括一帧或多帧。第一控制信号端VDDA和第 二控制信号端VDDB高电平阶段的电压可以等于移位寄存器单元中第二电源端VGH的电压，第一控制信号端VDDA和第二控制信号端VDDB低电平阶段的电压可以等于移位寄存器单元中第三电源端LVGL的电压。
本示例性实施例还提供一种显示面板驱动方法，所述显示面板驱动方法用于驱动上述的显示面板，所述显示面板驱动方法包括：
在同一帧中向同一所述像素驱动电路组中的像素驱动电路子组提供所述脉宽调制信号，所述像素驱动电路组中的部分像素驱动电路行形成所述像素驱动电路子组，且在至少部分不同帧中向同一所述像素驱动电路组中不同的所述像素驱动电路子组提供所述脉宽调制信号。
上述内容已经对该驱动方法进行了详细说明，此处不再赘述。
本示例性实施例还提供一种显示装置，其中，所述显示装置可以包括上述的显示面板。该显示装置可以为手机、平板电脑、电视的显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (22)

  1. 一种显示面板，其中，所述显示面板包括：
    多个像素驱动电路，多个所述像素驱动电路沿第一方向和第二方向阵列分布，所述第一方向和第二方向相交，多个所述像素驱动电路形成多个像素驱动电路组，每个所述像素驱动电路组包括多个像素驱动电路行，所述像素驱动电路行包括多个沿第一方向分布的所述像素驱动电路，所述像素驱动电路包括：
    驱动电路，连接第一节点、第二节点、第三节点，用于响应所述第一节点的信号通过所述第二节点向所述第三节点输入驱动电流；
    第一开关单元，第一端连接第一电源端，第二端连接所述第二节点，用于响应一脉宽调制信号以连接所述第一电源端和所述第二节点；
    其中，在同一所述像素驱动电路组中，任一所述第一开关单元的第二端与其他每一像素驱动电路行中至少一个所述第一开关单元的第二端连接。
  2. 根据权利要求1所述的显示面板，其中，所述驱动电路包括：
    驱动晶体管，第一极连接所述第二节点，第二极连接所述第三节点，栅极连接所述第一节点；
    所述第一开关单元包括：
    第一晶体管，第一极连接所述第一电源端，第二极连接所述第二节点，栅极连接脉宽调制信号端；
    所述像素驱动电路还包括：
    第二晶体管，第一极连接数据信号端，第二极连接所述第一节点，栅极连接第一栅极驱动信号端；
    第三晶体管，第一极连接所述第三节点，第二极连接感测信号端，栅极连接第二栅极驱动信号端；
    电容，连接于所述第一节点和所述第三节点之间。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    栅极驱动电路，所述栅极驱动电路包括多个输出端，所述输出端与所述像素驱动电路行对应设置，所述输出端用于向与其对应的所述像素驱动电路行中所述第一开关单元的控制端提供所述脉宽调制信号；
    所述栅极驱动电路用于在同一帧中向同一所述像素驱动电路组中的像素驱动电路子组提供所述脉宽调制信号，所述像素驱动电路组中的部分像素驱动电路行形成所述像素驱动电路子组，且所述栅极驱动电路用于在至少部分不同帧中向同一所述像素驱动电路组中不同的所述像素驱动电路子组提供所述脉宽调制信号。
  4. 根据权利要求1所述的显示面板，其中，所述像素驱动电路组包括在所述第二方向上相邻的多个像素驱动电路行，在同一所述像素驱动电路组中，在所述第二方向上分布的多个所述像素驱动电路中的第一开关单元的第二端相互连接。
  5. 根据权利要求3所述的显示面板，其中，所述像素驱动电路子组包括一个所述像素驱动电路行，所述像素驱动电路组包括位于奇数行的奇数像素驱动电路行和位于偶数行的偶数像素驱动电路行，且所述像素驱动电路组中的两像素驱动电路行在所述第二方向上相邻设置；
    所述栅极驱动电路用于在同一帧中向奇数像素驱动电路行或偶数像素驱动电路行择一提供所述脉宽调制信号，且所述栅极驱动电路用于在至少部分帧中向奇数像素驱动电路行提供所述脉宽调制信号，以及用于在至少部分帧中向偶数像素驱动电路行提供所述脉宽调制信号。
  6. 根据权利要求5所述的显示面板，其中，
    所述栅极驱动电路包括：
    第一栅极驱动电路，连接第一信号输入线、第一时钟信号线、第二时钟信号线，用于响应所述第一信号输入线、第一时钟信号线、第二时钟信号线的信号向奇数像素驱动电路行提供所述脉宽调制信号；
    第二栅极驱动电路，连接第二信号输入线、第一时钟信号线、第二时钟信号线，用于响应所述第二信号输入线、第一时钟信号线、第二时钟信号线的信号向偶数像素驱动电路行提供所述脉宽调制信号。
  7. 根据权利要求6所述的显示面板，其中，所述第一栅极驱动电路包括多个级联的移位寄存器单元，所述第二栅极驱动电路包括多个级联的移位寄存器单元；
    所述移位寄存器单元包括：
    第一输入电路，连接信号输入端、第一时钟信号端、第四节点，用于 响应所述第一时钟信号端的信号将所述信号输入端的信号传输到所述第四节点；
    第二输入电路，连接第二电源端，第二时钟信号端、第五节点、信号输入端，用于响应所述第二时钟信号端的信号将所述第二电源端的信号传输到所述第五节点，以及用于响应所述信号输入端的信号将所述第二时钟信号端的信号传输到所述第五节点；
    上拉电路，连接所述第一时钟信号端、第五节点、第六节点，用于响应所述第五节点和第一时钟信号端的信号将所述第一时钟信号端的信号传输到所述第六节点；
    下拉电路，连接所述第四节点、第三电源端、第六节点，用于响应所述第四节点的信号将所述第三电源端的信号传输到所述第六节点；
    第一输出电路，连接所述第四节点、第一输出端、第二电源端，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第一输出端；
    第二输出电路，连接所述第六节点、第三电源端、第一输出端，用于响应所述第六节点的信号将所述第三电源端的信号传输到所述第一输出端。
  8. 根据权利要求7所述的显示面板，其中，所述第一输入电路包括：
    第四晶体管，第一极连接所述信号输入端，第二极连接第七节点，栅极连接所述第一时钟信号端；
    第五晶体管，第一极连接所述第七节点，第二极连接所述第四节点，栅极连接所述第一时钟信号端；
    所述第二输入电路包括：
    第七晶体管，第一极连接所述第二电源端，第二极连接所述第五节点，栅极连接所述第二时钟信号端；
    第八晶体管，第一极连接所述第五节点，第二极连接第八节点，栅极连接所述信号输入端；
    第九晶体管，第一极连接所述第八节点，第二极连接所述第二时钟信号端，栅极连接所述信号输入端。
  9. 根据权利要求8所述的显示面板，其中，所述移位寄存器单元还 包括：
    第一隔离电路，连接所述第二电源端、第四节点、第七节点，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第七节点；
    第二隔离电路，连接所述第八节点、第二电源端、第五节点，用于响应所述第五节点的信号将所述第二电源端的信号传输到所述第八节点。
  10. 根据权利要求9所述的显示面板，其中，所述第一隔离电路包括：
    第六晶体管，第一极连接所述第七节点，第二极连接所述第二电源端，栅极连接所述第四节点；
    所述第二隔离电路包括：
    第十晶体管，第一极连接所述第二电源端，第二极连接所述第八节点，栅极连接所述第五节点。
  11. 根据权利要求7所述的显示面板，其中，所述上拉电路包括：
    第十一晶体管，第一极连接所述第一时钟信号端，第二极连接第九节点，栅极连接所述第五节点；
    第十二晶体管，第一极连接所述第九节点，第二极连接所述第六节点，栅极连接所述第一时钟信号端；
    第一电容，连接于所述第五节点；
    所述下拉电路包括：
    第十三晶体管，第一极连接所述第三电源端，第二极连接所述第六节点，栅极连接所述第四节点。
  12. 根据权利要求7所述的显示面板，其中，
    所述第一输出电路还连接第二输出端，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第二输出端；
    所述第二输出电路还连接第二输出端、第四电源端，用于响应所述第六节点的信号将所述第四电源端的信号传输到所述第二输出端；
    所述第一输出端或所述第二输出端形成所述栅极驱动电路的输出端。
  13. 根据权利要求12所述的显示面板，其中，所述第一输入电路、第二输入电路、上拉电路、第一输出电路、第二输出电路的有效驱动电平为高电平；
    所述第二电源端为高电平信号端，所述第四电源端和所述第三电源端 同为低电平信号端，且所述第三电源端的电压小于所述第四电源端的电压。
  14. 根据权利要求12所述的显示面板，其中，所述第一输出电路包括：
    第十四晶体管，第一极连接所述第二电源端，第二极连接所述第一输出端，栅极连接所述第四节点；
    第十五晶体管，第一极连接所述第二电源端，第二极连接所述第二输出端，栅极连接所述第四节点；
    第二电容，连接于所述第四节点；
    所述第二输出电路包括：
    第十六晶体管，第一极连接所述第三电源端，第二极连接所述第一输出端，栅极连接所述第六节点；
    第十七晶体管，第一极连接所述第四电源端，第二极连接所述第二输出端，栅极连接所述第六节点；
    第三电容，连接于所述第六节点。
  15. 根据权利要求9所述的显示面板，其中，所述第二输出电路包括：
    第十六晶体管，第一极连接所述第七节点，第二极连接所述第一输出端，栅极连接所述第六节点；
    第二十五晶体管，第一极连接所述第七节点，第二极连接所述第三电源端，栅极连接所述第六节点；
    第三电容，连接于所述第六节点。
  16. 根据权利要求7所述的显示面板，其中，所述移位寄存器单元还包括：
    复位电路，连接所述第四节点、第一时钟信号端、复位信号端、第二电源端、第六节点，用于响应所述复位信号端的信号将所述第一时钟信号端的信号传输到所述第四节点，以及用于响应所述复位信号端的信号将所述第二电源端的信号传输到所述第六节点。
  17. 根据权利要求16所述的显示面板，其中，所述第一输入电路包括：
    第四晶体管，第一极连接所述信号输入端，第二极连接第七节点，栅极连接所述第一时钟信号端；
    第五晶体管，第一极连接所述第七节点，第二极连接所述第四节点，栅极连接所述第一时钟信号端；
    所述移位寄存器单元还包括：
    第一隔离电路，连接所述第二电源端、第四节点、第七节点，用于响应所述第四节点的信号将所述第二电源端的信号传输到所述第七节点；
    所述复位电路包括：
    第十八晶体管，第一极连接所述第四节点，第二极连接第十节点，栅极连接所述复位信号端；
    第十九晶体管，第一极连接所述第十节点，第二极连接所述第一时钟信号端，栅极连接所述复位信号端；
    第二十晶体管，第一极连接所述第二电源端，第二极连接所述第六节点，栅极连接所述复位信号端；
    其中，所述第七节点连接所述第十节点。
  18. 根据权利要求7所述的显示面板，其中，
    在所述第一栅极驱动电路中：
    本级移位寄存器单元的第一输出端连接相邻下一级移位寄存器单元的信号输入端；
    所述第一信号输入线连接所述第一栅极驱动电路中首级移位寄存器单元的信号输入端；
    所述第一时钟信号线连接所述第一栅极驱动电路中奇数级移位寄存器单元的第一时钟信号端和偶数级移位寄存器单元的第二时钟信号端，所述第二时钟信号线连接所述第一栅极驱动电路中偶数级移位寄存器单元的第一时钟信号端和奇数级移位寄存器单元的第二时钟信号端；
    在所述第二栅极驱动电路中：
    本级移位寄存器单元的第一输出端连接相邻下一级移位寄存器单元的信号输入端；
    所述第二信号输入线连接所述第二栅极驱动电路中首级移位寄存器单元的信号输入端；
    所述第一时钟信号线连接所述第二栅极驱动电路中奇数级移位寄存器单元的第一时钟信号端和偶数级移位寄存器单元的第二时钟信号端，所 述第二时钟信号线连接所述第二栅极驱动电路中偶数级移位寄存器单元的第一时钟信号端和奇数级移位寄存器单元的第二时钟信号端。
  19. 根据权利要求5所述的显示面板，其中，所述栅极驱动电路包括：
    多个级联的移位寄存器单元，所述移位寄存器单元与所述像素驱动电路组对应设置，所述移位寄存器单元用于通过输出端输出所述脉宽调制信号；
    多个输出控制电路，所述输出控制电路与所述移位寄存器单元对应设置，所述输出控制电路连接与其对应的所述移位寄存器单元的输出端、第五电源端、第一控制信号端、第二控制信号端、第三输出端、第四输出端，所述输出控制电路用于响应所述第一控制信号端的信号将所述移位寄存器单元输出端的脉宽调制信号传输到所述第三输出端，以及响应所述第一控制信号端的信号将所述第五电源端的信号传输到所述第四输出端，所述输出控制电路还用于响应所述第二控制信号端的信号将所述移位寄存器单元输出端的脉宽调制信号传输到所述第四输出端，以及响应所述第二控制信号端的信号将所述第五电源端的信号传输到所述第三输出端；
    其中，所述第三输出端和所述第四输出端形成所述栅极驱动电路的输出端，所述第三输出端用于向所述输出控制电路对应的奇数像素驱动电路行提供所述脉宽调制信号，所述第四输出端用于向所述输出控制电路对应的偶数像素驱动电路行提供所述脉宽调制信号。
  20. 根据权利要求19所述的显示面板，其中，所述输出控制电路包括：
    第二十一晶体管，第一极连接与其对应的所述移位寄存器单元的输出端，第二极连接所述第三输出端，栅极连接所述第一控制信号端；
    第二十二晶体管，第一极连接与其对应的所述移位寄存器单元的输出端，第二极连接所述第四输出端，栅极连接所述第二控制信号端；
    第二十三晶体管，第一极连接所述第五电源端，第二极连接所述第三输出端，栅极连接所述第二控制信号端；
    第二十四晶体管，第一极连接所述第五电源端，第二极连接所述第四输出端，栅极连接所述第一控制信号端。
  21. 一种显示面板驱动方法，其中，所述显示面板驱动方法用于驱动 权利要求1-20任一项所述的显示面板，所述显示面板驱动方法包括：
    在同一帧中向同一所述像素驱动电路组中的像素驱动电路子组提供所述脉宽调制信号，所述像素驱动电路组中的部分像素驱动电路行形成所述像素驱动电路子组，且在至少部分不同帧中向同一所述像素驱动电路组中不同的所述像素驱动电路子组提供所述脉宽调制信号。
  22. 一种显示装置，其中，所述显示装置包括权利要求1-20任一项所述的显示面板。
PCT/CN2022/082864 2022-03-24 2022-03-24 显示面板及其驱动方法、显示装置 WO2023178621A1 (zh)

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