WO2024113203A1 - 驱动电路、驱动方法和显示装置 - Google Patents

驱动电路、驱动方法和显示装置 Download PDF

Info

Publication number
WO2024113203A1
WO2024113203A1 PCT/CN2022/135249 CN2022135249W WO2024113203A1 WO 2024113203 A1 WO2024113203 A1 WO 2024113203A1 CN 2022135249 W CN2022135249 W CN 2022135249W WO 2024113203 A1 WO2024113203 A1 WO 2024113203A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
control
electrically connected
transistor
terminal
Prior art date
Application number
PCT/CN2022/135249
Other languages
English (en)
French (fr)
Inventor
张星
徐攀
赵冬辉
韩影
罗程远
吕广爽
许程
刘苗
周丹丹
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/135249 priority Critical patent/WO2024113203A1/zh
Publication of WO2024113203A1 publication Critical patent/WO2024113203A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device.
  • the internal compensation technology has the advantages of simple driving system and low cost, compared with the external compensation technology, because it does not require expensive FPGA (field programmable gate array) or ASIC (Application Specific Integrated Circuit) chips, as well as external source driver, and does not require a bulky Tcon (timing controller).
  • FPGA field programmable gate array
  • ASIC Application Specific Integrated Circuit
  • Tcon timing controller
  • an embodiment of the present disclosure provides a driving circuit, including a first control node control circuit, a second control node control circuit, a first node control circuit, and a second node control circuit, wherein:
  • the first control node control circuit is used to control the potential of the first control node
  • the second control node control circuit is used to control the potential of the second control node
  • the first node control circuit is used to control the potential of the first node
  • the second node control circuit is electrically connected to the second control node, the first clock signal terminal and the second node respectively, and is used to control the connection between the first clock signal terminal and the second node under the control of the potential of the second control node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a third node control circuit and a fourth node control circuit;
  • the third node control circuit is electrically connected to the first control node, the third node and the first clock signal terminal respectively, and is used to control the connection between the third node and the first clock signal terminal under the control of the potential of the first control node, and control the potential of the third node according to the potential of the first control node;
  • the fourth node control circuit controls the third node to be connected to the fourth node under the control of the first clock signal provided by the first clock signal terminal, and controls the fourth node to be connected to the first voltage terminal under the control of the potential of the first node;
  • the second node control circuit is further configured to control the potential of the second node according to the potential of the second control node.
  • the first node control circuit is electrically connected to the first node, the first clock signal terminal and the fourth node respectively, and is used to control the connection between the fourth node and the first node under the control of the first clock signal.
  • the first node control circuit is also electrically connected to the second node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the second node.
  • the third node control circuit is electrically connected to the second node and the second voltage terminal respectively, and is used to control the connection between the third node and the second voltage terminal under the control of the potential of the second node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a driving signal output terminal, a second output circuit, a third output circuit and a fifth node control circuit, wherein:
  • the second output circuit is electrically connected to the second node, the drive signal output terminal and the fifth node respectively, and is used to control the connection between the drive signal output terminal and the fifth node under the control of the potential of the second node;
  • the third output circuit is electrically connected to the second node, the fifth node and the second voltage terminal respectively, and is used to control the connection between the fifth node and the second voltage terminal under the control of the potential of the second node;
  • the fifth node control circuit is electrically connected to the fifth node and the drive signal output terminal respectively, and the fifth node control circuit is also electrically connected to the third voltage terminal or the first voltage terminal, and is used to control the connection between the fifth node and the third voltage terminal or the first voltage terminal under the control of the drive signal provided by the drive signal output terminal.
  • the first control node control circuit is electrically connected to the first control node, the first clock signal terminal, the second control node and the second voltage terminal, respectively, and is used to control the connection between the first control node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the second control node.
  • the first control node control circuit is also electrically connected to the second clock signal terminal and the input terminal, respectively, for controlling the connection between the first control node and the input terminal under the control of a second clock signal provided by the second clock signal terminal.
  • the second control node control circuit is electrically connected to the second control node, the second clock signal terminal, the reset terminal, the third voltage terminal and the first control node, respectively, and is used to control the connection between the second control node and the third voltage terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection between the second control node and the third voltage terminal under the control of the reset signal provided by the reset terminal, and control the connection between the second control node and the second clock signal terminal under the control of the potential of the first control node, and control the connection between the second control node and the second clock signal terminal under the control of the potential of the first control node.
  • the driving circuit described in at least one embodiment of the present disclosure also includes a first output circuit; the first output circuit is electrically connected to the first node and the driving signal output terminal, respectively, and the first output circuit is electrically connected to the third voltage terminal or the output clock signal terminal, and is used to control the connection between the driving signal output terminal and the third voltage terminal or the output clock signal terminal under the control of the potential of the first node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;
  • the first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output end; the first energy storage circuit is used to maintain the potential of the first node;
  • the first end of the second energy storage circuit is electrically connected to the second node, and the second end of the second energy storage circuit is electrically connected to the second voltage end; the second energy storage circuit is used to maintain the potential of the second node.
  • the second node control circuit includes a first transistor
  • a gate of the first transistor is electrically connected to the second control node, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the second node.
  • the fourth node control circuit includes a second transistor and a third transistor
  • the gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • a gate of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the fourth node.
  • the fifth node control circuit includes a fourth transistor
  • a gate of the fourth transistor is electrically connected to the driving signal output terminal, a first electrode of the fourth transistor is electrically connected to the third voltage terminal or the first voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node.
  • the first control node control circuit includes a fifth transistor and a sixth transistor; a gate of the fifth transistor is electrically connected to the first clock signal terminal, and a first electrode of the fifth transistor is electrically connected to the first control node;
  • a gate of the sixth transistor is electrically connected to the second control node, a first electrode of the sixth transistor is electrically connected to a second electrode of the fifth transistor, and a second electrode of the sixth transistor is electrically connected to a second voltage terminal.
  • the first control node control circuit includes a fifth transistor and a sixth transistor;
  • the gate of the fifth transistor is electrically connected to the second control node, and the first electrode of the fifth transistor is electrically connected to the first control node;
  • a gate of the sixth transistor is electrically connected to the first clock signal terminal, a first electrode of the sixth transistor is electrically connected to a second electrode of the fifth transistor, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal.
  • the first control node control circuit includes a seventh transistor; the gate of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node.
  • the third node control circuit includes an eighth transistor and a third capacitor; the gate of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the third node;
  • a first end of the third capacitor is electrically connected to the first control node, and a second end of the third capacitor is electrically connected to the third node;
  • the second node control circuit further includes a fourth capacitor
  • a first end of the fourth capacitor is electrically connected to the second control node, and a second end of the fourth capacitor is electrically connected to the second node.
  • the third node control circuit further includes a ninth transistor
  • a gate of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the second voltage terminal.
  • the first node control circuit includes a tenth transistor
  • a gate of the tenth transistor is electrically connected to the first clock signal terminal, a first electrode of the tenth transistor is electrically connected to the fourth node, and a second electrode of the tenth transistor is electrically connected to the first node.
  • the first node control circuit includes an eleventh transistor
  • a gate of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to the second voltage terminal.
  • the second control node control circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor;
  • the gate of the twelfth transistor is electrically connected to the reset terminal, the first electrode of the twelfth transistor is electrically connected to the second control node, and the second electrode of the twelfth transistor is electrically connected to the third voltage terminal;
  • the gate of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the third voltage terminal, and the second electrode of the thirteenth transistor is electrically connected to the second control node;
  • the gate of the fourteenth transistor is electrically connected to the first control node, the first electrode of the fourteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the second control node.
  • the first output circuit includes a first output transistor; the gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to a third voltage terminal or an output clock signal terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal.
  • the second output circuit includes a second output transistor
  • the third output circuit includes a third output transistor
  • the gate of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the fifth node;
  • a gate of the third output transistor is electrically connected to the second node, a first electrode of the third output transistor is electrically connected to the fifth node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, wherein a display period includes a first stage, a second stage and a third stage which are arranged in sequence; the driving method includes:
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage, and the second node control circuit controls the second node to be connected to the first clock signal terminal under the control of the potential of the second control node; the first node control circuit controls the potential of the first node to be a turn-off voltage;
  • the first control node control circuit controls the potential of the first control node to be a turn-on voltage
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage
  • the second node control circuit controls the second node to be connected to the first clock signal terminal under the control of the potential of the second control node
  • the first control node control circuit controls the potential of the first control node to be the on voltage
  • the second control node control circuit controls the potential of the second control node to be the off voltage
  • the second node control circuit controls the potential of the second node to be the off voltage
  • the first node control circuit controls the potential of the first node to be the on voltage
  • the first control node control circuit controls the potential of the first control node to be a turn-off voltage
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage
  • the second node control circuit controls the second node to be connected to the first clock signal terminal under the control of the potential of the second control node
  • the first node control circuit controls the potential of the first node to be a turn-on voltage
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage
  • the first node control circuit controls the potential of the first node to be a turn-off voltage
  • the second node control circuit controls the connection between the second node and the first clock signal terminal under the control of the potential of the second control node.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned driving circuit.
  • FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG13;
  • FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG19 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG20 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG19;
  • FIG21 is a circuit diagram of a related internal compensation pixel circuit
  • FIG22 is a timing diagram of the operation of the internal compensation pixel circuit shown in FIG21;
  • FIG. 23 is a schematic diagram of a cascade connection of a three-stage driving circuit.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit includes a first control node control circuit 11, a second control node control circuit 12, a first node control circuit 13 and a second node control circuit 14, wherein:
  • the first control node control circuit 11 is electrically connected to the first control node PQ, and is used to control the potential of the first control node PQ;
  • the second control node control circuit 12 is electrically connected to the second control node PQB, and is used to control the potential of the second control node PQB;
  • the first node control circuit 13 is electrically connected to the first node Q and is used to control the potential of the first node Q;
  • the second node control circuit 14 is electrically connected to the second control node PQB, the first clock signal terminal CKB and the second node QB respectively, and is used to control the connection between the first clock signal terminal CKB and the second node QB under the control of the potential of the second control node PQB.
  • the second node control circuit 14 controls the connection between the second node QB and the first clock signal terminal CKB under the control of the potential of the second control node PQB, so that the potential of the second node QB switches between high and low levels, so that the transistor controlled by the second node QB will not be in a forward stress state for a long time, thereby improving the working stability of the driving circuit.
  • the clock signal connected to the first node control circuit 13 may be different from the clock signal connected to the first control node control circuit 11;
  • the clock signal connected to the first node control circuit 13 may be different from the clock signal connected to the second control node control circuit 12;
  • the clock signal connected to the first node control circuit 13 may be the same as the clock signal connected to the second node control circuit 14 .
  • the second node control circuit 14 controls the connection between the first clock signal terminal CKB and the second node QB under the control of the potential of the second control node PQB.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a first output circuit 110 ;
  • the first output circuit 110 is electrically connected to the first node Q, the third voltage terminal V3 and the drive signal output terminal O1 respectively, and is used to control the connection between the drive signal output terminal O1 and the third voltage terminal V3 under the control of the potential of the first node Q;
  • the first control node control circuit 11 and the second control node control circuit 12 may both be electrically connected to the second clock signal terminal CKA, but the present invention is not limited thereto.
  • the first output circuit 110 may be used to provide a light emitting control signal for the pixel circuit, but the present invention is not limited thereto.
  • the first output circuit 110 may not be electrically connected to the third voltage terminal, but may be electrically connected to the output clock signal terminal (the output clock signal terminal may be the first clock signal terminal or the second clock signal terminal).
  • the driving circuit may provide a gate driving signal for the pixel circuit, but is not limited to this.
  • the transistor included in the driving circuit may be an n-type transistor, but is not limited thereto; in a specific implementation, the transistor included in the driving circuit may also be a p-type transistor.
  • the driving circuit may further include a third node control circuit and a fourth node control circuit;
  • the third node control circuit is electrically connected to the first control node, the third node, the fourth node and the first clock signal terminal respectively, and is used to control the connection between the third node and the first clock signal terminal under the control of the potential of the first control node, and control the potential of the third node according to the potential of the first control node;
  • the fourth node control circuit controls the connection between the third node and the fourth node under the control of the first clock signal provided by the first clock signal terminal, and controls the connection between the fourth node and the first voltage terminal under the control of the potential of the first node.
  • the driving circuit may further include a third node control circuit and a fourth node control circuit, wherein the third node control circuit controls the potential of the third node under the control of the potential of the first control node, and the fourth node control circuit controls the potential of the fourth node under the control of the first clock signal;
  • the second node control circuit is further configured to control the potential of the second node according to the potential of the second control node.
  • the driving circuit may further include a third node control circuit 21 and a fourth node control circuit 22 ;
  • the third node control circuit 21 is electrically connected to the first control node PQ, the third node N3 and the first clock signal terminal CKB, respectively, and is used to control the connection between the third node N3 and the first clock signal terminal CKB under the control of the potential of the first control node PQ, and control the potential of the third node N3 according to the potential of the first control node PQ;
  • the fourth node control circuit 22 is electrically connected to the first clock signal terminal CKB, the third node N3, the fourth node N4, the first node Q and the first voltage terminal V1, respectively, and is used to control the third node N3 and the fourth node N4 to be connected under the control of the first clock signal provided by the first clock signal terminal CKB, and to control the fourth node N4 and the first voltage terminal V1 to be connected under the control of the potential of the first node Q;
  • the second node control circuit 14 is further used to control the potential of the second node QB according to the potential of the second control node PQB.
  • the first voltage terminal may be the second high voltage terminal VGH2 , but is not limited thereto.
  • the fourth node control circuit 22 controls the fourth node N4 to be connected with the first voltage terminal V1 under the control of the potential of the first node Q, so that when the potential of the first node Q is a turn-on voltage (for example, a high voltage), the fourth node N4 is controlled to be connected with the first voltage terminal V1 (the first voltage terminal V1 may be the second high voltage terminal VGH2) so that the potential of the fourth node N4 is a high voltage, thereby preventing the potential of the first node Q from being reduced due to leakage, thereby failing to correctly output the driving signal.
  • a turn-on voltage for example, a high voltage
  • the first node control circuit is electrically connected to the first node, the first clock signal terminal and the fourth node respectively, and is used to control the connection between the fourth node and the first node under the control of the first clock signal.
  • the first node control circuit may also control the connection between the first node and the fourth node under the control of the first clock signal.
  • the first node control circuit is also electrically connected to the second node and the second voltage terminal respectively, and is used to control the connection between the first node and the second voltage terminal under the control of the potential of the second node.
  • the first node control circuit can also control the connection between the first node and the second voltage terminal under the control of the potential of the second node.
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the first node control circuit 13 is electrically connected to the first node Q, the second node QB, the first clock signal terminal CKB, the fourth node N4 and the second voltage terminal V2, respectively, and is used to control the connection between the fourth node N4 and the first node Q under the control of the first clock signal provided by the first clock signal terminal CKB, and to control the connection between the first node Q and the second voltage terminal V2 under the control of the potential of the second node QB.
  • the third node control circuit may also be electrically connected to the second node and the second voltage terminal respectively, and is used to control the connection between the third node and the second voltage terminal under the control of the potential of the second node.
  • the third node control circuit can control the potential of the first node Q under the control of the potential of the second node.
  • the first node control circuit 13 is electrically connected to the first node Q, the first clock signal terminal CKB and the fourth node N4, respectively, and is used to control the fourth node N4 to be connected to the first node Q under the control of the first clock signal;
  • the third node control circuit 21 can also be electrically connected to the second node QB and the second voltage terminal V2 respectively, and is used to control the connection between the third node N3 and the second voltage terminal V2 under the control of the potential of the second node QB.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a driving signal output terminal, a second output circuit, a third output circuit and a fifth node control circuit, wherein:
  • the second output circuit is electrically connected to the second node, the drive signal output terminal and the fifth node respectively, and is used to control the connection between the drive signal output terminal and the fifth node under the control of the potential of the second node;
  • the third output circuit is electrically connected to the second node, the fifth node and the second voltage terminal respectively, and is used to control the connection between the fifth node and the second voltage terminal under the control of the potential of the second node;
  • the fifth node control circuit is electrically connected to the fifth node and the drive signal output terminal respectively, and the fifth node control circuit is also electrically connected to the third voltage terminal or the first voltage terminal, and is used to control the connection between the fifth node and the third voltage terminal or the first voltage terminal under the control of the drive signal provided by the drive signal output terminal.
  • the driving circuit may further include a second output circuit, a third output circuit and a fifth node control circuit.
  • the second output circuit and the third output circuit control the driving signal output from the driving signal output terminal under the control of the potential of the second node, and the fifth node control circuit controls the potential of the fifth node under the control of the driving signal.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a driving signal output terminal O1, a second output circuit 42, a third output circuit 43 and a fifth node control circuit 44, wherein:
  • the second output circuit 42 is electrically connected to the second node QB, the drive signal output terminal O1 and the fifth node N5 respectively, and is used to control the connection between the drive signal output terminal O1 and the fifth node N5 under the control of the potential of the second node QB;
  • the third output circuit 43 is electrically connected to the second node QB, the fifth node N5 and the second voltage terminal V2 respectively, and is used to control the connection between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the second node QB;
  • the fifth node control circuit 44 is electrically connected to the fifth node N5 and the drive signal output terminal O1 respectively, and the fifth node control circuit is also electrically connected to the third voltage terminal V3, and is used to control the connection between the fifth node N5 and the third voltage terminal V3 under the control of the drive signal provided by the drive signal output terminal O1.
  • the third voltage terminal V3 may be the first high voltage terminal VGH, but is not limited thereto.
  • the fifth node control circuit 44 controls the connection between the fifth node N5 and the third voltage terminal V3 (the third voltage terminal V3 can be the first high voltage terminal VGH) under the control of the driving signal, so as to avoid the potential of the driving signal output by the driving signal output terminal O1 from being reduced due to leakage, so as to output the driving signal normally.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a driving signal output terminal O1, a second output circuit 42, a third output circuit 43 and a fifth node control circuit 44, wherein:
  • the second output circuit 42 is electrically connected to the second node QB, the drive signal output terminal O1 and the fifth node N5 respectively, and is used to control the connection between the drive signal output terminal O1 and the fifth node N5 under the control of the potential of the second node QB;
  • the third output circuit 43 is electrically connected to the second node QB, the fifth node N5 and the second voltage terminal V2 respectively, and is used to control the connection between the fifth node N5 and the second voltage terminal V2 under the control of the potential of the second node QB;
  • the fifth node control circuit 44 is electrically connected to the fifth node N5 and the drive signal output terminal O1 respectively, and the fifth node control circuit is also electrically connected to the third voltage terminal V3, and is used to control the connection between the fifth node N5 and the third voltage terminal V3 under the control of the drive signal provided by the drive signal output terminal O1.
  • the third voltage terminal V3 may be the first high voltage terminal VGH, but is not limited thereto.
  • the fifth node control circuit 44 controls the connection between the fifth node N5 and the third voltage terminal V3 (the third voltage terminal V3 may be the first high voltage terminal VGH) under the control of the driving signal, so as to avoid the potential of the driving signal outputted from the driving signal output terminal O1 from being reduced due to leakage, so as to output the driving signal normally.
  • the first control node control circuit is electrically connected to the first control node, the first clock signal terminal, the second control node and the second voltage terminal, respectively, and is used to control the connection between the first control node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal and the potential of the second control node.
  • the first control node control circuit may control the potential of the first control node under the control of the first clock signal and the potential of the second control node.
  • the first control node control circuit is also electrically connected to the second clock signal terminal and the input terminal, respectively, for controlling the connection between the first control node and the input terminal under the control of a second clock signal provided by the second clock signal terminal.
  • the first control node control circuit may also control the connection between the first control node and the input end under the control of the second clock signal.
  • the first control node control circuit 11 is electrically connected to the first control node PQ, the first clock signal terminal CKB, the second control node PQB and the second voltage terminal V2 respectively, and is used to control the first control node PQ to be connected to the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the second control node PQB;
  • the first control node control circuit 11 is also electrically connected to the second clock signal terminal CKA and the input terminal STU, and is used to control the connection between the first control node PQ and the input terminal STU under the control of the second clock signal provided by the second clock signal terminal CKA.
  • the first control node control circuit 11 is electrically connected to the first control node PQ, the first clock signal terminal CKB, the second control node PQB and the second voltage terminal V2 respectively, and is used to control the first control node PQ to be connected to the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal CKB and the potential of the second control node PQB;
  • the first control node control circuit 11 is also electrically connected to the second clock signal terminal CKA and the input terminal STU, and is used to control the connection between the first control node PQ and the input terminal STU under the control of the second clock signal provided by the second clock signal terminal CKA.
  • the second control node control circuit is electrically connected to the second control node, the second clock signal terminal, the reset terminal, the third voltage terminal and the first control node, respectively, and is used to control the connection between the second control node and the third voltage terminal under the control of the second clock signal provided by the second clock signal terminal, control the connection between the second control node and the third voltage terminal under the control of the reset signal provided by the reset terminal, control the connection between the second control node and the second clock signal terminal under the control of the potential of the first control node, and control the connection between the second control node and the second clock signal terminal under the control of the potential of the first control node.
  • the second node control circuit can control the potential of the second node under the second clock signal, the reset signal and the potential of the first control node.
  • the second control node control circuit 12 is electrically connected to the second control node PQB, the second clock signal terminal CKA, the reset terminal RST, the third voltage terminal V3 and the first control node PQ, respectively, and is used to control the connection between the second control node PQB and the third voltage terminal V3 under the control of the second clock signal provided by the second clock signal terminal CKA, control the connection between the second control node PQB and the third voltage terminal V3 under the control of the reset signal provided by the reset terminal RST, and control the connection between the second control node PQB and the second clock signal terminal CKA under the control of the potential of the first control node PQ, and control the connection between the second control node PQB and the second clock signal terminal CKA under the control of the potential of the first control node PQ.
  • the second control node control circuit 12 is electrically connected to the second control node PQB, the second clock signal terminal CKA, the reset terminal RST, the third voltage terminal V3 and the first control node PQ, respectively, and is used to control the connection between the second control node PQB and the third voltage terminal V3 under the control of the second clock signal provided by the second clock signal terminal CKA, control the connection between the second control node PQB and the third voltage terminal V3 under the control of the reset signal provided by the reset terminal RST, and control the connection between the second control node PQB and the second clock signal terminal CKA under the control of the potential of the first control node PQ, and control the connection between the second control node PQB and the second clock signal terminal CKA under the control of the potential of the first control node PQ.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;
  • the first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output end; the first energy storage circuit is used to maintain the potential of the first node;
  • the first end of the second energy storage circuit is electrically connected to the second node, and the second end of the second energy storage circuit is electrically connected to the second voltage end; the second energy storage circuit is used to maintain the potential of the second node.
  • the first energy storage circuit may include a first capacitor
  • the second energy storage circuit may include a second capacitor
  • the driving circuit according to at least one embodiment of the present disclosure further includes a first energy storage circuit 111 and a second energy storage circuit 112 ;
  • the first end of the first energy storage circuit 111 is electrically connected to the first node Q, and the second end of the first energy storage circuit 111 is electrically connected to the drive signal output terminal O1; the first energy storage circuit 111 is used to maintain the potential of the first node Q;
  • the first end of the second energy storage circuit 112 is electrically connected to the second node QB, and the second end of the second energy storage circuit 112 is electrically connected to the second voltage terminal V2; the second energy storage circuit 112 is used to maintain the potential of the second node QB.
  • the first end of the first energy storage circuit 111 is electrically connected to the first node Q, and the second end of the first energy storage circuit 111 is electrically connected to the drive signal output terminal O1; the first energy storage circuit 111 is used to maintain the potential of the first node Q;
  • the first end of the second energy storage circuit 112 is electrically connected to the second node QB, and the second end of the second energy storage circuit 112 is electrically connected to the second voltage terminal V2; the second energy storage circuit 112 is used to maintain the potential of the second node QB.
  • the second node control circuit includes a first transistor
  • a gate of the first transistor is electrically connected to the second control node, a first electrode of the first transistor is electrically connected to the first clock signal terminal, and a second electrode of the first transistor is electrically connected to the second node.
  • the fourth node control circuit includes a second transistor and a third transistor
  • the gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the fourth node;
  • a gate of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the fourth node.
  • the fifth node control circuit includes a fourth transistor
  • a gate of the fourth transistor is electrically connected to the driving signal output terminal, a first electrode of the fourth transistor is electrically connected to the third voltage terminal or the first voltage terminal, and a second electrode of the fourth transistor is electrically connected to the fifth node.
  • the first control node control circuit includes a fifth transistor and a sixth transistor; a gate of the fifth transistor is electrically connected to the first clock signal terminal, and a first electrode of the fifth transistor is electrically connected to the first control node;
  • a gate of the sixth transistor is electrically connected to the second control node, a first electrode of the sixth transistor is electrically connected to a second electrode of the fifth transistor, and a second electrode of the sixth transistor is electrically connected to a second voltage terminal.
  • the first control node control circuit includes a fifth transistor and a sixth transistor;
  • the gate of the fifth transistor is electrically connected to the second control node, and the first electrode of the fifth transistor is electrically connected to the first control node;
  • a gate of the sixth transistor is electrically connected to the first clock signal terminal, a first electrode of the sixth transistor is electrically connected to a second electrode of the fifth transistor, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal.
  • the first control node control circuit includes a seventh transistor; the gate of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node.
  • the third node control circuit includes an eighth transistor and a third capacitor; the gate of the eighth transistor is electrically connected to the first control node, the first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighth transistor is electrically connected to the third node;
  • a first end of the third capacitor is electrically connected to the first control node, and a second end of the third capacitor is electrically connected to the third node;
  • the second node control circuit further includes a fourth capacitor
  • a first end of the fourth capacitor is electrically connected to the second control node, and a second end of the fourth capacitor is electrically connected to the second node.
  • the third node control circuit further includes a ninth transistor
  • a gate of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to the third node, and a second electrode of the ninth transistor is electrically connected to the second voltage terminal.
  • the first node control circuit includes a tenth transistor
  • a gate of the tenth transistor is electrically connected to the first clock signal terminal, a first electrode of the tenth transistor is electrically connected to the fourth node, and a second electrode of the tenth transistor is electrically connected to the first node.
  • the first node control circuit includes an eleventh transistor
  • a gate of the eleventh transistor is electrically connected to the second node, a first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to the second voltage terminal.
  • the second control node control circuit includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor;
  • the gate of the twelfth transistor is electrically connected to the reset terminal, the first electrode of the twelfth transistor is electrically connected to the second control node, and the second electrode of the twelfth transistor is electrically connected to the third voltage terminal;
  • the gate of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the third voltage terminal, and the second electrode of the thirteenth transistor is electrically connected to the second control node;
  • the gate of the fourteenth transistor is electrically connected to the first control node, the first electrode of the fourteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the second control node.
  • the first output circuit includes a first output transistor; the gate of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to a third voltage terminal or an output clock signal terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal.
  • the second output circuit includes a second output transistor
  • the third output circuit includes a third output transistor
  • the gate of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the fifth node;
  • a gate of the third output transistor is electrically connected to the second node, a first electrode of the third output transistor is electrically connected to the fifth node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.
  • the second node control circuit 14 includes a first transistor T1 and a fourth capacitor C4 ;
  • the gate of the first transistor T1 is electrically connected to the second control node PQB, the source of the first transistor T1 is electrically connected to the first clock signal terminal CKB, and the drain of the first transistor T1 is electrically connected to the second node QB;
  • a first end of the fourth capacitor C4 is electrically connected to the second control node PQB, and a second end of the fourth capacitor C4 is electrically connected to the second node QB;
  • the fourth node control circuit 22 includes a second transistor T2 and a third transistor T3;
  • the gate of the second transistor T2 is electrically connected to the first node Q, the source of the second transistor T2 is electrically connected to the second high voltage terminal VGH2, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the gate of the third transistor T3 is electrically connected to the first clock signal terminal CKB, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the fourth node N4;
  • the fifth node control circuit 44 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the driving signal output terminal O1, the source of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH, and the drain of the fourth transistor T4 is electrically connected to the fifth node N5;
  • the first control node control circuit 11 includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the first clock signal terminal CKB, and the source of the fifth transistor T5 is electrically connected to the first control node PQ;
  • the gate of the sixth transistor T6 is electrically connected to the second control node PQB, the source of the sixth transistor T6 is electrically connected to the drain of the fifth transistor T5, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;
  • the first control node control circuit 11 comprises a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the second clock signal terminal CKA, the source of the seventh transistor T7 is electrically connected to the input terminal STU, and the drain of the seventh transistor T7 is electrically connected to the first control node PQ;
  • the third node control circuit 21 includes an eighth transistor T8 and a third capacitor C3;
  • the gate of the eighth transistor T8 is electrically connected to the first control node PQ, the source of the eighth transistor T8 is electrically connected to the first clock signal terminal CKB, and the drain of the eighth transistor T8 is electrically connected to the third node N3;
  • a first end of the third capacitor C3 is electrically connected to the first control node PQ, and a second end of the third capacitor C3 is electrically connected to a third node N3.
  • the first node control circuit 13 includes a tenth transistor T10;
  • the gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CKB, the source of the tenth transistor T10 is electrically connected to the fourth node N4, and the drain of the tenth transistor T10 is electrically connected to the first node Q;
  • the first node control circuit 13 includes an eleventh transistor T11;
  • the gate of the eleventh transistor T11 is electrically connected to the second node QB, the source of the eleventh transistor T11 is electrically connected to the first node Q, and the drain of the eleventh transistor T11 is electrically connected to the low voltage terminal VGL;
  • the second control node control circuit 12 includes a twelfth transistor T12, a thirteenth transistor T13 and a fourteenth transistor T14;
  • the gate of the twelfth transistor T12 is electrically connected to the reset terminal RST, the source of the twelfth transistor T12 is electrically connected to the second control node PQB, and the drain of the twelfth transistor T12 is electrically connected to the first high voltage terminal VGH;
  • a gate of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CKA, a source of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH, and a drain of the thirteenth transistor T13 is electrically connected to the second control node PQB;
  • the gate of the fourteenth transistor T14 is electrically connected to the first control node PQ, the source of the fourteenth transistor T14 is electrically connected to the second clock signal terminal CKA, and the drain of the fourteenth transistor T14 is electrically connected to the second control node PQB;
  • the first output circuit 110 includes a first output transistor To1;
  • the gate of the first output transistor To1 is electrically connected to the first node Q, the source of the first output transistor To1 is electrically connected to the first high voltage terminal VGH, and the drain of the first output transistor To1 is electrically connected to the driving signal output terminal O1;
  • the second output circuit 42 includes a second output transistor To2, and the third output circuit 43 includes a third output transistor To3;
  • the gate of the second output transistor To2 is electrically connected to the second node QB, the source of the second output transistor To2 is electrically connected to the drive signal output terminal O1, and the drain of the second output transistor To2 is electrically connected to the fifth node N5;
  • the gate of the third output transistor To3 is electrically connected to the second node QB, the source of the third output transistor To3 is electrically connected to the fifth node N5, and the drain of the third output transistor To3 is electrically connected to the low voltage terminal VGL;
  • the first energy storage circuit 111 includes a first capacitor C1, and the second energy storage circuit 112 includes a second capacitor C2;
  • a first end of the first capacitor C1 is electrically connected to the first node Q, and a second end of the first capacitor C1 is electrically connected to the driving signal output terminal O1;
  • a first end of the second capacitor C2 is electrically connected to the second node QB, and a second end of the second capacitor C2 is electrically connected to the driving signal output terminal O1.
  • all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.
  • a transistor can also be set, the gate of the transistor is electrically connected to the first control node PQ, the first electrode of the transistor can be electrically connected to the first high voltage terminal VGH, and the second electrode of the transistor can be electrically connected to the third node N3; but this is not limited to it.
  • the input terminal STU can be electrically connected to the drive signal output terminal of the adjacent previous-level drive circuit, or the input terminal can be a high-level terminal or a clock signal terminal, but is not limited to this.
  • the gate of the third transistor may not be electrically connected to the first clock signal terminal CKB, and the gate of the third transistor may be electrically connected to the first high voltage terminal VGH or the second high voltage terminal VGH2.
  • the potential of the second high voltage signal provided by the second high voltage terminal VGH2 may be the same as the potential of the first high voltage signal provided by the first high voltage terminal VGH, or the potential of the second high voltage signal may be slightly greater than the potential of the first high voltage signal; for example, the potential of the second high voltage signal may be 24V, and the potential of the first high voltage signal may be 20V, but is not limited thereto.
  • the duty cycle of the first clock signal and the duty cycle of the second clock signal may be 25%, and the first clock signal provided by CKB may be shifted half a cycle later than the second clock signal provided by CKA;
  • a first clock signal is added, and T1 controls the second node QB to be connected to the first clock signal terminal CKB under the control of the potential of the second control node PQB, thereby preventing To2 and To3 from being in a positive stress state for a long time, thereby improving the working stability of the driving circuit;
  • At least one embodiment of the driving circuit shown in FIG13 is provided with T2 and T4 for preventing leakage;
  • T2 When the potential of the first node Q is a high voltage, T2 is turned on to control the fourth node N4 to be connected to the second high voltage terminal VGH2, thereby preventing the potential of the first node Q from decreasing due to leakage, so that O1 can output the driving signal normally;
  • T4 is turned on to control the connection between the fifth node N5 and the first high voltage terminal VGH to prevent the potential of the driving signal outputted from the driving signal output terminal O1 from decreasing due to leakage.
  • the fourth transistor T4 for preventing leakage when at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is working, if the fourth transistor T4 for preventing leakage is not provided, when the threshold voltage of To2 and/or the threshold voltage of To3 drifts negatively, T11 and/or T12 are abnormally turned on, which may cause output leakage.
  • at least one embodiment of the present disclosure adopts the fourth transistor T4 for preventing leakage, so that when O1 outputs a high voltage signal, T4 can be controlled to turn on, so as to control the connection between VGH and the intermediate node of To2 and To3, thereby preventing the voltage value of the signal output by O1 from being reduced due to leakage.
  • the driving circuit described in at least one embodiment of the present disclosure can normally output a driving signal when the threshold voltage of the oxide thin film transistor is between -2.5V and +4V.
  • the transistor included in the driving circuit may be an oxide thin film transistor, and a threshold voltage of the oxide thin film transistor may be greater than or equal to -2.5V and less than or equal to 4V, but is not limited thereto.
  • At least one embodiment of the driving circuit shown in FIG13 is provided with T5 and T6;
  • T5 and T6 are turned on to control the potential of PQ to a low voltage for noise immunity.
  • the driving cycle may include a first stage S1 , a second stage S2 , and a third stage S3 which are arranged successively;
  • RST provides a high voltage signal
  • T12 is turned on, when CKA outputs a low voltage signal and CKB outputs a high voltage signal, the potential of PQB is a high voltage
  • T1 is turned on to control the connection between QB and CKB
  • the potential of QB is a high voltage
  • T11 is turned on to control the potential of Q to be a low voltage
  • STU inputs a high voltage signal.
  • CKA outputs a high voltage signal
  • CKB outputs a low voltage signal
  • T7, T13, To1 and T1 are turned on
  • the potential of PQ and the potential of PQB are both high voltage
  • T1 is turned on
  • the potential of QB is low voltage.
  • T3 and T10 are turned on, the potential of Q is a high voltage, To1 is turned on, and O1 outputs a high voltage signal;
  • T2 is used to prevent leakage of the first node Q; at this time, T14 is turned on, PQB is connected to CKA, and the potential of PQB is a low voltage; T1 is turned off, and the potential of QB is maintained at a low voltage under the action of C2;
  • STU inputs a low voltage signal.
  • CKA outputs a high voltage signal
  • CKB outputs a low voltage signal
  • T7 is turned on
  • the potential of PQ is low voltage
  • T8 and T14 are turned off
  • T13 is turned on
  • the potential of PQB is high voltage
  • T1 is turned on to control the potential of QB to be low voltage
  • O1 outputs a high voltage signal
  • T1 and T11 are turned on, T1 is turned on, the potential of QB is a high voltage, T11 is turned on, the potential of Q is a low voltage, To2 and To3 are turned on, and O1 outputs a low voltage signal;
  • the potential of PQB is maintained at a high voltage, and the potential of QB is strongly correlated with the first clock signal provided by CKB. That is, when CKB outputs a high voltage signal, T1 and T11 are turned on, the potential of QB is a high voltage, the potential of Q is a low voltage, and To2 and To3 are turned off, avoiding To2 and To3 from being in a positive stress state for a long time, thereby improving reliability.
  • the voltage value of the low voltage signal provided by VGL may be -6V
  • the voltage value of the low voltage signal provided by CKB may be -8V.
  • the difference between the voltage value of the low voltage signal provided by the low voltage terminal VGL and the voltage value of the low voltage signal provided by the first clock signal terminal CKB may be greater than a predetermined voltage value, and the predetermined voltage value may be greater than or equal to 1.5V.
  • the predetermined voltage value may be 2V, but is not limited to this. The above setting can prevent output leakage when the threshold voltage of the second output transistor To2 and the threshold voltage of the third output transistor Vo3 drift negatively.
  • 1H is one-line scanning time
  • 3H is three-line scanning time
  • FIG. 15 is a simulation operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 13 .
  • the driving signal output by the pixel circuit described in at least one embodiment of the present disclosure may be a PWM (pulse width modulation) signal, which is made of an oxide transistor.
  • PWM pulse width modulation
  • the threshold voltage of the oxide transistor is easily affected by light, temperature, etc., which may cause the threshold voltage of the oxide transistor to drift negatively, and then cause leakage, etc., affecting the function of the driving circuit, at least one embodiment of the present disclosure uses two anti-leakage transistors to be able to output the driving signal normally even when the threshold voltage of the oxide transistor drifts negatively.
  • the second node control circuit 14 includes a first transistor T1 and a fourth capacitor C4;
  • the gate of the first transistor T1 is electrically connected to the second control node PQB, the source of the first transistor T1 is electrically connected to the first clock signal terminal CKB, and the drain of the first transistor T1 is electrically connected to the second node QB;
  • a first end of the fourth capacitor C4 is electrically connected to the second control node PQB, and a second end of the fourth capacitor C4 is electrically connected to the second node QB;
  • the fourth node control circuit 22 includes a second transistor T2 and a third transistor T3;
  • the gate of the second transistor T2 is electrically connected to the first node Q, the source of the second transistor T2 is electrically connected to the second high voltage terminal VGH2, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the gate of the third transistor T3 is electrically connected to the first clock signal terminal CKB, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the fourth node N4;
  • the fifth node control circuit 44 includes a fourth transistor T4;
  • the gate of the fourth transistor T4 is electrically connected to the driving signal output terminal O1, the source of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH, and the drain of the fourth transistor T4 is electrically connected to the fifth node N5;
  • the first control node control circuit 11 includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the first clock signal terminal CKB, and the source of the fifth transistor T5 is electrically connected to the first control node PQ;
  • the gate of the sixth transistor T6 is electrically connected to the second control node PQB, the source of the sixth transistor T6 is electrically connected to the drain of the fifth transistor T5, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;
  • the first control node control circuit 11 comprises a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the second clock signal terminal CKA, the source of the seventh transistor T7 is electrically connected to the input terminal STU, and the drain of the seventh transistor T7 is electrically connected to the first control node PQ;
  • the third node control circuit 21 includes an eighth transistor T8, a third capacitor C3 and a ninth transistor T9;
  • the gate of the eighth transistor T8 is electrically connected to the first control node PQ, the source of the eighth transistor T8 is electrically connected to the first clock signal terminal CKB, and the drain of the eighth transistor T8 is electrically connected to the third node N3;
  • a first end of the third capacitor C3 is electrically connected to the first control node PQ, and a second end of the third capacitor C3 is electrically connected to a third node N3;
  • the gate of the ninth transistor T9 is electrically connected to the second node QB, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the low voltage terminal VGL;
  • the first node control circuit 13 includes a tenth transistor T10;
  • the gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CKB, the source of the tenth transistor T10 is electrically connected to the fourth node N4, and the drain of the tenth transistor T10 is electrically connected to the first node Q;
  • the second control node control circuit 12 includes a twelfth transistor T12, a thirteenth transistor T13 and a fourteenth transistor T14;
  • the gate of the twelfth transistor T12 is electrically connected to the reset terminal RST, the source of the twelfth transistor T12 is electrically connected to the second control node PQB, and the drain of the twelfth transistor T12 is electrically connected to the first high voltage terminal VGH;
  • the gate of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CKA, the source of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH, and the drain of the thirteenth transistor T13 is electrically connected to the second control node PQB;
  • the gate of the fourteenth transistor is electrically connected to the first control node, the first electrode of the fourteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the second control node;
  • the first output circuit 110 includes a first output transistor To1;
  • the gate of the first output transistor To1 is electrically connected to the first node Q, the source of the first output transistor To1 is electrically connected to the first high voltage terminal VGH, and the drain of the first output transistor To1 is electrically connected to the driving signal output terminal O1;
  • the second output circuit 42 includes a second output transistor To2, and the third output circuit 43 includes a third output transistor To3;
  • the gate of the second output transistor To2 is electrically connected to the second node QB, the source of the second output transistor To2 is electrically connected to the drive signal output terminal O1, and the drain of the second output transistor To2 is electrically connected to the fifth node N5;
  • the gate of the third output transistor To3 is electrically connected to the second node QB, the source of the third output transistor To3 is electrically connected to the fifth node N5, and the drain of the third output transistor To3 is electrically connected to the low voltage terminal VGL;
  • the first energy storage circuit 111 includes a first capacitor C1, and the second energy storage circuit 112 includes a second capacitor C2;
  • a first end of the first capacitor C1 is electrically connected to the first node Q, and a second end of the first capacitor C1 is electrically connected to the driving signal output terminal O1;
  • a first end of the second capacitor C2 is electrically connected to the second node QB, and a second end of the second capacitor C2 is electrically connected to the driving signal output terminal O1.
  • all transistors are n-type transistors, and all transistors are oxide thin film transistors, but the present invention is not limited thereto.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that the transistor for pulling down the potential of the first node Q is moved to be electrically connected to the third node N3, that is, the gate of the ninth transistor T9 is electrically connected to the second node QB, the source of the ninth transistor T9 is electrically connected to the third node N3, and the drain of the ninth transistor T9 is electrically connected to the low voltage terminal VGL. Since the source of T9 is not directly electrically connected to the first node Q, leakage of the first node Q can be further prevented.
  • the source of the first output transistor To1 is electrically connected to the first high voltage terminal VGH
  • the source of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH
  • the drain of the third output transistor To3 is electrically connected to the low voltage terminal VGL;
  • the source of the first output transistor To1 and the source of the thirteenth transistor T13 are electrically connected to the same input terminal, and the source of the first output transistor To1 and the drain of the third output transistor To3 are electrically connected to different input terminals.
  • the driving circuit may include only To2 or To3 for output resetting.
  • an eleventh transistor T11 may be further provided, wherein a gate of the eleventh transistor T11 is electrically connected to the second node QB, a source of the eleventh transistor T11 is electrically connected to the first node Q, and a drain of the eleventh transistor T11 is electrically connected to the low voltage terminal VGL;
  • the driving circuit may include both the ninth transistor T9 and the eleventh transistor T11;
  • the ninth transistor T9 resets the potential of N3 under the control of the potential of the second node QB;
  • the eleventh transistor T11 resets the potential of the first node Q under the control of the second node QB.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 17 of the present disclosure and the driving circuit shown in FIG. 16 of the present disclosure is that the source of T4 is electrically connected to the second high voltage terminal VGH2 .
  • the difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and the driving circuit shown in FIG. 16 of the present disclosure is that the gate of T5 is electrically connected to the second control node PQB, and the gate of T6 is electrically connected to the first clock signal terminal CKB.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure and the driving circuit shown in FIG. 16 of the present disclosure is that the source of To1 is electrically connected to the first clock signal terminal CKB.
  • FIG. 20 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 19 .
  • At least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure may be used to provide a gate driving signal for a pixel circuit, but is not limited thereto.
  • the driving signal provided by the driving circuit described in at least one embodiment of the present disclosure may provide a control signal for the pixel circuit.
  • the related internal compensation pixel circuit may include a first control transistor M1, a second control transistor M2, a third control transistor M3, a fourth control transistor M4, a driving transistor M5, a storage capacitor Cst and an organic light emitting diode OL;
  • M1 is a data writing transistor, used to control the writing data voltage Vdata;
  • M2 is a compensation control transistor, which is used to control the compensation process and write the compensation voltage Vref;
  • M3 is a reset transistor, used to write the initialization voltage Vini into the source S of the driving transistor M5;
  • M4 is a light-emitting control transistor, used to control the light-emitting process
  • M5 is a driving transistor, used to drive OL to emit light
  • the symbol G is the gate of M5, and the symbol D is the drain of M5.
  • the driving circuit when the first output circuit is electrically connected to the third voltage terminal, the driving circuit is used to provide a light emitting control signal to the gate of the light emitting control transistor included in the internal compensation pixel circuit;
  • the driving circuit can be used to provide a gate driving signal for the gate of the data writing transistor
  • G1 is the first scan line
  • G2 is the second scan line
  • G3 is the third scan line
  • EM is the light-emitting control line
  • ELVDD is the power supply voltage terminal
  • ELVSS is the low level terminal
  • Da is the data line
  • Co is the capacitor at both ends of OL.
  • M1 , M2 , M3 , M4 and M5 are all n-type transistors, and M1 , M2 , M3 , M4 and M5 are all oxide transistors, but the present invention is not limited thereto.
  • a display cycle may include a reset phase t1 , a compensation phase t2 , a data writing phase t3 , and a light emitting phase t4 , which are successively arranged;
  • G2 In the compensation phase t2, G2 remains on, maintaining the voltage of the gate G of M5 at Vref, T3 is turned off, EM is turned on, and M4 is turned on;
  • M5 is turned on, and the power supply voltage provided by ELVDD charges Cst to increase the potential of the source S of M5 until the gate-source voltage of M5 is Vth. At this time, the potential of the source S of M5 is Vref-Vth, and Vth is the threshold voltage of M5;
  • the first-stage driving circuit is labeled A1
  • the second-stage driving circuit is labeled A2
  • the third-stage driving circuit is labeled A3;
  • Each level of driving circuit can drive two rows of pixel circuits
  • the pixel circuits labeled P1 are the first row
  • the pixel circuits labeled P2 are the second row
  • the pixel circuits labeled P3 are the third row
  • the pixel circuits labeled P4 are the fourth row
  • the pixel circuits labeled P5 are the fifth row
  • the pixel circuits labeled P4 are the sixth row;
  • the drive signal output terminal O1(1) of A1 is electrically connected to the input terminal of A2;
  • the drive signal output terminal O1 (2) of A2 is electrically connected to the input terminal of A3; the drive signal output terminal of A3 is marked as O1 (3).
  • each driving circuit may also be electrically connected to the driving signal output end of the adjacent next one or several driving circuits, but the present invention is not limited thereto.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the display period includes a first stage, a second stage and a third stage which are arranged in sequence; the driving method includes:
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage, and the second node control circuit controls the second node to be connected to the first clock signal terminal under the control of the potential of the second control node; the first node control circuit controls the potential of the first node to be a turn-off voltage;
  • the first control node control circuit controls the potential of the first control node to be a turn-on voltage
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage
  • the second node control circuit controls the second node to be connected to the first clock signal terminal under the control of the potential of the second control node
  • the first control node control circuit controls the potential of the first control node to be the on voltage
  • the second control node control circuit controls the potential of the second control node to be the off voltage
  • the second node control circuit controls the potential of the second node to be the off voltage
  • the first node control circuit controls the potential of the first node to be the on voltage
  • the first control node control circuit controls the potential of the first control node to be a turn-off voltage
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage
  • the second node control circuit controls the second node to be connected to the first clock signal terminal under the control of the potential of the second control node
  • the first node control circuit controls the potential of the first node to be a turn-on voltage
  • the second control node control circuit controls the potential of the second control node to be a turn-on voltage
  • the first node control circuit controls the potential of the first node to be a turn-off voltage
  • the second node control circuit controls the connection between the second node and the first clock signal terminal under the control of the potential of the second control node.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.
  • the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种驱动电路、驱动方法和显示装置。驱动电路包括第一控制节点控制电路(11)、第二控制节点控制电路(12)、第一节点控制电路(13)和第二节点控制电路(14)，其中，第一控制节点控制电路(11)用于控制第一控制节点(PQ)的电位;第二控制节点控制电路(12)用于控制第二控制节点(PQB)的电位；第一节点控制电路(13)用于控制第一节点(Q)的电位；第二节点控制电路(14)分别与第二控制节点(PQB)、第一时钟信号端(CKB)和第二节点(QB)电连接，用于在第二控制节点(PQB)的电位的控制下，控制第一时钟信号端(CKB)与第二节点(QB)之间连通。提升驱动电路的工作稳定性。

Description

驱动电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法和显示装置。
背景技术
在相关技术中，对于中尺寸显示产品，内部补偿技术相较于外部补偿技术，因无需昂贵的FPGA(现场可编程门阵列)或ASIC(Application Specific Integrated Circuit，专用集成电路)芯片，以及外部source driver(源极驱动器)，同时也不需要体积庞大的Tcon(时序控制器)，具有驱动系统简单、成本低等优势。同时内补像素电路相较于外部像素电路，像素驱动部分的结构更加复杂，即对应需要采用的GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)组数会更多，而GOA的工作稳定性较低。
发明内容
在第一个方面中，本公开实施例提供一种驱动电路，包括第一控制节点控制电路、第二控制节点控制电路、第一节点控制电路和第二节点控制电路，其中，
所述第一控制节点控制电路用于控制第一控制节点的电位；
所述第二控制节点控制电路用于控制第二控制节点的电位；
所述第一节点控制电路用于控制第一节点的电位；
所述第二节点控制电路分别与所述第二控制节点、第一时钟信号端和第二节点电连接，用于在所述第二控制节点的电位的控制下，控制所述第一时钟信号端与所述第二节点之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第三节点控制电路和第四节点控制电路；
所述第三节点控制电路分别与第一控制节点、第三节点和第一时钟信号端电连接，用于在所述第一控制节点的电位的控制下，控制所述第三节点与 所述第一时钟信号端之间连通，并根据所述第一控制节点的电位控制所述第三节点的电位；
所述第四节点控制电路在第一时钟信号端提供的第一时钟信号的控制下，控制所述第三节点与所述第四节点之间连通，在所述第一节点的电位的控制下，控制所述第四节点与所述第一电压端之间连通；
所述第二节点控制电路还用于根据所述第二控制节点的电位，控制所述第二节点的电位。
可选的，所述第一节点控制电路分别与第一节点、第一时钟信号端和第四节点电连接，用于在所述第一时钟信号的控制下，控制所述第四节点与所述第一节点之间连通。
可选的，所述第一节点控制电路还分别与第二节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第一节点与所述第二电压端之间连通。
可选的，所述第三节点控制电路分别与第二节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第三节点与所述第二电压端之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括驱动信号输出端、第二输出电路、第三输出电路和第五节点控制电路，其中，
所述第二输出电路分别与所述第二节点、所述驱动信号输出端和第五节点电连接，用于在所述第二节点的电位的控制下，控制所述驱动信号输出端与所述第五节点之间连通；
所述第三输出电路分别与所述第二节点、所述第五节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第五节点与所述第二电压端之间连通；
所述第五节点控制电路分别与所述第五节点和驱动信号输出端电连接，所述第五节点控制电路还与第三电压端或第一电压端电连接，用于在所述驱动信号输出端提供的驱动信号的控制下，控制所述第五节点与所述第三电压端或所述第一电压端之间连通。
可选的，第一控制节点控制电路分别与第一控制节点、第一时钟信号端、 第二控制节点和第二电压端电连接，用于在所述第一时钟信号端提供的第一时钟信号和所述第二控制节点的电位的控制下，控制所述第一控制节点与所述第二电压端之间连通。
可选的，所述第一控制节点控制电路还分别第二时钟信号端和输入端电连接，用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一控制节点与所述输入端之间连通。
可选的，所述第二控制节点控制电路分别与第二控制节点、第二时钟信号端、复位端、第三电压端和所述第一控制节点电连接，用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第二控制节点与所述第三电压端之间连通，在所述复位端提供的复位信号的控制下，控制所述第二控制节点与所述第三电压端之间连通，并在所述第一控制节点的电位的控制下，控制所述第二控制节点与第二时钟信号端之间连通，在第一控制节点的电位的控制下，控制第二控制节点与第二时钟信号端之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第一输出电路；所述第一输出电路分别与第一节点和驱动信号输出端电连接，所述第一输出电路与第三电压端或输出时钟信号端电连接，用于在所述第一节点的电位的控制下，控制所述驱动信号输出端与所述第三电压端或所述输出时钟信号端之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第一储能电路和第二储能电路；
所述第一储能电路的第一端与所述第一节点电连接，所述第一储能电路的第二端与驱动信号输出端电连接；所述第一储能电路用于维持第一节点的电位；
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第二电压端电连接；所述第二储能电路用于维持第二节点的电位。
可选的，所述第二节点控制电路包括第一晶体管；
所述第一晶体管的栅极与所述第二控制节点电连接，所述第一晶体管的第一极与所述第一时钟信号端电连接，所述第一晶体管的第二极与第二节点电连接。
可选的，所述第四节点控制电路包括第二晶体管和第三晶体管；
所述第二晶体管的栅极与所述第一节点电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第四节点电连接；
所述第三晶体管的栅极与所述第一时钟信号端电连接，所述第三晶体管的第一极与所述第三节点电连接，所述第三晶体管的第二极与所述第四节点电连接。
可选的，所述第五节点控制电路包括第四晶体管；
所述第四晶体管的栅极与所述驱动信号输出端电连接，所述第四晶体管的第一极与第三电压端或第一电压端电连接，所述第四晶体管的第二极与第五节点电连接。
可选的，所述第一控制节点控制电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极与第一时钟信号端电连接，所述第五晶体管的第一极与所述第一控制节点电连接；
所述第六晶体管的栅极与所述第二控制节点电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与第二电压端电连接。
可选的，所述第一控制节点控制电路包括第五晶体管和第六晶体管；
所述第五晶体管的栅极与第二控制节点电连接，所述第五晶体管的第一极与第一控制节点电连接；
所述第六晶体管的栅极与所述第一时钟信号端电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与所述第二电压端电连接。
可选的，所述第一控制节点控制电路包括第七晶体管；所述第七晶体管的栅极与所述第二时钟信号端电连接，所述第七晶体管的第一极与所述输入端电连接，所述第七晶体管的第二极与所述第一控制节点电连接。
可选的，所述第三节点控制电路包括第八晶体管和第三电容；所述第八晶体管的栅极与所述第一控制节点电连接，所述第八晶体管的第一极与第一时钟信号端电连接，所述第八晶体管的第二极与所述第三节点电连接；
所述第三电容的第一端与所述第一控制节点电连接，所述第三电容的第二端与第三节点电连接；
所述第二节点控制电路还包括第四电容；
所述第四电容的第一端与第二控制节点电连接，所述第四电容的第二端与所述第二节点电连接。
可选的，所述第三节点控制电路还包括第九晶体管；
所述第九晶体管的栅极与所述第二节点电连接，所述第九晶体管的第一极所述第三节点电连接，所述第九晶体管的第二极与所述第二电压端电连接。
可选的，所述第一节点控制电路包括第十晶体管；
所述第十晶体管的栅极与所述第一时钟信号端电连接，所述第十晶体管的第一极与所述第四节点电连接，所述第十晶体管的第二极与所述第一节点电连接。
可选的，所述第一节点控制电路包括第十一晶体管；
所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一极与第一节点电连接，所述第十一晶体管的第二极与第二电压端电连接。
可选的，所述第二控制节点控制电路包括第十二晶体管、第十三晶体管和第十四晶体管；
所述第十二晶体管的栅极与所述复位端电连接，所述第十二晶体管的第一极与所述第二控制节点电连接，所述第十二晶体管的第二极与所述第三电压端电连接；
所述第十三晶体管的栅极与所述第二时钟信号端电连接，所述第十三晶体管的第一极与第三电压端电连接，所述第十三晶体管的第二极与第二控制节点电连接；
所述第十四晶体管的栅极与第一控制节点电连接，所述第十四晶体管的第一极与第二时钟信号端电连接，所述第十四晶体管的第二极与第二控制节点电连接。
可选的，所述第一输出电路包括第一输出晶体管；所述第一输出晶体管的栅极与所述第一节点电连接，所述第一输出晶体管的第一极与第三电压端或输出时钟信号端电连接，所述第一输出晶体管的第二极与所述驱动信号输 出端电连接。
可选的，所述第二输出电路包括第二输出晶体管，所述第三输出电路包括第三输出晶体管；
所述第二输出晶体管的栅极与所述第二节点电连接，所述第二输出晶体管的第一极与所述驱动信号输出端电连接，所述第二输出晶体管的第二极与第五节点电连接；
所述第三输出晶体管的栅极与所述第二节点电连接，所述第三输出晶体管的第一极与所述第五节点电连接，所述第三输出晶体管的第二极与第二电压端电连接。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的驱动电路，显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在第一阶段包括的至少部分时间段，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通；第一节点控制电路控制第一节点的电位为关断电压；
在第二阶段包括的部分时间段，第一控制节点控制电路控制第一控制节点的电位为开启电压，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通；
在第二阶段包括的另一部分时间段，第一控制节点控制电路控制第一控制节点的电位为开启电压，第二控制节点控制电路控制第二控制节点的电位为关断电压，第二节点控制电路控制第二节点的电位为关断电压，第一节点控制电路控制第一节点的电位为开启电压；
在第三阶段包括的部分时间段，第一控制节点控制电路控制第一控制节点的电位为关断电压，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通，第一节点控制电路控制第一节点的电位为开启电压；
在第三阶段包括的另一部分时间段，第二控制节点控制电路控制第二控制节点的电位为开启电压，第一节点控制电路控制第一节点的电位为关断电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的驱动电路。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的结构图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7是本公开至少一实施例所述的驱动电路的结构图；
图8是本公开至少一实施例所述的驱动电路的结构图；
图9是本公开至少一实施例所述的驱动电路的结构图；
图10是本公开至少一实施例所述的驱动电路的结构图；
图11是本公开至少一实施例所述的驱动电路的结构图；
图12是本公开至少一实施例所述的驱动电路的结构图；
图13是本公开至少一实施例所述的驱动电路的电路图；
图14是图13所示的驱动电路的至少一实施例的工作时序图；
图15是图13所示的驱动电路的至少一实施例的仿真工作时序图；
图16是本公开至少一实施例所述的驱动电路的电路图；
图17是本公开至少一实施例所述的驱动电路的电路图；
图18是本公开至少一实施例所述的驱动电路的电路图；
图19是本公开至少一实施例所述的驱动电路的电路图；
图20是图19所示的驱动电路的至少一实施例的工作时序图；
图21是相关的内部补偿像素电路的电路图；
图22是图21所示的内部补偿像素电路的工作时序图；
图23是三级驱动电路的级联示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的驱动电路包括第一控制节点控制电路11、第二控制节点控制电路12、第一节点控制电路13和第二节点控制电路14，其中，
所述第一控制节点控制电路11与第一控制节点PQ电连接，用于控制第一控制节点PQ的电位；
所述第二控制节点控制电路12与第二控制节点PQB电连接，用于控制第二控制节点PQB的电位；
所述第一节点控制电路13与第一节点Q电连接，用于控制第一节点Q的电位；
所述第二节点控制电路14分别与所述第二控制节点PQB、第一时钟信号端CKB和第二节点QB电连接，用于在所述第二控制节点PQB的电位的控制下，控制所述第一时钟信号端CKB与所述第二节点QB之间连通。
本公开如图1所示的驱动电路的实施例在工作时，第二节点控制电路14在第二控制节点PQB的电位的控制下，控制所述第二节点QB与第一时钟信号端CKB之间连通，以使得第二节点QB的电位在高低电平间切换，从而使 得第二节点QB控制的晶体管不会长期处于正向stress(应力)状态，提升驱动电路的工作稳定性。
在本公开至少一实施例中，所述第一节点控制电路13接入的时钟信号可以与第一控制节点控制电路11接入的时钟信号不同；
所述第一节点控制电路13接入的时钟信号可以与第二控制节点控制电路12接入的时钟信号不同；
所述第一节点控制电路13接入的时钟信号可以第二节点控制电路14接入的时钟信号相同。
本公开如图1所示的驱动的至少一实施例在工作时，当PQB的电位为开启电压(例如，当PQB控制的晶体管为n型晶体管时，开启电压可以为高电压，当PQB控制的晶体管为p型晶体管时，开启电压可以为低电压)时，所述第二节点控制电路14所述第二控制节点PQB的电位的控制下，控制所述第一时钟信号端CKB与所述第二节点QB之间连通。
在图1所示的至少一实施例中，本公开至少一实施例所述的驱动电路还可以包括第一输出电路110；
所述第一输出电路110分别与第一节点Q、第三电压端V3和驱动信号输出端O1电连接，用于在所述第一节点Q的电位的控制下，控制所述驱动信号输出端O1与所述第三电压端V3之间连通；
第一控制节点控制电路11和第二控制节点控制电路12可以都与第二时钟信号端CKA电连接；但不以此为限。
在本公开图1所示的驱动电路的至少一实施例中，第一输出电路110可以用于为像素电路提供发光控制信号，但不以此为限。
在本公开至少一实施例中，所述第一输出电路110也可以不与第三电压端电连接，而是与输出时钟信号端(所述输出时钟信号端可以为第一时钟信号端或第二时钟信号端)电连接，此时，所述驱动电路可以为像素电路提供栅极驱动信号，但不以此为限。
在本公开至少一实施例中，所述驱动电路包括的晶体管可以为n型晶体管，但不以此为限；在具体实施时，所述驱动电路包括的晶体管也可以为p型晶体管。
本公开至少一实施例所述的驱动电路还可以包括第三节点控制电路和第四节点控制电路；
所述第三节点控制电路分别与第一控制节点、第三节点、第四节点和第一时钟信号端电连接，用于在所述第一控制节点的电位的控制下，控制所述第三节点与所述第一时钟信号端之间连通，并根据所述第一控制节点的电位控制所述第三节点的电位；
所述第四节点控制电路在第一时钟信号端提供的第一时钟信号的控制下，控制所述第三节点与所述第四节点之间连通，在所述第一节点的电位的控制下，控制所述第四节点与第一电压端之间连通。
在具体实施时，所述驱动电路还可以包括第三节点控制电路和第四节点控制电路，第三节点控制电路在第一控制节点的电位的控制下，控制所述第三节点的电位，第四节点控制电路在第一时钟信号的控制下，控制第四节点的电位；
所述第二节点控制电路还用于根据所述第二控制节点的电位，控制所述第二节点的电位。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第三节点控制电路21和第四节点控制电路22；
所述第三节点控制电路21分别与第一控制节点PQ、第三节点N3和第一时钟信号端CKB电连接，用于在所述第一控制节点PQ的电位的控制下，控制所述第三节点N3与所述第一时钟信号端CKB之间连通，并根据所述第一控制节点PQ的电位控制所述第三节点N3的电位；
所述第四节点控制电路22分别与第一时钟信号端CKB、第三节点N3、第四节点N4、第一节点Q和第一电压端V1电连接，用于在第一时钟信号端CKB提供的第一时钟信号的控制下，控制所述第三节点N3与所述第四节点N4之间连通，在所述第一节点Q的电位的控制下，控制所述第四节点N4与所述第一电压端V1之间连通；
所述第二节点控制电路14还用于根据所述第二控制节点PQB的电位，控制所述第二节点QB的电位。
在本公开至少一实施例中，所述第一电压端可以为第二高电压端VGH2，但不以此为限。
本公开如图2所示的驱动电路的至少一实施例在工作时，第四节点控制电路22在第一节点Q的电位的控制下，控制所述第四节点N4与第一电压端V1之间连通，以能够在第一节点Q的电位为开启电压(例如：高电压)时，控制第四节点N4与第一电压端V1(所述第一电压端V1可以为第二高电压端VGH2)之间连通，以使得第四节点N4的电位为高电压，从而避免第一节点Q的电位由漏电而降低，从而不能正确输出驱动信号。
在本公开至少一实施例中，所述第一节点控制电路分别与第一节点、第一时钟信号端和第四节点电连接，用于在所述第一时钟信号的控制下，控制所述第四节点与所述第一节点之间连通。
在具体实施时，所述第一节点控制电路还可以在第一时钟信号的控制下，控制第一节点与第四节点之间连通。
可选的，所述第一节点控制电路还分别与第二节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第一节点与所述第二电压端之间连通。
在具体实施时，所述第一节点控制电路还可以在第二节点的电位的控制下，控制第一节点与第二电压端之间连通。
在本公开至少一实施例中，所述第二电压端可以为低电压端，但不以此为限。
如图3所示，在图2所述的驱动电路的至少一实施例的基础上，所述第一节点控制电路13分别与第一节点Q、第二节点QB、第一时钟信号端CKB、第四节点N4和第二电压端V2电连接，用于在所述第一时钟信号端CKB提供的第一时钟信号的控制下，控制所述第四节点N4与所述第一节点Q之间连通，在所述第二节点QB的电位的控制下，控制所述第一节点Q与所述第二电压端V2之间连通。
可选的，所述第三节点控制电路还可以分别与第二节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第三节点与所述第二电压端之间连通。
在具体实施时，第三节点控制电路可以在第二节点的电位的控制下，控制第一节点Q的电位。
如图4所示，在图2所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路13分别与第一节点Q、第一时钟信号端CKB和第四节点N4电连接，用于在所述第一时钟信号的控制下，控制所述第四节点N4与所述第一节点Q之间连通；
所述第三节点控制电路21还可以分别与第二节点QB和第二电压端V2电连接，用于在所述第二节点QB的电位的控制下，控制所述第三节点N3与所述第二电压端V2之间连通。
本公开至少一实施例所述的驱动电路还包括驱动信号输出端、第二输出电路、第三输出电路和第五节点控制电路，其中，
所述第二输出电路分别与所述第二节点、所述驱动信号输出端和第五节点电连接，用于在所述第二节点的电位的控制下，控制所述驱动信号输出端与所述第五节点之间连通；
所述第三输出电路分别与所述第二节点、所述第五节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第五节点与所述第二电压端之间连通；
所述第五节点控制电路分别与所述第五节点和驱动信号输出端电连接，所述第五节点控制电路还与第三电压端或第一电压端电连接，用于在所述驱动信号输出端提供的驱动信号的控制下，控制所述第五节点与所述第三电压端或所述第一电压端之间连通。
在具体实施时，所述驱动电路还可以包括第二输出电路、第三输出电路和第五节点控制电路，第二输出电路和第三输出电路在第二节点的电位的控制下，控制所述驱动信号输出端输出的驱动信号，第五节点控制电路在驱动信号的控制下，控制所述第五节点的电位。
如图5所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括驱动信号输出端O1、第二输出电路42、第三输出电路43和第五节点控制电路44，其中，
所述第二输出电路42分别与所述第二节点QB、所述驱动信号输出端O1 和第五节点N5电连接，用于在所述第二节点QB的电位的控制下，控制所述驱动信号输出端O1与所述第五节点N5之间连通；
所述第三输出电路43分别与所述第二节点QB、所述第五节点N5和第二电压端V2电连接，用于在所述第二节点QB的电位的控制下，控制所述第五节点N5与所述第二电压端V2之间连通；
所述第五节点控制电路44分别与所述第五节点N5和驱动信号输出端O1电连接，所述第五节点控制电路还与第三电压端V3电连接，用于在所述驱动信号输出端O1提供的驱动信号的控制下，控制所述第五节点N5与所述第三电压端V3之间连通。
在本公开至少一实施例中，第三电压端V3可以为第一高电压端VGH，但不以此为限。
本公开如图5所示的驱动电路的至少一实施例在工作时，第五节点控制电路44在驱动信号的控制下，控制第五节点N5与第三电压端V3(所述第三电压端V3可以为第一高电压端VGH)之间连通，以避免驱动信号输出端O1输出的驱动信号的电位由于漏电而降低，以能正常输出驱动信号。
如图6所示，在图4所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括驱动信号输出端O1、第二输出电路42、第三输出电路43和第五节点控制电路44，其中，
所述第二输出电路42分别与所述第二节点QB、所述驱动信号输出端O1和第五节点N5电连接，用于在所述第二节点QB的电位的控制下，控制所述驱动信号输出端O1与所述第五节点N5之间连通；
所述第三输出电路43分别与所述第二节点QB、所述第五节点N5和第二电压端V2电连接，用于在所述第二节点QB的电位的控制下，控制所述第五节点N5与所述第二电压端V2之间连通；
所述第五节点控制电路44分别与所述第五节点N5和驱动信号输出端O1电连接，所述第五节点控制电路还与第三电压端V3电连接，用于在所述驱动信号输出端O1提供的驱动信号的控制下，控制所述第五节点N5与所述第三电压端V3之间连通。
在本公开至少一实施例中，第三电压端V3可以为第一高电压端VGH， 但不以此为限。
本公开如图6所示的驱动电路的至少一实施例在工作时，第五节点控制电路44在驱动信号的控制下，控制第五节点N5与第三电压端V3(所述第三电压端V3可以为第一高电压端VGH)之间连通，以避免驱动信号输出端O1输出的驱动信号的电位由于漏电而降低，以能正常输出驱动信号。
在本公开至少一实施例中，第一控制节点控制电路分别与第一控制节点、第一时钟信号端、第二控制节点和第二电压端电连接，用于在所述第一时钟信号端提供的第一时钟信号和所述第二控制节点的电位的控制下，控制所述第一控制节点与所述第二电压端之间连通。
在具体实施时，所述第一控制节点控制电路可以在第一时钟信号和第二控制节点的电位的控制下，控制所述第一控制节点的电位。
可选的，所述第一控制节点控制电路还分别第二时钟信号端和输入端电连接，用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一控制节点与所述输入端之间连通。
在具体实施时，所述第一控制节点控制电路还可以在第二时钟信号的控制下，控制第一控制节点与输入端之间连通。
如图7所示，在图5所示的驱动电路的至少一实施例的基础上，
第一控制节点控制电路11分别与第一控制节点PQ、第一时钟信号端CKB、第二控制节点PQB和第二电压端V2电连接，用于在所述第一时钟信号端CKB提供的第一时钟信号和所述第二控制节点PQB的电位的控制下，控制所述第一控制节点PQ与所述第二电压端V2之间连通；
所述第一控制节点控制电路11还分别第二时钟信号端CKA和输入端STU电连接，用于在所述第二时钟信号端CKA提供的第二时钟信号的控制下，控制所述第一控制节点PQ与所述输入端STU之间连通。
如图8所示，在图6所示的驱动电路的至少一实施例的基础上，
第一控制节点控制电路11分别与第一控制节点PQ、第一时钟信号端CKB、第二控制节点PQB和第二电压端V2电连接，用于在所述第一时钟信号端CKB提供的第一时钟信号和所述第二控制节点PQB的电位的控制下，控制所述第一控制节点PQ与所述第二电压端V2之间连通；
所述第一控制节点控制电路11还分别第二时钟信号端CKA和输入端STU电连接，用于在所述第二时钟信号端CKA提供的第二时钟信号的控制下，控制所述第一控制节点PQ与所述输入端STU之间连通。
在本公开至少一实施例中，所述第二控制节点控制电路分别与第二控制节点、第二时钟信号端、复位端、第三电压端和所述第一控制节点电连接，用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第二控制节点与所述第三电压端之间连通，在所述复位端提供的复位信号的控制下，控制所述第二控制节点与所述第三电压端之间连通，并在所述第一控制节点的电位的控制下，控制所述第二控制节点与第二时钟信号端之间连通，在第一控制节点的电位的控制下，控制第二控制节点与第二时钟信号端之间连通。
在具体实施时，第二节点控制电路可以在第二时钟信号、复位信号和第一控制节点的电位下，控制第二节点的电位。
如图9所示，在图7所示的驱动电路的至少一实施例的基础上，所述第二控制节点控制电路12分别与第二控制节点PQB、第二时钟信号端CKA、复位端RST、第三电压端V3和所述第一控制节点PQ电连接，用于在所述第二时钟信号端CKA提供的第二时钟信号的控制下，控制所述第二控制节点PQB与所述第三电压端V3之间连通，在所述复位端RST提供的复位信号的控制下，控制所述第二控制节点PQB与所述第三电压端V3之间连通，并在所述第一控制节点PQ的电位的控制下，控制所述第二控制节点PQB与第二时钟信号端CKA之间连通，在第一控制节点PQ的电位的控制下，控制第二控制节点PQB与第二时钟信号端CKA之间连通。
如图10所示，在图8所示的驱动电路的至少一实施例的基础上，所述第二控制节点控制电路12分别与第二控制节点PQB、第二时钟信号端CKA、复位端RST、第三电压端V3和所述第一控制节点PQ电连接，用于在所述第二时钟信号端CKA提供的第二时钟信号的控制下，控制所述第二控制节点PQB与所述第三电压端V3之间连通，在所述复位端RST提供的复位信号的控制下，控制所述第二控制节点PQB与所述第三电压端V3之间连通，并在所述第一控制节点PQ的电位的控制下，控制所述第二控制节点PQB与第二时钟信号端CKA之间连通，在第一控制节点PQ的电位的控制下，控制第二 控制节点PQB与第二时钟信号端CKA之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第一储能电路和第二储能电路；
所述第一储能电路的第一端与所述第一节点电连接，所述第一储能电路的第二端与驱动信号输出端电连接；所述第一储能电路用于维持第一节点的电位；
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第二电压端电连接；第二储能电路用于维持第二节点的电位。
在本公开至少一实施例中，所述第一储能电路可以包括第一电容，所述第二储能电路可以包括第二电容。
如图11所示，在图9所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第一储能电路111和第二储能电路112；
所述第一储能电路111的第一端与所述第一节点Q电连接，所述第一储能电路111的第二端与驱动信号输出端O1电连接；所述第一储能电路111用于维持第一节点Q的电位；
所述第二储能电路112的第一端与所述第二节点QB电连接，所述第二储能电路112的第二端与第二电压端V2电连接；第二储能电路112用于维持第二节点QB的电位。
如图12所示，在图10所示的驱动电路的至少一实施例的基础上，
所述第一储能电路111的第一端与所述第一节点Q电连接，所述第一储能电路111的第二端与驱动信号输出端O1电连接；所述第一储能电路111用于维持第一节点Q的电位；
所述第二储能电路112的第一端与所述第二节点QB电连接，所述第二储能电路112的第二端与第二电压端V2电连接；第二储能电路112用于维持第二节点QB的电位。
可选的，所述第二节点控制电路包括第一晶体管；
所述第一晶体管的栅极与所述第二控制节点电连接，所述第一晶体管的第一极与所述第一时钟信号端电连接，所述第一晶体管的第二极与第二节点电连接。
可选的，所述第四节点控制电路包括第二晶体管和第三晶体管；
所述第二晶体管的栅极与所述第一节点电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第四节点电连接；
所述第三晶体管的栅极与所述第一时钟信号端电连接，所述第三晶体管的第一极与所述第三节点电连接，所述第三晶体管的第二极与所述第四节点电连接。
可选的，所述第五节点控制电路包括第四晶体管；
所述第四晶体管的栅极与所述驱动信号输出端电连接，所述第四晶体管的第一极与第三电压端或第一电压端电连接，所述第四晶体管的第二极与第五节点电连接。
可选的，所述第一控制节点控制电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极与第一时钟信号端电连接，所述第五晶体管的第一极与所述第一控制节点电连接；
所述第六晶体管的栅极与所述第二控制节点电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与第二电压端电连接。
可选的，所述第一控制节点控制电路包括第五晶体管和第六晶体管；
所述第五晶体管的栅极与第二控制节点电连接，所述第五晶体管的第一极与第一控制节点电连接；
所述第六晶体管的栅极与所述第一时钟信号端电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与所述第二电压端电连接。
可选的，所述第一控制节点控制电路包括第七晶体管；所述第七晶体管的栅极与所述第二时钟信号端电连接，所述第七晶体管的第一极与所述输入端电连接，所述第七晶体管的第二极与所述第一控制节点电连接。
可选的，所述第三节点控制电路包括第八晶体管和第三电容；所述第八晶体管的栅极与所述第一控制节点电连接，所述第八晶体管的第一极与第一时钟信号端电连接，所述第八晶体管的第二极与所述第三节点电连接；
所述第三电容的第一端与所述第一控制节点电连接，所述第三电容的第二端与第三节点电连接；
所述第二节点控制电路还包括第四电容；
所述第四电容的第一端与第二控制节点电连接，所述第四电容的第二端与所述第二节点电连接。
可选的，所述第三节点控制电路还包括第九晶体管；
所述第九晶体管的栅极与所述第二节点电连接，所述第九晶体管的第一极所述第三节点电连接，所述第九晶体管的第二极与所述第二电压端电连接。
可选的，所述第一节点控制电路包括第十晶体管；
所述第十晶体管的栅极与所述第一时钟信号端电连接，所述第十晶体管的第一极与所述第四节点电连接，所述第十晶体管的第二极与所述第一节点电连接。
可选的，所述第一节点控制电路包括第十一晶体管；
所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一极与第一节点电连接，所述第十一晶体管的第二极与第二电压端电连接。
可选的，所述第二控制节点控制电路包括第十二晶体管、第十三晶体管和第十四晶体管；
所述第十二晶体管的栅极与所述复位端电连接，所述第十二晶体管的第一极与所述第二控制节点电连接，所述第十二晶体管的第二极与所述第三电压端电连接；
所述第十三晶体管的栅极与所述第二时钟信号端电连接，所述第十三晶体管的第一极与第三电压端电连接，所述第十三晶体管的第二极与第二控制节点电连接；
所述第十四晶体管的栅极与第一控制节点电连接，所述第十四晶体管的第一极与第二时钟信号端电连接，所述第十四晶体管的第二极与第二控制节点电连接。
可选的，所述第一输出电路包括第一输出晶体管；所述第一输出晶体管的栅极与所述第一节点电连接，所述第一输出晶体管的第一极与第三电压端或输出时钟信号端电连接，所述第一输出晶体管的第二极与所述驱动信号输 出端电连接。
可选的，所述第二输出电路包括第二输出晶体管，所述第三输出电路包括第三输出晶体管；
所述第二输出晶体管的栅极与所述第二节点电连接，所述第二输出晶体管的第一极与所述驱动信号输出端电连接，所述第二输出晶体管的第二极与第五节点电连接；
所述第三输出晶体管的栅极与所述第二节点电连接，所述第三输出晶体管的第一极与所述第五节点电连接，所述第三输出晶体管的第二极与第二电压端电连接。
如图13所示，在图11所示的驱动电路的至少一实施例的基础上，所述第二节点控制电路14包括第一晶体管T1和第四电容C4；
所述第一晶体管T1的栅极与所述第二控制节点PQB电连接，所述第一晶体管T1的源极与所述第一时钟信号端CKB电连接，所述第一晶体管T1的漏极与第二节点QB电连接；
所述第四电容C4的第一端与第二控制节点PQB电连接，所述第四电容C4的第二端与第二节点QB电连接；
所述第四节点控制电路22包括第二晶体管T2和第三晶体管T3；
所述第二晶体管T2的栅极与所述第一节点Q电连接，所述第二晶体管T2的源极与所述第二高电压端VGH2电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述第三晶体管T3的栅极与所述第一时钟信号端CKB电连接，所述第三晶体管T3的源极与所述第三节点N3电连接，所述第三晶体管T3的漏极与所述第四节点N4电连接；
所述第五节点控制电路44包括第四晶体管T4；
所述第四晶体管T4的栅极与所述驱动信号输出端O1电连接，所述第四晶体管T4的源极与第一高电压端VGH电连接，所述第四晶体管T4的漏极与第五节点N5电连接；
所述第一控制节点控制电路11包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与第一时钟信号端CKB电连接，所述第五晶 体管T5的源极与所述第一控制节点PQ电连接；
所述第六晶体管T6的栅极与所述第二控制节点PQB电连接，所述第六晶体管T6的源极与所述第五晶体管T5的漏极电连接，所述第六晶体管T6的漏极与低电压端VGL电连接；
所述第一控制节点控制电路11包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第二时钟信号端CKA电连接，所述第七晶体管T7的源极与所述输入端STU电连接，所述第七晶体管T7的漏极与所述第一控制节点PQ电连接；
所述第三节点控制电路21包括第八晶体管T8和第三电容C3；
所述第八晶体管T8的栅极与所述第一控制节点PQ电连接，所述第八晶体管T8的源极与第一时钟信号端CKB电连接，所述第八晶体管T8的漏极与所述第三节点N3电连接；
所述第三电容C3的第一端与所述第一控制节点PQ电连接，所述第三电容C3的第二端与第三节点N3电连接。
所述第一节点控制电路13包括第十晶体管T10；
所述第十晶体管T10的栅极与所述第一时钟信号端CKB电连接，所述第十晶体管T10的源极与所述第四节点N4电连接，所述第十晶体管T10的漏极与所述第一节点Q电连接；
所述第一节点控制电路13包括第十一晶体管T11；
所述第十一晶体管T11的栅极与所述第二节点QB电连接，所述第十一晶体管T11的源极与第一节点Q电连接，所述第十一晶体管T11的漏极与低电压端VGL电连接；
所述第二控制节点控制电路12包括第十二晶体管T12、第十三晶体管T13和第十四晶体管T14；
所述第十二晶体管T12的栅极与所述复位端RST电连接，所述第十二晶体管T12的源极与所述第二控制节点PQB电连接，所述第十二晶体管T12的漏极与所述第一高电压端VGH电连接；
所述第十三晶体管T13的栅极与所述第二时钟信号端CKA电连接，所述第十三晶体管T13的源极与第一高电压端VGH电连接，所述第十三晶体 管T13的漏极与第二控制节点PQB电连接；
所述第十四晶体管T14的栅极与第一控制节点PQ电连接，所述第十四晶体管T14的源极与第二时钟信号端CKA电连接，所述第十四晶体管T14的漏极与第二控制节点PQB电连接；
所述第一输出电路110包括第一输出晶体管To1；
所述第一输出晶体管To1的栅极与所述第一节点Q电连接，所述第一输出晶体管To1的源极与第一高电压端VGH电连接，所述第一输出晶体管To1的漏极与所述驱动信号输出端O1电连接；
所述第二输出电路42包括第二输出晶体管To2，所述第三输出电路43包括第三输出晶体管To3；
所述第二输出晶体管To2的栅极与所述第二节点QB电连接，所述第二输出晶体管To2的源极与所述驱动信号输出端O1电连接，所述第二输出晶体管To2的漏极与第五节点N5电连接；
所述第三输出晶体管To3的栅极与所述第二节点QB电连接，所述第三输出晶体管To3的源极与所述第五节点N5电连接，所述第三输出晶体管To3的漏极与低电压端VGL电连接；
第一储能电路111包括第一电容C1，第二储能电路112包括第二电容C2；
第一电容C1的第一端与第一节点Q电连接，第一电容C1的第二端与驱动信号输出端O1电连接；
第二电容C2的第一端与第二节点QB电连接，第二电容C2的第二端与驱动信号输出端O1电连接。
在图13所示的驱动电路的至少一实施例中，所有晶体管都为n型晶体管，所有的晶体管都为氧化物薄膜晶体管，但不以此为限。
在图13所示的驱动电路的至少一实施例中，还可以设置一个晶体管，该晶体管的栅极与第一控制节点PQ电连接，该晶体管的第一极可以与第一高电压端VGH电连接，该晶体管的第二极可以与第三节点N3电连接；但不以此为限。
在本公开至少一实施例中，所述输入端STU可以与相邻上一级驱动电路 的驱动信号输出端电连接，或者，所述输入端可以为高电平端或时钟信号端，但不以此为限。
在本公开至少一实施例中，所述第三晶体管的栅极可以不与第一时钟信号端CKB电连接，所述第三晶体管的栅极可以与第一高电压端VGH或第二高电压端VGH2电连接。
在本公开至少一实施例中，第二高电压端VGH2提供的第二高电压信号的电位可以与第一高电压端VGH提供的第一高电压信号的电位相同，或者，所述第二高电压信号的电位可以略大于所述第一高电压信号的电位；例如，第二高电压信号的电位可以为24V，第一高电压信号的电位可以为20V，但不以此为限。
在本公开至少一实施例中，所述第一时钟信号的占空比和所述第二时钟信号的占空比可以为25％，CKB提供的第一时钟信号可以比CKA提供的第二时钟信号后移半个周期；
但不以此为限。
在图13所示的驱动电路的至少一实施例中，增加了第一时钟信号，T1在第二控制节点PQB的电位的控制下，控制第二节点QB与第一时钟信号端CKB连通，从而避免To2和To3长期处于正向stress状态，提升驱动电路工作的稳定性；
图13所示的驱动电路的至少一实施例增设了用于防漏电的T2和T4；
当第一节点Q的电位为高电压时，T2打开，以控制第四节点N4与第二高电压端VGH2之间连通，从而防止第一节点Q的电位由于漏电而降低，使得O1能够正常输出驱动信号；
当驱动信号输出端O1输出高电压时，T4打开，以控制第五节点N5与第一高电压端VGH之间连通，防止驱动信号输出端O1输出的驱动信号的电位由于漏电而降低。
图13所示的驱动电路的至少一实施例在工作时，在驱动信号输出端O1需要输出高电压信号时，当To2的阈值电压和To3的阈值电压负向漂移，To2和To3异常打开时，T4打开，也能够使得驱动信号输出端O1正常输出驱动信号。
本公开图13所示的驱动电路的至少一实施例在工作时，如若不设置用于防漏电的第四晶体管T4，当To2的阈值电压和/或To3的阈值电压负漂时，T11和/或T12异常打开，会导致输出漏电，而本公开至少一实施例采用了用于防漏电的第四晶体管T4，以能够在O1输出高电压信号时，控制T4打开，以控制VGH与To2与To3的中间节点之间连通，防止O1输出的信号的电压值由于漏电而降低。
本公开至少一实施例所述的驱动电路能够在氧化物薄膜晶体管的阈值电压为-2.5V至+4V时正常输出驱动信号。
在本公开至少一实施例中，所述驱动电路包括的晶体管可以为氧化物薄膜晶体管，所述氧化物薄膜晶体管的阈值电压可以大于等于-2.5V而小于等于4V，但不以此为限。
图13所示的驱动电路的至少一实施例增设了T5和T6；
当CKB提供高电压信号，并PQB的电位为高电压时，T5和T6打开，以控制PQ的电位为低电压，以进行抗噪。
如图14所示，本公开图13所述的驱动电路的至少一实施例在工作时，驱动周期可以包括先后设置的第一阶段S1、第二阶段S2和第三阶段S3；
在第一阶段S1，RST提供高电压信号，T12打开，当CKA输出低电压信号，CKB输出高电压信号时，PQB的电位为高电压，T1打开，以控制QB与CKB之间连通，QB的电位为高电压，T11打开，以控制Q的电位为低电压；
在第二阶段S2，STU输入高电压信号，当CKA输出高电压信号，CKB输出低电压信号时，T7、T13、To1和T1打开，PQ的电位和PQB的电位都为高电压，T1打开，QB的电位为低电压；
当CKB输出高电压信号，CKA输出低电压信号时，由于T8和C3的作用，PQ的电位进一步自举拉升，T3和T10打开，Q的电位为高电压，To1打开，O1输出高电压信号；为了避免第一节点Q漏电导致输出异常，T2用于对第一节点Q进行防漏电；此时，T14打开，PQB与CKA之间连通，PQB的电位为低电压；T1关断，QB的电位在C2的作用下维持为低电压；
在第三阶段S3，STU输入低电压信号，当CKA输出高电压信号，CKB 输出低电压信号时，T7打开，PQ的电位为低电压，T8和T14关断，T13打开，PQB的电位为高电压，T1打开，以控制QB的电位为低电压，Q的电位维持为高电压；O1输出高电压信号；
当CKB输出高电压信号，CKA输出低电压信号时，T1和T11打开，T1打开，QB的电位为高电压，T11打开，Q的电位为低电压，To2和To3打开，O1输出低电压信号；
之后，PQB的电位维持为高电压，QB的电位与CKB提供的第一时钟信号强相关，也即当CKB输出高电压信号时，T1和T11打开，QB的电位为高电压，Q的电位为低电压，To2和To3关断，避免To2和To3长期处于正向stress状态，提升信赖性。
本公开图13所示的像素电路的至少一实施例在工作时，VGL提供的低电压信号的电压值可以为-6V，当CKB提供低电压信号时，CKB提供的低电压信号的电压值可以为-8V，这样，当驱动信号输出端O1输出高电压信号时，通过以上设置，也可以避免在To2的阈值电压和To3的阈值电压负漂时输出漏电。
在本公开至少一实施例中，所述低电压端VGL提供的低电压信号与第一时钟信号端CKB提供的低电压信号的电压值之间的差值可以大于预定电压值，所述预定电压值可以大于等于1.5V，例如，所述预定电压值可以为2V，但不以此为限；通过以上设定能够防止第二输出晶体管To2的阈值电压和第三输出晶体管Vo3的阈值电压负漂时输出漏电。
在图14中，1H为一行扫描时间，3H为三行扫描时间。
图15是图13所示的像素电路的至少一实施例的仿真工作时序图。
本公开至少一实施例所述的像素电路输出的驱动信号可以为PWM(脉宽调制)信号，采用氧化物晶体管制成，但是由于氧化物晶体管的阈值电压容易受光照、温度等影响，而导致氧化物晶体管的阈值电压负漂，进而导致漏电等情况，影响驱动电路功能，因此本公开至少一实施例采用了两个防漏电晶体管，以能够在氧化物晶体管的阈值电压负漂的情况下，也能够正常输出驱动信号。
如图16所示，在图12所示的驱动电路的至少一实施例的基础上，所述 第二节点控制电路14包括第一晶体管T1和第四电容C4；
所述第一晶体管T1的栅极与所述第二控制节点PQB电连接，所述第一晶体管T1的源极与所述第一时钟信号端CKB电连接，所述第一晶体管T1的漏极与第二节点QB电连接；
所述第四电容C4的第一端与第二控制节点PQB电连接，所述第四电容C4的第二端与第二节点QB电连接；
所述第四节点控制电路22包括第二晶体管T2和第三晶体管T3；
所述第二晶体管T2的栅极与所述第一节点Q电连接，所述第二晶体管T2的源极与所述第二高电压端VGH2电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述第三晶体管T3的栅极与所述第一时钟信号端CKB电连接，所述第三晶体管T3的源极与所述第三节点N3电连接，所述第三晶体管T3的漏极与所述第四节点N4电连接；
所述第五节点控制电路44包括第四晶体管T4；
所述第四晶体管T4的栅极与所述驱动信号输出端O1电连接，所述第四晶体管T4的源极与第一高电压端VGH电连接，所述第四晶体管T4的漏极与第五节点N5电连接；
所述第一控制节点控制电路11包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与第一时钟信号端CKB电连接，所述第五晶体管T5的源极与所述第一控制节点PQ电连接；
所述第六晶体管T6的栅极与所述第二控制节点PQB电连接，所述第六晶体管T6的源极与所述第五晶体管T5的漏极电连接，所述第六晶体管T6的漏极与低电压端VGL电连接；
所述第一控制节点控制电路11包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第二时钟信号端CKA电连接，所述第七晶体管T7的源极与所述输入端STU电连接，所述第七晶体管T7的漏极与所述第一控制节点PQ电连接；
所述第三节点控制电路21包括第八晶体管T8、第三电容C3和第九晶体管T9；
所述第八晶体管T8的栅极与所述第一控制节点PQ电连接，所述第八晶体管T8的源极与第一时钟信号端CKB电连接，所述第八晶体管T8的漏极与所述第三节点N3电连接；
所述第三电容C3的第一端与所述第一控制节点PQ电连接，所述第三电容C3的第二端与第三节点N3电连接；
所述第九晶体管T9的栅极与所述第二节点QB电连接，所述第九晶体管T9的源极所述第三节点N3电连接，所述第九晶体管T9的漏极与低电压端VGL电连接；
所述第一节点控制电路13包括第十晶体管T10；
所述第十晶体管T10的栅极与所述第一时钟信号端CKB电连接，所述第十晶体管T10的源极与所述第四节点N4电连接，所述第十晶体管T10的漏极与所述第一节点Q电连接；
所述第二控制节点控制电路12包括第十二晶体管T12、第十三晶体管T13和第十四晶体管T14；
所述第十二晶体管T12的栅极与所述复位端RST电连接，所述第十二晶体管T12的源极与所述第二控制节点PQB电连接，所述第十二晶体管T12的漏极与所述第一高电压端VGH电连接；
所述第十三晶体管T13的栅极与所述第二时钟信号端CKA电连接，所述第十三晶体管T13的源极与第一高电压端VGH电连接，所述第十三晶体管T13的漏极与第二控制节点PQB电连接；
所述第十四晶体管的栅极与第一控制节点电连接，所述第十四晶体管的第一极与第二时钟信号端电连接，所述第十四晶体管的第二极与第二控制节点电连接；
所述第一输出电路110包括第一输出晶体管To1；
所述第一输出晶体管To1的栅极与所述第一节点Q电连接，所述第一输出晶体管To1的源极与第一高电压端VGH电连接，所述第一输出晶体管To1的漏极与所述驱动信号输出端O1电连接；
所述第二输出电路42包括第二输出晶体管To2，所述第三输出电路43包括第三输出晶体管To3；
所述第二输出晶体管To2的栅极与所述第二节点QB电连接，所述第二输出晶体管To2的源极与所述驱动信号输出端O1电连接，所述第二输出晶体管To2的漏极与第五节点N5电连接；
所述第三输出晶体管To3的栅极与所述第二节点QB电连接，所述第三输出晶体管To3的源极与所述第五节点N5电连接，所述第三输出晶体管To3的漏极与低电压端VGL电连接；
第一储能电路111包括第一电容C1，第二储能电路112包括第二电容C2；
第一电容C1的第一端与第一节点Q电连接，第一电容C1的第二端与驱动信号输出端O1电连接；
第二电容C2的第一端与第二节点QB电连接，第二电容C2的第二端与驱动信号输出端O1电连接。
在图16所示的驱动电路的至少一实施例中，所有晶体管都为n型晶体管，所有的晶体管都为氧化物薄膜晶体管，但不以此为限。
本公开图16所示的驱动电路的至少一实施例与本公开图13所示的驱动电路的至少一实施例的区别在于：将对第一节点Q的电位进行下拉的晶体管移至与第三节点N3电连接，也即，所述第九晶体管T9的栅极与所述第二节点QB电连接，所述第九晶体管T9的源极所述第三节点N3电连接，所述第九晶体管T9的漏极与低电压端VGL电连接，由于T9的源极不直接与第一节点Q电连接，因此能够进一步防止第一节点Q漏电。
在图16所示的驱动电路的至少一实施例中，第一输出晶体管To1的源极与第一高电压端VGH电连接，第十三晶体管T13的源极与第一高电压端VGH电连接，所述第三输出晶体管To3的漏极与低电压端VGL电连接；
第一输出晶体管To1的源极与第十三晶体管T13的源极与同一输入端子电连接，所述第一输出晶体管To1的源极与所述第三输出晶体管To3的漏极与不同的输入端子电连接。
在图16所示的驱动电路的至少一实施例中，所述驱动电路可以仅包括To2或To3，用于进行输出复位。
在图16所示的驱动电路的至少一实施例中，还可以设置有第十一晶体管 T11，所述第十一晶体管T11的栅极与所述第二节点QB电连接，所述第十一晶体管T11的源极与第一节点Q电连接，所述第十一晶体管T11的漏极与低电压端VGL电连接；
也即，在本公开至少一实施例中，所述驱动电路可以同时包括第九晶体管T9和第十一晶体管T11；
第九晶体管T9在第二节点QB的电位的控制下，对N3的电位进行复位；
第十一晶体管T11在第二节点QB的控制下，对第一节点Q的电位进行复位。
本公开图17所示的驱动电路的至少一实施例与本公开图16所示的驱动电路的区别在于：T4的源极与第二高电压端VGH2电连接。
本公开图18所示的驱动电路的至少一实施例与本公开图16所示的驱动电路的区别在于，T5的栅极与第二控制节点PQB电连接，T6的栅极与第一时钟信号端CKB电连接。
本公开图19所示的驱动电路的至少一实施例与本公开图16所示的驱动电路的区别在于：To1的源极与第一时钟信号端CKB电连接。
图20是图19所示的驱动电路的至少一实施例的工作时序图。
本公开图19所示的驱动电路的至少一实施例可以用于为像素电路提供栅极驱动信号，但不以此为限。
本公开至少一实施例所述的驱动电路提供的驱动信号可以为像素电路提供控制信号。
如图21所示，相关的内部补偿像素电路可以包括第一控制晶体管M1、第二控制晶体管M2、第三控制晶体管M3、第四控制晶体管M4、驱动晶体管M5、存储电容Cst和有机发光二极管OL；
M1为数据写入晶体管，用于控制写入数据电压Vdata；
M2为补偿控制晶体管，用于控制补偿过程，写入补偿电压Vref；
M3为复位晶体管，用于将初始化电压Vini写入驱动晶体管M5的源极S；
M4为发光控制晶体管，用于控制发光过程；
M5为驱动晶体管，用于驱动OL发光；
标号为G的为M5的栅极，标号为D的为M5的漏极。
在本公开至少一实施例中，当第一输出电路与第三电压端电连接时，所述驱动电路用于为内部补偿像素电路包括的发光控制晶体管的栅极提供发光控制信号；
当第一输出电路与输出时钟信号端电连接时，所述驱动电路可以用于为数据写入晶体管的栅极提供栅极驱动信号；
但不以此为限。
在图21中，标号为G1的为第一扫描线、标号为G2的为第二扫描线，标号为G3的为第三扫描线，标号为EM的为发光控制线，ELVDD为电源电压端，ELVSS为低电平端、标号为Da的为数据线，标号为Co的为OL两端的电容。
在图21所示的像素电路的至少一实施例中，M1、M2、M3、M4和M5都为n型晶体管，M1、M2、M3、M4和M5都为氧化物晶体管，但不以此为限。
如图22所示，图21所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的复位阶段t1、补偿阶段t2、数据写入阶段t3和发光阶段t4；
在复位阶段t1，G2打开，M2打开，将Vref写入M5的栅极G；同时G3打开，将M5的源极S的电位复位为Vini，以使得在补偿阶段t2开始时，M5能够打开；
在补偿阶段t2，G2保持打开，维持M5的栅极G的电压为Vref，T3关断，EM打开，M4打开；
在补偿阶段t2开始时，M5打开，通过ELVDD提供的电源电压为Cst充电，以提升M5的源极S的电位，直至M5的栅源电压为Vth，此时M5的源极S的电位为Vref-Vth，Vth为M5的阈值电压；
在数据写入阶段t3，G2、G3和EM关断，G1打开，以将数据线Da上的数据电压Vdata写入M5的栅极G；
在发光阶段t4，G1、G2和G3都关断，EM打开，M4和M5打开，M5的源极S被充电至Voled(Voled为OL的启亮电压)，驱动OL发光；当显示面板低灰阶显示需求较高时，可以采用PWM调光模式改善低灰阶显示效果。
如图23所示，标号为A1的为第一级驱动电路，标号为A2的为第二级驱动电路，标号为A3的为第三级驱动电路；
每一级驱动电路可以驱动两行像素电路；
标号为P1的为第一行像素电路，标号为P2的为第二行像素电路，标号为P3的为第三行像素电路，标号为P4的为第四行像素电路，标号为P5的为第五行像素电路，标号为P4的为第六行像素电路；
A1的驱动信号输出端O1(1)与A2的输入端电连接；
A2的驱动信号输出端O1(2)与A3的输入端电连接；A3的驱动信号输出端标示为O1(3)。
在本公开至少一实施例中，各级驱动电路的复位端也可以与相邻下一级或几级驱动电路的驱动信号输出端电连接，但不以此为限。
本公开实施例所述的驱动方法，应用于上述的驱动电路，显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在第一阶段包括的至少部分时间段，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通；第一节点控制电路控制第一节点的电位为关断电压；
在第二阶段包括的部分时间段，第一控制节点控制电路控制第一控制节点的电位为开启电压，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通；
在第二阶段包括的另一部分时间段，第一控制节点控制电路控制第一控制节点的电位为开启电压，第二控制节点控制电路控制第二控制节点的电位为关断电压，第二节点控制电路控制第二节点的电位为关断电压，第一节点控制电路控制第一节点的电位为开启电压；
在第三阶段包括的部分时间段，第一控制节点控制电路控制第一控制节点的电位为关断电压，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通，第一节点控制电路控制第一节点的电位为开启 电压；
在第三阶段包括的另一部分时间段，第二控制节点控制电路控制第二控制节点的电位为开启电压，第一节点控制电路控制第一节点的电位为关断电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通。
本公开实施例所述的显示装置包括上述的驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (26)

  1. 一种驱动电路，包括第一控制节点控制电路、第二控制节点控制电路、第一节点控制电路和第二节点控制电路，其中，
    所述第一控制节点控制电路用于控制第一控制节点的电位；
    所述第二控制节点控制电路用于控制第二控制节点的电位；
    所述第一节点控制电路用于控制第一节点的电位；
    所述第二节点控制电路分别与所述第二控制节点、第一时钟信号端和第二节点电连接，用于在所述第二控制节点的电位的控制下，控制所述第一时钟信号端与所述第二节点之间连通。
  2. 如权利要求1所述的驱动电路，其中，还包括第三节点控制电路和第四节点控制电路；
    所述第三节点控制电路分别与第一控制节点、第三节点和第一时钟信号端电连接，用于在所述第一控制节点的电位的控制下，控制所述第三节点与所述第一时钟信号端之间连通，并根据所述第一控制节点的电位控制所述第三节点的电位；
    所述第四节点控制电路在第一时钟信号端提供的第一时钟信号的控制下，控制所述第三节点与所述第四节点之间连通，在所述第一节点的电位的控制下，控制所述第四节点与第一电压端之间连通；
    所述第二节点控制电路还用于根据所述第二控制节点的电位，控制所述第二节点的电位。
  3. 如权利要求2所述的驱动电路，其中，所述第一节点控制电路分别与第一节点、第一时钟信号端和第四节点电连接，用于在所述第一时钟信号的控制下，控制所述第四节点与所述第一节点之间连通。
  4. 如权利要求3所述的驱动电路，其中，所述第一节点控制电路还分别与第二节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第一节点与所述第二电压端之间连通。
  5. 如权利要求2所述的驱动电路，其中，所述第三节点控制电路分别与第二节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制 所述第三节点与所述第二电压端之间连通。
  6. 如权利要求1至5中任一权利要求所述的驱动电路，其中，还包括驱动信号输出端、第二输出电路、第三输出电路和第五节点控制电路，其中，
    所述第二输出电路分别与所述第二节点、所述驱动信号输出端和第五节点电连接，用于在所述第二节点的电位的控制下，控制所述驱动信号输出端与所述第五节点之间连通；
    所述第三输出电路分别与所述第二节点、所述第五节点和第二电压端电连接，用于在所述第二节点的电位的控制下，控制所述第五节点与所述第二电压端之间连通；
    所述第五节点控制电路分别与所述第五节点和驱动信号输出端电连接，所述第五节点控制电路还与第三电压端或第一电压端电连接，用于在所述驱动信号输出端提供的驱动信号的控制下，控制所述第五节点与所述第三电压端或所述第一电压端之间连通。
  7. 如权利要求1至5中任一权利要求所述的驱动电路，其中，第一控制节点控制电路分别与第一控制节点、第一时钟信号端、第二控制节点和第二电压端电连接，用于在所述第一时钟信号端提供的第一时钟信号和所述第二控制节点的电位的控制下，控制所述第一控制节点与所述第二电压端之间连通。
  8. 如权利要求7所述的驱动电路，其中，所述第一控制节点控制电路还分别第二时钟信号端和输入端电连接，用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一控制节点与所述输入端之间连通。
  9. 如权利要求1所述的驱动电路，其中，所述第二控制节点控制电路分别与第二控制节点、第二时钟信号端、复位端、第三电压端和所述第一控制节点电连接，用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第二控制节点与所述第三电压端之间连通，在所述复位端提供的复位信号的控制下，控制所述第二控制节点与所述第三电压端之间连通，并在所述第一控制节点的电位的控制下，控制所述第二控制节点与第二时钟信号端之间连通，在第一控制节点的电位的控制下，控制第二控制节点与第二时钟信号端之间连通。
  10. 如权利要求1所述的驱动电路，其中，还包括第一输出电路；所述第一输出电路分别与第一节点和驱动信号输出端电连接，所述第一输出电路与第三电压端或输出时钟信号端电连接，用于在所述第一节点的电位的控制下，控制所述驱动信号输出端与所述第三电压端或所述输出时钟信号端之间连通。
  11. 如权利要求1至5中任一权利要求所述的驱动电路，其中，还包括第一储能电路和第二储能电路；
    所述第一储能电路的第一端与所述第一节点电连接，所述第一储能电路的第二端与驱动信号输出端电连接；所述第一储能电路用于维持第一节点的电位；
    所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第二电压端电连接；所述第二储能电路用于维持第二节点的电位。
  12. 如权利要求1所述的驱动电路，其中，所述第二节点控制电路包括第一晶体管；
    所述第一晶体管的栅极与所述第二控制节点电连接，所述第一晶体管的第一极与所述第一时钟信号端电连接，所述第一晶体管的第二极与第二节点电连接。
  13. 如权利要求2所述的驱动电路，其中，所述第四节点控制电路包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述第一节点电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与所述第四节点电连接；
    所述第三晶体管的栅极与所述第一时钟信号端电连接，所述第三晶体管的第一极与所述第三节点电连接，所述第三晶体管的第二极与所述第四节点电连接。
  14. 如权利要求6所述的驱动电路，其中，所述第五节点控制电路包括第四晶体管；
    所述第四晶体管的栅极与所述驱动信号输出端电连接，所述第四晶体管的第一极与第三电压端或第一电压端电连接，所述第四晶体管的第二极与第 五节点电连接。
  15. 如权利要求7所述的驱动电路，其中，所述第一控制节点控制电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极与第一时钟信号端电连接，所述第五晶体管的第一极与所述第一控制节点电连接；
    所述第六晶体管的栅极与所述第二控制节点电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与第二电压端电连接。
  16. 如权利要求7所述的驱动电路，其中，所述第一控制节点控制电路包括第五晶体管和第六晶体管；
    所述第五晶体管的栅极与第二控制节点电连接，所述第五晶体管的第一极与第一控制节点电连接；
    所述第六晶体管的栅极与所述第一时钟信号端电连接，所述第六晶体管的第一极与所述第五晶体管的第二极电连接，所述第六晶体管的第二极与所述第二电压端电连接。
  17. 如权利要求8所述的驱动电路，其中，所述第一控制节点控制电路包括第七晶体管；所述第七晶体管的栅极与所述第二时钟信号端电连接，所述第七晶体管的第一极与所述输入端电连接，所述第七晶体管的第二极与所述第一控制节点电连接。
  18. 如权利要求2所述的驱动电路，其中，所述第三节点控制电路包括第八晶体管和第三电容；所述第八晶体管的栅极与所述第一控制节点电连接，所述第八晶体管的第一极与第一时钟信号端电连接，所述第八晶体管的第二极与所述第三节点电连接；
    所述第三电容的第一端与所述第一控制节点电连接，所述第三电容的第二端与第三节点电连接；
    所述第二节点控制电路还包括第四电容；
    所述第四电容的第一端与第二控制节点电连接，所述第四电容的第二端与所述第二节点电连接。
  19. 如权利要求5所述的驱动电路，其中，所述第三节点控制电路还包括第九晶体管；
    所述第九晶体管的栅极与所述第二节点电连接，所述第九晶体管的第一极所述第三节点电连接，所述第九晶体管的第二极与所述第二电压端电连接。
  20. 如权利要求3所述的驱动电路，其中，所述第一节点控制电路包括第十晶体管；
    所述第十晶体管的栅极与所述第一时钟信号端电连接，所述第十晶体管的第一极与所述第四节点电连接，所述第十晶体管的第二极与所述第一节点电连接。
  21. 如权利要求4所述的驱动电路，其中，所述第一节点控制电路包括第十一晶体管；
    所述第十一晶体管的栅极与所述第二节点电连接，所述第十一晶体管的第一极与第一节点电连接，所述第十一晶体管的第二极与第二电压端电连接。
  22. 如权利要求9所述的驱动电路，其中，所述第二控制节点控制电路包括第十二晶体管、第十三晶体管和第十四晶体管；
    所述第十二晶体管的栅极与所述复位端电连接，所述第十二晶体管的第一极与所述第二控制节点电连接，所述第十二晶体管的第二极与所述第三电压端电连接；
    所述第十三晶体管的栅极与所述第二时钟信号端电连接，所述第十三晶体管的第一极与第三电压端电连接，所述第十三晶体管的第二极与第二控制节点电连接；
    所述第十四晶体管的栅极与第一控制节点电连接，所述第十四晶体管的第一极与第二时钟信号端电连接，所述第十四晶体管的第二极与第二控制节点电连接。
  23. 如权利要求10所述的驱动电路，其中，所述第一输出电路包括第一输出晶体管；所述第一输出晶体管的栅极与所述第一节点电连接，所述第一输出晶体管的第一极与第三电压端或输出时钟信号端电连接，所述第一输出晶体管的第二极与所述驱动信号输出端电连接。
  24. 如权利要求6所述的驱动电路，其中，所述第二输出电路包括第二输出晶体管，所述第三输出电路包括第三输出晶体管；
    所述第二输出晶体管的栅极与所述第二节点电连接，所述第二输出晶体 管的第一极与所述驱动信号输出端电连接，所述第二输出晶体管的第二极与第五节点电连接；
    所述第三输出晶体管的栅极与所述第二节点电连接，所述第三输出晶体管的第一极与所述第五节点电连接，所述第三输出晶体管的第二极与第二电压端电连接。
  25. 一种驱动方法，应用于如权利要求1至24中任一权利要求所述的驱动电路，显示周期包括先后设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
    在第一阶段包括的至少部分时间段，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通；第一节点控制电路控制第一节点的电位为关断电压；
    在第二阶段包括的部分时间段，第一控制节点控制电路控制第一控制节点的电位为开启电压，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通；
    在第二阶段包括的另一部分时间段，第一控制节点控制电路控制第一控制节点的电位为开启电压，第二控制节点控制电路控制第二控制节点的电位为关断电压，第二节点控制电路控制第二节点的电位为关断电压，第一节点控制电路控制第一节点的电位为开启电压；
    在第三阶段包括的部分时间段，第一控制节点控制电路控制第一控制节点的电位为关断电压，第二控制节点控制电路控制第二控制节点的电位为开启电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通，第一节点控制电路控制第一节点的电位为开启电压；
    在第三阶段包括的另一部分时间段，第二控制节点控制电路控制第二控制节点的电位为开启电压，第一节点控制电路控制第一节点的电位为关断电压，第二节点控制电路在第二控制节点的电位的控制下，控制第二节点与第一时钟信号端之间连通。
  26. 一种显示装置，包括如权利要求1至24中任一权利要求所述的驱动电路。
PCT/CN2022/135249 2022-11-30 2022-11-30 驱动电路、驱动方法和显示装置 WO2024113203A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/135249 WO2024113203A1 (zh) 2022-11-30 2022-11-30 驱动电路、驱动方法和显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/135249 WO2024113203A1 (zh) 2022-11-30 2022-11-30 驱动电路、驱动方法和显示装置

Publications (1)

Publication Number Publication Date
WO2024113203A1 true WO2024113203A1 (zh) 2024-06-06

Family

ID=91322634

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/135249 WO2024113203A1 (zh) 2022-11-30 2022-11-30 驱动电路、驱动方法和显示装置

Country Status (1)

Country Link
WO (1) WO2024113203A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282287A (zh) * 2014-10-31 2015-01-14 合肥鑫晟光电科技有限公司 一种goa单元及驱动方法、goa电路和显示装置
CN111445832A (zh) * 2020-05-07 2020-07-24 合肥京东方卓印科技有限公司 移位寄存单元、信号生成单元电路、驱动方法和显示装置
CN113421528A (zh) * 2021-06-22 2021-09-21 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN113889022A (zh) * 2021-10-27 2022-01-04 合肥维信诺科技有限公司 移位寄存器、显示面板和显示装置
CN114842900A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN114945969A (zh) * 2020-10-23 2022-08-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、驱动电路和显示装置
CN115019731A (zh) * 2022-06-17 2022-09-06 合肥京东方卓印科技有限公司 驱动电路、驱动方法、驱动模组和显示装置
US20220343841A1 (en) * 2020-05-28 2022-10-27 Boe Technology Group Co., Ltd. Signal generation circuit, signal generation method, signal generation module and display device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282287A (zh) * 2014-10-31 2015-01-14 合肥鑫晟光电科技有限公司 一种goa单元及驱动方法、goa电路和显示装置
CN111445832A (zh) * 2020-05-07 2020-07-24 合肥京东方卓印科技有限公司 移位寄存单元、信号生成单元电路、驱动方法和显示装置
US20220343841A1 (en) * 2020-05-28 2022-10-27 Boe Technology Group Co., Ltd. Signal generation circuit, signal generation method, signal generation module and display device
CN114945969A (zh) * 2020-10-23 2022-08-26 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、驱动电路和显示装置
CN114842900A (zh) * 2021-02-01 2022-08-02 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示基板和显示装置
CN113421528A (zh) * 2021-06-22 2021-09-21 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN113889022A (zh) * 2021-10-27 2022-01-04 合肥维信诺科技有限公司 移位寄存器、显示面板和显示装置
CN115019731A (zh) * 2022-06-17 2022-09-06 合肥京东方卓印科技有限公司 驱动电路、驱动方法、驱动模组和显示装置

Similar Documents

Publication Publication Date Title
US11735119B2 (en) Shift register unit, gate driving circuit and control method thereof and display apparatus
KR102643142B1 (ko) 스캔 구동부 및 이를 포함하는 표시 장치
CN108648718B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11081061B2 (en) Shift register, gate driving circuit, display device and gate driving method
WO2023005661A1 (zh) 像素电路、驱动方法和显示装置
US20200265877A1 (en) Shift register, driving method thereof, gate driving circuit and display device
US20170061874A1 (en) Stage circuit and scan driver using the same
CN107481676B (zh) 一种像素电路的驱动方法、显示面板以及显示装置
KR20180096843A (ko) 스테이지 회로 및 이를 이용한 주사 구동부
CN103299546B (zh) 移位寄存器
CN112802422B (zh) 移位寄存器、栅极驱动电路和显示面板
WO2019037457A1 (zh) 一种移位寄存器、其驱动方法、驱动控制电路及显示装置
US20230306911A1 (en) Pixel circuit for threshold compensation, driving method thereof and display device for providing signals
US11663955B2 (en) Pixel circuit, drive method thereof, display substrate, and display device
CN110264948B (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US11100851B2 (en) Pixel circuit and driving method thereof, display device
CN112820234A (zh) 一种移位寄存电路和显示装置
US11587512B2 (en) Display panel and display device
CN114023264B (zh) 驱动电路、驱动模组、驱动方法和显示装置
US11967278B2 (en) Shift register, driving circuit and display substrate
US10783822B2 (en) Transfer circuit, shift register, gate driver, display panel, and flexible substrate
WO2024113203A1 (zh) 驱动电路、驱动方法和显示装置
US20190221164A1 (en) Transfer circuit, shift register, gate driver, display panel, and flexible substrate
CN115346472A (zh) 栅极驱动器和包括该栅极驱动器的电致发光显示设备
CN107909958B (zh) Goa电路单元、goa电路及显示面板