WO2021103535A1 - 存储器、存储器的衬底结构及其制备方法 - Google Patents

存储器、存储器的衬底结构及其制备方法 Download PDF

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WO2021103535A1
WO2021103535A1 PCT/CN2020/099985 CN2020099985W WO2021103535A1 WO 2021103535 A1 WO2021103535 A1 WO 2021103535A1 CN 2020099985 W CN2020099985 W CN 2020099985W WO 2021103535 A1 WO2021103535 A1 WO 2021103535A1
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mask layer
sacrificial
substrate
substrate structure
layer
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PCT/CN2020/099985
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English (en)
French (fr)
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周震
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长鑫存储技术有限公司
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Priority to EP20891550.4A priority Critical patent/EP3971974B1/en
Publication of WO2021103535A1 publication Critical patent/WO2021103535A1/zh
Priority to US17/396,690 priority patent/US12014932B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular to a method for preparing a memory, a substrate structure of the memory, and a substrate structure of the memory.
  • the memory includes a substrate structure and a capacitor structure on the substrate structure.
  • the bottom is etched to form an active area.
  • the stripe pattern is often difficult to break, making it difficult to form an active area on the substrate.
  • the purpose of the present disclosure is to provide a memory, a substrate structure of the memory, and a preparation method of the substrate structure of the memory.
  • a method for preparing a substrate structure of a memory including:
  • first mask layer Forming a first mask layer on the surface of the substrate, and a plurality of strip-shaped patterns distributed at intervals are formed in the first mask layer, and each of the strip-shaped patterns extends along the same direction;
  • Each of the sacrificial parts is removed, and the second medium in the gap is retained to form a second mask layer.
  • the regions of the second mask layer corresponding to each of the sacrificial parts are formed to expose the strips.
  • first mask layer and the second mask layer as masks, etch into the substrate layer by layer, and transfer the strip pattern and the through hole pattern into the substrate , To form a plurality of active areas arranged in an array.
  • patterning the first dielectric layer to form a plurality of sacrifice parts distributed at intervals includes:
  • a plurality of second through holes are formed on the first dielectric layer, and the plurality of second through holes are distributed in an array; the first through holes and the second through holes are in the first direction and perpendicular to the The first direction and the second direction are staggered. In the first direction and the second direction, any one of the first through holes and the adjacent second through holes are on the substrate The orthographic projections are touching or overlapping;
  • the portion of the first dielectric layer located between any one of the first through holes and the adjacent first through holes constitutes the sacrificial portion, and the third direction is opposite to the first
  • the deviation angle of the direction is ⁇ /4.
  • the cross-sectional shapes of the first through hole and the second through hole are the same.
  • both the first through hole and the second through hole are circular holes.
  • the diameter of the first through hole and the second through hole are the same.
  • removing each of the sacrificial parts and retaining the second medium in the gap includes:
  • the sacrificial portion is etched to form a second mask layer, and the area of the second mask layer corresponding to each sacrificial portion is formed with a through hole pattern exposing the stripe pattern.
  • the etching rate of the second medium is lower than the etching rate of the sacrificial portion, and etching the sacrificial portion includes:
  • the sacrificial portion and the second medium are etched to form a second mask layer, and the second mask layer corresponds to each of the sacrificial portions and forms through holes exposing the strip pattern Graphics.
  • the second dielectric is silicon oxide
  • the material of the sacrificial part is silicon nitride
  • etching the sacrificial part and the second medium includes:
  • Phosphoric acid is used to etch the sacrificial part and the second medium to form a second mask layer.
  • the second mask layer corresponds to each of the sacrificial parts and forms exposing the stripe patterns. Through hole pattern.
  • the second dielectric is silicon nitride
  • the material of the sacrificial part is silicon oxide
  • etching the sacrificial part and the second medium includes:
  • the sacrificial part and the second medium are etched with hydrofluoric acid to form a second mask layer, and the area of the second mask layer corresponding to each sacrificial part is formed to expose the strips Graphical through-hole pattern.
  • etching into the substrate layer by layer includes:
  • the substrate is etched using the first mask layer in which the stripe pattern is interrupted as a mask, and the stripe pattern and the through hole pattern are transferred to the substrate to A plurality of active regions arranged in an array are formed.
  • the distance between any two adjacent sacrificial portions is greater than the maximum dimension of any sacrificial portion in a direction parallel to the substrate.
  • filling a gap between the sacrificial parts with a second medium includes:
  • the part of the second dielectric layer outside the gap is removed.
  • removing the part of the second dielectric layer outside the gap includes:
  • the part of the second dielectric layer outside the gap is removed by a chemical mechanical polishing process.
  • a substrate structure of a memory is provided, which is prepared by the method for preparing a substrate structure of a memory as described in any one of the above.
  • a memory including the substrate structure of the memory described in any one of the above.
  • the memory, the substrate structure of the memory, and the preparation method of the substrate structure of the memory of the present disclosure form the second mask layer by removing each sacrificial part and retaining the second medium filled in the gap between the sacrificial parts. Since each sacrificial portion is covered with the stripe pattern, the area corresponding to each sacrificial portion of the formed second mask layer is formed with through holes exposing the stripe pattern.
  • the first mask layer and the second mask layer are used as The mask can conveniently transfer the strip pattern and the through hole pattern into the substrate, so that a plurality of active regions arranged in an array can be conveniently formed.
  • FIG. 1 schematically shows a flowchart of a method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a schematic diagram after completion of step S110 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a flowchart of step S130 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure
  • FIG. 4 schematically shows a schematic diagram after step S1301 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure is completed;
  • FIG. 5 schematically shows a schematic diagram after step S1302 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure is completed;
  • FIG. 6 schematically shows a schematic diagram of a first through hole, a second through hole, and a sacrificial part in a method for manufacturing a substrate structure of a memory in an exemplary embodiment of the present disclosure
  • FIG. 7 schematically shows a schematic diagram after step S140 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure is completed;
  • FIG. 8 schematically shows a schematic diagram after completion of step S150 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure
  • FIG. 9 schematically shows a schematic diagram after step S160 in the method for preparing a substrate structure of a memory in an exemplary embodiment of the present disclosure is completed.
  • This exemplary embodiment first proposes a method for preparing a substrate structure of a memory.
  • the method for preparing a substrate structure of the memory may include step S100 to step S160, wherein:
  • Step S100 providing a substrate.
  • Step S110 A first mask layer is formed on the surface of the substrate. A plurality of strip-shaped patterns distributed at intervals are formed in the first mask layer, and each strip-shaped pattern extends along the same direction.
  • Step S120 forming a first dielectric layer covering the first mask layer.
  • Step S130 patterning the first dielectric layer to form a plurality of sacrificial parts distributed at intervals, and each sacrificial part covers the striped pattern.
  • Step S140 filling the gap between the sacrificial parts with a second medium.
  • Step S150 removing each sacrificial portion, and leaving the second medium in the gap to form a second mask layer, and the area of the second mask layer corresponding to each sacrificial portion forms a through hole pattern exposing a stripe pattern.
  • Step S160 using the first mask layer and the second mask layer as masks, etch into the substrate layer by layer, and transfer the strip pattern and the through hole pattern into the substrate to form a plurality of arrays arranged Active area.
  • each sacrificial portion is removed and the second medium filled in the gap position between the sacrificial portions is retained to form the second mask layer. Since each sacrificial portion is covered with the stripe pattern, the area corresponding to each sacrificial portion of the formed second mask layer is formed with through holes exposing the stripe pattern.
  • the first mask layer and the second mask layer are used as The mask can conveniently transfer the strip pattern and the through hole pattern into the substrate to form a plurality of active regions arranged in an array.
  • step S100 a substrate is provided.
  • the substrate may be a single crystal silicon substrate, a single crystal germanium substrate, or a silicon-on-insulator (SOI) substrate, but this example embodiment does not specifically limit this.
  • SOI silicon-on-insulator
  • step S110 a first mask layer is formed on the surface of the substrate, and a plurality of strip-shaped patterns distributed at intervals are formed in the first mask layer, and each strip-shaped pattern extends along the same direction.
  • the material of the first mask layer may be silicon oxide, but is not limited thereto.
  • the distance between any two adjacent strip patterns 101 can be the same, but is not limited to this, and can also be different.
  • the strip patterns 101 are all raised structures.
  • forming the first mask layer on the surface of the substrate 1 may include: forming a first material layer on the surface of the substrate 1; and patterning the first material layer to form the first mask layer.
  • the first material layer can be prepared by chemical vapor deposition, of course, it can also be prepared by atomic layer deposition, but it is not limited to this, and can also be prepared by other methods.
  • the patterning process may be a self-aligned double patterning (SADP) technology, of course, it may also be a self-aligned quadruple patterning (SAQP) technology, but this example embodiment does not specifically limit this.
  • SADP self-aligned double patterning
  • SAQP self-aligned quadruple patterning
  • step S120 a first dielectric layer covering the first mask layer is formed.
  • the first dielectric layer can be prepared by chemical vapor deposition, of course, can also be prepared by atomic layer deposition, but it is not limited to this, and can also be prepared by other methods.
  • the material of the first dielectric layer may be silicon nitride, of course, it may also be silicon oxynitride (SiON), silicon carbon nitride (SiCN), etc., but it is not limited to this, and may also be silicon oxide. This exemplary embodiment does not specifically limit the thickness of the first dielectric layer.
  • step S130 the first dielectric layer is patterned to form a plurality of sacrificial parts distributed at intervals, and each sacrificial part covers the striped pattern.
  • patterning the first dielectric layer to form a plurality of sacrifice parts distributed at intervals may include step S1301 and step S1302, wherein:
  • step S1301 a plurality of first through holes are formed on the first dielectric layer, and the plurality of first through holes are distributed in an array.
  • the present disclosure may form a plurality of first through holes on the first medium through a photolithography process.
  • the photolithography process includes: forming a photoresist layer on the first dielectric layer; exposing and developing the photoresist layer to form multiple channels; using the photoresist layer with multiple channels as a mask.
  • the film is etched on the first dielectric layer to form a first through hole in a region corresponding to the channel on the first dielectric layer.
  • the first through hole 201 may be a circular hole, of course, it may also be an elliptical hole, but it is not limited to this, and may also be a square hole or the like.
  • step S1302 a plurality of second through holes are formed on the first dielectric layer, and the plurality of second through holes are distributed in an array.
  • the second through hole 202 may be a circular hole, of course, it may also be an elliptical hole, but it is not limited to this, and may also be a square hole or the like.
  • the cross-sectional shape of the second through hole 202 and the first through hole 201 may be the same, for example, the second through hole 202 and the first through hole 201 are both circular holes.
  • the size of the first through hole 201 and the second through hole 202 can be the same, of course, they can also be different, which is not particularly limited in the present disclosure.
  • the first through holes 201 and the second through holes 202 are staggered in the first direction, that is, in the first direction, any first through hole 201 is connected to a second through hole.
  • the holes 202 are adjacent.
  • the first direction is the X direction.
  • the first direction is parallel to the substrate 1. Further, in the first direction, the orthographic projections of any one of the first through holes 201 and the adjacent second through holes 202 on the substrate 1 all contact or overlap.
  • the orthographic projection of any first through hole 201 and the adjacent second through hole 202 on the substrate 1 All contact or overlap, that is, the distance between the axis of any first through hole 201 and the axis of the adjacent second through hole 202 is less than or equal to the sum of the radius of the first through hole 201 and the radius of the second through hole 202 .
  • the first direction is different from the extending direction of the strip pattern 101.
  • the first through holes 201 and the second through holes 202 are staggered in the second direction, that is, in the second direction, any first through hole 201 is connected to a second through hole.
  • the holes 202 are adjacent.
  • the second direction is the Y direction.
  • the second direction is parallel to the substrate 1 and perpendicular to the first direction. Further, in the second direction, the orthographic projections of any one of the first through holes 201 and the adjacent second through holes 202 on the substrate 1 all contact or overlap.
  • the orthographic projection of any first through hole 201 and the adjacent second through hole 202 on the substrate 1 All contact or overlap, that is, the distance between the axis of any first through hole 201 and the axis of the adjacent second through hole 202 is less than or equal to the sum of the radius of the first through hole 201 and the radius of the second through hole 202 .
  • the second direction is different from the extending direction of the strip pattern 101.
  • the portion of the first dielectric layer 2 located between any first through hole 201 and the adjacent first through hole 201 constitutes the aforementioned sacrificial portion 203.
  • the third direction is the M direction.
  • the third direction is parallel to the substrate 1, and the deviation angle of the third direction relative to the first direction is ⁇ /4, that is, the included angle between the third direction and the first direction is ⁇ /4.
  • the diameter of the first through hole 201 and the second through hole 202 are both larger than the sacrificial portion 203 in a direction parallel to the substrate 1.
  • the third direction is different from the extending direction of the strip pattern 101.
  • step S140 the gap between the sacrificial parts is filled with a second medium.
  • the etching rate of the second medium 3 may be lower than the etching rate of the sacrificial portion 203.
  • the material of the second medium 3 may be silicon oxide.
  • the material of the second medium 3 may also be BPSG (borophosphosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), etc., but not limited to It can also be silicon nitride.
  • filling the second dielectric 3 into the gap between the sacrificial parts 203 may include: forming a second dielectric layer covering the sacrificial part 203 and the gap between the sacrificial parts 203; and removing the part of the second dielectric layer located outside the gap.
  • the second dielectric layer can be prepared by chemical vapor deposition, of course, it can also be prepared by atomic layer deposition, but it is not limited to this, and can also be prepared by other methods. Wherein, in the present disclosure, the part of the second dielectric layer located outside the gap can be removed by grinding. Wherein, the polishing may be chemical mechanical polishing. Taking the portion of the first dielectric layer 2 between any one of the first through holes 201 and the adjacent first through holes 201 to constitute the sacrificial portion 203 as an example, the second dielectric 3 can fill each of the first through holes 201 and each Inside the second through hole 202.
  • step S150 each sacrificial portion is removed, and the second medium in the gap is retained to form a second mask layer.
  • the regions of the second mask layer corresponding to each sacrificial portion are formed with through hole patterns exposing the stripe patterns.
  • the sacrificial portion 203 may be etched to form the above-mentioned second mask layer. Further, in the present disclosure, the sacrificial portion 203 and the second medium 3 may be etched to form the above-mentioned second mask layer. The etching may adopt a dry etching process, of course, a wet etching process may also be adopted.
  • the second dielectric 3 is silicon oxide
  • the material of the sacrificial part 203 is silicon nitride.
  • phosphoric acid may be used to etch the sacrificial part 203 and the second dielectric 3 to form a second mask.
  • the area corresponding to each sacrificial portion 203 is formed with a through hole pattern exposing the strip pattern 101.
  • the second dielectric 3 is silicon nitride, and the material of the sacrificial portion 203 is silicon oxide.
  • the present disclosure may use hydrofluoric acid to etch the sacrificial portion 203 and the second dielectric 3 to form a Two mask layers, the second mask layer corresponding to each sacrificial portion 203 is formed with a through hole pattern exposing the stripe pattern 101.
  • the size of the through hole pattern in the direction perpendicular to the extending direction of the strip pattern 101 is larger than the width of the strip pattern 101, that is, the projection of the through hole pattern on the substrate 1 covers the strip pattern 101 on the substrate 1. Projection.
  • step S160 the first mask layer and the second mask layer are used as masks to etch into the substrate layer by layer, and the strip patterns and through hole patterns are transferred to the substrate to form a plurality of array rows.
  • the active area of the cloth is not limited to the first mask layer and the second mask layer.
  • using the first mask layer and the second mask layer as masks to etch into the substrate layer by layer may include: etching the first mask layer using the second mask layer as a mask, The through hole pattern is transferred to the first mask layer to break the strip pattern; the first mask layer with the strip pattern broken is used as a mask to etch the substrate, and the strip pattern and the through hole pattern Transfer to the substrate to form a plurality of active regions arranged in an array.
  • the etching can be performed by a dry etching process, but is not limited to this, and an etching process can also be used.
  • a plurality of active regions 102 are distributed at intervals.
  • This example embodiment also provides a substrate structure of a memory.
  • the substrate structure of the memory can be prepared by the method for preparing the substrate structure of the memory described in any of the above embodiments, and therefore, it has the same beneficial effects, which will not be repeated here.
  • This example embodiment also provides a memory.
  • the memory includes the substrate structure of the memory described in the above embodiments.
  • the memory may also include a capacitor structure, etc., but the present disclosure does not specifically limit this. Since the substrate structure included in the memory of this exemplary embodiment is the same as the substrate structure of the above-mentioned embodiment of the substrate structure of the memory, it has the same beneficial effects, which will not be repeated here.

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Abstract

一种存储器、存储器的衬底结构及存储器的衬底结构的制备方法，该制备方法包括：提供衬底(1)；在衬底(1)上形成包括多个间隔分布的条状图形(101)的第一掩膜层，各条状图形(101)均沿着同一方向延伸；形成覆盖第一掩膜层的第一介质层(2)；在第一介质层(2)上形成多个间隔分布的牺牲部(203)，各牺牲部(203)均覆盖于条状图形(101)；向牺牲部(203)之间的间隙填充第二介质(3)；去除各牺牲部(203)，并保留间隙内的第二介质(3)，以形成第二掩膜层，第二掩膜层对应于各牺牲部(203)的区域均形成暴露条状图形(101)的通孔图形；以第一掩膜层和第二掩膜层为掩膜，逐层刻蚀至衬底(1)内，以形成多个阵列排布的有源区。

Description

存储器、存储器的衬底结构及其制备方法
相关申请的交叉引用
本申请要求于2019年11月26日提交的申请号为201911175485.7、名称为“存储器、存储器的衬底结构及其制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种存储器、存储器的衬底结构及存储器的衬底结构的制备方法。
背景技术
随着集成电路技术的快速发展，存储器引起了人们越来越多的关注。
存储器包括衬底结构以及位于衬底结构上的电容器结构。在制备存储器的衬底结构的过程中，需要先在衬底上形成多个条状图形，接着需要打断该条状图形，以形成掩膜层，并以此掩膜层为掩膜对衬底进行刻蚀，以形成有源区。然而，该条状图形常常难以打断，导致衬底上难以形成有源区。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种存储器、存储器的衬底结构及存储器的衬底结构的制备方法。
根据本公开的一个方面，提供一种存储器的衬底结构的制备方法，包括：
提供衬底；
在所述衬底的表面形成第一掩膜层，所述第一掩膜层内形成有多个间隔分布的条状图形，各所述条状图形均沿着同一方向延伸；
形成覆盖所述第一掩膜层的第一介质层；
对所述第一介质层进行图案化，以形成多个间隔分布的牺牲部，各所述牺牲部均覆盖于所述条状图形；
向所述牺牲部之间的间隙填充第二介质；
去除各所述牺牲部，并保留所述间隙内的所述第二介质，以形成第二掩膜层，所述 第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形；
以所述第一掩膜层和所述第二掩膜层为掩膜，逐层刻蚀至所述衬底内，将所述条状图形和所述通孔图形传递至所述衬底内，以形成多个呈阵列排布的有源区。
在本公开的一种示例性实施例中，对所述第一介质层进行图案化，以形成多个间隔分布的牺牲部包括：
在所述第一介质层上形成多个第一通孔，多个所述第一通孔呈阵列分布；
在所述第一介质层上形成多个第二通孔，多个所述第二通孔呈阵列分布；所述第一通孔和所述第二通孔在第一方向和垂直于所述第一方向的第二方向上均交错排列，在所述第一方向和所述第二方向上，任一所述第一通孔与相邻的所述第二通孔在所述衬底上的正投影均接触或重叠；
在第三方向上，所述第一介质层位于任一所述第一通孔与相邻的所述第一通孔之间的部分构成所述牺牲部，所述第三方向相对所述第一方向的偏离角度为π/4。
在本公开的一种示例性实施例中，所述第一通孔和所述第二通孔的横截面的形状相同。
在本公开的一种示例性实施例中，所述第一通孔和所述第二通孔均为圆形孔。
在本公开的一种示例性实施例中，所述第一通孔和所述第二通孔的直径相同。
在本公开的一种示例性实施例中，去除各所述牺牲部，并保留所述间隙内的所述第二介质包括：
对所述牺牲部进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
在本公开的一种示例性实施例中，所述第二介质的刻蚀速率小于所述牺牲部的刻蚀速率，对所述牺牲部进行刻蚀包括：
对所述牺牲部和所述第二介质进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
在本公开的一种示例性实施例中，所述第二介质为氧化硅，所述牺牲部的材料为氮化硅。
在本公开的一种示例性实施例中，对所述牺牲部和所述第二介质进行刻蚀包括：
采用磷酸对所述牺牲部和所述第二介质进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
在本公开的一种示例性实施例中，所述第二介质为氮化硅，所述牺牲部的材料为氧化硅。
在本公开的一种示例性实施例中，对所述牺牲部和所述第二介质进行刻蚀包括：
采用氢氟酸对所述牺牲部和所述第二介质进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
在本公开的一种示例性实施例中，以所述第一掩膜层和所述第二掩膜层为掩膜，逐层刻蚀至所述衬底内包括：
以所述第二掩膜层为掩膜对所述第一掩膜层进行刻蚀，将所述通孔图形传递至所述第一掩膜层，以打断所述条状图形；
以所述条状图形被打断的所述第一掩膜层为掩膜对所述衬底进行刻蚀，将所述条状图形和所述通孔图形传递至所述衬底内，以形成多个呈阵列排布的有源区。
在本公开的一种示例性实施例中，任意相邻的两个所述牺牲部之间的距离大于任一所述牺牲部在平行于所述衬底的方向上的最大尺寸。
在本公开的一种示例性实施例中，向所述牺牲部之间的间隙填充第二介质包括：
形成覆盖所述牺牲部以及所述牺牲部之间的间隙的第二介质层；
去除所述第二介质层位于所述间隙以外的部分。
在本公开的一种示例性实施例中，去除所述第二介质层位于所述间隙以外的部分包括：
通过化学机械研磨工艺去除所述第二介质层位于所述间隙以外的部分。
根据本公开的一个方面，提供一种存储器的衬底结构，由上述任意一项所述的存储器的衬底结构的制备方法制备而成。
根据本公开的一个方面，提供一种存储器，包括上述任意一项所述的存储器的衬底结构。
本公开的存储器、存储器的衬底结构及存储器的衬底结构的制备方法，通过去除各牺牲部，并保留填充于牺牲部之间的间隙位置的第二介质，以形成第二掩膜层。由于各牺牲部均覆盖于条状图形，从而使形成的第二掩膜层对应于各牺牲部的区域均形成暴露条状图形的通孔，以第一掩膜层和第二掩膜层为掩膜，可以方便地将条状图形和通孔图形传递至衬底内，从而可以方便地形成多个呈阵列排布的有源区。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例， 并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出本公开示例性实施例中存储器的衬底结构的制备方法的流程图；
图2示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S110完成后的示意图；
图3示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S130的流程图；
图4示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S1301完成后的示意图；
图5示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S1302完成后的示意图；
图6示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中第一通孔、第二通孔以及牺牲部的示意图；
图7示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S140完成后的示意图；
图8示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S150完成后的示意图；
图9示意性示出本公开示例性实施例中存储器的衬底结构的制备方法中步骤S160完成后的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是 功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
用语“一个”、“一”以及“该”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本示例实施方式首先提出了一种存储器的衬底结构的制备方法，参照图1所示，该存储器的衬底结构的制备方法可以包括步骤S100至步骤S160，其中：
步骤S100、提供衬底。
步骤S110、在衬底的表面形成第一掩膜层，第一掩膜层内形成有多个间隔分布的条状图形，各条状图形均沿着同一方向延伸。
步骤S120、形成覆盖第一掩膜层的第一介质层。
步骤S130、对第一介质层进行图案化，以形成多个间隔分布的牺牲部，各牺牲部均覆盖于条状图形。
步骤S140、向牺牲部之间的间隙填充第二介质。
步骤S150、去除各牺牲部，并保留间隙内的第二介质，以形成第二掩膜层，第二掩膜层对应于各牺牲部的区域均形成暴露条状图形的通孔图形。
步骤S160、以第一掩膜层和第二掩膜层为掩膜，逐层刻蚀至衬底内，将条状图形和通孔图形传递至衬底内，以形成多个呈阵列排布的有源区。
本示例实施方式的存储器的衬底结构的制备方法，通过去除各牺牲部，并保留填充于牺牲部之间的间隙位置的第二介质，以形成第二掩膜层。由于各牺牲部均覆盖于条状图形，从而使形成的第二掩膜层对应于各牺牲部的区域均形成暴露条状图形的通孔，以第一掩膜层和第二掩膜层为掩膜，可以方便地将条状图形和通孔图形传递至衬底内，以形成多个呈阵列排布的有源区。
下面，将对本示例实施方式中的存储器的衬底结构的制备方法进行进一步的说明。
在步骤S100中，提供衬底。
该衬底可以为单晶硅衬底、单晶锗衬底或绝缘体上硅(SOI)衬底，但本示例实施方式对此不做特殊限定。
在步骤S110中，在衬底的表面形成第一掩膜层，第一掩膜层内形成有多个间隔分布的条状图形，各条状图形均沿着同一方向延伸。
参照图2所示，该第一掩膜层的材料可以为氧化硅，但不限于此。任意相邻的两个 条状图形101之间的距离可以相同，但不限于此，还可以不同。该条状图形101均为凸起结构。举例而言，在衬底1的表面形成第一掩膜层可以包括：在衬底1的表面形成第一材料层；对第一材料层进行图形化，以形成第一掩膜层。其中，该第一材料层可以通过化学气相沉积制备而成，当然，也可以通过原子层沉积制备而成，但不以此为限，还可以通过其它方式制备而成。该图形化工艺可以为自对准双图形化(SADP)技术，当然，也可以为自对准四次图形化(SAQP)技术，但本示例实施方式对此不做特殊限定。
在步骤S120中，形成覆盖第一掩膜层的第一介质层。
该第一介质层可以通过化学气相沉积制备而成，当然，也可以通过原子层沉积制备而成，但不以此为限，还可以通过其它方式制备而成。该第一介质层的材料可以为氮化硅，当然，也可以为氮氧化硅(SiON)、硅碳氮(SiCN)等，但不限于此，还可以为氧化硅。本示例实施方式对第一介质层的厚度不做具体限定。
在步骤S130中，对第一介质层进行图案化，以形成多个间隔分布的牺牲部，各牺牲部均覆盖于条状图形。
本公开可以利用光刻-蚀刻-光刻-蚀刻工艺对第一介质层进行图案化。具体地，参照图3所示，对第一介质层进行图案化以形成多个间隔分布的牺牲部可以包括步骤S1301和步骤S1302，其中：
步骤S1301、在第一介质层上形成多个第一通孔，多个第一通孔呈阵列分布。
本公开可以通过光刻工艺在第一介质上形成多个第一通孔。具体地，该光刻工艺包括：在第一介质层上形成光刻胶层；对光刻胶层进行曝光并显影，以形成多个通道；以形成有多个通道的光刻胶层为掩膜，对第一介质层进行刻蚀，以在第一介质层上对应于通道的区域形成第一通孔。参照图4所示，第一通孔201可以为圆形孔，当然，也可以为椭圆形孔，但不限于此，还可以方形孔等。
步骤S1302、在第一介质层上形成多个第二通孔，多个第二通孔呈阵列分布。
参照图5所示，第二通孔202可以为圆形孔，当然，也可以为椭圆形孔，但不限于此，还可以方形孔等。优选地，该第二通孔202和第一通孔201的横截面的形状可以相同，例如，且第二通孔202和第一通孔201均为圆形孔。其中，该第一通孔201和第二通孔202的尺寸可以相等，当然，也可以不同，本公开对此不做特殊限定。
参照图5和图6所示，该第一通孔201和第二通孔202在第一方向上交错排列，也就是在第一方向上，任一第一通孔201均与一第二通孔202相邻。该第一方向为X方向。该第一方向平行于衬底1。进一步地，在第一方向上，任一第一通孔201与相邻的第二通孔202在衬底1上的正投影均接触或重叠。以第一通孔201和第二通孔202均呈圆形孔为例，在第一方向上，任一第一通孔201与相邻的第二通孔202在衬底1上的正投影 均接触或重叠，即任一第一通孔201的轴线与相邻的第二通孔202的轴线之间的距离小于或等于第一通孔201的半径与第二通孔202的半径的和。此外，该第一方向与条状图形101的延伸方向不同。
参照图5和图6所示，该第一通孔201和第二通孔202在第二方向上交错排列，也就是在第二方向上，任一第一通孔201均与一第二通孔202相邻。该第二方向为Y方向。该第二方向平行于衬底1，且与第一方向垂直。进一步地，在第二方向上，任一第一通孔201与相邻的第二通孔202在衬底1上的正投影均接触或重叠。以第一通孔201和第二通孔202均呈圆形孔为例，在第二方向上，任一第一通孔201与相邻的第二通孔202在衬底1上的正投影均接触或重叠，即任一第一通孔201的轴线与相邻的第二通孔202的轴线之间的距离小于或等于第一通孔201的半径与第二通孔202的半径的和。此外，该第二方向与条状图形101的延伸方向不同。
参照图5和图6所示，在第三方向上，该第一介质层2位于任一第一通孔201与相邻的第一通孔201之间的部分构成上述的牺牲部203。该第三方向为M方向。该第三方向平行于衬底1，且第三方向相对第一方向的偏离角度为π/4，也就是第三方向与第一方向之间的夹角为π/4。此外，以第一通孔201和第二通孔202均为圆形孔为例，该第一通孔201和第二通孔202的直径均大于牺牲部203在平行于衬底1的方向上的最大尺寸。此外，该第三方向与条状图形101的延伸方向不同。
在步骤S140中，向牺牲部之间的间隙填充第二介质。
参照图6和图7所示，该第二介质3的刻蚀速率可以小于牺牲部203的刻蚀速率。该第二介质3的材料可以为氧化硅，当然，该第二介质3的材料还可以为BPSG(硼磷硅玻璃)、BSG(硼硅玻璃)、PSG(磷硅玻璃)等，但不限于此，还可以为氮化硅。举例而言，向牺牲部203之间的间隙填充第二介质3可以包括：形成覆盖牺牲部203以及牺牲部203之间的间隙的第二介质层；去除第二介质层位于间隙以外的部分。该第二介质层可以通过化学气相沉积制备而成，当然，也可以通过原子层沉积制备而成，但不以此为限，还可以通过其它方式制备而成。其中，本公开可以通过研磨去除第二介质层位于间隙以外的部分。其中，该研磨可以为化学机械研磨。以第一介质层2位于任一第一通孔201与相邻的第一通孔201之间的部分构成牺牲部203为例，该第二介质3可以填充该各第一通孔201和各第二通孔202内。
在步骤S150中，去除各牺牲部，并保留间隙内的第二介质，以形成第二掩膜层，第二掩膜层对应于各牺牲部的区域均形成暴露条状图形的通孔图形。
参照图8所示，本公开可以通过对牺牲部203进行刻蚀，以形成上述的第二掩膜层。进一步地，本公开可以通过对牺牲部203和第二介质3进行刻蚀，以形成上述的第二掩 膜层。该刻蚀可以采用干刻工艺，当然，也可以采用湿刻工艺。在一实施方式中，该第二介质3为氧化硅，该牺牲部203的材料为氮化硅，本公开可以采用磷酸对牺牲部203和第二介质3进行刻蚀，以形成第二掩膜层，第二掩膜层对应于各牺牲部203的区域均形成暴露条状图形101的通孔图形。在另一实施方式中，该第二介质3为氮化硅，该牺牲部203的材料为氧化硅，本公开可以采用氢氟酸对牺牲部203和第二介质3进行刻蚀，以形成第二掩膜层，第二掩膜层对应于各牺牲部203的区域均形成暴露条状图形101的通孔图形。此外，该通孔图形在垂直于条状图形101的延伸方向的方向上的尺寸大于条状图形101的宽度，即通孔图形在衬底1上的投影覆盖条状图形101在衬底1上的投影。
在步骤S160中，以第一掩膜层和第二掩膜层为掩膜，逐层刻蚀至衬底内，将条状图形和通孔图形传递至衬底内，以形成多个阵列排布的有源区。
举例而言，以第一掩膜层和第二掩膜层为掩膜，逐层刻蚀至衬底内可以包括：以第二掩膜层为掩膜对第一掩膜层进行刻蚀，将通孔图形传递至第一掩膜层，以打断条状图形；以条状图形被打断的第一掩膜层为掩膜对衬底进行刻蚀，将条状图形和通孔图形传递至衬底内，以形成多个阵列排布的有源区。其中，该刻蚀可以采用干刻工艺进行，但不限于此，还可以采用蚀刻工艺进行。此外，参照图9所示，多个有源区102间隔分布。
本示例实施方式还提供一种存储器的衬底结构。该存储器的衬底结构可以由上述任一实施方式所述的存储器的衬底结构的制备方法制备而成，因此，其具有相同的有益效果，在此不再赘述。
本示例实施方式还提供一种存储器。该存储器包括上述实施方式所述的存储器的衬底结构。当然，该存储器还可以包括电容器结构等，但本公开对此不做特殊限定。由于本示例实施方式的存储器所包括的衬底结构同上述存储器的衬底结构的实施方式中的衬底结构相同，因此，其具有相同的有益效果，在此不再赘述。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (17)

  1. 一种存储器的衬底结构的制备方法，包括：
    提供衬底；
    在所述衬底的表面形成第一掩膜层，所述第一掩膜层内形成有多个间隔分布的条状图形，各所述条状图形均沿着同一方向延伸；
    形成覆盖所述第一掩膜层的第一介质层；
    对所述第一介质层进行图案化，以形成多个间隔分布的牺牲部，各所述牺牲部均覆盖于所述条状图形；
    向所述牺牲部之间的间隙填充第二介质；
    去除各所述牺牲部，并保留所述间隙内的所述第二介质，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形；
    以所述第一掩膜层和所述第二掩膜层为掩膜，逐层刻蚀至所述衬底内，将所述条状图形和所述通孔图形传递至所述衬底内，以形成多个呈阵列排布的有源区。
  2. 根据权利要求1所述的存储器的衬底结构的制备方法，其中，对所述第一介质层进行图案化，以形成多个间隔分布的牺牲部包括：
    在所述第一介质层上形成多个第一通孔，多个所述第一通孔呈阵列分布；
    在所述第一介质层上形成多个第二通孔，多个所述第二通孔呈阵列分布；所述第一通孔和所述第二通孔在第一方向和垂直于所述第一方向的第二方向上均交错排列，在所述第一方向和所述第二方向上，任一所述第一通孔与相邻的所述第二通孔在所述衬底上的正投影均接触或重叠；
    在第三方向上，所述第一介质层位于任一所述第一通孔与相邻的所述第一通孔之间的部分构成所述牺牲部，所述第三方向相对所述第一方向的偏离角度为π/4。
  3. 根据权利要求2所述的存储器的衬底结构的制备方法，其中，所述第一通孔和所述第二通孔的横截面的形状相同。
  4. 根据权利要求3所述的存储器的衬底结构的制备方法，其中，所述第一通孔和所述第二通孔均为圆形孔。
  5. 根据权利要求4所述的存储器的衬底结构的制备方法，其中，所述第一通孔和所述第二通孔的直径相同。
  6. 根据权利要求1所述的存储器的衬底结构的制备方法，其中，去除各所述牺牲部，并保留所述间隙内的所述第二介质包括：
    对所述牺牲部进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
  7. 根据权利要求6所述的存储器的衬底结构的制备方法，其中，所述第二介质的刻蚀速率小于所述牺牲部的刻蚀速率，对所述牺牲部进行刻蚀包括：
    对所述牺牲部和所述第二介质进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
  8. 根据权利要求7所述的存储器的衬底结构的制备方法，其中，所述第二介质为氧化硅，所述牺牲部的材料为氮化硅。
  9. 根据权利要求8所述的存储器的衬底结构的制备方法，其中，对所述牺牲部和所述第二介质进行刻蚀包括：
    采用磷酸对所述牺牲部和所述第二介质进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
  10. 根据权利要求7所述的存储器的衬底结构的制备方法，其中，所述第二介质为氮化硅，所述牺牲部的材料为氧化硅。
  11. 根据权利要求10所述的存储器的衬底结构的制备方法，其中，对所述牺牲部和所述第二介质进行刻蚀包括：
    采用氢氟酸对所述牺牲部和所述第二介质进行刻蚀，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形。
  12. 根据权利要求1所述的存储器的衬底结构的制备方法，其中，以所述第一掩膜层和所述第二掩膜层为掩膜，逐层刻蚀至所述衬底内包括：
    以所述第二掩膜层为掩膜对所述第一掩膜层进行刻蚀，将所述通孔图形传递至所述第一掩膜层，以打断所述条状图形；
    以所述条状图形被打断的所述第一掩膜层为掩膜对所述衬底进行刻蚀，将所述条状图形和所述通孔图形传递至所述衬底内，以形成多个呈阵列排布的有源区。
  13. 根据权利要求1所述的存储器的衬底结构的制备方法，其中，任意相邻的两个所述牺牲部之间的距离大于任一所述牺牲部在平行于所述衬底的方向上的最大尺寸。
  14. 根据权利要求1所述的存储器的衬底结构的制备方法，其中，向所述牺牲部之间的间隙填充第二介质包括：
    形成覆盖所述牺牲部以及所述牺牲部之间的间隙的第二介质层；
    去除所述第二介质层位于所述间隙以外的部分。
  15. 根据权利要求14所述的存储器的衬底结构的制备方法，其中，去除所述第二介质层位于所述间隙以外的部分包括：
    通过化学机械研磨工艺去除所述第二介质层位于所述间隙以外的部分。
  16. 一种存储器的衬底结构，所述存储器的衬底结构的制备方法包括：
    提供衬底；
    在所述衬底的表面形成第一掩膜层，所述第一掩膜层内形成有多个间隔分布的条状图形，各所述条状图形均沿着同一方向延伸；
    形成覆盖所述第一掩膜层的第一介质层；
    对所述第一介质层进行图案化，以形成多个间隔分布的牺牲部，各所述牺牲部均覆盖于所述条状图形；
    向所述牺牲部之间的间隙填充第二介质；
    去除各所述牺牲部，并保留所述间隙内的所述第二介质，以形成第二掩膜层，所述第二掩膜层对应于各所述牺牲部的区域均形成暴露所述条状图形的通孔图形；
    以所述第一掩膜层和所述第二掩膜层为掩膜，逐层刻蚀至所述衬底内，将所述条状图形和所述通孔图形传递至所述衬底内，以形成多个呈阵列排布的有源区。
  17. 一种存储器，包括权利要求16所述的存储器的衬底结构。
PCT/CN2020/099985 2019-11-26 2020-07-02 存储器、存储器的衬底结构及其制备方法 WO2021103535A1 (zh)

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