WO2020253813A1 - 阵列基板及其制备方法、以及显示装置 - Google Patents

阵列基板及其制备方法、以及显示装置 Download PDF

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Publication number
WO2020253813A1
WO2020253813A1 PCT/CN2020/097025 CN2020097025W WO2020253813A1 WO 2020253813 A1 WO2020253813 A1 WO 2020253813A1 CN 2020097025 W CN2020097025 W CN 2020097025W WO 2020253813 A1 WO2020253813 A1 WO 2020253813A1
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Prior art keywords
line segments
substrate
line
layer
array substrate
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PCT/CN2020/097025
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English (en)
French (fr)
Inventor
刘宁
宋威
胡迎宾
王庆贺
张沣
刘冲冲
周斌
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/283,425 priority Critical patent/US20210343757A1/en
Publication of WO2020253813A1 publication Critical patent/WO2020253813A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device.
  • the length of the gate line and the data line and the number of the gate line and the data line in the display panel increase, resulting in the voltage drop of the gate line and the data line (due to the signal line
  • the inherent resistance causes a voltage difference between the signal input end of the signal line and the far end opposite to the signal input end to increase accordingly.
  • an array substrate including: a substrate; a plurality of gate lines and a plurality of data lines arranged on the substrate; the plurality of data lines all extend in a first direction, and the plurality of gate lines all extend in a second direction Extending, the first direction and the second direction are intersected; at least one of the plurality of data lines includes a plurality of first line segments and a plurality of second line segments extending along the first direction, and the plurality of first line segments and The plurality of second line segments are arranged alternately; the plurality of second line segments are arranged on the side of the plurality of gate lines close to the substrate, the plurality of first line segments are arranged on the side of the plurality of gate lines away from the substrate, and the plurality of first line segments There is no overlap between the orthographic projection of the line segment on the substrate and the orthographic projection of the multiple grid lines on the substrate; the insulating layer is arranged between the plurality of first line segments and the plurality of second line segments, and the insulating layer
  • the substrate has a plurality of sub-pixel regions; the array substrate further includes: a plurality of pixel circuits disposed on the substrate, each pixel circuit is disposed in a sub-pixel region, the pixel circuit and a gate line Electrically connected to a data line; wherein, the pixel circuit includes a first switching transistor, the first gate of the first switching transistor and the gate line have the same layer and the same material, and a plurality of first line segments are connected to the first source of the first switching transistor The electrode and the first drain electrode have the same layer and the same material.
  • the width of the second line segment is greater than the width of the first line segment.
  • the first switching transistor is a top-gate thin film transistor;
  • the array substrate further includes: a plurality of first metal light-shielding patterns arranged on the substrate; each first metal light-shielding pattern is arranged on a corresponding pixel circuit
  • the first switching transistor is close to the substrate side, and the orthographic projection of the first active layer of the first switching transistor in the pixel circuit on the substrate is within the range of the orthographic projection of the first metal shading pattern on the substrate;
  • the second line segment and the plurality of first metal shading patterns have the same layer and the same material, and are insulated from each other.
  • the insulating layer further includes a plurality of second vias, and one of the first source and the first drain of the first switching transistor is electrically connected to the first metal shading pattern through the at least one second via. connection.
  • the thickness of the second line segment is equal to the thickness of the first metal shading pattern.
  • the array substrate further includes: a plurality of pixel electrodes arranged on the substrate, each pixel electrode being arranged in a sub-pixel area; wherein the first source electrode of the first switching transistor is electrically connected to the data line , The first drain of the first switch transistor is electrically connected with the pixel electrode; the pixel electrode is arranged on the side of the first drain away from the substrate.
  • the array substrate further includes a plurality of light emitting devices arranged on the substrate, each light emitting device is arranged in a sub-pixel area, and the light emitting device is connected to a corresponding pixel circuit.
  • the pixel circuit further includes a driving transistor, the driving transistor is a top-gate thin film transistor;
  • the array substrate further includes: a plurality of second metal light-shielding patterns arranged on the substrate, and each second metal light-shielding pattern is arranged In a corresponding pixel circuit, the driving transistor is close to the substrate side, and the orthographic projection of the second active layer of the driving transistor is within the orthographic projection range of the second metal shading pattern on the substrate; wherein, a plurality of second line segments And a plurality of second metal shading patterns have the same layer and the same material, and are insulated from each other.
  • the array substrate further includes: a plurality of power lines, the plurality of power lines all extend along the first direction, the pixel circuit is electrically connected to one power line; one power line of the plurality of power lines includes Multiple third line segments and multiple fourth line segments extending in the direction, multiple third line segments and multiple fourth line segments are alternately arranged; the orthographic projection of multiple third line segments on the substrate and multiple grid lines on the substrate The orthographic projection on the upper part has no overlap; multiple third line segments and multiple first line segments have the same layer and the same material, and multiple fourth line segments have the same layer and same material as the multiple second line segments; the insulating layer also includes multiple third line segments. Along the first direction, every two adjacent third line segments are electrically connected to a fourth line segment located between the two through at least two third via holes.
  • the width of the fourth line segment is greater than the width of the third line segment.
  • the power line is electrically connected to the second source of the driving transistor in the pixel circuit, and the second drain of the driving transistor is electrically connected to the anode of the light emitting device.
  • the insulating layer includes a buffer layer and an interlayer dielectric layer stacked on the substrate.
  • a display device including any of the above-mentioned array substrates.
  • a method for preparing an array substrate including: providing a substrate; forming a plurality of second line segments on the substrate; and the plurality of second line segments are arranged in a second direction into a plurality of second line segments, each column
  • the second line segment includes a plurality of second line segments extending along the first direction and arranged at intervals; the first direction and the second direction are intersectingly arranged; a plurality of gate lines are formed on the substrate on which the plurality of second line segments are formed, and the plurality of gate lines
  • the lines extend in the second direction; then an insulating layer is formed on the substrate on which a plurality of second line segments are formed, and the insulating layer includes a plurality of first via holes; and a plurality of first lines are formed on the substrate on which the insulating layer is formed Segment, the orthographic projection of the multiple first line segments on the substrate does not overlap with the orthographic projection of the multiple grid lines on the substrate; the multiple first line segments are arranged in multiple rows of first line segments
  • the method for preparing the above-mentioned array substrate further includes: forming a plurality of pixel circuits on the substrate on which the plurality of second line segments are formed, and each pixel circuit is located in a sub-pixel area.
  • the pixel circuit includes a first switching transistor; wherein a plurality of gate lines and the first gate of the first switching transistor are formed by the same patterning process; a plurality of first line segments and the first source of the first switching transistor are The first drain is formed by the same patterning process.
  • the insulating layer includes a buffer layer and an interlayer dielectric layer; forming the insulating layer includes: forming a buffer film after forming a plurality of second line segments and before forming a plurality of gate lines; after forming a plurality of gate lines , Forming an interlayer dielectric film; patterning the interlayer dielectric film and the buffer film to form an interlayer dielectric layer and a buffer layer including a plurality of first via holes.
  • forming a plurality of second line segments includes: forming a plurality of second line segments and a plurality of first metal light-shielding patterns through a single patterning process, and the plurality of second line segments are insulated from the plurality of first metal light-shielding patterns;
  • the orthographic projection of the first active layer of the first switch transistor in the pixel circuit on the substrate is within the orthographic projection of the corresponding first metal shading pattern on the substrate.
  • the insulating layer includes a buffer layer and an interlayer dielectric layer; patterning the interlayer dielectric film and the buffer film to form the interlayer dielectric layer and the buffer layer including a plurality of first via holes includes: The dielectric film and the buffer film are patterned to form an interlayer dielectric layer and a buffer layer including a plurality of first via holes and a plurality of second via holes; one of the first source and the first drain of the first switching transistor The electrode is electrically connected to the first metal shading pattern through the second via hole.
  • FIG. 1 is a schematic top view of a display panel according to some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of a sub-pixel structure according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of another sub-pixel structure according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic top view of an array substrate according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic cross-sectional view of the array substrate of FIG. 4 along the B-B' direction;
  • FIG. 6 is a schematic top view of another array substrate according to some embodiments of the present disclosure.
  • Fig. 7 is a schematic cross-sectional view of the array substrate of Fig. 6 along the D-D' direction;
  • FIG. 8 is a schematic top view of an array substrate in the related art.
  • FIG. 9 is a schematic cross-sectional view of the array substrate in FIG. 8 along the direction C-C';
  • FIG. 10 is a schematic structural diagram of yet another array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic structural diagram of yet another array substrate according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic top view of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic cross-sectional view of the array substrate of FIG. 12 along the E-E' direction;
  • FIG. 14 is a schematic top view of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic cross-sectional view of the array substrate of FIG. 14 along the direction F-F';
  • FIG. 16 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure.
  • FIG. 17 is a schematic diagram of the structure of an array substrate during the manufacturing process according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • a and/or B include the following combinations: A only, B only, and a combination of A and B.
  • C and D with the same layer and the same material means that C and D are based on the same bearing surface, use the same film forming process to form a film layer for forming a specific pattern, and then use the same mask to form a layer structure through a patterning process.
  • the patterning process may include exposure, development and etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • connection may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “connected” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • the embodiments of the present disclosure provide a display device, which includes, but is not limited to, a mobile phone, a TV, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, a display panel, and the like.
  • a display device which includes, but is not limited to, a mobile phone, a TV, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, a display panel, and the like.
  • FIG. 1 is a schematic top view of a structure of a display panel according to some embodiments of the present disclosure. As shown in FIG. 1, the display panel 100 has a display area AA and a peripheral area S.
  • the specific location of the peripheral area S can be changed accordingly.
  • the peripheral area S surrounds the display area AA; or, the peripheral area S is located at one or more sides of the periphery of the display area AA, but does not surround the display area AA.
  • the display area AA is provided with multiple sub-pixels, and each sub-pixel is located in a sub-pixel area P.
  • the plurality of sub-pixels include at least a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel.
  • the first, second, and third colors are three primary colors (for example, red, green, and blue).
  • the above-mentioned multiple sub-pixels are arranged in an array as an example for illustration.
  • the sub-pixels arranged in a row along the horizontal direction X (for example, the row direction) are called the same row of sub-pixels
  • the sub-pixels arranged in a row along the vertical direction Y (for example, the column direction) are called the same column.
  • Sub-pixel the sub-pixels arranged in a row along the vertical direction Y (for example, the column direction) are called the same column.
  • the same row of sub-pixels can be connected to one gate line 1, and the same column of sub-pixels can be connected to one data line 2.
  • the above-mentioned display panel 100 may be, for example, a liquid crystal display panel or a self-luminous display panel.
  • the display panel 100 is a liquid crystal display panel.
  • the sub-pixel area P is provided with a pixel circuit 30, a pixel electrode 50 and a common electrode 60.
  • the pixel circuit 30 includes a first switching transistor.
  • the gate 301 of the first switching transistor is connected to the gate line 1
  • the source 302 is connected to the data line 2
  • the drain 303 is connected to the pixel electrode 50 (as shown in FIG. 2).
  • the gate 301 of the first switching transistor is connected to the gate line 1
  • the source 302 is connected to the pixel electrode 50
  • the drain 303 is connected to the data line 2.
  • the pixel electrode 50 and the common electrode 60 are configured to apply an electric field to the liquid crystal molecular layer 70 of the sub-pixel region P, so that the liquid crystal molecules in the liquid crystal molecular layer 70 are deflected under the action of the above electric field.
  • FIG. 2 only exemplarily shows the case where the common electrode 60 and the pixel electrode 50 are respectively disposed on both sides of the liquid crystal layer molecular layer 70.
  • the common electrode 60 and the pixel electrode 50 may also be disposed. On the same side of the liquid crystal molecule layer 70.
  • a color filter pattern is also provided in the sub-pixel area P.
  • the color of the color filter pattern located in the first color sub-pixel is the first color
  • the color of the color filter pattern located in the second color sub-pixel is the second color, which is located in the third color sub-pixel
  • the color of the color filter pattern is the third color
  • the display panel 100 is a self-luminous display panel.
  • the sub-pixel area P is provided with a pixel circuit 30 and a light emitting device 40 on the substrate 10.
  • the pixel circuit 30 at least includes a first switching transistor, a driving transistor, and a capacitor (Capacitor, C for short).
  • the pixel circuit 30 may be a pixel circuit with a 2T1C structure. That is, the pixel circuit 30 includes two Thin Film Transistors (TFTs for short) and a capacitor 33.
  • the two TFTs include a switching TFT (for example, the first switching transistor 31 in FIG. 6) and a driving TFT (for example, as shown in FIG. 6 in the drive transistor 32).
  • the structure of the pixel circuit 30 can also be other structures besides the 2T1C structure, such as 3T1C (that is, the pixel circuit 30 includes three TFTs and one capacitor), 5T1C (that is, the pixel circuit 30 includes five TFTs and one capacitor), or 7T1C (that is, the pixel circuit 30 includes seven TFTs and one capacitor), and so on. That is, the pixel circuit 30 may include at least two TFTs and at least one capacitor. The at least two TFTs include at least one switching TFT and one driving TFT.
  • the light emitting device 40 includes a cathode 45, an anode 41, and a light emitting function layer located between the cathode 45 and the anode 41.
  • the light-emitting function layer includes an organic light-emitting layer 43 and a hole transport layer located between the organic light-emitting layer 43 and the anode 41 42, and an electron transport layer 44 between the organic light emitting layer 43 and the cathode 45.
  • the light-emitting function layer further includes a hole injection layer disposed between the hole transport layer 42 and the anode 41 and/or an electron injection layer disposed between the electron transport layer 44 and the cathode 45.
  • FIG. 3 only exemplarily shows the structural schematic diagram of the self-luminous display panel, and does not show the electrical connection relationship between the pixel circuit 30 and the light emitting device 40.
  • the embodiment of the present disclosure does not limit the electrical connection mode between the pixel circuit 30 and the light emitting device 40, and the electrical connection mode suitable for the pixel circuit 30 and the light emitting device 40 can be selected according to the structure of the pixel circuit 30.
  • the light emitted by the light emitting device 40 is white light, and a color filter pattern is also provided in the sub-pixel area P.
  • the light emitting mode of the light emitting device 40 may be top emission (that is, the light emitted by the light emitting device 40 is emitted from a side away from the substrate 10) or bottom emission (that is, the light emitted by the light emitting device 40 is emitted through the substrate 10).
  • the light emitting device 40 is a top emission type light emitting device, and the color filter pattern is located on the side of the light emitting device 40 away from the pixel circuit 30.
  • the light emitting device 40 is a bottom emission type light emitting device, and the color filter pattern 60 is located on the side of the light emitting device 40 close to the pixel circuit 30.
  • the display panel includes an array substrate.
  • some embodiments of the present disclosure provide an array substrate 200 including: a substrate 10, a plurality of gate lines 1 and a plurality of data lines 2 arranged on the substrate 10.
  • the multiple data lines 2 all extend along the first direction Y
  • the multiple gate lines all extend along the second direction X
  • the first direction and the second direction are intersected.
  • the first direction and the second direction are perpendicular.
  • At least one data line 2 of the plurality of data lines 2 includes a plurality of first line segments 21 and a plurality of second line segments 22 extending along the first direction Y.
  • a line segment 21 and the plurality of second line segments 22 are alternately arranged.
  • each data line 2 includes a plurality of first line segments 21 and a plurality of second line segments 22 extending along the first direction Y, and the plurality of first line segments 21 and the plurality of second line segments 22 are alternately arranged .
  • the plurality of second line segments 22 in the data line 2 are arranged on the side of the plurality of gate lines 1 close to the substrate 10, and the plurality of first line segments 21 in the data line 2 are arranged On the side of the plurality of gate lines 1 away from the substrate 10, and the orthographic projection of the plurality of first line segments 21 on the substrate 10 does not overlap with the orthographic projection of the plurality of gate lines 1 on the substrate 10.
  • the orthographic projection of each second line segment 22 on the substrate 10 overlaps with the orthographic projection of a corresponding grid line 1 on the substrate 10.
  • the array substrate 200 further includes an insulating layer 16 disposed between the plurality of first line segments 21 and the plurality of second line segments 22.
  • the insulating layer 16 includes a plurality of first via holes 81. Along the first direction, every two adjacent first line segments 21 are electrically connected to a second line segment 22 located between the two first line segments 21 through at least two first vias 81.
  • every two adjacent first line segments 21 are electrically connected to a second line segment 22 located between the two first line segments 21 through two first vias 81 .
  • the two first vias 81 are respectively located on opposite sides of a corresponding gate line 1 along the first direction, and the orthographic projection of one of the first vias 81 on the substrate 10 and the two first line segments One of 21 overlaps with the orthographic projection of the second line segment 22 on the substrate 10, and the orthographic projection of the other first via 81 on the substrate 10 overlaps with the other first line segment 21 and the second line segment 22.
  • the orthographic projections on the substrate 10 overlap.
  • the insulating layer 16 includes a buffer layer 11 and an interlayer dielectric layer 15 stacked on the substrate 10.
  • the buffer layer 11 is disposed between the plurality of second line segments 22 and the plurality of gate lines 1 so that the plurality of second line segments 22 are insulated from the plurality of gate lines 1.
  • the buffer layer 11 may have a one-layer or multi-layer structure.
  • the buffer layer 11 is a one-layer structure, and the material of the buffer layer 11 may include, for example, silicon oxide (SiOx) or silicon nitride (SiNx).
  • the buffer layer 11 has a two-layer or two-layer structure, and the buffer layer 11 includes at least one silicon oxide layer and at least one silicon nitride layer.
  • the interlayer dielectric layer 15 is disposed between the plurality of gate lines 1 and the plurality of data lines 2.
  • the interlayer dielectric layer 15 may have a one-layer or multi-layer structure.
  • the interlayer dielectric layer 15 has a one-layer structure, and the material of the interlayer dielectric layer 15 may include, for example, silicon oxide (SiOx) or silicon nitride (SiNx).
  • the interlayer dielectric layer 15 has a structure of two or more layers, and the interlayer dielectric layer 15 includes at least one silicon oxide layer and at least one silicon nitride layer.
  • the length of the gate line 1 is longer, especially in a large-size display panel, the length of the gate line 1 is longer, resulting in a serious voltage drop problem.
  • the part of the isolation layer 16' covering the gate line 1 has a larger step than the part of the insulating layer 16' not covering the gate line 1. It can be seen that the greater the thickness of the gate line 1 is, the greater the step difference of the isolation layer 16' will be. A larger step difference will cause the thickness of the isolation layer 16' to be uneven, which will result in a larger portion of the isolation layer 16' covering the gate line 1. Even a part of the gate line 1 is not covered by the isolation layer 16', so that the coverage of the gate line 1 by the isolation layer 16' decreases.
  • the data line 2 includes a plurality of first line segments 21 and a plurality of second line segments 22 in a first direction, and the plurality of first line segments 21 are located far away from the substrate.
  • a plurality of second line segments 22 are located on the side of the gate line 1 close to the substrate 10
  • the insulating layer 16 includes a plurality of first vias 81, which makes every two adjacent first lines in the first direction
  • the segment 21 is electrically connected to a second line segment 22 located between the two adjacent first line segments 21 through at least two first vias 81, so that a plurality of first line segments 21 electrically connected in the first direction
  • a data line 2 is formed with a plurality of second line segments 22.
  • the array substrate 200 provided by the embodiment of the present disclosure effectively avoids the occurrence of defective problems such as data line disconnection and DGS caused by the large thickness of the gate line 1 or film particles, and effectively improves the product yield.
  • the substrate 10 has a plurality of sub-pixel regions P, and the array substrate 200 further includes a plurality of pixel circuits 30.
  • Each pixel circuit 30 is disposed in one sub-pixel region P.
  • the circuit 30 is electrically connected to one gate line 1 and one data line 2.
  • the pixel circuit 30 includes a first switch transistor 31.
  • the first switching transistor 31 includes a first gate 311, a first source 312, a first drain 313, a first active layer 314, and a first gate insulating pattern 315.
  • the first gate 311 of the first switching transistor 31 has the same layer and the same material as the gate line 1 connected to the pixel circuit 30, and the first source 312 and the first drain 313 of the first switching transistor 31 are the same as the first line segment 21. Layers of the same material.
  • the orthographic projection of the first active layer 314 of the first switching transistor 31 on the substrate 10 is within the range of the orthographic projection of the first gate 311 on the substrate 10.
  • the first switching transistor 31 is a top-gate thin film transistor.
  • the first active layer 314 of the first switching transistor 31 is located on the side of the first gate 311 close to the substrate 10, and the interlayer dielectric layer 15 is located on the layer where the first source 312 and the first drain 313 are located.
  • the first source 312 and the first drain 313 are electrically connected to the first active layer 314 of the first switching transistor 31 through a first connection via 84 penetrating the interlayer dielectric layer 15 respectively.
  • the first switching transistor 31 is a bottom-gate thin film transistor.
  • the first active layer 314 of the first switching transistor 31 is located on the side of the first gate 311 away from the substrate 10, and the interlayer dielectric layer 15 is located on the layer where the first source 312 and the first drain 313 are located.
  • the first source electrode 312 and the first drain electrode 313 are electrically connected to the first active layer 314 of the first switching transistor 31 through the first connection via 84 penetrating the interlayer dielectric layer 15 respectively. connection.
  • the interlayer dielectric layer 15 may also be referred to as an etching barrier layer.
  • the material of the first gate 311 and the gate line 1 includes at least one of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W).
  • the gate 311 and the gate line 1 may be made of one of the foregoing simple metals, or a metal alloy composed of two or more of the foregoing simple metals.
  • the materials of the first line segment 21, the first source 312 and the first drain 313 of the first switching transistor 31 may include simple metals such as copper (Cu) or aluminum (Al).
  • the width of the second line segment 22 is greater than the width of the first line segment 21. In this way, the yield rate of the electrical connection between the first line segment 21 and the second line segment 22 can be ensured.
  • the first switching transistor 31 is a top-gate thin film transistor.
  • the array substrate 200 further includes: a plurality of first metal light-shielding patterns 12 disposed on the substrate 10.
  • Each first metal light-shielding pattern 12 is arranged on a side of the first switch transistor 31 close to the substrate 10 in a corresponding pixel circuit. Since the active layer of the transistor is more sensitive to light, its electrical properties are easily changed when exposed to light. Therefore, the orthographic projection of the first active layer 314 of the first switching transistor 31 is located on the first metal shading pattern 12 on the substrate 10. Within the range of the orthographic projection, so that the first metal shading pattern 12 can shield the light emitted to the first active layer 314.
  • the plurality of second line segments 22 and the plurality of first metal shading patterns 12 have the same layer and the same material, and are insulated from each other.
  • the thickness of the second line segment 22 is equal to the thickness of the first metal light-shielding pattern 12. In this way, the level difference between the buffer layer 11 on the side of the second line segment 22 and the first metal light-shielding pattern 12 is reduced as much as possible to prevent the level difference of the buffer layer 11 from greatly affecting the product yield of the display panel.
  • the material of the second line segment 22 and the first metal shading pattern 12 includes metal materials such as molybdenum, aluminum, etc., which have a shading effect.
  • the material of the first active layer 314 includes, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AlZnO), zinc oxide (ZnO) or gallium zinc oxide ( GZO) and other metal oxides.
  • the insulating layer 16 further includes a plurality of second via holes 82, and one of the first source 312 and the first drain 313 of the first switching transistor 31 passes through at least one second The via 82 is electrically connected to the first metal light shielding pattern 12.
  • the first drain 313 of the first switching transistor 31 is electrically connected to the first metal light shielding pattern 12 through the second via 82.
  • the first source 312 of the first switching transistor 31 is electrically connected to the first metal light shielding pattern 12 through the second via 82.
  • the first source 312 or the first drain 313 of the first switching transistor 31 is electrically connected to the first metal shading pattern 12, and the first source 312 and the first drain 313 are also connected to the first switching transistor 31.
  • the source layer 314 is electrically connected. In this way, the induced charges on the first metal shading pattern 12 can be allowed to flow to the first source 312 and the first drain 313, avoiding the influence on the first switching transistor 31, and making the first active of the first switching transistor 31
  • the layer 314, the first source 312, and the first drain 313 are at the same potential, thereby enhancing the electrical stability of the first switching transistor 31 and improving the electrical performance of the first switching transistor 31.
  • the array substrate 200 further includes a plurality of pixel electrodes 50 disposed on the substrate 10, and each pixel electrode 50 is disposed in a sub-pixel area P.
  • the first drain electrode 313 of the first switch transistor 31 is electrically connected to the pixel electrode 50.
  • the pixel electrode 50 is disposed on a side of the first drain 313 of the first switching transistor 31 away from the substrate 10.
  • the material of the pixel electrode 50 may be indium tin oxide (ITO).
  • the array substrate 200 further includes a passivation layer 34 and an organic insulating layer 35 disposed between the pixel electrode 50 and the first drain electrode 313 of the first switching transistor 31.
  • the pixel electrode 50 may be electrically connected to the first drain electrode 313 of the first switching transistor 31 through a third connection via hole penetrating the organic insulating layer 35 and the passivation layer 34.
  • the material of the passivation layer 34 may include an inorganic material, such as silicon nitride; the material of the organic insulating layer 35 may include an organic polymer material, such as acrylic.
  • the array substrate 200 further includes: a plurality of light emitting devices 40 arranged on the substrate 10, each light emitting device 40 is arranged in a sub-pixel area P and emits light The device 40 is connected to a pixel circuit 30 located in the sub-pixel region P.
  • the pixel circuit 30 further includes a driving transistor 32, which is the above-mentioned top-gate thin film transistor.
  • the driving transistor 32 includes a second active layer 324, a second gate insulating pattern 325 and a second gate 321 disposed on the side of the second active layer 324 away from the substrate 10, and a second source 322 and second drain 323.
  • the second source electrode 322 and the second drain electrode 323 are in contact with the second active layer 324 of the driving transistor 32 through at least one second connection via 85 in the interlayer insulating layer 15 respectively.
  • the material of the second active layer 324 includes, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AlZnO), zinc oxide (ZnO), gallium zinc oxide ( GZO) and other metal oxides.
  • the array substrate 200 further includes a plurality of second metal light-shielding patterns 13 disposed on the substrate 10.
  • Each second metal light-shielding pattern 13 is disposed on a side of the driving transistor 32 in a corresponding pixel circuit 30 close to the substrate 10.
  • the orthographic projection of the second active layer 324 of the driving transistor 32 is within the range of the orthographic projection of the second metal light-shielding pattern 13 on the substrate 10, so that the second metal light-shielding pattern 13 can be directed toward the second active layer 324. The light is blocked.
  • the plurality of second line segments 22 and the plurality of second metal shading patterns 13 have the same layer and the same material, and are insulated from each other.
  • the material of the second line segment 22 and the second metal shading pattern 13 includes, for example, metal materials with shading effects such as molybdenum and aluminum.
  • the plurality of second line segments 22 and the plurality of first metal shading patterns 12 are arranged in the same layer, the plurality of second metal shading patterns 13, the plurality of first metal shading patterns 12, and the plurality of first metal shading patterns Two line segments 22 are set on the same floor.
  • the second gate 321 of the driving transistor 32, the first gate 311 of the first switching transistor 31, and the gate line 1 are of the same layer and the same material.
  • the second source 322 and the second drain 323 of the driving transistor 32, the first source 312 and the first drain 313 of the first switching transistor 31, and the first line segment 21 have the same layer and the same material.
  • one of the second source 322 and the second drain 323 of the driving transistor 32 passes through a fourth via 86 and is located on the side of the driving transistor 32 close to the substrate 10.
  • the second metal shading pattern 13 is electrically connected.
  • the array substrate 200 further includes a plurality of power lines 9 electrically connected to the plurality of pixel circuits 30.
  • the power cord 9 extends in the first direction Y.
  • One of the plurality of power lines 9 includes a plurality of third line segments 91 and a plurality of fourth line segments 92 extending along the first direction, and the plurality of third line segments 91 and the plurality of fourth line segments 92 alternate Arrangement.
  • each power cord 9 includes a plurality of third line segments 91 and a plurality of fourth line segments 92 extending along the first direction, and the plurality of third line segments 91 and the plurality of fourth line segments 92 are alternately arranged.
  • the orthographic projections of the plurality of third line segments 91 on the substrate 10 do not overlap with the orthographic projections of the plurality of grid lines 1 on the substrate 10, and the orthographic projections of each fourth line segment 92 on the substrate 10 correspond to a corresponding one.
  • the orthographic projection of the root grid line 1 on the substrate 10 overlaps.
  • the multiple third line segments 91 and the multiple first line segments 21 have the same layer and the same material, and the multiple fourth line segments 92 have the same layer and the same material as the second line segments 22.
  • the insulating layer 16 also includes a plurality of third via holes 83. Along the first direction Y, every two adjacent third line segments 91 are electrically connected to a fourth line segment 92 located between the two third line segments 91 through at least two third via holes 83.
  • the power supply line 9 is electrically connected to the second source 322 of the driving transistor 32 in the pixel circuit 30.
  • the second drain 323 of the driving transistor 32 is electrically connected to the light emitting device 40.
  • the power supply line 9 is electrically connected to the second drain 323 of the driving transistor 32 in the pixel circuit 30.
  • the second source 322 of the driving transistor 32 is electrically connected to the light emitting device 40.
  • the width of the fourth line segment 92 is greater than the width of the third line segment 91 to ensure the yield of the electrical connection between the third line segment 91 and the fourth line segment 92.
  • the second line segment 22 is provided in the same layer as the first metal shading pattern 12 and the second metal shading pattern 13, the fourth line segment 92, the second line segment 22, the second metal shading pattern 13, and the first metal shading pattern 12 Same layer settings.
  • the third line segment 91, the first line segment 21, the second source 322 and the second drain 323 of the driving transistor 32, and the first source of the first switching transistor 31 312 and the first drain electrode 313 are arranged in the same layer.
  • the power line 9 is divided into a plurality of third line segments 91 and a plurality of fourth line segments 92 in the first direction Y, and the plurality of third line segments 91 are located in the gate.
  • a plurality of fourth line segments 92 are located on the side of the gate line 1 close to the substrate 10, and a plurality of third vias 83 are provided on the insulating layer 16, so that each phase in the first direction
  • Two adjacent third line segments 91 are electrically connected to a fourth line segment 92 located between the two adjacent third line segments 91 through at least two third vias 83, so that a plurality of third line segments 91 in the first direction It is electrically connected to a plurality of fourth line segments 92 to form a power line 9.
  • the level difference of the insulating layer 16 is large, the uneven thickness of the power line 9 due to the level difference can be effectively avoided, the thickness uniformity of the power line 9 is ensured, and the yield of the display panel is improved.
  • the power line 9 is electrically connected to the second source 322 of the driving transistor 32 in the pixel circuit 30, and the second drain 323 of the driving transistor 32 is electrically connected to the anode 41 of the light emitting device 40.
  • the material of the anode 40 includes ITO (Indium Tin Oxide).
  • the pixel circuit 30 further includes at least one second switching transistor.
  • the second switching transistor is a top-gate thin film transistor.
  • a third switching transistor may be provided between the second switching transistor and the substrate 10.
  • the metal shading pattern, the orthographic projection of the third metal shading pattern on the substrate 10 covers the orthographic projection of the active layer of the second switching transistor, the third metal shading pattern and the first metal shading pattern 12 have the same layer and the same material, and are insulated from each other .
  • Some embodiments of the present disclosure also provide a method for manufacturing an array substrate, as shown in FIG. 16, including the following steps:
  • a substrate 10 is provided, and a plurality of columns of second line segments 22 are formed along the second direction X on the substrate 10.
  • Each column of second line segments 22 includes a plurality of second line segments 22 extending along the first direction Y and arranged at intervals. The first direction and the second direction are intersected.
  • the first direction and the second direction are perpendicular.
  • a plurality of pixel circuits 30 are formed on the substrate 10 on which the plurality of second line segments 22 are formed.
  • the pixel circuit 30 includes a first switching transistor 31.
  • first switch transistor 31 For the structure of the first switch transistor 31, reference may be made to the description of the first switch transistor 31 in the above-mentioned embodiment, which will not be repeated here.
  • a plurality of second line segments 22 and a plurality of first metal light-shielding patterns 12 are formed on the substrate 10 through a single patterning process, and a plurality of second line segments 22 and a plurality of The first metal light shielding patterns 12 are insulated from each other.
  • the orthographic projection of the first active layer 314 of the first switching transistor 31 on the substrate 10 is within the range of the orthographic projection of a corresponding first metal light shielding pattern 12 on the substrate 10.
  • the first metal shading pattern 12 and the second line segment 22 have the same thickness, so that in the subsequent step S20, a buffer film 11' is formed on the first metal shading pattern 12 and the second line segment 22 to ensure that the buffer film 11 'The thickness is uniform along the thickness direction of the substrate 10.
  • the pixel circuit 30 further includes a driving transistor 32.
  • a driving transistor 32 As shown in part a in FIG. 17, multiple second line segments 22, multiple first metal light-shielding patterns 12, and multiple second metal light-shielding patterns 13 can be formed on the substrate 10 through a single patterning process. 22.
  • the plurality of first metal shading patterns 12 and the plurality of second metal shading patterns 13 are insulated from each other.
  • the orthographic projection of the second active layer 324 of the driving transistor 32 is located in the range of the orthographic projection of the corresponding second metal light-shielding pattern 13 on the substrate 10.
  • the thickness of the first metal light-shielding pattern 12, the second line segment 22, and the second metal light-shielding pattern 13 may be the same.
  • the material of the second line segment 22 includes metal materials with a light-shielding effect, such as molybdenum and aluminum.
  • the materials of the first metal light-shielding pattern 12 and the second metal light-shielding pattern 13 are the same as the material of the second line segment 22.
  • a plurality of gate lines 1 arranged along a first direction Y are formed on a substrate 10 on which a plurality of second line segments 22 are formed, and each gate line 1 extends along a second direction X.
  • the multiple gate lines 2 and the first gate 311 of the first switching transistor 31 are formed by the same patterning process.
  • the multiple gate lines 2, the first gate 311 of the first switching transistor 31, and the second gate 321 of the driving transistor 32 are formed by the same patterning process.
  • the material of the gate line 2 may include, for example, at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten.
  • the first via 81 is used to electrically connect the second line segment 22 with the first line segment 21 formed later.
  • the first via 81 exposes a partial area of the second line segment 22.
  • the orthographic projections of the plurality of first line segments 21 on the substrate 10 and the orthographic projections of the plurality of grid lines 1 on the substrate 10 do not overlap.
  • the multiple first line segments 21 are arranged in multiple rows along the second direction X, and the multiple first line segments 21 in each column extend along the first direction and are arranged at intervals.
  • every two adjacent first line segments 21 are electrically connected to a second line segment 22 located between them through at least two first vias 81. All the first line segments 21 and all the second line segments 22 electrically connected in each column constitute a data line 2.
  • the plurality of first line segments 21 and the first source 312 and the first drain 313 of the first switching transistor 31 may be formed by the same patterning process.
  • the plurality of first line segments 21, the first source 312 and the first drain 313 of the first switching transistor 31, and the second source of the driving transistor 32 can be formed by the same patterning process.
  • the material of the first line segment 21 may include, for example, a simple metal such as copper or aluminum.
  • the insulating layer 16 includes a buffer layer 11 and an interlayer dielectric layer 15.
  • a buffer film 11' is formed on the substrate 10.
  • the buffer film 11' may have a one-layer or multi-layer structure.
  • the buffer film 11' has a one-layer structure, and the material of the buffer film 11' is silicon oxide (SiOx) or silicon nitride (SiNx).
  • the buffer film 11' has a structure of two or more layers, and the buffer film 11' is, for example, a composite film layer of a silicon oxide layer and a silicon nitride layer.
  • the first active layer 314 of the first switching transistor 31 is formed by one patterning process.
  • the first active layer 314 of the first switching transistor 31 and the second active layer of the driving transistor 32 are formed by one patterning process. 324.
  • the buffer film 11' can prevent harmful impurities and ions in the substrate 10 from diffusing into the first active layer 314 of the first switching transistor 31 and the second active layer 324 of the driving transistor 32.
  • the material of the first active layer 314 of the first switching transistor 31 includes, for example, metal oxides such as indium gallium zinc oxide, indium gallium oxide, indium tin zinc oxide, aluminum oxide zinc, zinc oxide, or gallium zinc oxide.
  • the material of the second active layer 324 of the driving transistor 32 includes metal oxides such as indium gallium zinc oxide, indium gallium oxide, indium tin zinc oxide, aluminum oxide zinc, zinc oxide, or gallium zinc oxide.
  • a gate insulating film is formed on the substrate 10 on which the first active layer 314 is formed, and the gate insulating film is patterned using the first gate 311 and the gate line 1 as a mask to form a first
  • the first gate insulating pattern 315 of the switching transistor 31 and the reserved pattern 14 overlap the orthographic projection of the gate line 1 on the substrate 10.
  • a gate insulating film 330 is formed on the buffer film 11' on which the first active layer 314 and the second active layer 324 are formed, and A gate electrode 311, a second gate electrode 321 and a gate line 1 pattern the gate insulating film 330 to form the first gate insulating pattern 315 of the first switching transistor 31, the second gate insulating pattern 325 of the driving transistor 32, and the remaining pattern 14.
  • the remaining pattern 14 overlaps with the orthographic projection of the gate line 1 on the substrate 10.
  • the gate insulating film 330 may not be patterned. In this case, the first gate insulating pattern 315, the second gate insulating pattern 325, and the remaining pattern 14 are integrated.
  • the material of the gate insulating film 330 includes, for example, at least one of silicon nitride, silicon oxide, aluminum oxide (Al 2 O 3 ), and aluminum nitride (AlN).
  • the first active layer 314 of the first switching transistor 31 is not covered by the first gate 311 Part of the conductive treatment is performed, thereby increasing the conductivity of the portion of the first active layer 314 that is in contact with the first source 312 and the first drain 313.
  • the conductive treatment may be to bombard the portion of the first active layer 314 of the first switching transistor 31 beyond the first gate 311 with plasma to bombard the oxygen ions to make the first active layer 314 Partially conductive.
  • the gas forming the plasma includes a protective atmosphere or a reactive atmosphere.
  • the protective gas may include, for example, one or a mixed gas of nitrogen, argon, helium, and neon
  • the reactive gas may include, for example, one or a mixed gas of air, oxygen, hydrogen, ammonia, and carbon dioxide.
  • the portion of the second active layer 324 of the driving transistor 32 that is not covered by the second gate 321 is subjected to a conductive process, thereby The conductivity of the portion of the second active layer 324 in contact with the second source electrode 322 and the first drain electrode 323 is increased.
  • the same method can be used to treat the portion of the second active layer 324 of the driving transistor 32 that is not covered by the second gate 321. Carry out the above-mentioned conductorization treatment.
  • an interlayer dielectric film 15' is formed on the buffer film 11' on which the gate line 1 is formed, and then the interlayer dielectric film 15' and the buffer film 11' are The patterning, as shown in part g in FIG. 17, forms an interlayer dielectric layer 15 and a buffer layer 11.
  • the first via 81 penetrates the interlayer dielectric layer 15 and the buffer layer 11, so that every two adjacent first line segments 21 along the first direction pass through at least two first vias 81 and are located in the adjacent two first lines.
  • a second line segment 22 between the line segments 21 is electrically connected.
  • first connection via 84 penetrating through the interlayer dielectric layer 15 are also formed, so that the first source 312 and the first drain 313 can pass through a first The connection via 84 is in contact with the first active layer 314.
  • first connection vias 84 and a plurality of second connection vias 85 penetrating the interlayer dielectric layer 15 are also formed.
  • first source 312 and the first drain 313 can respectively contact the first active layer 314 through a first connection via 84
  • the second source 322 and the second drain 323 can respectively be connected through a second connection.
  • the via hole 85 is in contact with the second active layer 324.
  • a plurality of second vias 82 penetrating the buffer layer 11 and the interlayer dielectric layer 15 are also formed.
  • One of the first source 312 and the first drain 313 of the first switching transistor 31 is electrically connected to the first metal light shielding pattern 12 through the second via 82.
  • a plurality of second vias 82 and a plurality of fourth vias 86 penetrating through the buffer layer 11 and the interlayer dielectric layer 15 are also formed.
  • One of the first source 312 and the first drain 313 of the first switching transistor 31 is electrically connected to the first metal light shielding pattern 12 through the second via 82.
  • One of the second source 322 and the second drain 323 of the driving transistor 32 is electrically connected to the second metal light shielding pattern 13 through a fourth via 86.
  • the manufacturing method of the array substrate further includes: referring to FIG. 14, forming a plurality of power lines.
  • Each power cord 9 includes a plurality of third line segments 91 and a plurality of fourth line segments 92 extending along the first direction, and the plurality of third line segments 91 and the plurality of fourth line segments 92 are alternately arranged.
  • the orthographic projections of the plurality of third line segments 91 on the substrate 10 do not overlap with the orthographic projections of the plurality of grid lines 1 on the substrate 10, and the orthographic projections of each fourth line segment 92 on the substrate 10 correspond to a corresponding one.
  • the orthographic projection of the root grid line 1 on the substrate 10 overlaps.
  • the multiple third line segments 91 and the multiple first line segments 21 are formed through the same patterning process, and the multiple fourth line segments 92 and the second line segments 22 are formed through the same patterning process.
  • the insulating layer 16 further includes a plurality of third via holes 83. Along the first direction, every two adjacent third line segments 91 are electrically connected to a fourth line segment 92 located between the two third line segments 91 through at least two third via holes 83.
  • the power supply line 9 is electrically connected to the second source 322 of the driving transistor 32 in the pixel circuit 30.
  • the specific structure of the power line 9 can refer to the structure of the power line 9 in the array substrate 200 described above, which will not be repeated here.

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Abstract

一种阵列基板，包括：衬底；设置于衬底上的多根栅线和多根数据线；多根数据线均沿第一方向延伸，多根栅线均沿第二方向延伸，第一方向和第二方向交叉设置；多根数据线中的至少一根数据线包括沿第一方向延伸的多个第一线段以及多个第二线段，多个第一线段和多个第二线段交替排布；多个第二线段设置于多根栅线靠近衬底的一侧，多个第一线段设置于多根栅线远离衬底一侧，且多个第一线段在衬底上的正投影与多根栅线在衬底上的正投影无交叠；绝缘层包括多个第一过孔；沿第一方向，每相邻两个第一线段通过至少两个第一过孔与位于二者之间的一个第二线段电连接。

Description

阵列基板及其制备方法、以及显示装置
本申请要求于2019年6月20日提交的、申请号为201910536367.8的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、以及显示装置。
背景技术
随着显示面板的尺寸不断增大以及分辨率不断增高，显示面板中栅线和数据线的长度及栅线和数据线的数量随之增加，导致栅线和数据线的压降(由于信号线本身存在的电阻导致信号线的信号输入端和与信号输入端相对的远端产生电压差)也随之增大。
发明内容
一方面，提供一种阵列基板，包括：衬底；设置于衬底上的多根栅线和多根数据线；多根数据线均沿第一方向延伸，多根栅线均沿第二方向延伸，第一方向和第二方向交叉设置；多根数据线中的至少一根数据线包括沿第一方向延伸的多个第一线段以及多个第二线段，多个第一线段和多个第二线段交替排布；多个第二线段设置于多根栅线靠近衬底的一侧，多个第一线段设置于多根栅线远离衬底一侧，且多个第一线段在衬底上的正投影与多根栅线在衬底上的正投影无交叠；设置于多个第一线段和多个第二线段之间的绝缘层，绝缘层包括多个第一过孔；其中，沿第一方向，每相邻两个第一线段通过至少两个第一过孔与位于二者之间的一个第二线段电连接。
在一些实施例中，衬底具有多个亚像素区；阵列基板还包括：设置于衬底上的多个像素电路，每个像素电路设置于一个亚像素区中，像素电路与一根栅线和一根数据线电连接；其中，像素电路包括第一开关晶体管，第一开关晶体管的第一栅极与栅线同层同材料，多个第一线段与第一开关晶体管的第一源极和第一漏极同层同材料。
在一些实施例中，沿第二方向，第二线段的宽度大于第一线段的宽度。
在一些实施例中，第一开关晶体管为顶栅型薄膜晶体管；阵列基板还包括：设置于衬底上的多个第一金属遮光图案；每个第一金属遮光图案设置在对应的一个像素电路中第一开关晶体管靠近衬底一侧，像素电 路中第一开关晶体管的第一有源层在衬底上的正投影位于第一金属遮光图案在衬底上的正投影的范围内；多个第二线段与多个第一金属遮光图案同层同材料，且相互绝缘。
在一些实施例中，绝缘层还包括多个第二过孔，第一开关晶体管的第一源极和第一漏极中的其中一极通过至少一个第二过孔与第一金属遮光图案电连接。
在一些实施例中，沿衬底的厚度方向，第二线段的厚度等于第一金属遮光图案的厚度。
在一些实施例中，阵列基板还包括：设置于衬底上的多个像素电极，每个像素电极设置于一个亚像素区中；其中，第一开关晶体管的第一源极与数据线电连接，第一开关晶体管的第一漏极与像素电极电连接；像素电极设置于第一漏极远离衬底的一侧。
在一些实施例中，阵列基板还包括：设置于衬底上的多个发光器件，每个发光器件设置于一个亚像素区中，且发光器件与对应的一个像素电路连接。
在一些实施例中，像素电路还包括一个驱动晶体管，驱动晶体管为顶栅型薄膜晶体管；阵列基板还包括：设置于衬底上的多个第二金属遮光图案，每个第二金属遮光图案设置在对应的一个像素电路中驱动晶体管靠近衬底一侧，驱动晶体管的第二有源层的正投影位于第二金属遮光图案在衬底上的正投影的范围内；其中，多个第二线段以及多个第二金属遮光图案同层同材料，且相互绝缘。
在一些实施例中，阵列基板还包括：多根电源线，多根电源线均沿第一方向延伸，像素电路与一个电源线电连接；多根电源线中的一根电源线包括沿第一方向延伸的多个第三线段和多个第四线段，多个第三线段和多个第四线段交替排布；多个第三线段在衬底上的正投影与多根栅线在衬底上的正投影无交叠；多个第三线段与多个第一线段同层同材料，多个第四线段与多个第二线段同层同材料；绝缘层还包括多个第三过孔，沿第一方向，每相邻两个第三线段通过至少两个第三过孔与位于二者之间的一个第四线段电连接。
在一些实施例中，沿第二方向，第四线段的宽度大于第三线段的宽度。
在一些实施例中，电源线与像素电路中的驱动晶体管的第二源极电连接，驱动晶体管的第二漏极与发光器件的阳极电连接。
在一些实施例中，绝缘层包括层叠设置在衬底上的缓冲层和层间介质层。
另一方面，提供一种显示装置，包括上述任一种阵列基板。
再一方面，提供一种阵列基板的制备方法，包括：提供衬底；在衬底上形成多个第二线段；多个第二线段沿第二方向排布成多列第二线段，每列第二线段包括沿第一方向延伸且间隔设置的多个第二线段；第一方向和第二方向交叉设置；在形成有多个第二线段的衬底上形成多根栅线，多根栅线均沿第二方向延伸；然后在形成有多个第二线段的衬底上形成绝缘层，绝缘层包括多个第一过孔；在形成有绝缘层的衬底上形成多个第一线段，多个第一线段在衬底上的正投影与多根栅线在衬底上的正投影无交叠；多个第一线段沿第二方向排布成多列第一线段，每列第一线段包括沿第一方向延伸且间隔设置的多个第一线段，且沿第一方向，每相邻两个第一线段通过至少两个第一过孔与位于二者之间的一个第二线段电连接；每列中电连接的所有第一线段和所有第二线段构成一根数据线。
在一些实施例中，形成多个第二线段之后，上述阵列基板的制备方法还包括：在形成有多个第二线段的衬底上形成多个像素电路，每个像素电路位于一个亚像素区中，像素电路包括第一开关晶体管；其中，多根栅线与第一开关晶体管的第一栅极通过同一次构图工艺形成；多个第一线段与第一开关晶体管的第一源极和第一漏极通过同一次构图工艺形成。
在一些实施例中，绝缘层包括缓冲层和层间介质层；形成绝缘层，包括：在形成多个第二线段之后，形成多根栅线之前，形成缓冲薄膜；在形成多根栅线之后，形成层间介质薄膜；对层间介质薄膜和缓冲薄膜进行构图，形成包括多个第一过孔的层间介质层和缓冲层。
在一些实施例中，形成多个第二线段包括：通过一次构图工艺形成多个第二线段，以及多个第一金属遮光图案，多个第二线段与多个第一金属遮光图案相互绝缘；像素电路中第一开关晶体管的第一有源层在衬底上的正投影位于对应的一个第一金属遮光图案在衬底上的正投影的范围内。
在一些实施例中，绝缘层包括缓冲层和层间介质层；对层间介质薄膜和缓冲薄膜进行构图，形成包括多个第一过孔的层间介质层和缓冲层，包括：对层间介质薄膜和缓冲薄膜进行构图，形成包括多个第一过孔和 多个第二过孔的层间介质层和缓冲层；第一开关晶体管的第一源极和第一漏极中的其中一极通过第二过孔与第一金属遮光图案电连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，然而，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例的一种显示面板的俯视示意图；
图2为根据本公开一些实施例的一种亚像素的结构示意图；
图3为根据本公开一些实施例的另一种亚像素的结构示意图；
图4为根据本公开一些实施例的一种阵列基板的俯视示意图；
图5为图4的阵列基板沿B-B’方向的剖视示意图；
图6为根据本公开一些实施例的另一种阵列基板的俯视示意图；
图7为图6的阵列基板沿D-D’方向的剖视示意图；
图8为相关技术中的一种阵列基板的俯视示意图；
图9为图8的阵列基板沿C-C’方向的剖视示意图；
图10为根据本公开一些实施例的又一种阵列基板的结构示意图；
图11为根据本公开一些实施例的又一种阵列基板的结构示意图；
图12为根据本公开一些实施例的又一种阵列基板的俯视示意图；
图13为图12的阵列基板沿E-E’方向的剖视示意图；
图14为根据本公开一些实施例的又一种阵列基板的俯视示意图；
图15为图14的阵列基板沿F-F’方向的剖视示意图；
图16为根据本公开一些实施例的一种阵列基板的制备方法的流程图；
图17为根据本公开一些实施例的一种阵列基板的制备过程中的结构示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
A和/或B包括以下组合：仅A，仅B，A和B的组合。
C和D同层同材料指C与D基于同一承载面，采用同一成膜工艺形成用于形成特定图形的膜层，再利用同一掩模板通过构图工艺形成的层结构。其中，构图工艺可能包括曝光、显影和刻蚀工艺，而形成的层结构中的特定图形可以是连续的，也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。然而，术语“连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本公开实施例提供一种显示装置，该显示装置包括但不限于手机、电视、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑以及显示面板等。
图1是根据本公开一些实施例的一种显示面板的俯视结构示意图。如图1所示，显示面板100具有显示区AA和周边区S。
根据显示面板100的不同设计，周边区S的具体位置可以相应地改变。例如，周边区S围绕显示区AA；或者，周边区S位于显示区AA周边的一侧或多侧处，但不围绕显示区AA。
显示区AA设置有多个亚像素，每个亚像素位于一个亚像素区P中。多个亚像素至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素，第一颜色、第二颜色和第三颜色为三基色(例如红色、绿色和蓝色)。
图1中以上述多个亚像素呈阵列形式排列为例进行的说明。如图1所示，沿水平方向X(例如为行方向)排列成一排的亚像素称为同一行亚像素，沿竖直方向Y(例如为列方向)排列成一排的亚像素称为同一列亚像素。
在一些示例中，同一行亚像素可以与一根栅线1连接，同一列亚像素可以与一根数据线2连接。
上述显示面板100例如可以为液晶显示面板或者自发光型显示面板。
在一些实施例中，显示面板100为液晶显示面板。
在此情况下，如图2所示，亚像素区P设置有像素电路30、像素电极50和公共电极60。像素电路30包括第一开关晶体管。
在一些示例中，第一开关晶体管的栅极301与栅线1连接，源极302与数据线2连接，漏极303与像素电极50连接(如图2所示)。
在另一些示例中，第一开关晶体管的栅极301与栅线1连接，源极302与像素电极50连接，漏极303与数据线2连接。
如图2所示，像素电极50和公共电极60被配置为向该亚像素区P的液晶分子层70施加电场，以使得液晶分子层70中的液晶分子在上述电场作用下发生偏转。需要说明的是，图2仅为示例性示出了公共电极60与像素电极50分别设置在液晶层分子层70的两侧这一种情况，当然，公共电极60与像素电极50也可以是设置在液晶分子层70的同侧。
在一些示例中，亚像素区P中还设置有彩色滤光图案。
可以理解的是，位于第一颜色亚像素中的彩色滤光图案的颜色为第一颜色，位于第二颜色亚像素中的彩色滤光图案的颜色为第二颜色，位于第三颜色亚像素中的彩色滤光图案的颜色为第三颜色。
在另一些实施例中，显示面板100为自发光型显示面板。
在此情况下，如图3所示，亚像素区P设置有位于衬底10上的像素电路30和发光器件40。
像素电路30至少包括一个第一开关晶体管和一个驱动晶体管、以及一个电容器(Capacitor，简称C)。
示例性地，参见图6所示，像素电路30可以是2T1C结构的像素电路。即：该像素电路30包括两个薄膜晶体管(Thin Film Transistor，简称TFT)和一个电容器33，上述两个TFT包括一个开关TFT(例如图6中第一开关晶体管31)和一个驱动TFT(例如图6中驱动晶体管32)。
当然，像素电路30的结构还可以是除2T1C结构以外的其他结构，例如3T1C(即像素电路30包括三个TFT和一个电容器)，5T1C(即像素电路30包括五个TFT和一个电容器)，或者7T1C(即像素电路30包括七个TFT和一个电容器)，等等。也就是说，像素电路30可以包括至少两个TFT和至少一个电容器。该至少两个TFT至少包括一个开关TFT和一个驱动TFT。
发光器件40包括阴极45、阳极41、以及位于阴极45和阳极41之间的发光功能层。
以发光器件40为OLED(有机发光二极管，Organic Light-Emitting Diode)为例，如图3所示，发光功能层包括有机发光层43、位于有机发光层43和阳极41之间的空穴传输层42、以及位于有机发光层43和阴极45之间的电子传输层44。
在一些示例中，发光功能层还包括设置在空穴传输层42和阳极41之间的空穴注入层，和/或设置在电子传输层44和阴极45之间的电子注入层。
需要说明的是，图3仅示例性示出了自发光型显示面板的结构示意图，并未示出像素电路30与发光器件40的电性连接关系。本公开实施例对像素电路30与发光器件40的电性连接方式的不作限定，可以根据像素电路30的结构选择适用于该像素电路30和发光器件40的电性连接方式。
在一些实施例中，发光器件40发出的光为白色光，亚像素区P中还设置有彩色滤光图案。
发光器件40的出光方式可以为顶发射(即发光器件40发出的光从远离衬底10一侧射出)或底发射(即发光器件40发出的光穿过衬底10射出)。
在一些示例中，发光器件40为顶发射型发光器件，彩色滤光图案位于发光器件40远离像素电路30的一侧。
在另一些示例中，如图3所示，发光器件40为底发射型发光器件， 彩色滤光图案60位于发光器件40靠近像素电路30的一侧。
不管显示面板是哪种类型的显示面板，其均包括阵列基板。
如图4-图7所示，本公开一些实施例提供一种阵列基板200包括：衬底10、设置于衬底10上的多根栅线1以及多根数据线2。多根数据线2均沿第一方向Y延伸，多根栅线均沿第二方向X延伸，第一方向和第二方向交叉设置。
在一些示例中，如图4所示，第一方向和第二方向垂直。
如图4-图7所示，该多根数据线2中的至少一根数据线2包括沿第一方向Y延伸的多个第一线段21以及多个第二线段22，该多个第一线段21与该多个第二线段22交替排布。示例的，每根数据线2包括沿第一方向Y延伸的多个第一线段21以及多个第二线段22，该多个第一线段21与该多个第二线段22交替排布。
如图4-图7所示，该数据线2中的多个第二线段22设置于多根栅线1靠近衬底10的一侧，该数据线2中的多个第一线段21设置于多根栅线1远离衬底10的一侧，且多个第一线段21在衬底10上的正投影与多根栅线1在衬底10上的正投影无交叠。每个第二线段22在衬底10上的正投影与对应的一根栅线1在衬底10上的正投影重叠。
如图5和图7所示，阵列基板200还包括：设置于多个第一线段21和多个第二线段22之间的绝缘层16。绝缘层16包括多个第一过孔81。沿第一方向，每相邻两个第一线段21通过至少两个第一过孔81与位于该两个第一线段21之间的一个第二线段22电连接。
示例的，如图4和图6所示，每相邻两个第一线段21通过两个第一过孔81与位于该两个第一线段21之间的一个第二线段22电连接，该两个第一过孔81分别位于对应的一根栅线1沿第一方向的相对两侧，其中一个第一过孔81在衬底10上的正投影与该两个第一线段21中的一个和该第二线段22在衬底10上的正投影重叠，另一个第一过孔81在衬底10上的正投影与另一个第一线段21和该第二线段22在衬底10上的正投影重叠。
在一些实施例中，如图5和图7所示，绝缘层16包括层叠设置在衬底10上的缓冲层11和层间介质层15。
缓冲层11设置在多个第二线段22与多根栅线1之间，使得多个第二线段22与多根栅线1绝缘。
缓冲层11可以为一层或多层结构。示例的，缓冲层11为一层结构， 缓冲层11的材料例如可以包括氧化硅(SiOx)或氮化硅(SiNx)等。又示例的，缓冲层11为两层或两层以上的结构，缓冲层11包括至少一层氧化硅层和至少一层氮化硅层。
层间介质层15设置于多根栅线1与多根数据线2之间。
层间介质层15可以为一层或多层结构。示例的，层间介质层15为一层结构，层间介质层15的材料例如可以包括氧化硅(SiOx)或氮化硅(SiNx)等。又示例的，层间介质层15为两层或两层以上的结构，层间介质层15包括至少一层氧化硅层和至少一层氮化硅层。
参见图8及图9所示，相关技术中，多根栅线1与多根第一数据线2’交叉设置，第一数据线2’位于栅线1远离衬底10的一侧，栅线1与第一数据线2’之间设置有隔离层16’，隔离层16’包括第一层间介质层15”和第一缓冲层11”。
由于栅线1的长度较长，尤其是大尺寸显示面板中，栅线1的长度更长，导致严重的压降问题。
由于压降的大小与导线的横截面积成反比(ΔU＝L/(σ*S)，ΔU为导线的压降，L为导线长度，σ为导线材料的电导率，S为导线的横截面积)，由此可见，为了降低上述压降，在栅线的材料选用具有较高的电导率σ的材料的情况下，可以通过增加栅线的横截面面积来实现降低上述压降的目的。基于此，在不会降低显示面板开口率的前提下，可以在衬底厚度方向上增大栅线1的厚度。在此情况下，由于栅线1的厚度较大，使得隔离层16’覆盖栅线1的部分相较于该绝缘层16’未覆盖栅线1的部分产生较大的段差。由此可见，栅线1的厚度越大，隔离层16’的段差便越大，较大的段差会导致隔离层16’的厚度不均匀，从而导致隔离层16’覆盖栅线1的部分较薄甚至一部分栅线1未被隔离层16’覆盖，使得隔离层16’对栅线1的覆盖率下降。
在此情况下，在隔离层16’上形成第一数据线2’时，由于隔离层16’的段差较大，一方面，第一数据线2’存在断线的风险；另一方面，由于栅线1和第一数据线2’分别设置在隔离层16’的两侧，由于隔离层16’的厚度不均匀，在栅线1和第一数据线2’交叠的位置周围，很容易因ESD(Electro-Static Discharge，静电放电)导致栅线1中的金属粒子穿过隔离层16’中厚度较小的部分漂移至第一数据线2’，从而使得第一数据线2’与栅线1发生DGS(Data Gate Short，数据线栅线短路)不良。
此外，由于工艺条件限制，位于栅线1与衬底10之间的膜层中存在 颗粒，使得栅线1的远离衬底10的表面不均匀，从而导致隔离层16’的不均匀，由此便进一步增大了隔离层16’的段差以及第一数据线2’的段差，使得产品良率进一步降低。
在本公开实施例提供的阵列基板200中，数据线2在第一方向上包括多个第一线段21以及多个第二线段22，多个第一线段21位于栅线1远离衬底10的一侧，多个第二线段22位于栅线1靠近衬底10的一侧，且绝缘层16包括多个第一过孔81，这使得第一方向上每相邻两个第一线段21通过至少两个第一过孔81与位于该相邻两个第一线段21之间的一个第二线段22电连接，从而使得第一方向上电连接的多个第一线段21和多个第二线段22形成一根数据线2。由于多个第一线段21在衬底10上的正投影与数据线2在衬底10上的正投影无交叠，每相邻两个第一线段21通过位于栅线1靠近衬底10一侧的第二线段22连接(即，数据线2在与栅线1交叠的部分从栅线1与衬底10之间穿过)，因而，数据线2不会上跨栅线1。由此，本公开实施例提供的阵列基板200，有效避免了由于栅线1厚度大或者膜层颗粒导致的数据线断线、DGS等不良问题的出现，有效提高了产品良率。
在一些实施例中，如图4所示，衬底10具有多个亚像素区P，阵列基板200还包括多个像素电路30，每个像素电路30设置于一个亚像素区P中，该像素电路30与一根栅线1以及一根数据线2电连接。
结合图4和图5所示，该像素电路30包括第一开关晶体管31。第一开关晶体管31包括第一栅极311、第一源极312、第一漏极313、第一有源层314、以及第一栅绝缘图案315。
第一开关晶体管31的第一栅极311与连接该像素电路30的栅线1同层同材料，第一开关晶体管31的第一源极312以及第一漏极313与第一线段21同层同材料。第一开关晶体管31的第一有源层314在衬底10上的正投影位于第一栅极311在衬底10上的正投影的范围内。
在一些示例中，如图5所示，第一开关晶体管31为顶栅型薄膜晶体管。在此情况下，第一开关晶体管31的第一有源层314位于第一栅极311靠近衬底10的一侧，层间介质层15位于第一源极312和第一漏极313所在层和栅极311之间，第一源极312和第一漏极313分别通过贯穿层间介质层15的第一连接过孔84与第一开关晶体管31的第一有源层314电连接。
在另一些示例中，第一开关晶体管31为底栅型薄膜晶体管。在此情 况下，第一开关晶体管31的第一有源层314位于第一栅极311远离衬底10的一侧，层间介质层15位于第一源极312和第一漏极313所在层与第一有源层314之间，第一源极312和第一漏极313分别通过贯穿层间介质层15的第一连接过孔84与第一开关晶体管31的第一有源层314电连接。此处，层间介质层15也可称为刻蚀阻挡层。
示例的，第一栅极311和栅线1的材料包括铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)和钨(W)等金属单质中的至少一种。即栅极311和栅线1可以由上述金属单质中的一种制成，或者由上述金属单质中的两种或两种以上金属单质构成的金属合金制成。
第一线段21、第一开关晶体管31的第一源极312以及第一漏极313的材料可以包括铜(Cu)或铝(Al)等金属单质。
在一些实施例中，如图4所示，沿第二方向(即行方向X)，第二线段22的宽度大于第一线段21的宽度。这样，可以保证第一线段21和第二线段22电连接的良率。
在一些实施例中，如图5所示，第一开关晶体管31为顶栅型薄膜晶体管。阵列基板200还包括：设置于衬底10上的多个第一金属遮光图案12。每个第一金属遮光图案12设置在对应的一个像素电路中第一开关晶体管31靠近衬底10的一侧。由于晶体管的有源层对对光线较为敏感，在受到光照时电学性能易改变，因此设置第一开关晶体管31的第一有源层314的正投影位于第一金属遮光图案12在衬底10上的正投影的范围内，以使第一金属遮光图案12能够对射向第一有源层314的光线进行遮挡。
多个第二线段22与多个第一金属遮光图案12同层同材料，且相互绝缘。在一些示例中，沿衬底10的厚度方向，第二线段22的厚度等于第一金属遮光图案12的厚度。这样，尽可能减小位于第二线段22和第一金属遮光图案12一侧的缓冲层11的段差，防止由于缓冲层11的段差较大影响显示面板的产品良率。
第二线段22与第一金属遮光图案12的材料例如包括钼、铝等金属材料，具有遮光效果。第一有源层314的材料例如包括氧化铟镓锌(IGZO)、氧化铟镓(IGO)、氧化铟锡锌(ITZO)、氧化铝锌(AlZnO)、氧化锌(ZnO)或氧化镓锌(GZO)等金属氧化物。
可选的，如图5所示，绝缘层16还包括多个第二过孔82，第一开关晶体管31的第一源极312和第一漏极313中的其中一极通过至少一个 第二过孔82与第一金属遮光图案12电连接。
在一些示例中，如图5和图10所示，第一开关晶体管31的第一漏极313通过第二过孔82与第一金属遮光图案12电连接。
在另一些示例中，如图11所示，第一开关晶体管31的第一源极312通过第二过孔82与第一金属遮光图案12电连接。
第一开关晶体管31的第一源极312或第一漏极313与第一金属遮光图案12电连接，且第一源极312和第一漏极313还与第一开关晶体管31的第一有源层314电连接。这样，可以让第一金属遮光图案12上的感应电荷流向第一源极312和第一漏极313，避免对第一开关晶体管31的影响，并且，使得第一开关晶体管31的第一有源层314、第一源极312和第一漏极313处于同一电势，从而提升第一开关晶体管31的电学稳定性，改善第一开关晶体管31的电学性能。
在一些实施例中，如图12-图13所示，阵列基板200还包括设置于衬底10上的多个像素电极50，每个像素电极50设置于一亚像素区P中。
结合图12-图13所示，第一开关晶体管31的第一漏极313与像素电极50电连接。像素电极50设置于第一开关晶体管31的第一漏极313远离衬底10的一侧。
在一些示例中，像素电极50的材料可以为氧化铟锡(ITO)。
在一些实施例中，如图12-图13所示，阵列基板200还包括设置在像素电极50与第一开关晶体管31的第一漏极313之间的钝化层34和有机绝缘层35。像素电极50可以通过贯穿有机绝缘层35和钝化层34的第三连接过孔与第一开关晶体管31的第一漏极313电连接。
在一些示例中，钝化层34的材料可以包括无机材料，例如氮化硅；有机绝缘层35的材料可以包括有机高分子材料，例如亚克力。
在一些实施例中，如图14以及图15所示，阵列基板200还包括：设置于衬底10上的多个发光器件40，每个发光器件40设置于一个亚像素区P中，且发光器件40与位于亚像素区P中的一个像素电路30连接。
在一些实施例中，如图6所示，像素电路30还包括一个驱动晶体管32，驱动晶体管32为上述顶栅型薄膜晶体管。
如图7所示，驱动晶体管32包括第二有源层324、设置于第二有源层324远离衬底10一侧的第二栅绝缘图案325和第二栅极321、以第二源极322和第二漏极323。第二源极322和第二漏极323分别通过层间绝缘层15中的至少一个第二连接过孔85与驱动晶体管32的第二有源层 324接触。第二有源层324的材料例如包括氧化铟镓锌(IGZO)、氧化铟镓(IGO)、氧化铟锡锌(ITZO)、氧化铝锌(AlZnO)、氧化锌(ZnO)、氧化镓锌(GZO)等金属氧化物。
结合图6和图7所示，阵列基板200还包括：设置于衬底10上的多个第二金属遮光图案13。每个第二金属遮光图案13设置在对应的一个像素电路30中的驱动晶体管32靠近衬底10的一侧。驱动晶体管32的第二有源层324的正投影位于第二金属遮光图案13在衬底10上的正投影的范围内，以便第二金属遮光图案13能够对射向第二有源层324的光线进行遮挡。
多个第二线段22与多个第二金属遮光图案13同层同材料，且相互绝缘。第二线段22与第二金属遮光图案13的材料例如包括钼、铝等具有遮光效果的金属材料。
需要说明的是，在多个第二线段22与多个第一金属遮光图案12同层设置的情况下，多个第二金属遮光图案13、多个第一金属遮光图案12，以及多个第二线段22同层设置。
在一些实施例中，如图7所示，驱动晶体管32的第二栅极321、第一开关晶体管31的第一栅极311、以及栅线1同层同材料。驱动晶体管32的第二源极322和第二漏极323、第一开关晶体管31的第一源极312和第一漏极313、以及第一线段21同层同材料。
在一些实施例中，如图7所示，驱动晶体管32的第二源极322和第二漏极323中的其中一极通过一个第四过孔86与位于驱动晶体管32靠近衬底10一侧的第二金属遮光图案13电连接。在一些实施例中，如图6以及图7所示，阵列基板200还包括：与多个像素电路30电连接的多根电源线9。电源线9沿第一方向Y延伸。
多根电源线9中的一根电源线9包括沿第一方向延伸的多个第三线段91和多个第四线段92，且该多个第三线段91和该多个第四线段92交替排布。示例的，每根电源线9包括沿第一方向延伸的多个第三线段91和多个第四线段92，且该多个第三线段91和该多个第四线段92交替排布。
多个第三线段91在衬底10上的正投影与多根栅线1在衬底10上的正投影无交叠，每个第四线段92在衬底10上的正投影与对应的一根栅线1在衬底10上的正投影重叠。多个第三线段91与多个第一线段21同层同材料，多个第四线段92与第二线段22同层同材料。绝缘层16还包 括多个第三过孔83。沿第一方向Y，每相邻两个第三线段91通过至少两个第三过孔83与位于该两个第三线段91之间的一个第四线段92电连接。
在一些示例中，电源线9与像素电路30中的驱动晶体管32的第二源极322电连接。在此情况下，对于2T1C结构的像素电路30，驱动晶体管32的第二漏极323与发光器件40电连接。
在另一些示例中，如图7所示，电源线9与像素电路30中的驱动晶体管32的第二漏极323电连接。在此情况下，对于2T1C结构的像素电路30，驱动晶体管32的第二源极322与发光器件40电连接。
在一些实施例中，沿第二方向X，第四线段92的宽度大于第三线段91的宽度，以保证第三线段91和第四线段92电连接的良率。在第二线段22与第一金属遮光图案12和第二金属遮光图案13同层设置的情况下，第四线段92、第二线段22、第二金属遮光图案13、以及第一金属遮光图案12同层设置。
在一些实施例中，如图7所示，第三线段91、第一线段21、驱动晶体管32的第二源极322和第二漏极323、以及第一开关晶体管31的第一源极312和第一漏极313同层设置。
与数据线2的设置方式类似，本公开的实施例中，在第一方向Y上将电源线9分为多个第三线段91以及多个第四线段92，多个第三线段91位于栅线1远离衬底10的一侧，多个第四线段92位于栅线1靠近衬底10的一侧，且在绝缘层16上设置多个第三过孔83，使得第一方向上每相邻两个第三线段91通过至少两个第三过孔83与位于该相邻两个第三线段91之间的一个第四线段92电连接，使得第一方向上的多个第三线段91和多个第四线段92电连接以形成一根电源线9。在此情况下，即使绝缘层16的段差较大，也能够有效地避免由于上述段差导致电源线9出现厚度不均匀性的情况，保证电源线9厚度的均匀性，提高显示面板的良率。
在一些实施例中，电源线9与像素电路30中的驱动晶体管32的第二源极322电连接，驱动晶体管32的第二漏极323与发光器件40的阳极41电连接。
在一些示例中，阳极40的材料包括ITO(氧化铟锡)。
在一些实施例中，像素电路30还包括至少一个第二开关晶体管，第二开关晶体管为顶栅型薄膜晶体管，在此情况下，第二开关晶体管和衬 底10之间还可以设置有第三金属遮光图案，第三金属遮光图案在衬底10上的正投影覆盖第二开关晶体管的有源层的正投影，第三金属遮光图案与第一金属遮光图案12同层同材料，且相互绝缘。
本公开的一些实施例还提供一种阵列基板的制备方法，如图16所示，包括如下步骤：
S10、在衬底10上，形成多个第二线段22。
参考图4-图7，提供衬底10，在衬底10上沿第二方向X形成多列第二线段22。每列第二线段22包括沿第一方向Y延伸且间隔设置的多个第二线段22。第一方向和第二方向交叉设置。
在一些示例中，第一方向和第二方向垂直。
在一些实施例中，形成多个第二线段22之后，在形成有多个第二线段22的衬底10上形成多个像素电路30。
像素电路30包括第一开关晶体管31。第一开关晶体管31的结构可以参见上述实施例中关于第一开关晶体管31的描述，此处不再赘述。
在一些实施例中，如图17中a部分所示，在衬底10上通过一次构图工艺形成多个第二线段22以及多个第一金属遮光图案12，多个第二线段22与多个第一金属遮光图案12相互绝缘。第一开关晶体管31的第一有源层314在衬底10上的正投影位于对应的一个第一金属遮光图案12在衬底10上的正投影的范围内。
在一些示例中，第一金属遮光图案12与第二线段22的厚度相同，以便于后续步骤S20中，在第一金属遮光图案12与第二线段22上形成缓冲薄膜11’，保证缓冲薄膜11’在沿衬底10厚度方向上的厚度均匀。
在一些实施例中，像素电路30还包括一个驱动晶体管32。如图17中a部分所示，可以通过一次构图工艺在衬底10形成多个第二线段22、多个第一金属遮光图案12、以及多个第二金属遮光图案13，多个第二线段22、多个第一金属遮光图案12、以及多个第二金属遮光图案13相互绝缘。驱动晶体管32的第二有源层324的正投影位于对应的一个第二金属遮光图案13在衬底10上的正投影的范围内。
第一金属遮光图案12、第二线段22以及第二金属遮光图案13的厚度可以相同。
在一些示例中，第二线段22的材料包括钼、铝等具有遮光效果的金属材料。第一金属遮光图案12和第二金属遮光图案13的材料与第二线 段22的材料相同。
S20、在形成有多个第二线段22的衬底10上形成多根线栅1，多根栅线1均沿第二方向X延伸。
参考图4-图7，在形成有多个第二线段22的衬底10上，形成沿第一方向Y排布的多根栅线1，每根栅线1沿第二方向X延伸。
在一些实施例中，多根栅线2与第一开关晶体管31的第一栅极311通过同一次构图工艺形成。
在另一些实施例中，多根栅线2、第一开关晶体管31的第一栅极311、以及驱动晶体管32的第二栅极321通过同一次构图工艺形成。
栅线2的材料例如可以包括铜、铝、钼、钛、铬和钨的金属单质中的至少一种。
S30、在形成有多个第二线段22的衬底10上形成绝缘层16，该绝缘层包括多个第一过孔81。
参考图5和图7，第一过孔81用于使第二线段22与后续形成的第一线段21电连接。
参见图17中g部分所示，第一过孔81暴露出第二线段22的部分区域。
S40、在形成有绝缘层16的衬底10上形成多个第一线段21。
参考图4-图7，多个第一线段21在衬底10上的正投影与多根栅线1在衬底10上的正投影无交叠。多个第一线段21沿第二方向X排布成多列，每列的多个第一线段21沿第一方向延伸且间隔设置。沿第一方向Y，每相邻两个第一线段21通过至少两个第一过孔81与位于二者之间的一个第二线段22电连接。每列中电连接的所有第一线段21和所有第二线段22构成一根数据线2。
在一些实施例中，多个第一线段21与第一开关晶体管31的第一源极312和第一漏极313可通过同一次构图工艺形成。
在另一些实施例中，参见图17中h部分所示，多个第一线段21、第一开关晶体管31的第一源极312和第一漏极313、以及驱动晶体管32的第二源极322和第二漏极323可通过同一次构图工艺形成。
第一线段21的材料例如可以包括铜或铝等金属单质。
在一些实施例中，绝缘层16包括缓冲层11和层间介质层15。
如图17中b部分所示，在形成多个第二线段22之后，形成多根线栅1之前，在衬底10上形成缓冲薄膜11’。缓冲薄膜11’可以为一层或 多层结构。示例性地，缓冲薄膜11’为一层结构，缓冲薄膜11’的材料为氧化硅(SiOx)或氮化硅(SiNx)等。缓冲薄膜11’为两层或两层以上的结构，缓冲薄膜11’例如为氧化硅层和氮化硅层的复合膜层。
在一些实施例中，在缓冲薄膜11’上，通过一次构图工艺形成第一开关晶体管31的第一有源层314。
在另一些实施例中，参见图17中c部分所示，在缓冲薄膜11’上，通过一次构图工艺形成第一开关晶体管31的第一有源层314以及驱动晶体管32的第二有源层324。
缓冲薄膜11’可防止衬底10中的有害杂质以及离子扩散到第一开关晶体管31的第一有源层314以及驱动晶体管32的第二有源层324中。
第一开关晶体管31的第一有源层314的材料例如包括氧化铟镓锌、氧化铟镓、氧化铟锡锌、氧化铝锌、氧化锌、或氧化镓锌等金属氧化物。
驱动晶体管32的第二有源层324的材料例如包括氧化铟镓锌、氧化铟镓、氧化铟锡锌、氧化铝锌、氧化锌、或氧化镓锌等金属氧化物。
在一些实施例中，在形成有第一有源层314的衬底10上形成栅绝缘薄膜，并以第一栅极311和栅线1为掩膜对该栅绝缘薄膜进行构图，形成第一开关晶体管31的第一栅绝缘图案315和保留图案14，该保留图案14与栅线1在衬底10上的正投影重叠。
在另一些实施例中，参见图17中d部分和e部分所示，在形成有第一有源层314和第二有源层324的缓冲薄膜11’上形成栅绝缘薄膜330，并以第一栅极311、第二栅极321和栅线1对该栅绝缘薄膜330进行构图，形成第一开关晶体管31的第一栅绝缘图案315、驱动晶体管32的第二栅绝缘图案325和保留图案14，该保留图案14与栅线1在衬底10上的正投影重叠。
当然，在形成栅绝缘薄膜330后，也可以不对栅绝缘薄膜330进行构图，在此情况下，上述第一栅绝缘图案315、第二栅绝缘图案325以及保留图案14为一体结构。
栅绝缘薄膜330的材料例如包括氮化硅、氧化硅、氧化铝(Al 2O 3)、以及氮化铝(AlN)中的至少一种。
可以理解的是，在形成第一开关晶体管31的第一栅极311和第一栅绝缘图案315之后，对第一开关晶体管31的第一有源层314中未被第一栅极311覆盖的部分进行导体化处理，从而增加第一有源层314中与第一源极312和第一漏极313接触部分的导电性。示例性地，导体化处理 的方式可以是利用等离子体轰击第一开关晶体管31的第一有源层314超出第一栅极311的部分，轰击出氧离子，使第一有源层314的该部分导体化。其中，形成等离子体的气体包括保护性气氛或者反应性气氛。保护性气体例如可以包括：氮气、氩气、氦气、氖气中的一种或者混合气体，反应性气体例如可以包括：空气、氧气、氢气、氨气、二氧化碳中的一种或者混合气体。
当然，在形成驱动晶体管32的第二栅极321和第二栅绝缘图案325之后，对驱动晶体管32的第二有源层324中未被第二栅极321覆盖的部分进行导体化处理，从而增加第二有源层324中与第二源极322和第一漏极323接触部分的导电性。
在对第一开关晶体管31的第一有源层314的部分进行导体化处理时，也可以采用同样的方式对驱动晶体管32的第二有源层324中未被第二栅极321覆盖的部分进行上述导体化处理。参见图17中f部分所示，在形成栅线1之后，在形成有栅线1的缓冲薄膜11’上形成层间介质薄膜15’，然后对层间介质薄膜15’和缓冲薄膜11’进行构图，如图17中g部分所示，形成层间介质层15和缓冲层11。第一过孔81贯穿层间介质层15和缓冲层11，以使沿第一方向每相邻两个第一线段21通过至少两个第一过孔81与位于该相邻两个第一线段21之间的一个第二线段22电连接。
此外，在形成第一过孔81的过程中，还形成贯穿层间介质层15的多个第一连接过孔84，这样，第一源极312和第一漏极313可分别通过一个第一连接过孔84与第一有源层314接触。
当然，在形成第一过孔81的过程中，还形成贯穿层间介质层15的多个第一连接过孔84和多个第二连接过孔85。这样，第一源极312和第一漏极313可分别通过一个第一连接过孔84与第一有源层314接触，第二源极322和第二漏极323可分别通过一个第二连接过孔85与第二有源层324接触。
在一些实施例中，在形成第一过孔81的过程中，还形成贯穿缓冲层11和层间介质层15的多个第二过孔82。第一开关晶体管31的第一源极312和第一漏极313中的其中一极通过第二过孔82与第一金属遮光图案12电连接。
在另一些实施例中，在形成第一过孔81的过程中，还形成贯穿缓冲 层11和层间介质层15的多个第二过孔82和多个第四过孔86。第一开关晶体管31的第一源极312和第一漏极313中的其中一极通过第二过孔82与第一金属遮光图案12电连接。驱动晶体管32的第二源极322和第二漏极323中的其中一极通过一个第四过孔86与第二金属遮光图案13电连接。
在一些实施例中，阵列基板的制备方法还包括：参考图14所示，形成多根电源线。每根电源线9包括沿第一方向延伸的多个第三线段91和多个第四线段92，且该多个第三线段91和该多个第四线段92交替排布。
多个第三线段91在衬底10上的正投影与多根栅线1在衬底10上的正投影无交叠，每个第四线段92在衬底10上的正投影与对应的一根栅线1在衬底10上的正投影重叠。多个第三线段91与多个第一线段21通过同一次构图工艺形成，多个第四线段92与第二线段22通过同一次构图工艺形成。
绝缘层16还包括多个第三过孔83。沿第一方向，每相邻两个第三线段91通过至少两个第三过孔83与位于该两个第三线段91之间的一个第四线段92电连接。
在一些示例中，电源线9与像素电路30中的驱动晶体管32的第二源极322电连接。
需要说明的是，对于电源线9的具体结构可参考上述阵列基板200中电源线9的结构，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种阵列基板，包括：
    衬底；
    设置于所述衬底上的多根栅线和多根数据线；所述多根数据线均沿第一方向延伸，所述多根栅线均沿第二方向延伸，所述第一方向和所述第二方向交叉设置；所述多根数据线中的至少一根数据线包括沿所述第一方向延伸的多个第一线段以及多个第二线段，所述多个第一线段和所述多个第二线段交替排布；所述多个第二线段设置于所述多根栅线靠近所述衬底的一侧，所述多个第一线段设置于所述多根栅线远离所述衬底一侧，且所述多个第一线段在所述衬底上的正投影与所述多根栅线在所述衬底上的正投影无交叠；
    设置于所述多个第一线段和所述多个第二线段之间的绝缘层，所述绝缘层包括多个第一过孔；其中，沿所述第一方向，每相邻两个第一线段通过至少两个第一过孔与位于二者之间的一个第二线段电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述衬底具有多个亚像素区；
    所述阵列基板还包括：
    设置于所述衬底上的多个像素电路，每个像素电路设置于一个亚像素区中，所述像素电路与一根栅线和一根数据线电连接；其中，
    所述像素电路包括第一开关晶体管，所述第一开关晶体管的第一栅极与所述栅线同层同材料，所述多个第一线段与所述第一开关晶体管的第一源极和第一漏极同层同材料。
  3. 根据权利要求1或2所述的阵列基板，其中，沿所述第二方向，所述第二线段的宽度大于所述第一线段的宽度。
  4. 根据权利要求1-3任一项所述的阵列基板，其中，所述第一开关晶体管为顶栅型薄膜晶体管；
    所述阵列基板还包括：
    设置于所述衬底上的多个第一金属遮光图案；每个第一金属遮光图案设置在对应的一个像素电路中所述第一开关晶体管靠近所述衬底一侧，所述像素电路中所述第一开关晶体管的第一有源层在所述衬底上的正投影位于所述第一金属遮光图案在所述衬底上的正投影的范围内；
    所述多个第二线段与所述多个第一金属遮光图案同层同材料，且相互绝缘。
  5. 根据权利要求4所述的阵列基板，其中，所述绝缘层还包括多个 第二过孔，所述第一开关晶体管的第一源极和第一漏极中的其中一极通过至少一个第二过孔与所述第一金属遮光图案电连接。
  6. 根据权利要求4或5所述的阵列基板，其中，沿所述衬底的厚度方向，所述第二线段的厚度等于所述第一金属遮光图案的厚度。
  7. 根据权利要求2-6任一项所述的阵列基板，还包括：
    设置于所述衬底上的多个像素电极，每个像素电极设置于一个亚像素区中；其中，
    所述第一开关晶体管的第一源极与所述数据线电连接，所述第一开关晶体管的第一漏极与所述像素电极电连接；所述像素电极设置于所述第一漏极远离所述衬底的一侧。
  8. 根据权利要求2-6任一项所述的阵列基板，还包括：
    设置于所述衬底上的多个发光器件，每个发光器件设置于一个亚像素区中，且所述发光器件与对应的一个所述像素电路连接。
  9. 根据权利要求8所述的阵列基板，其中，所述像素电路还包括一个驱动晶体管，所述驱动晶体管为顶栅型薄膜晶体管；
    所述阵列基板还包括：
    设置于所述衬底上的多个第二金属遮光图案，每个第二金属遮光图案设置在对应的一个所述像素电路中所述驱动晶体管靠近所述衬底一侧，所述驱动晶体管的第二有源层的正投影位于所述第二金属遮光图案在所述衬底上的正投影的范围内；其中，
    所述多个第二线段以及所述多个第二金属遮光图案同层同材料，且相互绝缘。
  10. 根据权利要求9所述的阵列基板，还包括：
    多根电源线，所述多根电源线均沿所述第一方向延伸，所述像素电路与一个电源线电连接；
    所述多根电源线中的一根电源线包括沿所述第一方向延伸的多个第三线段和多个第四线段，所述多个第三线段和所述多个第四线段交替排布；所述多个第三线段在所述衬底上的正投影与所述多根栅线在所述衬底上的正投影无交叠；所述多个第三线段与所述多个第一线段同层同材料，所述多个第四线段与所述多个第二线段同层同材料；
    所述绝缘层还包括多个第三过孔，沿所述第一方向，每相邻两个第三线段通过至少两个第三过孔与位于二者之间的一个第四线段电连接。
  11. 根据权利要求10所述的阵列基板，其中，沿所述第二方向，所 述第四线段的宽度大于所述第三线段的宽度。
  12. 根据权利要求10所述的阵列基板，其中，所述电源线与所述像素电路中的驱动晶体管的第二源极电连接，所述驱动晶体管的第二漏极与所述发光器件的阳极电连接。
  13. 根据权利要求1-12任一项所述的阵列基板，其中，所述绝缘层包括层叠设置在所述衬底上的缓冲层和层间介质层。
  14. 一种显示装置，包括权利要求1-13任一项所述的阵列基板。
  15. 一种阵列基板的制备方法，包括：
    提供衬底；在所述衬底上形成多个第二线段；所述多个第二线段沿第二方向排布成多列第二线段，每列第二线段包括沿第一方向延伸且间隔设置的多个第二线段；所述第一方向和所述第二方向交叉设置；
    在形成有所述多个第二线段的衬底上形成多根栅线，所述多根栅线均沿所述第二方向延伸；
    然后在形成有所述多个第二线段的衬底上形成绝缘层，所述绝缘层包括多个第一过孔；
    在形成有所述绝缘层的衬底上形成多个第一线段，所述多个第一线段在所述衬底上的正投影与所述多根栅线在所述衬底上的正投影无交叠；所述多个第一线段沿第二方向排布成多列第一线段，每列第一线段包括沿第一方向延伸且间隔设置的多个第一线段，且沿所述第一方向，每相邻两个第一线段通过至少两个第一过孔与位于二者之间的一个第二线段电连接；每列中电连接的所有所述第一线段和所有所述第二线段构成一根数据线。
  16. 根据权利要求15所述的阵列基板的制备方法，形成多个第二线段之后，所述方法还包括：
    在形成有所述多个第二线段的所述衬底上形成多个像素电路，每个像素电路位于一个亚像素区中，所述像素电路包括第一开关晶体管；其中，
    所述多根栅线与第一开关晶体管的第一栅极通过同一次构图工艺形成；
    所述多个第一线段与所述第一开关晶体管的第一源极和第一漏极通过同一次构图工艺形成。
  17. 根据权利要求16所述的阵列基板的制备方法，所述绝缘层包括缓冲层和层间介质层；形成绝缘层，包括：
    在形成所述多个第二线段之后，形成所述多根栅线之前，形成缓冲薄膜；
    在形成所述多根栅线之后，形成层间介质薄膜；
    对所述层间介质薄膜和所述缓冲薄膜进行构图，形成包括所述多个第一过孔的所述层间介质层和所述缓冲层。
  18. 根据权利要求16或17所述的阵列基板的制备方法，其中，形成多个第二线段包括：通过一次构图工艺形成多个第二线段，以及多个第一金属遮光图案，所述多个第二线段与所述多个第一金属遮光图案相互绝缘；
    所述像素电路中所述第一开关晶体管的第一有源层在所述衬底上的正投影位于对应的一个第一金属遮光图案在所述衬底上的正投影的范围内。
  19. 根据权利要求18所述的阵列基板的制备方法，其中，所述绝缘层包括缓冲层和层间介质层；
    对所述层间介质薄膜和所述缓冲薄膜进行构图，形成包括所述多个第一过孔的所述层间介质层和所述缓冲层，包括：对所述层间介质薄膜和所述缓冲薄膜进行构图，形成包括所述多个第一过孔和多个第二过孔的所述层间介质层和所述缓冲层；
    所述第一开关晶体管的第一源极和第一漏极中的其中一极通过所述第二过孔与第一金属遮光图案电连接。
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