WO2020084687A1 - Dispositif optique intégré à semi-conducteur - Google Patents

Dispositif optique intégré à semi-conducteur Download PDF

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WO2020084687A1
WO2020084687A1 PCT/JP2018/039350 JP2018039350W WO2020084687A1 WO 2020084687 A1 WO2020084687 A1 WO 2020084687A1 JP 2018039350 W JP2018039350 W JP 2018039350W WO 2020084687 A1 WO2020084687 A1 WO 2020084687A1
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layer
type
integrated device
optical integrated
semiconductor optical
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PCT/JP2018/039350
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English (en)
Japanese (ja)
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直幹 中村
八木　哲哉
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三菱電機株式会社
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Priority to PCT/JP2018/039350 priority Critical patent/WO2020084687A1/fr
Priority to JP2020505940A priority patent/JPWO2020084858A1/ja
Priority to PCT/JP2019/030503 priority patent/WO2020084858A1/fr
Priority to TW108137224A priority patent/TW202017269A/zh
Publication of WO2020084687A1 publication Critical patent/WO2020084687A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30

Definitions

  • the present application relates to a semiconductor optical integrated device in which a plurality of optical semiconductor devices are integrated.
  • Patent Document 1 discloses a structure in which a semi-insulating Fe-doped InP layer and an n-type InP layer are stacked on an n-type InP substrate having conductivity, and an active layer and a p-type InP layer are stacked thereon.
  • a method for ensuring insulation between cathodes between adjacent elements by providing a cathode electrode in the n-type InP layer and an anode electrode in the p-type InP layer and forming a groove reaching the Fe-doped InP layer between the elements Is disclosed.
  • Patent Document 2 as a method for ensuring insulation between adjacent elements, a p-type-n-type-p type or an n-type-p-type-n structure is provided on a substrate and There is disclosed a method of ensuring cathode-to-cathode isolation between devices by forming a groove reaching the substrate.
  • JP-A-8-046279 (paragraphs 0025 to 0031, FIG. 1) Japanese Patent Laid-Open No. 11-274634 (paragraphs 0028 to 0110, FIG. 1)
  • Patent Document 1 in consideration of the energy band structure of each layer, at the junction boundary between the n-type InP layer and the Fe-doped InP layer or the p-type InP layer, a potential barrier for an electron that is a carrier for the n-type conductivity type is provided. Form. When the potential barrier is formed, it cannot penetrate into the Fe-doped InP layer or the p-type InP layer.
  • the amount of current (the amount of electrons) supplied to the n-type InP layer increases, there are not a few electrons that have the energy to overcome the potential barrier, which causes a leakage current and reduces the insulation between the elements.
  • the current supplied to the n-type InP layer cannot sufficiently block the current leaking toward the substrate only by inserting the Fe-doped InP layer or the p-type InP layer.
  • a leakage current flows between the cathode electrodes and the isolation cannot be secured.
  • the p-type InP layer is doped at a higher concentration in order to increase the potential barrier, but if a thick p-type-doped layer exists near the active layer, a p-type layer is formed. Light loss increases due to carrier absorption or valence band absorption by the carriers that are generated. Therefore, there is a problem that the optical output characteristics of the laser deteriorate.
  • Patent Document 2 has a problem that the structure is not suitable for manufacturing an element, for example, the layer thickness of each layer is 3 ⁇ m and a considerable layer thickness is required from the viewpoint of crystal growth.
  • the present application discloses a technique for solving the above problems, and suppresses a leakage current through a substrate and absorption loss of light, secures isolation, and is suitable for manufacturing an element.
  • An object is to provide a semiconductor optical integrated device that can realize a structure.
  • a semiconductor optical integrated device disclosed in the present application includes an epitaxial layer in which a material having a wider bandgap than that of the InP substrate is epitaxially grown on a surface of an InP substrate, and an isoform formed on the surface of the epitaxial layer and reaching the epitaxial layer.
  • a plurality of optical semiconductor elements which are arranged in a row and sandwich a groove.
  • an isolation groove that reaches an epitaxial layer made of a material having a bandgap wider than that of an InP substrate between the optical semiconductor elements, leakage current and light absorption loss through the substrate are suppressed, It is possible to secure isolation and realize a structure suitable for manufacturing an element.
  • FIG. 1 is a perspective view showing a configuration of a semiconductor optical integrated device according to a first embodiment.
  • FIG. 3 is a sectional view and a potential distribution diagram showing the configuration of the semiconductor optical integrated device according to the first embodiment.
  • FIG. 9 is a cross-sectional view and a potential distribution diagram showing a configuration of a conventional semiconductor optical integrated device.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the first embodiment.
  • FIG. 4 is a diagram showing an example of a result of simulating an isolation resistance in the structure of the semiconductor optical integrated device according to the first embodiment.
  • FIG. 9 is a cross-sectional view showing a configuration of a semiconductor optical integrated device according to a second embodiment.
  • FIG. 9 is a cross-sectional view showing a configuration of a semiconductor optical integrated device according to a second embodiment. It is sectional drawing which shows the structure of the conventional semiconductor optical integrated device. It is sectional drawing which shows the structure of the conventional semiconductor optical integrated device.
  • FIG. 10 is a diagram showing an example of a result of simulating an isolation resistance in the structure of the semiconductor optical integrated device according to the second embodiment.
  • FIG. 10 is a diagram showing an example of a result of simulating an isolation resistance in the structure of the semiconductor optical integrated device according to the second embodiment.
  • FIG. 9 is a sectional view showing a configuration of a semiconductor optical integrated device according to a third embodiment.
  • FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the third embodiment.
  • FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the third embodiment.
  • FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor optical integrated device according to the third embodiment.
  • FIG. 1 is a perspective view showing the configuration of the semiconductor optical integrated device according to the first embodiment.
  • 2A is a cross-sectional view of the semiconductor optical integrated device at the position of arrow AA in FIG.
  • the semiconductor optical integrated device 501 is an array type optical semiconductor device formed on a semi-insulating semiconductor substrate, and includes an Fe-doped semi-insulating InP substrate 101 and an Fe-doped semi-insulating InP substrate.
  • P-type AlInAs layer 102 formed on the surface of 101, n-type InP clad layer 103 provided on the p-type AlInAs layer 102 and provided with a ridge 103a, and ridge 103a of the n-type InP clad 103
  • the active layer 104 formed above, the ridge portion 103a and the current blocking layer 105 provided on both sides of the active layer 104, and the p formed on the active layer 104 at the top of the ridge portion 103a sandwiched by the current blocking layers 105.
  • the InP cladding layer 106 is formed.
  • the semiconductor optical integrated device 501 includes a plurality of semiconductor laser devices 120 as a semiconductor device including the n-type InP clad layer 103, the active layer 104, the current blocking layer 105, and the p-type InP clad layer.
  • the anode electrode 108 is provided on the surface of the p-type InP clad layer at the top of the ridge portion 103a
  • the cathode electrode 109 is provided on the n-type InP clad layer 103 beside the ridge portion 103a.
  • an isolation groove 110 whose bottom reaches the surface of the p-type AlInAs layer 102 is provided between the semiconductor laser devices 120, and each semiconductor laser device 120 is electrically separated by the isolation groove 110. It is designed to be insulated.
  • An insulating film 107 is formed on the surface of the semiconductor optical integrated device 501 except for the portion where the anode electrode 108 and the cathode electrode 109 are provided.
  • the Fe-doped semi-insulating InP substrate 101 is a semi-insulating semiconductor substrate, and is a Fe-doped semi-insulating InP substrate.
  • the p-type AlInAs layer 102 is an epitaxial layer formed on the surface of the Fe-doped semi-insulating InP substrate 101 and made of a material having a wider band gap than the semiconductor material InP used for the semi-insulating semiconductor substrate.
  • the n-type InP clad layer 103 is laminated on the p-type AlInAs layer 102, and the ridge portion 103a is provided on the surface.
  • An active layer 104 is formed on the ridge portion 103a of the n-type InP clad layer 103, and current blocking layers 105 are provided on both sides of the ridge portion 103a and the active layer 104.
  • a quaternary mixed crystal semiconductor material such as InGaAsP is used.
  • the current blocking layer 105 constricts the current in the ridge 103a portion in order to increase the luminous efficiency of the active layer 104.
  • the p-type InP clad layer 106 is formed on the active layer 104 at the top of the ridge 103 a sandwiched by the current blocking layers 105.
  • FIG. 2B is a diagram showing a potential distribution in the Fe-doped semi-insulating InP substrate 101, the p-type AlInAs layer 102, and the n-type InP clad layer 103 in the semiconductor optical integrated device 501.
  • VB is a valence band
  • CB is a conduction band energy band.
  • bands are discontinuous at the interface between the Fe-doped semi-insulating InP substrate 101 and the p-type AlInAs layer 102, and the interface between the p-type AlInAs layer 102 and the n-type InP clad layer 103.
  • the potential for electrons E is increased between the n-type InP clad layer 103 and the Fe-doped semi-insulating InP substrate 101. Barriers can be provided. Due to this potential barrier, the electrons E are less likely to leak to the Fe-doped semi-insulating InP substrate side, and insulation can be secured.
  • the p-type AlInAs layer 102 serves as a layer for suppressing leakage current.
  • the carrier concentration of the p-type AlInAs layer may be any carrier concentration as long as it is p-type.
  • the p-type AlInAs layer can maintain a potential barrier for electrons regardless of the carrier concentration, and can suppress leakage current of electrons into the Fe-doped semi-insulating InP substrate 101.
  • FIG. 3A is a sectional view showing the structure of a conventional semiconductor optical integrated device
  • FIG. 3B is a Fe-doped semi-insulating InP substrate 101 and p-type InP layer 111 in the semiconductor optical integrated device 501.
  • 3 is a diagram showing a potential distribution in the n-type InP clad layer 103.
  • FIG. 3B VB is a valence band and CB is a conduction band energy band.
  • FIGS. 4 to 15 are sectional views showing the manufacturing steps of the semiconductor optical integrated device 501 according to the first embodiment.
  • AlInAs 102, n-type InP clad layer 103, active layer 104, and p-type InP clad layer 106 are sequentially laminated on the surface of Fe-doped semi-insulating InP substrate 101 by epitaxial growth. These are crystal-grown by a metal organic chemical vapor deposition (MOCVD, hereinafter MOCVD) method.
  • MOCVD metal organic chemical vapor deposition
  • an insulating film is formed on the surface of the p-type InP clad layer 106 and is etched to form a stripe-shaped insulating film 112. To form.
  • the p-type InP clad layer 106 and the active layer 104 are etched into stripes using the formed insulating film 112 as a mask, and the n-type InP clad layer 103 is formed to a thickness of about half the film thickness. Etching is performed up to the position in a stripe shape to form a ridge portion 103a in the n-type InP clad layer 103.
  • the insulating film 112 used for forming the ridge portion 103a is used as a mask to fill the n-type InP clad layer 103 with the current block layer 105 on both sides of the p-type InP clad layer 106.
  • Epitaxial growth is performed up to the position by the MOCVD method.
  • the insulating film 112 used as a mask for processing and forming the ridge portion 103a and growing the current blocking layer 105 is removed.
  • an etching solution such as hydrofluoric acid is used.
  • the p-type InP clad layer 106 is further epitaxially grown on the exposed p-type InP clad layer 106 and the current blocking layer 105.
  • an insulating film is formed on the entire surface of the grown p-type InP clad layer 106, and the active layer 104 and the current blocking layers 105 on both sides of the active layer 104 are partially included in the width. Etching is done in stripes.
  • the p-type InP clad layer 106 and the current block layer 105 are etched by using the formed insulating film 114 as a mask so as to reach the root portion of the ridge portion 103a of the n-type InP clad layer 103. , Mesa groove 115b is provided. After the etching process, the insulating film 114 is removed by etching with hydrofluoric acid or the like.
  • an insulating film 116 is formed on the entire surface provided with the mesa groove 115b, and the insulating film 116 covering the n-type InP clad layer 103 is etched at the bottom of the mesa groove 115b.
  • a striped opening portion 116a is formed in a portion of the insulating film 116 that covers the n-type InP cladding layer 103.
  • the n-type InP clad layer 103 is etched through the openings 116a to reach the surface of the p-type AlInAs layer 102, and the isolation groove 110 is formed. .
  • the insulating film 116 is removed by etching with hydrofluoric acid or the like.
  • an insulating film 107 is formed on the entire surface of the mesa groove 115b in which the isolation groove 110 is formed.
  • the film 107 is etched to form stripe-shaped openings 107a and 107b in the insulating film 107 portion covering the p-type InP clad layer 106 and the n-type InP clad layer 103, respectively.
  • an anode electrode 108 connected to the p-type InP clad layer 106 is formed in the opening 107a, and a cathode electrode 109 connected to the n-type InP clad layer 103 is formed in the opening 107b.
  • a semiconductor optical integrated device 501 as shown in a) is obtained.
  • a laser having a buried waveguide structure has been described here, a laser having a ridge waveguide structure may be used.
  • FIG. 16 is a diagram showing an example of the result of simulating the isolation resistance in the structure of the semiconductor optical integrated device 501 according to the first embodiment, in which a voltage is applied to the electrodes between the adjacent cathodes and the voltage between the cathodes at that time is applied. Indicates the resistance value.
  • the Fe-doped semi-insulating InP substrate 101 is doped with Fe at 5 ⁇ 10 16 cm ⁇ 3
  • the p-type AlInAs layer 102 has a film thickness of 100 nm
  • the carrier concentration is 5 ⁇ 10 5.
  • n-type InP cladding layer 103 has a carrier concentration of 1 ⁇ 10 18 cm -3.
  • the conventional semiconductor optical integrated device was simulated with the structure of FIG.
  • the p-type InP layer 111 has a film thickness of 100 nm and a carrier concentration of 5 ⁇ 10 16 cm ⁇ 3 .
  • the carrier concentration settings of the Fe-doped semi-insulating InP substrate 101 and the n-type InP clad layer 103 of the conventional semiconductor optical integrated device were the same as those of the simulation model of the semiconductor optical integrated device 501.
  • the curve 201 of the semiconductor optical integrated device 501 of the present application in which the p-type AlInAs layer 102 is inserted is larger than the curve 205 of the conventional semiconductor optical integrated device between the cathodes of the adjacent devices.
  • a resistance value can be realized.
  • the p-type AlInAs layer 102 has a film thickness of only 100 nm and the carrier concentration is 5 ⁇ 10 16 cm ⁇ 3, which is close to the undoped level. Is also appropriate from the viewpoint of manufacturing and from the viewpoint of suppressing light loss due to carrier absorption.
  • a material having a wider band gap than the Fe-doped semi-insulating InP substrate 101 is epitaxially grown on the surface of the Fe-doped semi-insulating InP substrate 101.
  • the p-type AlInAs layer 102 thus formed, and a plurality of semiconductor laser elements 120 formed on the surface of the p-type AlInAs layer 102 and arranged in rows with an isolation groove 110 reaching the p-type AlInAs layer 102 interposed therebetween.
  • Embodiment 2 Although the bottom of the isolation groove 110 reaches the surface of the p-type AlInAs layer 102 in the first embodiment, the second embodiment shows a case where the depth of the bottom of the isolation groove 110 is different.
  • 17 and 18 are sectional views showing the configuration of the semiconductor optical integrated device according to the second embodiment.
  • 19 and 20 are sectional views of a conventional semiconductor optical integrated device corresponding to FIGS. 17 and 18, respectively.
  • the bottom of the isolation groove 110 in the semiconductor optical integrated device 502 reaches the surface of the Fe-doped semi-insulating InP substrate 101, and in FIG. 18, the bottom of the isolation groove 110 in the semiconductor optical integrated device 503. However, the structure reaches the inside of the Fe-doped semi-insulating InP substrate 101.
  • Other configurations and manufacturing methods of the semiconductor optical integrated devices 502 and 503 according to the second embodiment are similar to those of the semiconductor optical integrated device 501 according to the first embodiment, and corresponding parts are designated by the same reference numerals and the description thereof will be omitted. Is omitted.
  • the conventional semiconductor optical integrated devices corresponding to the semiconductor optical integrated devices 502 and 503 respectively use the p-type InP layer 111 instead of the p-type AlInAs layer 102.
  • 21 and 22 are diagrams showing examples of results of simulation of isolation resistance in the structures of the semiconductor optical integrated devices 502 and 503 according to the second embodiment, respectively, in which a voltage is applied to adjacent cathode electrodes, The resistance value between the cathodes at that time is shown.
  • the conventional semiconductor optical integrated device was simulated by the structures of FIGS. 19 and 20, respectively. In the simulation, conditions such as carrier concentration of the Fe-doped semi-insulating InP substrate 101, the p-type AlInAs layer 102, the n-type InP clad layer 103, and the p-type InP layer 111 were the same as those in the first embodiment.
  • the bottom of the isolation groove 110 penetrates the p-type AlInAs layer 102 and reaches the surface of the Fe-doped semi-insulating InP substrate 101.
  • a larger resistance value can be realized when the applied voltage exceeds 1 V between the cathodes of the adjacent devices, as compared with the curve 206 of the conventional semiconductor optical integrated device.
  • the isolation groove 110 is etched so as to penetrate the p-type AlInAs layer 102 and removed, so that the band discontinuity generated between the n-type InP clad layer 103 and the p-type AlInAs layer 102 is formed. Since the current path flowing therethrough can be cut off, the resistance can be further increased. Further, the etching depth including the boundary between the n-type InP clad layer 103 and the p-type AlInAs layer 102 is further etched toward the substrate, whereby the resistance can be further increased.
  • the isolation groove 110 is configured to penetrate the p-type AlInAs layer, so that the leakage current and the light of the leakage current through the substrate are prevented. Not only can absorption loss be suppressed and isolation be ensured, a structure suitable for manufacturing an element can be realized, and further higher resistance can be achieved.
  • the isolation groove 110 is provided in order to separate and electrically insulate each semiconductor laser element 120, but in the second embodiment, instead of forming the isolation groove, The case where ion implantation is performed will be described.
  • FIG. 23 is a sectional view showing the configuration of the semiconductor optical integrated device according to the third embodiment.
  • the semiconductor optical integrated device 504 instead of forming the isolation groove 110 and separating the respective semiconductor laser devices 120 in the first embodiment, the semiconductor optical integrated device 504 is subjected to ion implantation to n between the semiconductor laser devices 120. Ions are implanted into the type InP clad layer 103 to a predetermined depth to provide an ion implantation section 117 having a high resistance, thereby separating the respective semiconductor laser elements 120.
  • the semiconductor optical integrated device 504 according to the third embodiment are the same as those of the semiconductor optical integrated device 501 of the first embodiment, and corresponding parts are denoted by the same reference numerals and the description thereof will be omitted.
  • FIGS. 24 to 26 are cross-sectional views showing the manufacturing process of the semiconductor optical integrated device 504 according to the third embodiment.
  • a striped opening 116a is formed in a portion of the insulating film 116 covering the n-type InP cladding layer 103, and then the n-type InP exposed from the opening 116a is formed. Ions are implanted into the cladding layer 103 to form an ion-implanted portion 117, as shown in FIG. After forming the ion-implanted portion 117, the insulating film 116 is removed by etching with hydrofluoric acid or the like.
  • an insulating film 107 is formed on the entire surface of the mesa groove 115b on which the ion implantation portion 117 is formed.
  • an anode electrode 108 connected to the p-type InP clad layer 106 is formed in the opening 107a, and a cathode electrode 109 connected to the n-type InP clad layer 103 is formed in the opening 107b.
  • a semiconductor optical integrated device 504 as shown is obtained.
  • an ion implantation part may be provided instead of the isolation groove 110 in the second embodiment.
  • the isolation groove 110 not only the effect of the second embodiment can be obtained, but also because it is not necessary to form the isolation groove 110, the unevenness of the wafer surface at the time of device fabrication can be reduced, and the ease of manufacturing is improved.
  • the ion implantation part 117 is provided instead of the isolation groove 110. Therefore, the effects of the first and second embodiments can be obtained. Not only is it obtained, but since it is not necessary to form the isolation groove 110, the unevenness of the wafer surface at the time of device fabrication can be reduced, and the ease of manufacturing is improved.
  • the present invention is not limited to this.
  • An n-type or undoped AlInAs layer may be formed.
  • the p-type AlInAs layer 102 may be replaced with another material having a bandgap larger than that of InP.
  • the band gap of InP is 1.344 eV. growing.
  • the layer is not limited to the p-type Al y Ga x In (1-xy) As layer, and an n-type or undoped Al y Ga x In (1-xy) As layer may be formed. Good.
  • the n-type AlInAs layer or the n-type Al y Ga x In (1-xy) As is formed, the n-type InP clad layer 103 is a p-type InP clad layer, and the p-type InP clad layer 106 is an n-type.
  • the InP clad layer, the anode electrode 108 is a cathode electrode, and the cathode electrode 109 is an anode electrode.
  • the p-type Al y Ga x In (1-xy) As When the p-type Al y Ga x In (1-xy) As is formed, it has the same configuration as that of the first embodiment. When an undoped Al y Ga x In (1-xy) As layer is formed, either structure may be used. In any case, it is possible to obtain the same effect as that of the above embodiment.
  • the Fe-doped semi-insulating InP substrate 101 is used as the InP substrate, the present invention is not limited to this.
  • An n-type InP substrate or a p-type InP substrate may be used.
  • an n-type InP substrate may be doped with S or Si, and a p-type InP substrate may be doped with Zn, Mg or the like.
  • the same effect as that of the above embodiment can be obtained. Since the leakage current in the substrate direction is suppressed by a material having a wider bandgap than the substrate material formed on the substrate, the substrate polarity does not matter.
  • an n-type semiconductor substrate is preferable from the viewpoint of laser characteristics due to light absorption. It is generally known that absorption by electrons having n-type conductivity has a smaller light absorption coefficient than holes having p-type conductivity.
  • the invention is not limited to this.
  • the optical semiconductor element and the electronic device other than the optical semiconductor element may be arranged, and the cathode or the anode of the optical semiconductor element and the electronic device other than the optical semiconductor element may be electrically separated. Also in this case, the same effect as that of the above embodiment can be obtained.
  • 101 Fe-doped semi-insulating InP substrate 102 p-type AlInAs layer, 103 n-type InP clad layer, 103a ridge portion, 104 active layer, 105 current blocking layer, 106 p-type InP clad layer, 110 isolation groove, 117 ion implantation Part, 120 semiconductor laser device, 501, 502, 503, 504 semiconductor optical integrated device.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Optics & Photonics (AREA)
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Abstract

Ce dispositif optique intégré à semi-conducteur est pourvu d'une couche d'AlInAs de type p (102) qui est formée sur la surface d'un substrat InP semi-isolant dopé au Fe (101) par croissance épitaxiale d'un matériau qui a une bande interdite plus large que le substrat InP semi-isolant dopé au Fe (101), et de multiples dispositifs laser à semi-conducteur (120) qui sont formés sur la surface de la couche d'AlInAs de type p (102) et qui sont agencés dans une rangée séparée par des rainures d'isolation (110) qui atteignent la couche d'AlInAs de type p (102). Ce dispositif optique intégré à semi-conducteur supprime la perte d'absorption de lumière et de courant de fuite à travers le substrat, assure l'isolation et permet d'obtenir une structure appropriée pour la fabrication de dispositif.
PCT/JP2018/039350 2018-10-23 2018-10-23 Dispositif optique intégré à semi-conducteur WO2020084687A1 (fr)

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PCT/JP2018/039350 WO2020084687A1 (fr) 2018-10-23 2018-10-23 Dispositif optique intégré à semi-conducteur
JP2020505940A JPWO2020084858A1 (ja) 2018-10-23 2019-08-02 半導体光集積素子
PCT/JP2019/030503 WO2020084858A1 (fr) 2018-10-23 2019-08-02 Dispositif optique à semi-conducteur intégré
TW108137224A TW202017269A (zh) 2018-10-23 2019-10-16 半導體光積體元件

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Citations (8)

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