WO2020077731A1 - 显示面板的测试电路布局构造 - Google Patents

显示面板的测试电路布局构造 Download PDF

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Publication number
WO2020077731A1
WO2020077731A1 PCT/CN2018/116406 CN2018116406W WO2020077731A1 WO 2020077731 A1 WO2020077731 A1 WO 2020077731A1 CN 2018116406 W CN2018116406 W CN 2018116406W WO 2020077731 A1 WO2020077731 A1 WO 2020077731A1
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WO
WIPO (PCT)
Prior art keywords
area
metal layer
test circuit
cof
areas
Prior art date
Application number
PCT/CN2018/116406
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English (en)
French (fr)
Inventor
李雪
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/349,984 priority Critical patent/US11127642B2/en
Publication of WO2020077731A1 publication Critical patent/WO2020077731A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the invention relates to a test circuit layout structure of a display, in particular to a test circuit layout structure of a display panel.
  • OLED organic light-emitting diode
  • the present invention provides various test circuit layout structures for display panels to solve the problem of color mixing existing in panel testing in the prior art.
  • an aspect of the present invention provides a test circuit layout structure of a display panel, wherein the display panel has a panel outline, and a boundary layout area defined around an effective area is defined in the panel outline, so The boundary layout area is used to set the test circuit layout structure.
  • the test circuit layout structure includes: a COF junction area, two power supply conductor areas, a test circuit area, two test pad areas, and two electrostatic protection areas.
  • the COF Two ends of the bonding area communicate with the two power supply conductor areas, the two power supply conductor areas extend toward the effective area, the test circuit area is located between the COF bonding area and the two power supply conductor areas, the two The test pad area and the two electrostatic protection areas are distributed on both sides of the COF bonding area; wherein, several traces extend from the test pad area to couple the electrostatic protection area and the COF bonding area And the test circuit area, the resistivity of the trace is the same as the resistivity of the power conductor area, the trace bypasses the power conductor area provided on the same layer, or the trace
  • the power conductor regions overlap insulatively; a central axis extends between the two test pad regions through the COF junction region and the test circuit region, and the several traces are respectively on two sides of the central axis Symmetrically distributed on the side; and the traces are formed by several different metal layers and are coupled by a plurality of through pieces, and the through pieces penetrate and connect at least two metal layers among the pluralit
  • test pad area located on the same side of the COF junction area is located between the electrostatic protection area and the power supply conductor area.
  • the COF junction area, the test circuit area, the test pad area, and the electrostatic protection area are coupled by a plurality of stacked and insulated metal layers, and the plurality of metals
  • the layer includes a first metal layer, a second metal layer, and a third metal layer.
  • the resistivity of the third metal layer is less than that of the first metal layer and the second metal layer.
  • a metal layer forms several first sections extending from the two sides of the test circuit area toward the two power supply conductor areas, and the second metal layer forms from the two sides of the test circuit area toward the two power supplies
  • a plurality of second sections extending from the conductor area, a layout in the COF junction area and the power supply conductor area are formed by the third metal layer, and the third metal layer also forms several third sections, The plurality of third sections respectively traverse a layout in the electrostatic protection area from the test pad area, and turn away from the two power supply conductor areas to traverse the layout in the COF junction area, And extends to between the test circuit area and the two power conductor areas , Individually coupled to the first section and the second section.
  • the two electrostatic protection regions are located at a distance between a boundary line of the COF junction region away from the test circuit region and a boundary line of the boundary layout region away from the test circuit region Within range.
  • the third section turns in the distance range away from the two power supply conductor regions, and then traverses the layout in the COF junction region.
  • the electrostatic protection area located on the same side of the COF junction area is located between the test pad area and the power supply conductor area.
  • the COF junction area, the test circuit area, the test pad area, and the electrostatic protection area are coupled by a plurality of stacked and insulated metal layers, and the plurality of metals
  • the layer includes a first metal layer, a second metal layer and a third metal layer, the first metal layer, the second metal layer and the third metal layer have the same resistivity, the first metal A plurality of fourth sections formed by the layer or the second metal layer, the plurality of fourth sections respectively traverse the two power supply conductor areas from both sides of the test circuit area, and then traverse the two electrostatic protection Area to extend to the two test pad areas, a layout in the COF bonding area and the power conductor area are formed by the third metal layer, the third metal layer also forms several fifth sections , The plurality of fifth sections extend from the COF junction area toward the test circuit area to between the test circuit area and the two power supply conductor areas to individually couple the fourth section .
  • the COF junction area, the test circuit area, the test pad area, and the electrostatic protection area are coupled by a plurality of stacked and insulated metal layers, and the plurality of metals
  • the layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, the resistivity of the first metal layer and the resistivity of the second metal layer are greater than the third The resistivity of the metal layer, the resistivity of the third metal layer is equal to the resistivity of the fourth metal layer, the fourth metal layer forms a plurality of sixth sections, and the sixth sections are respectively composed of Two sides of the test circuit area traverse the two power supply conductor areas, and turn to traverse the two electrostatic protection areas, and extend to the two test pad areas, a layout in the COF junction area and the power supply
  • the conductor region is formed by the third metal layer, and the third metal layer further forms a plurality of seventh sections, which respectively extend from the COF bonding area toward the test circuit area to all The test circuit area and the two power supply
  • test circuit layout structure of a display panel, the display panel having a panel outline, a border layout area defined around an effective area defined in the panel outline, the The boundary layout area is used to set the test circuit layout structure.
  • the test circuit layout structure includes: a COF junction area, two power supply conductor areas, a test circuit area, two test pad areas, and two electrostatic protection areas.
  • the COF junction The two ends of the zone communicate with the two power supply conductor areas, the two power supply conductor areas extend toward the effective area, the test circuit area is located between the COF junction area and the two power supply conductor areas, the second test The pad area and the two electrostatic protection areas are distributed on both sides of the COF bonding area; wherein, several traces extend from the test pad area to couple the electrostatic protection area, the COF bonding area and In the test circuit area, the resistivity of the trace is the same as the resistivity of the power conductor area, the trace bypasses the power conductor area provided on the same layer, or the trace and all Power supply conductor insulation overlap region.
  • test pad area located on the same side of the COF junction area is located between the electrostatic protection area and the power supply conductor area.
  • the COF junction area, the test circuit area, the test pad area, and the electrostatic protection area are coupled by a plurality of stacked and insulated metal layers, and the plurality of metals
  • the layer includes a first metal layer, a second metal layer, and a third metal layer.
  • the resistivity of the third metal layer is less than that of the first metal layer and the second metal layer.
  • a metal layer forms several first sections extending from the two sides of the test circuit area toward the two power supply conductor areas, and the second metal layer forms from the two sides of the test circuit area toward the two power supplies
  • a plurality of second sections extending from the conductor area, a layout in the COF junction area and the power supply conductor area are formed by the third metal layer, and the third metal layer also forms several third sections, The third sections respectively traverse a layout in the electrostatic protection area from the test pad area, and turn away from the two power conductor areas to traverse the layout in the COF junction area and extend Between the test circuit area and the two power conductor areas, to Respectively coupled to the first section and the second section.
  • the two electrostatic protection regions are located at a distance between a boundary line of the COF junction region away from the test circuit region and a boundary line of the boundary layout region away from the test circuit region Within range.
  • the third section turns in the distance range away from the two power supply conductor regions, and then traverses the layout in the COF junction region.
  • the electrostatic protection area located on the same side of the COF junction area is located between the test pad area and the power supply conductor area.
  • the COF junction area, the test circuit area, the test pad area, and the electrostatic protection area are coupled by a plurality of stacked and insulated metal layers, and the plurality of metals
  • the layer includes a first metal layer, a second metal layer and a third metal layer, the first metal layer, the second metal layer and the third metal layer have the same resistivity, the first metal A plurality of fourth sections formed by the layer or the second metal layer, the plurality of fourth sections respectively traverse the two power supply conductor areas from both sides of the test circuit area, and then traverse the two electrostatic protection Area to extend to the two test pad areas, a layout in the COF bonding area and the power conductor area are formed by the third metal layer, the third metal layer also forms several fifth sections , The plurality of fifth sections extend from the COF junction area toward the test circuit area to between the test circuit area and the two power supply conductor areas to individually couple the fourth section .
  • the electrostatic protection area is located between the test pad area and the power supply conductor area; wherein the COF junction area, the test circuit area, the test pad area and the The electrostatic protection zone is coupled by a plurality of stacked and insulated metal layers.
  • the metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer.
  • the resistivity of a metal layer and the resistivity of the second metal layer are greater than the resistivity of the third metal layer, the resistivity of the third metal layer is equal to the resistivity of the fourth metal layer, the first The four metal layers form a plurality of sixth sections, which respectively traverse the two power supply conductor areas from both sides of the test circuit area and turn to traverse the two electrostatic protection areas and extend To the two test pad areas, a layout in the COF junction area and the power supply conductor area are formed by the third metal layer, and the third metal layer also forms several seventh sections, the number A seventh section from the COF junction area toward the test circuit area Extending to the region between the two test circuit power supply conductor areas to individually couple the sixth section.
  • a central axis between the two test pad areas extends through the COF junction area and the test circuit area, and the several traces are respectively on both sides of the central axis Symmetrically distributed.
  • the plurality of traces are formed by a plurality of different metal layers and are coupled by a plurality of through members, the through members penetrate and connect at least two of the plurality of metal layers Metal layer.
  • the test circuit layout structure of the display panel of the present invention because the output signal of the test pad area is transmitted by a trace with a low resistivity, and the trace bypasses the power supply provided on the same layer
  • the conductor area or the insulation overlap with the power conductor area will not cause short circuit problems and no obvious signal delay, thereby avoiding the occurrence of color mixing due to signal delay, such as in the COF junction area and the film-based After the chip (COF) is connected, the test drive situation can be similar to that in normal operation, as a reference for subsequent signal adjustment.
  • Figure 1 is a schematic diagram of the outline of a COF panel.
  • FIG. 2 is a schematic diagram of the test circuit layout structure of the display panel according to the first embodiment of the present invention.
  • FIG. 3 is a schematic view of the layout of the COF junction area, test pad area and electrostatic protection area of the present invention.
  • FIG. 4 is a schematic diagram of a test circuit layout structure of a display panel according to a second embodiment of the invention.
  • FIG. 5 is a schematic diagram of a test circuit layout structure of a display panel according to a third embodiment of the invention.
  • the test circuit layout structure of the display panel of the present invention can be applied to a display panel, such as a COF type panel, etc.
  • the display panel has a panel profile P, and a panel profile P can be defined in the panel profile P
  • An effective area (Active Area) A and a border layout area D around the effective area, the effective area A may have a display function, the effective area A within the panel outline P has up, down, left , The right border area.
  • the lower boundary area may be defined as the boundary layout area D for setting the test circuit layout structure
  • the test circuit layout structure may include at least a COF junction area B, a test circuit area T and Two test pad areas P
  • the COF bonding area B can be used to perform the COF bonding function of the panel
  • the test circuit area T can be used to set up a panel test circuit to test the electrical function of the effective area A
  • the test pad area P can input a test signal.
  • the test circuit layout structure of the display panel may further include two power supply conductor areas V and Two electrostatic protection areas E, two ends of the COF junction area B communicate with the two power supply conductor areas V, the two power supply conductor areas V extend toward the effective area A, and the test circuit area T is located at the COF junction Between the area B and the two power conductor areas V, the two test pad areas P and the two electrostatic protection areas E are distributed on both sides of the COF junction area.
  • traces extend from the test pad area P to couple the electrostatic protection area E, the COF junction area B and the test circuit area T, and the resistivity of the traces and the The resistivity of the power supply conductor region V is the same, the trace bypasses the power supply conductor region V provided in the same layer, or the trace overlaps the power supply conductor region V in an insulated manner.
  • test circuit layout structure of the display panel of the present invention by way of example.
  • the test pad area P located on the same side of the COF junction area B is located between the electrostatic protection area E and the power supply conductor area V.
  • the two electrostatic protection regions E are located at a boundary B1 of the COF junction region B away from the test circuit region T and a boundary of the boundary layout region D away from the test circuit region T Within a distance a between the boundaries D1.
  • the COF junction area B, the test circuit area T, the test pad area P, and the electrostatic protection area E may be coupled by several stacked and mutually insulated metal layers.
  • at least two metal layers among the metal layers may be penetrated and connected by a plurality of through pieces, and the through pieces are composed of electrical conductors (such as metals or alloys).
  • the metal layers may include a first metal layer, a second metal layer, and a third metal layer, and the first metal layer may be respectively oriented from two sides of the test circuit region T
  • the two power supply conductor regions V extend several first sections M1
  • the second metal layer may extend from the two sides of the test circuit region T toward the second power supply conductor regions T several second sections M2
  • a layout (as shown in FIG. 3) in the COF junction region B and the power conductor region V are formed by the third metal layer
  • the third metal layer also forms several third sections M3, the plurality of third sections M3 respectively traverse a layout in the electrostatic protection area E by the test pad area P (as shown in FIG.
  • the third section M3 can communicate with multiple layouts in the layout At least one of the wire segments), and turn away from the two power conductor regions T to traverse the layout in the COF junction region B, for example: the third section M3 may be within the distance range a. Turn inside and away from the two power conductor regions, and then traverse the layout in the COF junction area; then, the third section M3 enters a Extending to the region T between the test circuit and the second power conductor region V, individually coupled to the first section and the second section M1 M2.
  • first section M1, the second section M2, and the third section M3 may be coupled by a plurality of through pieces (not shown).
  • the resistivity of the third metal layer is less than that of the first metal layer and the second metal layer, for example: the resistivity of the first metal layer and the second metal layer 10 times the resistivity of the third metal layer, for example: the material of the first metal layer and the second metal layer is molybdenum (Mo), the material of the third metal layer is titanium (Ti) / Aluminum (Al) / Ti (Ti).
  • FIG. 2 there is a central axis C between the two test pad areas P extending through the COF junction area B and the test circuit area T, and the plurality of first sections M, the second sections M2 and the third sections M3 may be symmetrically distributed on both sides of the central axis C, respectively.
  • the routing of the third section of the third metal layer will bypass the two power conductor regions of the third metal layer, and no short circuit problem will occur; moreover, due to the routing of the output signal of the test pad area Formed with a third metal layer with a low resistivity, no significant signal delay will occur, thereby avoiding the occurrence of color mixing due to signal delay. Make the test drive situation similar to the normal operation, as a reference for subsequent signal adjustment.
  • the second electrostatic protection area is changed to be marked as E ′.
  • the position of the two electrostatic protection area E ′ is different from that of the first embodiment in the first embodiment.
  • the electrostatic protection area E ′ on the same side of the COF junction area B is located between the test pad area P and the power supply conductor area V.
  • the COF junction area B, the test circuit area T, the test pad area P, and the electrostatic protection area E ' may be coupled by a plurality of stacked and insulated metal layers.
  • the metal layers may include a first metal layer, a second metal layer, and a third metal layer, the first metal layer, the second metal layer, and the third metal layer
  • the resistivity is the same.
  • the materials of the third metal layer, the first metal layer, and the second metal layer may be the same as titanium (Ti) / aluminum (Al) / titanium (with a lower resistivity Ti) material.
  • the first metal layer or the second metal layer forms a plurality of fourth sections M4, the plurality of fourth sections M4 traverses the two power supply conductor areas V from both sides of the test circuit area T Turning across the two electrostatic protection areas E 'to extend to the two test pad areas P, a layout (as shown in FIG.
  • the third metal layer further forms a plurality of fifth sections M5, which respectively extend from the COF bonding area B toward the test circuit area T to the test Between the circuit area T and the two power supply conductor areas V, the fourth section M4 is individually coupled.
  • the fourth section M4 and the fifth section M5 may be coupled by a plurality of connecting pieces (not shown).
  • a central axis C between the two test pad areas P extends through the COF junction area B and the test circuit area T, and the fourth sections M4 and the fifth sections M5 may be distributed symmetrically on both sides of the central axis C, respectively.
  • the traces of the fourth section formed by the first metal layer or the second metal layer and the third metal layer form the two power conductor regions insulated from each other, and no short circuit problem will occur;
  • the traces of the output signal of the test pad area are formed by the first metal layer or the second metal layer with a low resistivity, and no obvious signal delay will occur, thereby avoiding the occurrence of color mixing due to the signal delay
  • the test driving situation can be similar to that during normal operation, which is used as a reference for subsequent signal adjustment.
  • the electrostatic protection area E 'located on the same side of the COF junction area B may be located between the test pad area P and the power supply conductor area V.
  • the COF junction area B, the test circuit area T, the test pad area P, and the electrostatic protection area E ' may be coupled by several stacked and insulated metal layers.
  • the metal layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the resistivity of the first metal layer and the second metal
  • the resistivity of the layer is greater than the resistivity of the third metal layer
  • the resistivity of the third metal layer is equal to the resistivity of the fourth metal layer
  • the fourth metal layer forms several sixth sections M6,
  • the sixth sections M6 respectively cross the two power conductor regions V from both sides of the test circuit region T and turn across the two electrostatic protection regions E ′ to extend to the two test pad regions P, A layout (as shown in FIG.
  • the third metal layer in the COF junction region B and the power conductor region are formed by the third metal layer, and the third metal layer further forms a plurality of seventh sections M7, the Several seventh sections M7 extend from the COF junction area B toward the test circuit area T to between the test circuit area T and the two power supply conductor areas V to individually couple the sixth Section M6.
  • the sixth section M6 and the seventh section M7 may be coupled by several through pieces (not shown).
  • a central axis C between the two test pad areas P extends through the COF junction area B and the test circuit area T, and the sixth sections M6 and the seventh segments M7 may be symmetrically distributed on both sides of the central axis C, respectively.
  • the fourth metal layer can be added on the basis of the existing circuit layout, and the traces of the sixth section formed by the fourth metal layer and the third metal layer form the mutual relationship between the two power conductor regions Insulation, no short-circuit problem will occur; moreover, because the traces of the output signal of the test pad area are formed by the fourth metal layer with low resistivity, no obvious signal delay will occur, thereby avoiding color mixing due to signal delay.
  • the test driving condition may be similar to that during normal operation, as a reference for subsequent signal adjustment.

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Abstract

一种显示面板的测试电路布局构造，包括：一COF接合区的二端连通二电源导体区，所述二电源导体区朝向一有效区域延伸；一测试电路区位于所述COF接合区与所述二电源导体区之间；二测试垫区及所述二静电保护区分布于所述COF接合区的二侧，由所述测试垫区延伸数条走线，用以耦接所述静电保护区、所述COF接合区及所述测试电路区，所述走线与所述电源导体区的电阻率相同，所述走线绕开同层设置的所述电源导体区，或者，所述走线与所述电源导体区绝缘地交叠。

Description

显示面板的测试电路布局构造 技术领域
本发明是有关于一种显示器的测试电路布局构造，特别是有关于一种显示面板的测试电路布局构造。
 背景技术
随着科技的不断发展，对平面显示器的要求越来越高。举例而言，有机发光二极管(OLED)显示器具有边框窄、制成重量轻、可卷曲、易于携带等诸多优势，受到了人们的广泛关注，成为时代的主流。
在一般OLED显示器件的制备过程中，通常包括四个阶段：Array、EL (electroluminescence)、TFE(thin-film encapsulation)及Module。在制备过程中，对产品各个阶段性能的测试，显得尤为重要，因为这将决定产品的良率、可靠性等特性。
在常规的柔性(flexible)OLED结构中, 都会存在Array Tester和Cell Test的电路设计，目的是为了在Array阶段和EL阶段结束后，检测产品的性能是否符合规格，确定产品有没有继续生产的必要性，以减少资源损耗。在EL阶段结束后进行的Cell Test也为后续产品如何供给讯号以进行驱动奠定基础，因此，Cell Test的结果显得尤为重要。
但是，基于现有的常规设计，对于COF(chip on film)类型的面板(panel)，在进行Cell Test测试时会存在一些混色问题。因此，现有技术存在缺陷，急需改进。
 技术问题
本发明提供多种显示面板的测试电路布局构造，以解决现有技术进行面板测试时存在的混色问题。
 技术解决方案
为了解决前述问题，本发明的一个方面提供一种显示面板的测试电路布局构造，其中，所述显示面板具有一面板轮廓，所述面板轮廓内定义在一有效区域周围的一边界布局区，所述边界布局区用以设置所述测试电路布局构造，所述测试电路布局构造包括：一COF接合区、二电源导体区、一测试电路区、二测试垫区及二静电保护区，所述COF接合区的二端连通所述二电源导体区，所述二电源导体区朝向所述有效区域延伸，所述测试电路区位于所述COF接合区与所述二电源导体区之间，所述二测试垫区、所述二静电保护区分布于所述COF接合区的二侧；其中，由所述测试垫区延伸数条走线，用以耦接所述静电保护区、所述COF接合区及所述测试电路区，所述走线的电阻率与所述电源导体区的电阻率相同，所述走线绕开同层设置的所述电源导体区，或者，所述走线与所述电源导体区绝缘地交叠；所述二测试垫区之间具有一中轴线延伸通过所述COF接合区及所述测试电路区，所述数条走线分别在所述中轴线的两侧对称地分布；及所述数条走线由数个不同金属层形成并通过数个贯接件耦接，所述贯接件贯通并连接所述数个金属层中的至少二金属层。
在本发明的一实施例中，位于所述COF接合区同一侧的所述测试垫区位于所述静电保护区与所述电源导体区之间。
在本发明的一实施例中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第三金属层的电阻率小于所述第一金属层及所述第二金属层的电阻率，所述第一金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第一区段，所述第二金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第二区段，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第三区段，所述数个第三区段分别由所述测试垫区横越所述静电保护区内的一布局，并转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局，并延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第一区段及所述第二区段。
在本发明的一实施例中，所述二静电保护区位于所述COF接合区远离所述测试电路区的一界线与所述边界布局区远离所述测试电路区的一界线之间的一间距范围内。
在本发明的一实施例中，所述第三区段在所述间距范围内转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局。
在本发明的一实施例中，位于所述COF接合区同一侧的所述静电保护区位于所述测试垫区与所述电源导体区之间。
在本发明的一实施例中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第一金属层、所述第二金属层与所述第三金属层的电阻率相同，所述第一金属层或所述第二金属层形成数个第四区段，所述数个第四区段分别由所述测试电路区的二侧横越所述二电源导体区，而转折横越所述二静电保护区，以延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第五区段，所述数个第五区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第四区段。
在本发明的一实施例中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层、一第三金属层及一第四金属层，所述第一金属层的电阻率及所述第二金属层的电阻率大于所述第三金属层的电阻率，所述第三金属层的电阻率等于所述第四金属层的电阻率，所述第四金属层形成数个第六区段，所述数个第六区段分别由所述测试电路区的二侧横越所述二电源导体区，并转折以横越所述二静电保护区，并延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第七区段，所述数个第七区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第六区段。
为了解决前述问题，本发明的另一个方面提供一种显示面板的测试电路布局构造，所述显示面板具有一面板轮廓，所述面板轮廓内定义在一有效区域周围的一边界布局区，所述边界布局区用以设置所述测试电路布局构造，所述测试电路布局构造包括：一COF接合区、二电源导体区、一测试电路区、二测试垫区及二静电保护区，所述COF接合区的二端连通所述二电源导体区，所述二电源导体区朝向所述有效区域延伸，所述测试电路区位于所述COF接合区与所述二电源导体区之间，所述二测试垫区、所述二静电保护区分布于所述COF接合区的二侧；其中，由所述测试垫区延伸数条走线，用以耦接所述静电保护区、所述COF接合区及所述测试电路区，所述走线的电阻率与所述电源导体区的电阻率相同，所述走线绕开同层设置的所述电源导体区，或者，所述走线与所述电源导体区绝缘地交叠。
在本发明的一实施例中，位于所述COF接合区同一侧的所述测试垫区位于所述静电保护区与所述电源导体区之间。
在本发明的一实施例中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第三金属层的电阻率小于所述第一金属层及所述第二金属层的电阻率，所述第一金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第一区段，所述第二金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第二区段，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第三区段，所述数个第三区段分别由所述测试垫区横越所述静电保护区内的一布局，并转折而远离所述二电源导体区，以横越所述COF接合区内的布局，并延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第一区段及所述第二区段。
在本发明的一实施例中，所述二静电保护区位于所述COF接合区远离所述测试电路区的一界线与所述边界布局区远离所述测试电路区的一界线之间的一间距范围内。
在本发明的一实施例中，所述第三区段在所述间距范围内转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局。
在本发明的一实施例中，位于所述COF接合区同一侧的所述静电保护区位于所述测试垫区与所述电源导体区之间。
在本发明的一实施例中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第一金属层、所述第二金属层与所述第三金属层的电阻率相同，所述第一金属层或所述第二金属层形成数个第四区段，所述数个第四区段分别由所述测试电路区的二侧横越所述二电源导体区，而转折横越所述二静电保护区，以延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第五区段，所述数个第五区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第四区段。
在本发明的一实施例中，所述静电保护区位于所述测试垫区与所述电源导体区之间；其中所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层、一第三金属层及一第四金属层，所述第一金属层的电阻率及所述第二金属层的电阻率大于所述第三金属层的电阻率，所述第三金属层的电阻率等于所述第四金属层的电阻率，所述第四金属层形成数个第六区段，所述数个第六区段分别由所述测试电路区的二侧横越所述二电源导体区，并转折以横越所述二静电保护区，并延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第七区段，所述数个第七区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第六区段。
在本发明的一实施例中，所述二测试垫区之间具有一中轴线延伸通过所述COF接合区及所述测试电路区，所述数条走线分别在所述中轴线的两侧对称地分布。
在本发明的一实施例中，所述数条走线由数个不同金属层形成并通过数个贯接件耦接，所述贯接件贯通并连接所述数个金属层中的至少二金属层。
 有益效果
与现有技术相比较，本发明的显示面板的测试电路布局构造，由于所述测试垫区输出信号以电阻率较小的走线传输，且所述走线绕开同层设置的所述电源导体区或与所述电源导体区绝缘地交叠，不会发生短路问题，也不会发生明显的信号延迟，进而避免因信号延迟导致混色情况的发生，如在所述COF接合区与基于薄膜的芯片(COF)接合后，可使测试驱动的情况与正常工作时相似，以作为后续信号调节的参考。
 附图说明
图1是一COF型面板轮廓的示意图。
图2是本发明第一实施例的显示面板的测试电路布局构造的示意图。
图3是本发明的COF接合区、测试垫区及静电保护区内的布局示意图。
图4是本发明第二实施例的显示面板的测试电路布局构造的示意图。
图5是本发明第三实施例的显示面板的测试电路布局构造的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图1所示，本发明的显示面板的测试电路布局构造可适用于一显示面板，例如：COF型面板等，所述显示面板具有一面板轮廓P，所述面板轮廓P内可定义一有效区域(Active Area)A及在所述有效区域周围的一边界布局区D，所述有效区域A可具有显示功能，所述面板轮廓P内的所述有效区域A四周具有上、下、左、右边界区。具体地，所述下边界区可定义为所述边界布局区D，用以设置所述测试电路布局构造，所述测试电路布局构造至少可包括：一COF接合区B、一测试电路区T及二测试垫区P，所述COF接合区B可用于进行面板的COF接合(bonding)功能，所述测试电路区T可用于设置一面板测试电路，用以测试所述有效区域A的电性功能，所述测试垫区P可输入测试用的信号。
请再参阅图1所示，所述显示面板的测试电路布局构造除了包括所述COF接合区B、所述测试电路区T、所述二测试垫区P，还可包括二电源导体区V及二静电保护区E，所述COF接合区B的二端连通所述二电源导体区V，所述二电源导体区V朝向所述有效区域A延伸，所述测试电路区T位于所述COF接合区B与所述二电源导体区V之间，所述二测试垫区P、所述二静电保护区E分布于所述COF接合区的二侧。
其中，由所述测试垫区P延伸数条走线，用以耦接所述静电保护区E、所述COF接合区B及所述测试电路区T，所述走线的电阻率与所述电源导体区V的电阻率相同，所述走线绕开同层设置的所述电源导体区V，或者，所述走线与所述电源导体区V绝缘地交叠。
以下通过举例方式说明本发明的显示面板的测试电路布局构造的不同实施例。
在第一实施例中。如图1及图2所示，位于所述COF接合区B同一侧的所述测试垫区P位于所述静电保护区E与所述电源导体区V之间。具体地，如图2所示，所述二静电保护区E位于所述COF接合区B远离所述测试电路区T的一界线B1与所述边界布局区D远离所述测试电路区T的一界线D1之间的一间距范围a内。
请再参阅图2所示，所述COF接合区B、所述测试电路区T、所述测试垫区P及所述静电保护区E可通过数个层叠且相互绝缘的金属层耦接。举例而言，所述数个金属层中的至少二金属层可由数个贯接件贯通并连接，所述贯接件由电导体(例如金属或合金)构成。
举例而言，所述数个金属层可包括一第一金属层、一第二金属层及一第三金属层，所述第一金属层可分别由所述测试电路区T的二侧朝向所述二电源导体区V延伸数个第一区段M1，所述第二金属层可分别由所述测试电路区T的二侧朝向所述二电源导体区T延伸数个第二区段M2，所述COF接合区B内的一布局(layout)(如图3所示)及所述电源导体区V由所述第三金属层形成，所述第三金属层还形成数个第三区段M3，所述数个第三区段M3分别由所述测试垫区P横越所述静电保护区E内的一布局(如图3所示，第三区段M3可连通所述布局内的多个导线段中的至少一个)，并转折而远离所述二电源导体区T，以转折而横越所述COF接合区B内的布局，例如：所述第三区段M3可于所述间距范围a内转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局；接着，所述第三区段M3进一步延伸至所述测试电路区T与所述二电源导体区V之间，以个别地耦接所述第一区段M1及所述第二区段M2。
具体地，所述第一区段M1、所述第二区段M2与所述第三区段M3可通过数个贯接件(未绘示)耦接。
在一实施例中，所述第三金属层的电阻率小于所述第一金属层及所述第二金属层的电阻率，例如：第一金属层及所述第二金属层的电阻率为所述第三金属层的电阻率的10倍，例如：所述第一金属层及所述第二金属层的材料为钼(Mo)，所述第三金属层的材料为钛(Ti)/铝(Al)/钛(Ti)。
在一实施例中，如图2所示，所述二测试垫区P之间具有一中轴线C延伸通过所述COF接合区B及所述测试电路区T，所述数个第一区段M、所述数个第二区段M2及所述数个第三区段M3可分别在所述中轴线C的两侧对称地分布。
从而，所述第三金属层的第三区段的走线会绕开所述第三金属层的二电源导体区，不会发生短路问题；而且，由于所述测试垫区输出信号的走线以电阻率较小的第三金属层形成，不会发生明显的信号延迟，进而避免因信号延迟导致混色情况的发生，如在所述COF接合区与基于薄膜的芯片(COF)接合后，可使测试驱动的情况与正常工作时相似，以作为后续信号调节的参考。
在第二实施例中，如图4所示，所述二静电保护区更改标示为E’，所述二静电保护区E’与第一实施例中的二静电保护区E的位置不同，位于所述COF接合区B同一侧的所述静电保护区E’位于所述测试垫区P与所述电源导体区V之间。请再参阅图4所示，所述COF接合区B、所述测试电路区T、所述测试垫区P及所述静电保护区E’可通过数个层叠且相互绝缘的金属层耦接。
举例而言，所述数个金属层可包括一第一金属层、一第二金属层及一第三金属层，所述第一金属层、所述第二金属层与所述第三金属层的电阻率相同，具体地，所述第三金属层、所述第一金属层及所述第二金属层的材料可同为电阻率较小的钛(Ti)/铝(Al)/钛(Ti)材料。所述第一金属层或所述第二金属层形成数个第四区段M4，所述数个第四区段M4由所述测试电路区T的二侧横越所述二电源导体区V而转折横越所述二静电保护区E’以延伸至所述二测试垫区P，所述COF接合区B内的一布局(如第3图所示)及所述电源导体区V由所述第三金属层形成，所述第三金属层还形成数个第五区段M5，所述数个第五区段M5分别由所述COF接合区B朝向所述测试电路区T延伸至所述测试电路区T与所述二电源导体区V之间，以个别地耦接所述第四区段M4。
具体地，所述第四区段M4与所述第五区段M5可通过数个贯接件(未绘示)耦接。
在一实施例中，如图4所示，所述二测试垫区P之间具有一中轴线C延伸通过所述COF接合区B及所述测试电路区T，所述数个第四区段M4及所述数个第五区段M5可分别在所述中轴线C的两侧对称地分布。
从而，所述第一金属层或所述第二金属层形成的第四区段的走线与所述第三金属层形成所述二电源导体区相互绝缘，不会发生短路问题；而且，由于所述测试垫区输出信号的走线改以电阻率较小的所述第一金属层或所述第二金属层形成，不会发生明显的信号延迟，进而避免因信号延迟导致混色情况的发生，如在所述COF接合区与基于薄膜的芯片(COF)接合后，可使测试驱动的情况与正常工作时相似，以作为后续信号调节的参考。
在第三实施例中，如图5所示，位于所述COF接合区B同一侧的所述静电保护区E’可位于所述测试垫区P与所述电源导体区V之间。请再参阅图5所示，所述COF接合区B、所述测试电路区T、所述测试垫区P及所述静电保护区E’可通过数个层叠且相互绝缘的金属层耦接。
举例而言，所述数个金属层包括一第一金属层、一第二金属层、一第三金属层及一第四金属层，所述第一金属层的电阻率及所述第二金属层的电阻率大于所述第三金属层的电阻率，所述第三金属层的电阻率等于所述第四金属层的电阻率，所述第四金属层形成数个第六区段M6，所述数个第六区段M6分别由所述测试电路区T的二侧横越所述二电源导体区V而转折横越所述二静电保护区E’以延伸至所述二测试垫区P，所述COF接合区B内的一布局(如图3所示)及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第七区段M7，所述数个第七区段M7分别由所述COF接合区B朝向所述测试电路区T延伸至所述测试电路区T与所述二电源导体区V之间，以个别地耦接所述第六区段M6。
具体地，所述第六区段M6与所述第七区段M7可通过数个贯接件(未绘示)耦接。
在一实施例中，如图5所示，所述二测试垫区P之间具有一中轴线C延伸通过所述COF接合区B及所述测试电路区T，所述数个第六区段M6及所述数个第七区段M7可分别在所述中轴线C的两侧对称地分布。
从而，可在现有的电路布局基础上新增所述第四金属层，所述第四金属层形成的第六区段的走线与所述第三金属层形成所述二电源导体区相互绝缘，不会发生短路问题；而且，由于所述测试垫区输出信号的走线以电阻率较小的所述第四金属层形成，不会发生明显的信号延迟，进而避免因信号延迟导致混色情况的发生，如在所述COF接合区与基于薄膜的芯片(COF)接合后，可使测试驱动的情况与正常工作时相似，以作为后续信号调节的参考。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (18)

  1. 一种显示面板的测试电路布局构造，其中，所述显示面板具有一面板轮廓，所述面板轮廓内定义在一有效区域周围的一边界布局区，所述边界布局区用以设置所述测试电路布局构造，所述测试电路布局构造包括：
    一COF接合区、二电源导体区、一测试电路区、二测试垫区及二静电保护区，所述COF接合区的二端连通所述二电源导体区，所述二电源导体区朝向所述有效区域延伸，所述测试电路区位于所述COF接合区与所述二电源导体区之间，所述二测试垫区、所述二静电保护区分布于所述COF接合区的二侧；
    其中，由所述测试垫区延伸数条走线，用以耦接所述静电保护区、所述COF接合区及所述测试电路区，所述走线的电阻率与所述电源导体区的电阻率相同，所述走线绕开同层设置的所述电源导体区，或者，所述走线与所述电源导体区绝缘地交叠；
    所述二测试垫区之间具有一中轴线延伸通过所述COF接合区及所述测试电路区，所述数条走线分别在所述中轴线的两侧对称地分布；及
    所述数条走线由数个不同金属层形成并通过数个贯接件耦接，所述贯接件贯通并连接所述数个金属层中的至少二金属层。
  2. 如权利要求1所述的显示面板的测试电路布局构造，其中，位于所述COF接合区同一侧的所述测试垫区位于所述静电保护区与所述电源导体区之间。
  3. 如权利要求2所述的显示面板的测试电路布局构造，其中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第三金属层的电阻率小于所述第一金属层及所述第二金属层的电阻率，所述第一金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第一区段，所述第二金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第二区段，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第三区段，所述数个第三区段分别由所述测试垫区横越所述静电保护区内的一布局，并转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局，并延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第一区段及所述第二区段。
  4. 如权利要求3所述的显示面板的测试电路布局构造，其中，所述二静电保护区位于所述COF接合区远离所述测试电路区的一界线与所述边界布局区远离所述测试电路区的一界线之间的一间距范围内。
  5. 如权利要求4所述的显示面板的测试电路布局构造，其中，所述第三区段在所述间距范围内转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局。
  6. 如权利要求1所述的显示面板的测试电路布局构造，其中，位于所述COF接合区同一侧的所述静电保护区位于所述测试垫区与所述电源导体区之间。
  7. 如权利要求6所述的显示面板的测试电路布局构造，其中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第一金属层、所述第二金属层与所述第三金属层的电阻率相同，所述第一金属层或所述第二金属层形成数个第四区段，所述数个第四区段分别由所述测试电路区的二侧横越所述二电源导体区，而转折横越所述二静电保护区，以延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第五区段，所述数个第五区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第四区段。
  8. 如权利要求6所述的显示面板的测试电路布局构造，其中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层、一第三金属层及一第四金属层，所述第一金属层的电阻率及所述第二金属层的电阻率大于所述第三金属层的电阻率，所述第三金属层的电阻率等于所述第四金属层的电阻率，所述第四金属层形成数个第六区段，所述数个第六区段分别由所述测试电路区的二侧横越所述二电源导体区，并转折以横越所述二静电保护区，并延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第七区段，所述数个第七区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第六区段。
  9. 一种显示面板的测试电路布局构造，其特征在于：所述显示面板具有一面板轮廓，所述面板轮廓内定义在一有效区域周围的一边界布局区，所述边界布局区用以设置所述测试电路布局构造，所述测试电路布局构造包括：
    一COF接合区、二电源导体区、一测试电路区、二测试垫区及二静电保护区，所述COF接合区的二端连通所述二电源导体区，所述二电源导体区朝向所述有效区域延伸，所述测试电路区位于所述COF接合区与所述二电源导体区之间，所述二测试垫区、所述二静电保护区分布于所述COF接合区的二侧；
    其中，由所述测试垫区延伸数条走线，用以耦接所述静电保护区、所述COF接合区及所述测试电路区，所述走线的电阻率与所述电源导体区的电阻率相同，所述走线绕开同层设置的所述电源导体区，或者，所述走线与所述电源导体区绝缘地交叠。
  10. 如权利要求9所述的显示面板的测试电路布局构造，其中，位于所述COF接合区同一侧的所述测试垫区位于所述静电保护区与所述电源导体区之间。
  11. 如权利要求10所述的显示面板的测试电路布局构造，其中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第三金属层的电阻率小于所述第一金属层及所述第二金属层的电阻率，所述第一金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第一区段，所述第二金属层形成由所述测试电路区的二侧朝向所述二电源导体区延伸的数个第二区段，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第三区段，所述数个第三区段分别由所述测试垫区横越所述静电保护区内的一布局，并转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局，并延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第一区段及所述第二区段。
  12. 如权利要求11所述的显示面板的测试电路布局构造，其中，所述二静电保护区位于所述COF接合区远离所述测试电路区的一界线与所述边界布局区远离所述测试电路区的一界线之间的一间距范围内。
  13. 如权利要求12所述的显示面板的测试电路布局构造，其中，所述第三区段在所述间距范围内转折而远离所述二电源导体区，以转折而横越所述COF接合区内的布局。
  14. 如权利要求9所述的显示面板的测试电路布局构造，其特征在于：位于所述COF接合区同一侧的所述静电保护区位于所述测试垫区与所述电源导体区之间。
  15. 如权利要求14所述的显示面板的测试电路布局构造，其中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层及一第三金属层，所述第一金属层、所述第二金属层与所述第三金属层的电阻率相同，所述第一金属层或所述第二金属层形成数个第四区段，所述数个第四区段分别由所述测试电路区的二侧横越所述二电源导体区，而转折横越所述二静电保护区，以延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第五区段，所述数个第五区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第四区段。
  16. 如权利要求14所述的显示面板的测试电路布局构造，其中，所述COF接合区、所述测试电路区、所述测试垫区及所述静电保护区通过数个层叠且相互绝缘的金属层耦接，所述数个金属层包括一第一金属层、一第二金属层、一第三金属层及一第四金属层，所述第一金属层的电阻率及所述第二金属层的电阻率大于所述第三金属层的电阻率，所述第三金属层的电阻率等于所述第四金属层的电阻率，所述第四金属层形成数个第六区段，所述数个第六区段分别由所述测试电路区的二侧横越所述二电源导体区，并转折以横越所述二静电保护区，并延伸至所述二测试垫区，所述COF接合区内的一布局及所述电源导体区由所述第三金属层形成，所述第三金属层还形成数个第七区段，所述数个第七区段分别由所述COF接合区朝向所述测试电路区延伸至所述测试电路区与所述二电源导体区之间，以个别地耦接所述第六区段。
  17. 如权利要求9所述的显示面板的测试电路布局构造，其中，所述二测试垫区之间具有一中轴线延伸通过所述COF接合区及所述测试电路区，所述数条走线分别在所述中轴线的两侧对称地分布。
  18. 如权利要求9所述的显示面板的测试电路布局构造，其中，所述数条走线由数个不同金属层形成并通过数个贯接件耦接，所述贯接件贯通并连接所述数个金属层中的至少二金属层。
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