WO2022252112A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022252112A1
WO2022252112A1 PCT/CN2021/097632 CN2021097632W WO2022252112A1 WO 2022252112 A1 WO2022252112 A1 WO 2022252112A1 CN 2021097632 W CN2021097632 W CN 2021097632W WO 2022252112 A1 WO2022252112 A1 WO 2022252112A1
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WO
WIPO (PCT)
Prior art keywords
pads
sub
power supply
display
pad
Prior art date
Application number
PCT/CN2021/097632
Other languages
English (en)
French (fr)
Inventor
杜丽丽
周宏军
魏锋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21943484.2A priority Critical patent/EP4202893A4/en
Priority to CN202180001402.1A priority patent/CN115701309A/zh
Priority to US17/782,164 priority patent/US20240194101A1/en
Priority to PCT/CN2021/097632 priority patent/WO2022252112A1/zh
Publication of WO2022252112A1 publication Critical patent/WO2022252112A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H10K59/1275—Electrical connections of the two substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode, referred to as OLED
  • OLED Organic Light-Emitting Diode
  • OLED organic light-emitting diode
  • An embodiment of the present disclosure provides a display substrate, including a display area and a non-display area at least partially surrounding the display area, the non-display area includes a binding area,
  • a plurality of first pads located in the binding area are configured to be electrically connected to an external electrical test circuit during the panel test phase, and configured to be bound to the circuit board, during the display phase transmitting the electrical signal of the circuit board to the display area;
  • a plurality of second pads located in the binding area are configured to be bound to the circuit board, and transmit the electrical signal of the circuit board to the display area during the display phase;
  • the plurality of first bonding pads and the plurality of second bonding pads are arranged side by side in the first direction, and the width of the plurality of first bonding pads in the first direction is larger than at least some of the plurality of second bonding pads. The width of the pad in the first direction.
  • the distance between two adjacent first pads is greater than at least part of the distance between two adjacent second pads, wherein the display area and The binding regions are arranged sequentially in a second direction, and the first direction intersects with the second direction.
  • the extension directions of the plurality of first pads and the plurality of second pads are substantially parallel to the second direction.
  • the orthographic projections of the plurality of first pads and the plurality of second pads on the display substrate are rectangles.
  • the lengths of the plurality of first pads in the second direction are greater than the lengths of at least part of the plurality of second pads in the second direction.
  • the plurality of first pads includes a first sub-pad group and a second sub-pad group
  • the first sub-pad group includes a plurality of first sub-pads
  • the second sub-pad group The pad group includes a plurality of second sub-pads located between the first sub-pad group and the second sub-pad group.
  • the plurality of second pads includes a third sub-pad group, a fourth sub-pad group, and a fifth sub-pad group
  • the third sub-pad group includes a plurality of third sub-pads pad
  • the fourth sub-pad group includes a plurality of fourth sub-pads
  • the fifth sub-pad group includes a plurality of fifth sub-pads
  • the fifth sub-pad group is located in the third sub-pad between the pad group and the fourth sub-pad group
  • the third sub-pad group and the fourth sub-pad group are located between the fifth sub-pad group.
  • the width of the plurality of third sub-pads and the plurality of fourth sub-pads in the first direction is greater than the width of at least part of the fifth sub-pads in the first direction .
  • the plurality of third sub-pads and the plurality of fourth sub-pads are configured to be electrically connected to an external electrical test circuit during the panel testing phase, and configured to be bound to the circuit board, and are configured to be bound to the circuit board during the display phase.
  • the electric signal of the circuit board is transmitted to the display area.
  • the display area includes a first boundary, a second boundary, a third boundary and a fourth boundary arranged in sequence, and the binding area is located in the non-display area close to the fourth boundary;
  • the display substrate also includes a first power supply line (VDD), a first power supply pin and a second power supply pin, and the first power supply line is connected to the first power supply pin and the second power supply pin;
  • VDD first power supply line
  • the first power line extends along the first direction and is located in the non-display area between the display area and the binding area;
  • the first power supply pin is located on a side of the plurality of first sub-pads away from the plurality of second pads
  • the second power supply pin is located on a side of the plurality of second sub-pads away from the plurality of second pads. one side of the plurality of second pads.
  • the display substrate further includes a second power line (VSS), a third power pin, and a fourth power pin, and the second power line, the third power pin, and the fourth power pin connections;
  • VSS second power line
  • third power pin third power pin
  • fourth power pin fourth power pin
  • the second power line is located in the non-display area and at least partially surrounds the first boundary, the second boundary and the third boundary, and the third power supply pin and the fourth power supply pin are located at the non-display area adjacent to the fourth boundary;
  • the third power supply pin is located on a side of the first power supply pin away from the plurality of second pads, and the fourth power supply pin is located on the side of the third power supply pin away from the plurality of second pads side.
  • the first power supply pin, the second power supply pin, the third power supply pin and the fourth power supply pin are configured to be electrically connected to an external electrical test circuit during the panel test phase , and is configured to bind with the circuit board, and transmit the electrical signal of the circuit board to the display area during the display phase.
  • the plurality of first sub-pads are located between the first power supply pin and the third power supply pin, and the plurality of second sub-pads are located between the second power supply pin and the fourth supply pin.
  • the plurality of first sub-pads are located on the side of the third power pin away from the first power pin, and the plurality of second sub-pads are located on the side of the fourth power pin. pin away from the side of the second supply pin.
  • the first power line is a positive voltage power line
  • the second power line is a negative voltage power line
  • At least one of the first power supply pin, the second power supply pin, the third power supply pin and the fourth power supply pin has a width in the first direction greater than the The width of the plurality of first bonding pads or the plurality of second bonding pads in the first direction.
  • the first pad is configured to transmit at least one of a gate driving signal, a multiplexer signal, and an electrical test signal.
  • the third sub-pad and the fourth sub-pad are respectively configured to transmit a high-level signal and a low-level signal
  • the fifth sub-pad is configured to transmit a data signal
  • it also includes a plurality of input pins and a plurality of output pins, the plurality of input pins and the plurality of output pins are located between the display area and the plurality of second pads , the multiple input pins are located on the side of the multiple output pins away from the display area;
  • the plurality of input pins and the plurality of output pins are configured to be bound to a driver IC;
  • the multiple input pins are connected to the multiple second pads through wires.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate, and the display device further includes a circuit board, and the plurality of first pads and the plurality of second pads are connected with the circuit board. board binding.
  • Figure 1 is a schematic diagram of the appearance of an OLED display product
  • FIG. 2 is a schematic structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 3-FIG. 6 are schematic structural diagrams of binding regions according to embodiments of the present disclosure.
  • the display substrate is provided with an electrical test pad area 01.
  • the probes of the electrical test circuit are connected to the electrical test pads in the electrical test pad area 01.
  • the width Dx of the lower border of the display substrate is closely related to the width of the left and right borders L/R of the display substrate.
  • the circuit board pad area 02 and the electrical test pad area 01 are set on the lower frame of the display substrate, resulting in a relatively large width Dx of the lower frame of the display substrate, and the width of the lower frame will drive the left and right sides of the display substrate.
  • the width of the frame L/R increases, especially for small-sized display products, if the area of the circuit board pad area 02 and the electrical test pad area 01 is too large, the width Dx of the lower frame of the display substrate will be much larger than that of the display The width of the area, and then widen the width of the left and right borders, resulting in a decrease in the screen ratio of the display area.
  • Embodiments of the present disclosure provide a display substrate and a display device, which can increase the screen-to-body ratio of a display area.
  • An embodiment of the present disclosure provides a display substrate, including a display area and a non-display area at least partially surrounding the display area, the non-display area includes a binding area,
  • a plurality of first pads located in the binding area are configured to be electrically connected to an external electrical test circuit during the panel test phase, and configured to be bound to the circuit board, during the display phase transmitting the electrical signal of the circuit board to the display area;
  • a plurality of second pads located in the binding area are configured to be bound to the circuit board, and transmit the electrical signal of the circuit board to the display area during the display phase;
  • the plurality of first bonding pads and the plurality of second bonding pads are arranged side by side in the first direction, and the width of the plurality of first bonding pads in the first direction is larger than at least some of the plurality of second bonding pads. The width of the pad in the first direction.
  • the first pad can be electrically connected to the external electrical test circuit during the panel testing stage, and can also be bound to the circuit board, and the electrical signal of the circuit board can be transmitted to the display area during the display stage, that is, the first pad can be As an electrical test pad, it can also be used as a circuit board pad, so that there is no need to set up a special area to place the electrical test pad, which can reduce the total area occupied by the circuit board pad area 02 and the electrical test pad area 01, and reduce The width Dx of the lower border of the display substrate can further reduce the width of the left and right borders of the display substrate, increase the screen-to-body ratio of the display area, and realize a narrow border.
  • the external electrical test circuit is electrically connected to the first pad to conduct an electrical test on the display substrate to detect whether there are foreign objects, uneven brightness (mura), bright spots, dark spots and the like in the display substrate. Defective, to ensure that the layout and routing of the display substrate and the display function are intact.
  • the driving circuit board is bound to the first pad and the second pad, so that in the display stage, the circuit board can pass the electrical signal through the first pad and the second pad. It is transmitted to the display area, and the display area is driven for display.
  • the first pad has two boundaries approximately perpendicular to the first direction, and the shortest distance between the two boundaries is the width of the first pad in the first direction; the second pad has a width parallel to the first direction. For two substantially perpendicular boundaries, the shortest distance between the two boundaries is the width of the second pad in the first direction.
  • the first pad 031 in the pads of the circuit board is multiplexed as an electrical test pad.
  • Probe connection because the size of the probe of the electrical test circuit is relatively large, therefore, the width of the first pad 031 in the first direction should be greater than the width of at least part of the second pad 032 in the first direction, so that the first pad 032 can be guaranteed.
  • a pad 031 is electrically connected to the probes of the electrical test circuit.
  • the distance between adjacent first pads 031 also needs to be designed relatively large, so that short circuits between adjacent probes can be avoided during electrical testing.
  • the second pads 032 are used to input electrical signals to the display area. In order to reduce the area occupied by pads on the circuit board, the distance between adjacent second pads 032 can be set relatively small. Therefore, in the first direction, the distance between two adjacent first pads is greater than at least part of the distance between two adjacent second pads, wherein the display area and the binding
  • the fixed areas are arranged sequentially in a second direction, and the first direction intersects with the second direction.
  • the extension directions of the plurality of first pads 031 and the plurality of second pads 032 are substantially parallel to the second direction.
  • the layout of the display area and the non-display area may not need to be changed compared with the display substrate of the related art.
  • the non-display area of the display substrate includes the binding area located in the lower border of the display substrate, the circuit units located in the upper half of the left and right borders of the display substrate, and the clock multiplexing circuit and fan-out area located in the lower half of the left and right borders of the display substrate.
  • part of the circuit board pads can be reused as electrical test pads, which is low cost and easy to popularize.
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a base substrate, and the base substrate includes a display area 10 and a non-display area 11 surrounding the display area 10 .
  • a plurality of sub-pixels P, a plurality of data lines DATA and a plurality of gate lines are arranged in the display area 10 .
  • the display substrate also includes a plurality of first power lines VD located in the display area 10 and a first power bus VDD located in the non-display area 11 close to the first boundary (lower side boundary) of the display area 10.
  • the power line VD is electrically connected to the first power bus VDD.
  • each column of sub-pixels P is electrically connected to a first power supply line VD, and a plurality of first power supply lines VD electrically connected to multiple columns of sub-pixels P are drawn out from the display area 10 to connect to the non-display area 11. in the first power bus VDD.
  • the display area 10 includes a first border 101, a second border 102, a third border 103 and a fourth border 104 (such as a lower border, a left border, an upper border and a right border) connected in sequence, wherein the binding area 40 is located in the non-display area 11 near the first border (lower border) of the display area 10 .
  • the number of the first pads depends on the test requirements, and the number of the first pads needs to be determined according to the requirements of the electrical test; the total number of the circuit board pads depends on the resolution of the display substrate and the properties of the driving circuit board .
  • the total number of pads on the circuit board can be determined according to the resolution of the display substrate and the properties of the driving circuit board, and then the number of the first pads can be determined according to the requirements of the electrical test.
  • the total number of circuit board pads and the number of first pads determine the number of second pads; then determine the spacing between the first pads and the spacing between the second pads according to the space of the lower frame of the display substrate and the process conditions, The spacing of the first pads meets the requirements of the electrical test, and the spacing of the second pads meets the requirements of the input electrical signal.
  • the first pad acts as an electrical test pad.
  • the first pad and the second pad jointly serve as the pads of the circuit board to transmit the electric signal for driving the circuit board to the display area.
  • the number of the first pads can be 10-50, such as 21; the width of the first pads in the first direction can be 50-500um, when the first pads are used to communicate with VDD signal lines and When the VSS signal line is connected, the width of the first pad in the first direction can be 50-500um, such as 280um; when the first pad is used to connect with other signal lines, the width of the first pad in the first direction
  • the width can be 20-200um, such as 90um.
  • the number of the second pads may be 20-1000, such as 104; the width of the second pads in the first direction may be 10-100um, such as 57um.
  • the first pad is first connected to the electrical test circuit of the display substrate through wiring, and then the electrical test circuit is connected to the signal line of the AA area (display area) to test whether the display substrate can be displayed normally; the second pad is passed through
  • the wiring is first connected to the IC PIN (pin of the drive circuit board) at the input end of the display substrate, and the signal is transmitted to the IC bound on the display substrate for processing, and then transmitted to the data line in the AA area through the IC PIN at the output end to make it The corresponding screen is displayed.
  • IC PIN pin of the drive circuit board
  • the display substrate here refers to the structure when the driving circuit board has not been bound in the binding area during the production process of the display device. Before the circuit board is bound, the external electrical test circuit and the first pad The display substrate can be detected to determine whether there is an abnormality in the display substrate. Only the display substrate with a normal substrate detection can be further bound to the circuit board, which is conducive to improving the production yield of the product.
  • the first pad has two boundaries approximately perpendicular to the second direction, and the shortest distance between the two boundaries is the length of the first pad in the second direction;
  • the shortest distance between two boundaries approximately perpendicular to the second direction is the length of the second pad in the second direction.
  • the orthographic projections of the plurality of first pads 031 and the plurality of second pads 032 on the display substrate are rectangular, which can match the probes of the external electrical test circuit and the pins of the circuit board, wherein, the orthographic projection is a rectangle, which means that the width of the first pad in the first direction is smaller than the length in the second direction; the orthographic projection is a rectangle, which means that the width of the second pad in the first direction is smaller than the length in the second direction. length.
  • the plurality of first pads 031 and the length in the second direction are longer than at least part of the plurality of second pads 032 length in the second direction. In this way, the electrical connection between the first pad 031 and the probes of the electrical test circuit can be ensured.
  • the plurality of first pads 031 includes a first sub-pad group and a second sub-pad group
  • the first sub-pad group includes a plurality of first sub-pads pad 0311
  • the second sub-pad group includes a plurality of second sub-pads 0312
  • the plurality of second pads 032 are located between the first sub-pad group and the second sub-pad group .
  • the plurality of second pads 032 includes a third sub-pad group, a fourth sub-pad group, and a fifth sub-pad group, and the third sub-pad group
  • the pad group includes a plurality of third sub-pads 0323
  • the fourth sub-pad group includes a plurality of fourth sub-pads 0324
  • the fifth sub-pad group includes a plurality of fifth sub-pads 0325
  • Part or all of the fifth sub-pad group may be located between the third sub-pad group and the fourth sub-pad group; or
  • the third sub-pad group and the fourth sub-pad group are located between the fifth sub-pad group.
  • the third sub-pad group and the fourth sub-pad group are located between the fifth sub-pad group; it may also be a part of the third sub-pad group Located between the fifth sub-pad group, another part of the third sub-pad is located outside the fifth sub-pad group; it may also be that a part of the fourth sub-pad is located in the fifth sub-pad Between the groups, another part of the fourth sub-pads is located outside the fifth sub-pad group; it may also be that both the third sub-pad group and the fourth sub-pad group are located outside the fifth sub-pad group.
  • the third sub-pad group is located between the fifth sub-pad group, but the fourth sub-pad group is located between the fifth sub-pad group outside.
  • both the third sub-pad group and the fourth sub-pad group are located outside the fifth sub-pad group.
  • the width of the plurality of third sub-pads 0323 and the plurality of fourth sub-pads 0324 in the first direction is larger than that of at least part of the fifth sub-pads 0325 in the first direction. Width up.
  • the plurality of third sub-pads The sub-pad 0323 and the plurality of fourth sub-pads 0324 are configured to be electrically connected to an external electrical test circuit during the panel testing phase, and configured to be bound to the circuit board, and to transmit electrical signals of the circuit board during the display phase to the display area.
  • the display area includes a first boundary, a second boundary, a third boundary and a fourth boundary arranged in sequence, and the binding area is located in the non-display area close to the fourth boundary;
  • the display substrate also includes a first power supply line 038 (VDD), a first power supply pin 033 and a second power supply pin 034, and the first power supply line 038 is connected to the first power supply pin 033.
  • the second power supply pin 034 is connected;
  • the first power line 038 extends along the first direction and is located in the non-display area between the display area and the binding area;
  • the first power pin 033 is located on the side of the plurality of first sub-pads 0311 away from the plurality of second pads 032, and the second power pin 034 is located on the side of the plurality of second sub-pads.
  • the pad 0312 is away from the side of the plurality of second pads.
  • the display substrate further includes a second power supply line 037 (VSS), a third power supply pin 035 and a fourth power supply pin 036, and the second power supply line 037 and the The third power supply pin 035 and the fourth power supply pin 036 are connected;
  • VSS second power supply line
  • third power supply pin 035 and a fourth power supply pin 036 are connected;
  • the second power line 037 is located in the non-display area and at least partially surrounds the first border, the second border and the third border, the third power pin 035 and the fourth power pin
  • the pin 036 is located in the non-display area close to the fourth boundary
  • the third power supply pin 035 is located on the side of the first power supply pin 033 away from the plurality of second pads 032, and the fourth power supply pin 036 is located on the side of the third power supply pin 034 away from the multiple second pads 032. One side of the second pad 032.
  • the first power supply pin 033, the second power supply pin 034, the third power supply pin 035 and the fourth power supply pin 036 are configured to communicate with external electrical
  • the test circuit is electrically connected and configured to be bound to the circuit board, and transmits the electrical signal of the circuit board to the display area during the display phase.
  • the first power supply pin 033, the second power supply pin 034, the third power supply pin 035 and the fourth power supply pin 036 can be used as circuit board pins, and can also be reused as electrical Test pins can reduce the number of pins in the bonding area.
  • the plurality of first sub-pads 0311 are located between the first power supply pin 033 and the third power supply pin 035, and the plurality of second sub-pads
  • the disk 0312 is located between said second power supply pin 034 and said fourth power supply pin 036 .
  • the plurality of first sub-pads 0311 are located on the side of the third power supply pin 035 away from the first power supply pin 033, and the plurality of second sub-pads
  • the pad 0312 is located on a side of the fourth power pin 036 away from the second power pin 034 .
  • the first power line 038 may be a positive voltage power line
  • the second power line 037 may be a negative voltage power line.
  • the first power supply pin 033, the second power supply pin 034, the third power supply pin 035 and the fourth power supply pin 036 At least one width in the first direction is greater than the width in the first direction of the plurality of first pads or the plurality of second pads.
  • the first pad 031 is configured to transmit at least one of a gate driving signal, a multiplexer signal, and an electrical test signal.
  • the third subpad 0323 and the fourth subpad 0324 are configured to transmit high level signals and low level signals respectively, and the fifth subpad 0325 is configured to transmit data Signal.
  • the installation area of the first pad 031 is symmetrically arranged at both ends of the binding area.
  • electrical test signals need to be respectively input to both sides of the display area in the first direction through the first pads.
  • the first pads are arranged at both ends of the bonding area.
  • the display The substrate also includes a plurality of input pins 041 and a plurality of output pins 042, the plurality of input pins 041 and the plurality of output pins 042 are located between the display area and the plurality of second pads 032 Between, the multiple input pins 041 are located on the side of the multiple output pins 042 away from the display area;
  • the plurality of input pins 041 and the plurality of output pins 042 are configured to be bound to a driver IC;
  • the plurality of input pins 041 are connected to the plurality of second pads 032 through wires 039 .
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate, the display device further includes a circuit board, the plurality of first pads and the plurality of second pads are connected to the Board binding.
  • the display device includes but not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply.
  • a radio frequency unit a network module
  • an audio output unit an input unit
  • a sensor a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor and a power supply.
  • the display device includes but is not limited to a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer, wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a display area and a non-display area at least partially surrounding the display area, the non-display area includes a binding area, the manufacturing method Also includes:
  • a plurality of first pads are formed in the bonding region, and the plurality of first pads are configured to be electrically connected to an external electrical test circuit during the panel testing phase, and configured to be bound to a circuit board, and are configured to be bound to a circuit board during the display phase. transmitting the electrical signal of the circuit board to the display area;
  • a plurality of second pads are formed in the binding area, the plurality of second pads are configured to be bound to the circuit board, and transmit the electrical signal of the circuit board to the display area during the display stage;
  • the plurality of first bonding pads and the plurality of second bonding pads are arranged side by side in the first direction, and the width of the plurality of first bonding pads in the first direction is larger than at least some of the plurality of second bonding pads. The width of the pad in the first direction.
  • the first pad can be electrically connected to the external electrical test circuit during the panel testing stage, and can also be bound to the circuit board, and the electrical signal of the circuit board can be transmitted to the display area during the display stage, that is, the first pad can be As an electrical test pad, it can also be used as a circuit board pad, so that there is no need to set up a special area to place the electrical test pad, which can reduce the total area occupied by the circuit board pad area 02 and the electrical test pad area 01, and reduce The width Dx of the lower border of the display substrate can further reduce the width of the left and right borders of the display substrate, increase the screen-to-body ratio of the display area, and realize a narrow border.
  • the external electrical test circuit is electrically connected to the first pad to conduct an electrical test on the display substrate to detect whether there are foreign objects, uneven brightness (mura), bright spots, dark spots and the like in the display substrate. Defective, to ensure that the layout and routing of the display substrate and the display function are intact.
  • the driving circuit board is bound to the first pad and the second pad, so that in the display stage, the circuit board can pass the electrical signal through the first pad and the second pad. It is transmitted to the display area, and the display area is driven for display.
  • the first pad has two boundaries approximately perpendicular to the first direction, and the shortest distance between the two boundaries is the width of the first pad in the first direction; the second pad has a width parallel to the first direction. For two substantially perpendicular boundaries, the shortest distance between the two boundaries is the width of the second pad in the first direction.
  • the first pad 031 in the pads of the circuit board is multiplexed as an electrical test pad.
  • Probe connection because the size of the probe of the electrical test circuit is relatively large, therefore, the width of the first pad 031 in the first direction should be greater than the width of at least part of the second pad 032 in the first direction, so that the first pad 032 can be guaranteed
  • a pad 031 is electrically connected to the probes of the electrical test circuit.
  • the distance between adjacent first pads 031 also needs to be designed relatively large, so that short circuits between adjacent probes can be avoided during electrical testing.
  • the second pads 032 are used to input electrical signals to the display area. In order to reduce the area occupied by pads on the circuit board, the distance between adjacent second pads 032 can be set relatively small. Therefore, in the first direction, the distance between two adjacent first pads is greater than at least part of the distance between two adjacent second pads, wherein the display area and the binding
  • the fixed areas are arranged sequentially in a second direction, and the first direction intersects with the second direction.
  • the extension directions of the plurality of first pads 031 and the plurality of second pads 032 are substantially parallel to the second direction.
  • the layout of the display area and the non-display area may not need to be changed compared with the display substrate of the related art.
  • the non-display area of the display substrate includes the binding area located in the lower border of the display substrate, the circuit units located in the upper half of the left and right borders of the display substrate, and the clock multiplexing circuit and fan-out area located in the lower half of the left and right borders of the display substrate.
  • part of the circuit board pads in the binding area part of the circuit board pads can be reused as electrical test pads, which is low cost and easy to popularize.
  • forming a plurality of first pads and second pads includes:
  • the number of the first pads depends on the test requirements, and the number of the first pads needs to be determined according to the requirements of the electrical test; the total number of the circuit board pads depends on the resolution of the display substrate and the properties of the driving circuit board . Therefore, in this embodiment, before manufacturing the display substrate, the total number of pads on the circuit board can be determined according to the resolution of the display substrate and the properties of the driving circuit board, and then the number of the first pads can be determined according to the requirements of the electrical test.
  • the total number of circuit board pads and the number of first pads determine the number of second pads; then determine the spacing between the first pads and the spacing between the second pads according to the space of the lower frame of the display substrate and the process conditions, The spacing of the first pads meets the requirements of the electrical test, and the spacing of the second pads meets the requirements of the input electrical signal. In this way, when the display substrate is electrically tested, the first pad acts as an electrical test pad. After the circuit board is bound, the first pad and the second pad jointly serve as the pads of the circuit board to transmit the electric signal for driving the circuit board to the display area.
  • the number of the first pads can be 10-50, such as 21; the width of the first pads in the first direction can be 50-500um, when the first pads are used to communicate with VDD signal lines and When the VSS signal line is connected, the width of the first pad in the first direction can be 50-500um, such as 280um; when the first pad is used to connect with other signal lines, the width of the first pad in the first direction
  • the width can be 20-200um, such as 90um.
  • the number of the second pads may be 20-1000, such as 104; the width of the second pads in the first direction may be 10-100um, such as 57um.
  • the first pad is first connected to the electrical test circuit of the display substrate through wiring, and then the electrical test circuit is connected to the signal line of the AA area (display area) to test whether the display substrate can be displayed normally; the second pad is passed through
  • the wiring is first connected to the IC PIN (pin of the drive circuit board) at the input end of the display substrate, and the signal is transmitted to the IC bound on the display substrate for processing, and then transmitted to the data line in the AA area through the IC PIN at the output end to make it The corresponding screen is displayed.
  • IC PIN pin of the drive circuit board
  • the display substrate here refers to the structure when the driving circuit board has not been bound in the binding area during the production process of the display device. Before the circuit board is bound, the external electrical test circuit and the first pad The display substrate can be detected to determine whether there is an abnormality in the display substrate. Only the display substrate with a normal substrate detection can be further bound to the circuit board, which is conducive to improving the production yield of the product.
  • the first pad has two boundaries approximately perpendicular to the second direction, and the shortest distance between the two boundaries is the length of the first pad in the second direction;
  • the shortest distance between two boundaries approximately perpendicular to the second direction is the length of the second pad in the second direction.
  • the orthographic projections of the plurality of first pads 031 and the plurality of second pads 032 on the display substrate are rectangular, which can match the probes of the external electrical test circuit and the pins of the circuit board, wherein, the orthographic projection is a rectangle, which means that the width of the first pad in the first direction is smaller than the length in the second direction; the orthographic projection is a rectangle, which means that the width of the second pad in the first direction is smaller than the length in the second direction. length.
  • the plurality of first pads 031 and the length in the second direction are longer than at least part of the plurality of second pads 032 length in the second direction. In this way, the electrical connection between the first pad 031 and the probes of the electrical test circuit can be ensured.
  • An embodiment of the present disclosure also provides a test method for a display substrate, which is applied to the above-mentioned display substrate, and the test method includes:
  • an electrical testing signal is sent to the first pad through an external electrical testing circuit.
  • the display substrate here refers to the structure when the driving circuit board has not been bound in the binding area during the production process of the display device. Before the driving circuit board is bound, the external electrical test circuit and the first pad The display substrate can be detected to determine whether there is an abnormality in the display substrate. Only the display substrate with a normal substrate detection can be further bound to the driving circuit board, which is conducive to improving the production yield of the product.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for related parts, please refer to the description of the product embodiment.

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Abstract

本公开提供了一种显示基板及显示装置，属于显示技术领域。显示基板包括显示区和至少部分围绕所述显示区的非显示区，所述非显示区包括绑定区，多个第一焊盘，位于所述绑定区，所述多个第一焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；多个第二焊盘，位于所述绑定区，所述多个第二焊盘被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；所述多个第一焊盘和所述多个第二焊盘在第一方向上并排排布，所述多个第一焊盘在第一方向上的宽度大于至少部分所述多个第二焊盘在所述第一方向上的宽度。本公开的技术方案能够提升显示区的屏占比。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，特别是指一种显示基板及显示装置。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管，简称OLED)显示装置由于具有薄、轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，已被列为极具发展前景的下一代显示技术，在电视、智能手机、智能穿戴、VR、汽车显示等各大领域得到广泛应用。
随着OLED显示产品的发展，“屏占比”已经成为智能手机和穿戴设备等OLED智能产品外观中极为热门的词汇，然而产品的尺寸不能无限增长，想获得更高的屏占比就只能从缩减显示屏幕边框入手。所以，随着消费者对显示产品便携、视角效果等方面的追求，极致窄边框甚至全屏显示成为OLED产品发展的新趋势。
发明内容
本公开的实施例提供一种显示基板，包括显示区和至少部分围绕所述显示区的非显示区，所述非显示区包括绑定区，
多个第一焊盘，位于所述绑定区，所述多个第一焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
多个第二焊盘，位于所述绑定区，所述多个第二焊盘被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
所述多个第一焊盘和所述多个第二焊盘在第一方向上并排排布，所述多个第一焊盘在第一方向上的宽度大于至少部分所述多个第二焊盘在所述第一方向上的宽度。
一些实施例中，在第一方向上，相邻两个所述第一焊盘之间的距离大于至少部分相邻两个所述第二焊盘之间的距离，其中，所述显示区和所述绑定区在第二方向上依次排布，所述第一方向与所述第二方向相交。
一些实施例中，所述多个第一焊盘和所述多个第二焊盘的延伸方向与所述第二方向大致平行。
一些实施例中，所述多个第一焊盘和所述多个第二焊盘在所述显示基板上的正投影为矩形。
一些实施例中，所述多个第一焊盘在所述第二方向上的长度大于至少部分所述多个第二焊盘在所述第二方向上的长度。
一些实施例中，所述多个第一焊盘包括第一子焊盘组和第二子焊盘组，所述第一子焊盘组包括多个第一子焊盘，所述第二子焊盘组包括多个第二子焊盘，所述多个第二焊盘位于所述第一子焊盘组和所述第二子焊盘组之间。
一些实施例中，所述多个第二焊盘包括第三子焊盘组、第四子焊盘组和第五子焊盘组，所述第三子焊盘组包括多个第三子焊盘，所述第四子焊盘组包括多个第四子焊盘，所述第五子焊盘组包括多个第五子焊盘，所述第五子焊盘组位于所述第三子焊盘组和所述第四子焊盘组之间；或
所述第三子焊盘组和所述第四子焊盘组位于所述第五子焊盘组之间。
一些实施例中，所述多个第三子焊盘、多个第四子焊盘在所述第一方向上的宽度大于至少部分所述第五子焊盘在所述第一方向上的宽度。
一些实施例中，所述多个第三子焊盘、多个第四子焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区。
一些实施例中，所述显示区包括依次设置的第一边界、第二边界、第三边界和第四边界，所述绑定区位于靠近所述第四边界的所述非显示区；
所述显示基板还包括第一电源线(VDD)、第一电源引脚和第二电源引脚，所述第一电源线与所述第一电源引脚、所述第二电源引脚连接；
所述第一电源线沿所述第一方向延伸，且位于所述显示区和所述绑定区之间的所述非显示区；
所述第一电源引脚位于所述多个第一子焊盘远离所述多个第二焊盘的一侧，所述第二电源引脚位于所述多个第二子焊盘远离所述多个第二焊盘的一侧。
一些实施例中，所述显示基板还包括第二电源线(VSS)、第三电源引脚和第四电源引脚，所述第二电源线和所述第三电源引脚、所述第四电源引脚连接；
所述第二电源线位于所述非显示区且至少部分围绕所述第一边界、所述第二边界和所述第三边界，所述第三电源引脚和所述第四电源引脚位于靠近所述第四边界的所述非显示区；
所述第三电源引脚位于所述第一电源引脚远离所述多个第二焊盘的一侧，所述第四电源引脚位于第三电源引脚远离所述多个第二焊盘的一侧。
一些实施例中，所述第一电源引脚、所述第二电源引脚、所述第三电源引脚和所述第四电源引脚被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区。
一些实施例中，所述多个第一子焊盘位于所述第一电源引脚和所述第三电源引脚之间，所述多个第二子焊盘位于所述第二电源引脚和所述第四电源引脚之间。
一些实施例中，所述多个第一子焊盘位于所述第三电源引脚远离所述第一电源引脚的一侧，所述多个第二子焊盘位于所述第四电源引脚远离所述第二电源引脚的一侧。
一些实施例中，所述第一电源线为正电压电源线，所述第二电源线为负电压电源线。
一些实施例中，所述第一电源引脚、所述第二电源引脚、所述第三电源引脚和所述第四电源引脚中的至少一个在所述第一方向的宽度大于所述多个第一焊盘或所述多个第二焊盘在所述第一方向的宽度。
一些实施例中，所述第一焊盘被配置为传输栅极驱动信号，多路复用器信号、电学测试信号中的至少一项。
一些实施例中，所述第三子焊盘和所述第四子焊盘分别被配置为传输高电平信号和低电平信号，所述第五子焊盘被配置为传输数据信号。
一些实施例中，还包括多个输入引脚和多个输出引脚，所述多个输入引脚和所述多个输出引脚位于所述显示区和所述多个第二焊盘之间，所述多个输入引脚位于所述多个输出引脚远离所述显示区的一侧；
所述多个输入引脚和所述多个输出引脚被配置为与驱动IC绑定；
所述多个输入引脚通过导线与所述多个第二焊盘连接。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板，所述显示装置还包括电路板，所述多个第一焊盘和所述多个第二焊盘与所述电路板绑定。
附图说明
图1为OLED显示产品的外形示意图；
图2为本公开实施例显示基板的结构示意图；
图3-图6为本公开实施例绑定区的结构示意图。
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
在显示基板的制程中，在绑定电路板前，一般要进行电学测试，检测显示基板内是否有异物、亮度不均(mura)、亮点、暗点之类的不良，以确保显示基板的布局走线和显示功能完好，如图1所示，显示基板上设置有电学测试焊盘区01，在进行电学测试时，电学测试电路的探针与电学测试焊盘区01的电学测试焊盘连接，进行电学测试；另外，如图1所示，显示基板上还设置有电路板焊盘区02，电路板焊盘区02包括多个用于与驱动电路板绑定的电路板焊盘。
显示基板的下边框的宽度Dx与显示基板的左右边框L/R的宽度紧密相关。如图1所示，电路板焊盘区02和电学测试焊盘区01设置在显示基板的 下边框，导致显示基板的下边框的宽度Dx比较大，下边框的宽度又会带动显示基板的左右边框L/R的宽度增加，尤其对于小尺寸的显示产品来说，如果电路板焊盘区02和电学测试焊盘区01的面积过大，会导致显示基板的下边框的宽度Dx远大于显示区的宽度，进而加宽左右边框的宽度，导致显示区的屏占比降低。
本公开实施例提供一种显示基板及显示装置，能够提升显示区的屏占比。
本公开的实施例提供一种显示基板，包括显示区和至少部分围绕所述显示区的非显示区，所述非显示区包括绑定区，
多个第一焊盘，位于所述绑定区，所述多个第一焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
多个第二焊盘，位于所述绑定区，所述多个第二焊盘被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
所述多个第一焊盘和所述多个第二焊盘在第一方向上并排排布，所述多个第一焊盘在第一方向上的宽度大于至少部分所述多个第二焊盘在所述第一方向上的宽度。
本实施例中，第一焊盘可以在面板测试阶段与外接电学测试电路电连接，还可以与电路板绑定，在显示阶段将电路板的电信号传输至显示区，即第一焊盘可以作为电学测试焊盘，还可以作为电路板焊盘，这样无需设置专门的区域来放置电学测试焊盘，能够减少电路板焊盘区02和电学测试焊盘区01所占的总面积，减小显示基板下边框的宽度Dx，进而减小显示基板左右边框的宽度，提高显示区的屏占比，实现窄边框。
其中，在面板测试阶段，将外部电学测试电路与第一焊盘电连接，以对显示基板进行电学测试，检测显示基板内是否有异物、亮度不均(mura)、亮点、暗点之类的不良，以确保显示基板的布局走线和显示功能完好。在制作好显示基板并进行电学测试后，将驱动用电路板与第一焊盘和第二焊盘绑定，这样在显示阶段，电路板可以通过第一焊盘和第二焊盘将电信号传输至显示区，驱动显示区进行显示。其中，第一焊盘具有与第一方向大致垂直的两个 边界，该两个边界之间的最短距离即为第一焊盘在第一方向上的宽度；第二焊盘具有与第一方向大致垂直的两个边界，该两个边界之间的最短距离即为第二焊盘在第一方向上的宽度。
本实施例中，如图3-图6所示，电路板焊盘中的第一焊盘031复用为电学测试焊盘，在进行电学测试时，第一焊盘031需要与电学测试电路的探针连接，由于电学测试电路的探针的尺寸较大，因此，第一焊盘031在第一方向上的宽度应大于至少部分第二焊盘032第一方向上的宽度，这样可以保证第一焊盘031与电学测试电路的探针的电连接。
另外，相邻第一焊盘031之间的距离也需要设计的比较大，这样在进行电学测试时，可以避免相邻探针之间短路。而第二焊盘032是为了向显示区输入电信号，为了减小电路板焊盘所占面积，相邻第二焊盘032之间的间距可以设置的比较小。因此，在第一方向上，相邻两个所述第一焊盘之间的距离大于至少部分相邻两个所述第二焊盘之间的距离，其中，所述显示区和所述绑定区在第二方向上依次排布，所述第一方向与所述第二方向相交。
一些实施例中，所述多个第一焊盘031和所述多个第二焊盘032的延伸方向与所述第二方向大致平行。本实施例中，显示区和非显示区的布局与相关技术的显示基板相比，可以无需改变。显示基板的非显示区包括位于显示基板下边框的绑定区、位于显示基板左右边框上半部分的电路单元以及位于显示基板左右边框下半部分的时钟多路复用电路、扇出区等。本实施例仅对绑定区的部分电路板焊盘的间距和/或尺寸进行调整即可实现将部分电路板焊盘复用为电学测试焊盘，实现成本低，易于推广。
图2为本公开实施例显示基板的结构示意图，显示基板包括衬底基板，衬底基板包括显示区域10和围绕显示区域10的非显示区域11。
显示区域10中布置有多个子像素P、多条数据线DATA和多条栅极线。显示基板还包括位于显示区域10中的多条第一电源线VD和位于靠近显示区域10的第一边界(下侧边界)的非显示区域11的第一电源总线VDD，所述多条第一电源线VD和第一电源总线VDD电连接。在显示区域10中，每一列子像素P电连接一条第一电源线VD，与多列子像素P分别电连接的多条 第一电源线VD从显示区域10引出，从而连接到位于非显示区域11中的第一电源总线VDD。
显示区域10包括依次连接的第一边界101、第二边界102、第三边界103和第四边界104(例如下侧边界、左侧边界、上侧边界和右侧边界)，其中，绑定区40位于靠近显示区域10的第一边界(下侧边界)的非显示区域11。本实施例中，第一焊盘的数量取决于测试要求，需要根据电学测试的需求来确定第一焊盘的数量；电路板焊盘的总数取决于显示基板的分辨率以及驱动电路板的属性。因此，本实施例中，在制作显示基板前，可以根据显示基板的分辨率以及驱动电路板的属性确定电路板焊盘的总数，再根据电学测试的需求来确定第一焊盘的数量，根据电路板焊盘的总数和第一焊盘的数量确定第二焊盘的数量；再根据显示基板的下边框的空间以及工艺条件确定第一焊盘之间的间距和第二焊盘的间距，使得第一焊盘的间距满足电学测试的要求，第二焊盘的间距满足输入电信号的要求，这样在显示基板进行电学测试时，第一焊盘充当电学测试焊盘，在显示基板与驱动电路板绑定后，第一焊盘和第二焊盘共同作为电路板焊盘将驱动电路板的电信号传递至显示区。
一具体实施例中，第一焊盘的数量可以为10-50，比如21；第一焊盘在第一方向上的宽度可以为50-500um，当第一焊盘用于与VDD信号线以及VSS信号线连接时，第一焊盘在第一方向上的宽度可以为50-500um，比如280um；当第一焊盘用于与其他信号线连接时，第一焊盘在第一方向上的宽度可以为20-200um，比如90um。
第二焊盘的数量可以为20—1000，比如104；第二焊盘在第一方向上的宽度可以为10-100um，比如57um。
第一焊盘是通过走线先与显示基板的电学测试电路连接，电学测试电路再与AA区(显示区)的信号线连接，用来测试显示基板是否可以正常显示；第二焊盘是通过走线先与显示基板的输入端的IC PIN(驱动电路板的引脚)连接，把信号传输给绑定在显示基板上的IC处理，然后通过输出端的IC PIN传输给AA区的数据线使其显示对应的画面。在进行电学测试时，仅是将测试探针搭在第一焊盘上给其信号测试，测试完成后，用于电学测试的第一焊 盘没有任何损害，故仍可用于进行绑定FPC(柔性电路板)，而不会受到影响。
还需说明的是，这里的显示基板指的是显示装置生产过程中尚未在绑定区绑定驱动用电路板时的结构，在绑定电路板之前，通过外部电学测试电路和第一焊盘可以对显示基板进行检测，判断显示基板是否存在异常，仅基板检测正常的显示基板方可进一步绑定电路板，从而有利于提升产品的生产良率。
一些实施例中，第一焊盘具有与第二方向大致垂直的两个边界，该两个边界之间的最短距离即为第一焊盘在第二方向上的长度；第二焊盘具有与第二方向大致垂直的两个边界，该两个边界之间的最短距离即为第二焊盘在第二方向上的长度。
所述多个第一焊盘031和所述多个第二焊盘032在所述显示基板上的正投影为矩形，这样可以与外部电学测试电路的探针以及电路板的引脚相匹配，其中，正投影为矩形表示第一焊盘在第一方向上的宽度小于在第二方向上的长度；正投影为矩形表示第二焊盘在第一方向上的宽度小于在第二方向上的长度。
由于电学测试电路的探针的尺寸较大，因此，一些实施例中，所述多个第一焊盘031和在所述第二方向上的长度大于至少部分所述多个第二焊盘032在所述第二方向上的长度。这样可以保证第一焊盘031与电学测试电路的探针的电连接。
一些实施例中，如图3所示，所述多个第一焊盘031包括第一子焊盘组和第二子焊盘组，所述第一子焊盘组包括多个第一子焊盘0311，所述第二子焊盘组包括多个第二子焊盘0312，所述多个第二焊盘032位于所述第一子焊盘组和所述第二子焊盘组之间。
一些实施例中，如图3-图6所示，所述多个第二焊盘032包括第三子焊盘组、第四子焊盘组和第五子焊盘组，所述第三子焊盘组包括多个第三子焊盘0323，所述第四子焊盘组包括多个第四子焊盘0324，所述第五子焊盘组包括多个第五子焊盘0325，
部分或全部所述第五子焊盘组可以位于所述第三子焊盘组和所述第四子 焊盘组之间；或
一些实施例中，所述第三子焊盘组和所述第四子焊盘组位于所述第五子焊盘组之间。
如图6所示，可以是全部所述第三子焊盘组和所述第四子焊盘组均位于所述第五子焊盘组之间；还可以是一部分所述第三子焊盘位于所述第五子焊盘组之间，另一部分第三子焊盘位于所述第五子焊盘组之外；还可以是一部分所述第四子焊盘位于所述第五子焊盘组之间，另一部分第四子焊盘位于所述第五子焊盘组之外；还可以是第三子焊盘组和第四子焊盘组均位于第五子焊盘组之外。
一具体示例中，如图3所示，所述第三子焊盘组位于所述第五子焊盘组之间，但所述第四子焊盘组位于所述第五子焊盘组之外。
另一具体示例中，如图4-图5所示，所述第三子焊盘组和所述第四子焊盘组均位于所述第五子焊盘组之外。
一些实施例中，所述多个第三子焊盘0323、多个第四子焊盘0324在所述第一方向上的宽度大于至少部分所述第五子焊盘0325在所述第一方向上的宽度。
一些实施例中，由于第三子焊盘0323和第四子焊盘0324在第一方向上的宽度比较大，满足与外部电学测试电路的探针连接的要求，因此，所述多个第三子焊盘0323、多个第四子焊盘0324被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区。
一些实施例中，所述显示区包括依次设置的第一边界、第二边界、第三边界和第四边界，所述绑定区位于靠近所述第四边界的所述非显示区；
如图3所示，所述显示基板还包括第一电源线038(VDD)、第一电源引脚033和第二电源引脚034，所述第一电源线038与所述第一电源引脚033、所述第二电源引脚034连接；
所述第一电源线038沿所述第一方向延伸，且位于所述显示区和所述绑定区之间的所述非显示区；
所述第一电源引脚033位于所述多个第一子焊盘0311远离所述多个第二焊盘032的一侧，所述第二电源引脚034位于所述多个第二子焊盘0312远离所述多个第二焊盘的一侧。
一些实施例中，如图3所示，所述显示基板还包括第二电源线037(VSS)、第三电源引脚035和第四电源引脚036，所述第二电源线037和所述第三电源引脚035、所述第四电源引脚036连接；
所述第二电源线037位于所述非显示区且至少部分围绕所述第一边界、所述第二边界和所述第三边界，所述第三电源引脚035和所述第四电源引脚036位于靠近所述第四边界的所述非显示区；
所述第三电源引脚035位于所述第一电源引脚033远离所述多个第二焊盘032的一侧，所述第四电源引脚036位于第三电源引脚034远离所述多个第二焊盘032的一侧。
一些实施例中，所述第一电源引脚033、所述第二电源引脚034、所述第三电源引脚035和所述第四电源引脚036被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区。这样所述第一电源引脚033、所述第二电源引脚034、所述第三电源引脚035和所述第四电源引脚036可为作为电路板引脚，还可复用为电学测试引脚，能够减少绑定区的引脚数量。
一些实施例中，如图4所示，所述多个第一子焊盘0311位于所述第一电源引脚033和所述第三电源引脚035之间，所述多个第二子焊盘0312位于所述第二电源引脚034和所述第四电源引脚036之间。
一些实施例中，如图5所示，所述多个第一子焊盘0311位于所述第三电源引脚035远离所述第一电源引脚033的一侧，所述多个第二子焊盘0312位于所述第四电源引脚036远离所述第二电源引脚034的一侧。
上述实施例中，所述第一电源线038可以为正电压电源线，所述第二电源线037可以为负电压电源线。
一些实施例中，为了保证电连接的可靠性，所述第一电源引脚033、所述第二电源引脚034、所述第三电源引脚035和所述第四电源引脚036中的 至少一个在所述第一方向的宽度大于所述多个第一焊盘或所述多个第二焊盘在所述第一方向的宽度。
一些实施例中，所述第一焊盘031被配置为传输栅极驱动信号，多路复用器信号、电学测试信号中的至少一项。
一些实施例中，所述第三子焊盘0323和所述第四子焊盘0324分别被配置为传输高电平信号和低电平信号，所述第五子焊盘0325被配置为传输数据信号。
一些实施例中，如图3所示，沿第一方向，所述第一焊盘031的设置区域对称设置于所述绑定区的两端。在进行电学测试时，需要通过第一焊盘向显示区在第一方向上的两侧分别输入电学测试信号，为了方便走线，因此将第一焊盘设置在绑定区的两端。
在显示基板制备好,未与驱动电路板绑定之前，显示基板上只有待与驱动电路板绑定的输入引脚和输出引脚，一些实施例中，如图4-图6所示，显示基板还包括多个输入引脚041和多个输出引脚042，所述多个输入引脚041和所述多个输出引脚042位于所述显示区和所述多个第二焊盘032之间，所述多个输入引脚041位于所述多个输出引脚042远离所述显示区的一侧；
所述多个输入引脚041和所述多个输出引脚042被配置为与驱动IC绑定；
所述多个输入引脚041通过导线039与所述多个第二焊盘032连接。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板，所述显示装置还包括电路板，所述多个第一焊盘和所述多个第二焊盘与所述电路板绑定。
该显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开的实施例还提供了一种显示基板的制作方法，所述显示基板包括显示区和至少部分围绕所述显示区的非显示区，所述非显示区包括绑定区，所述制作方法还包括：
在所述绑定区形成多个第一焊盘，所述多个第一焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
在所述绑定区形成多个第二焊盘，所述多个第二焊盘被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
所述多个第一焊盘和所述多个第二焊盘在第一方向上并排排布，所述多个第一焊盘在第一方向上的宽度大于至少部分所述多个第二焊盘在所述第一方向上的宽度。
本实施例中，第一焊盘可以在面板测试阶段与外接电学测试电路电连接，还可以与电路板绑定，在显示阶段将电路板的电信号传输至显示区，即第一焊盘可以作为电学测试焊盘，还可以作为电路板焊盘，这样无需设置专门的区域来放置电学测试焊盘，能够减少电路板焊盘区02和电学测试焊盘区01所占的总面积，减小显示基板下边框的宽度Dx，进而减小显示基板左右边框的宽度，提高显示区的屏占比，实现窄边框。
其中，在面板测试阶段，将外部电学测试电路与第一焊盘电连接，以对显示基板进行电学测试，检测显示基板内是否有异物、亮度不均(mura)、亮点、暗点之类的不良，以确保显示基板的布局走线和显示功能完好。在制作好显示基板并进行电学测试后，将驱动用电路板与第一焊盘和第二焊盘绑定，这样在显示阶段，电路板可以通过第一焊盘和第二焊盘将电信号传输至显示区，驱动显示区进行显示。
其中，第一焊盘具有与第一方向大致垂直的两个边界，该两个边界之间的最短距离即为第一焊盘在第一方向上的宽度；第二焊盘具有与第一方向大 致垂直的两个边界，该两个边界之间的最短距离即为第二焊盘在第一方向上的宽度。
本实施例中，如图3-图6所示，电路板焊盘中的第一焊盘031复用为电学测试焊盘，在进行电学测试时，第一焊盘031需要与电学测试电路的探针连接，由于电学测试电路的探针的尺寸较大，因此，第一焊盘031在第一方向上的宽度应大于至少部分第二焊盘032第一方向上的宽度，这样可以保证第一焊盘031与电学测试电路的探针的电连接。
另外，相邻第一焊盘031之间的距离也需要设计的比较大，这样在进行电学测试时，可以避免相邻探针之间短路。而第二焊盘032是为了向显示区输入电信号，为了减小电路板焊盘所占面积，相邻第二焊盘032之间的间距可以设置的比较小。因此，在第一方向上，相邻两个所述第一焊盘之间的距离大于至少部分相邻两个所述第二焊盘之间的距离，其中，所述显示区和所述绑定区在第二方向上依次排布，所述第一方向与所述第二方向相交。
一些实施例中，所述多个第一焊盘031和所述多个第二焊盘032的延伸方向与所述第二方向大致平行。
本实施例中，显示区和非显示区的布局与相关技术的显示基板相比，可以无需改变。显示基板的非显示区包括位于显示基板下边框的绑定区、位于显示基板左右边框上半部分的电路单元以及位于显示基板左右边框下半部分的时钟多路复用电路、扇出区等。本实施例仅对绑定区的部分电路板焊盘的间距和/或尺寸进行调整即可实现将部分电路板焊盘复用为电学测试焊盘，实现成本低，易于推广。
一些实施例中，形成多个第一焊盘和第二焊盘包括：
确定用于与外部的电学测试电路连接的第一焊盘的数量和尺寸，在所述绑定区按照所述数量和尺寸制作所述第一焊盘，并在所述绑定区按照电路板焊盘的尺寸制作第二焊盘，所述第二焊盘与所述第一焊盘之和等于需要的电路板焊盘的数量。
本实施例中，第一焊盘的数量取决于测试要求，需要根据电学测试的需求来确定第一焊盘的数量；电路板焊盘的总数取决于显示基板的分辨率以及 驱动电路板的属性。因此，本实施例中，在制作显示基板前，可以根据显示基板的分辨率以及驱动电路板的属性确定电路板焊盘的总数，再根据电学测试的需求来确定第一焊盘的数量，根据电路板焊盘的总数和第一焊盘的数量确定第二焊盘的数量；再根据显示基板的下边框的空间以及工艺条件确定第一焊盘之间的间距和第二焊盘的间距，使得第一焊盘的间距满足电学测试的要求，第二焊盘的间距满足输入电信号的要求，这样在显示基板进行电学测试时，第一焊盘充当电学测试焊盘，在显示基板与驱动电路板绑定后，第一焊盘和第二焊盘共同作为电路板焊盘将驱动电路板的电信号传递至显示区。
一具体实施例中，第一焊盘的数量可以为10-50，比如21；第一焊盘在第一方向上的宽度可以为50-500um，当第一焊盘用于与VDD信号线以及VSS信号线连接时，第一焊盘在第一方向上的宽度可以为50-500um，比如280um；当第一焊盘用于与其他信号线连接时，第一焊盘在第一方向上的宽度可以为20-200um，比如90um。
第二焊盘的数量可以为20—1000，比如104；第二焊盘在第一方向上的宽度可以为10-100um，比如57um。
第一焊盘是通过走线先与显示基板的电学测试电路连接，电学测试电路再与AA区(显示区)的信号线连接，用来测试显示基板是否可以正常显示；第二焊盘是通过走线先与显示基板的输入端的IC PIN(驱动电路板的引脚)连接，把信号传输给绑定在显示基板上的IC处理，然后通过输出端的IC PIN传输给AA区的数据线使其显示对应的画面。在进行电学测试时，仅是将测试探针搭在第一焊盘上给其信号测试，测试完成后，用于电学测试的第一焊盘没有任何损害，故仍可用于进行绑定FPC(柔性电路板)，而不会受到影响。
还需说明的是，这里的显示基板指的是显示装置生产过程中尚未在绑定区绑定驱动用电路板时的结构，在绑定电路板之前，通过外部电学测试电路和第一焊盘可以对显示基板进行检测，判断显示基板是否存在异常，仅基板检测正常的显示基板方可进一步绑定电路板，从而有利于提升产品的生产良率。
一些实施例中，第一焊盘具有与第二方向大致垂直的两个边界，该两个 边界之间的最短距离即为第一焊盘在第二方向上的长度；第二焊盘具有与第二方向大致垂直的两个边界，该两个边界之间的最短距离即为第二焊盘在第二方向上的长度。
所述多个第一焊盘031和所述多个第二焊盘032在所述显示基板上的正投影为矩形，这样可以与外部电学测试电路的探针以及电路板的引脚相匹配，其中，正投影为矩形表示第一焊盘在第一方向上的宽度小于在第二方向上的长度；正投影为矩形表示第二焊盘在第一方向上的宽度小于在第二方向上的长度。
由于电学测试电路的探针的尺寸较大，因此，一些实施例中，所述多个第一焊盘031和在所述第二方向上的长度大于至少部分所述多个第二焊盘032在所述第二方向上的长度。这样可以保证第一焊盘031与电学测试电路的探针的电连接。
本公开的实施例还提供了一种显示基板的测试方法，应用于如上所述的显示基板，所述测试方法包括：
在面板测试阶段，通过外部的电学测试电路向与第一焊盘发送电学测试信号。
还需说明的是，这里的显示基板指的是显示装置生产过程中尚未在绑定区绑定驱动电路板时的结构，在绑定驱动电路板之前，通过外部电学测试电路和第一焊盘可以对显示基板进行检测，判断显示基板是否存在异常，仅基板检测正常的显示基板方可进一步绑定驱动电路板，从而有利于提升产品的生产良率。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不 同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，其特征在于，包括显示区和至少部分围绕所述显示区的非显示区，所述非显示区包括绑定区，
    多个第一焊盘，位于所述绑定区，所述多个第一焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
    多个第二焊盘，位于所述绑定区，所述多个第二焊盘被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区；
    所述多个第一焊盘和所述多个第二焊盘在第一方向上并排排布，所述多个第一焊盘在第一方向上的宽度大于至少部分所述多个第二焊盘在所述第一方向上的宽度。
  2. 根据权利要求1所述的显示基板，其特征在于，在第一方向上，相邻两个所述第一焊盘之间的距离大于至少部分相邻两个所述第二焊盘之间的距离，其中，所述显示区和所述绑定区在第二方向上依次排布，所述第一方向与所述第二方向相交。
  3. 根据权利要求2所述的显示基板，其特征在于，所述多个第一焊盘和所述多个第二焊盘的延伸方向与所述第二方向大致平行。
  4. 根据权利要求1所述的显示基板，其特征在于，所述多个第一焊盘和所述多个第二焊盘在所述显示基板上的正投影为矩形。
  5. 根据权利要求2所述的显示基板，其特征在于，所述多个第一焊盘在所述第二方向上的长度大于至少部分所述多个第二焊盘在所述第二方向上的长度。
  6. 根据权利要求1所述的显示基板，其特征在于，所述多个第一焊盘包括第一子焊盘组和第二子焊盘组，所述第一子焊盘组包括多个第一子焊盘，所述第二子焊盘组包括多个第二子焊盘，所述多个第二焊盘位于所述第一子焊盘组和所述第二子焊盘组之间。
  7. 根据权利要求1所述的显示基板，其特征在于，所述多个第二焊盘包 括第三子焊盘组、第四子焊盘组和第五子焊盘组，所述第三子焊盘组包括多个第三子焊盘，所述第四子焊盘组包括多个第四子焊盘，所述第五子焊盘组包括多个第五子焊盘，所述第五子焊盘组位于所述第三子焊盘组和所述第四子焊盘组之间；或
    所述第三子焊盘组和所述第四子焊盘组位于所述第五子焊盘组之间。
  8. 根据权利要求7所述的显示基板，其特征在于，所述多个第三子焊盘、多个第四子焊盘在所述第一方向上的宽度大于至少部分所述第五子焊盘在所述第一方向上的宽度。
  9. 根据权利要求7所述的显示基板，其特征在于，所述多个第三子焊盘、多个第四子焊盘被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区。
  10. 根据权利要求6所述的显示基板，其特征在于，所述显示区包括依次设置的第一边界、第二边界、第三边界和第四边界，所述绑定区位于靠近所述第四边界的所述非显示区；
    所述显示基板还包括第一电源线、第一电源引脚和第二电源引脚，所述第一电源线与所述第一电源引脚、所述第二电源引脚连接；
    所述第一电源线沿所述第一方向延伸，且位于所述显示区和所述绑定区之间的所述非显示区；
    所述第一电源引脚位于所述多个第一子焊盘远离所述多个第二焊盘的一侧，所述第二电源引脚位于所述多个第二子焊盘远离所述多个第二焊盘的一侧。
  11. 根据权利要求10所述的显示基板，其特征在于，所述显示基板还包括第二电源线、第三电源引脚和第四电源引脚，所述第二电源线和所述第三电源引脚、所述第四电源引脚连接；
    所述第二电源线位于所述非显示区且至少部分围绕所述第一边界、所述第二边界和所述第三边界，所述第三电源引脚和所述第四电源引脚位于靠近所述第四边界的所述非显示区；
    所述第三电源引脚位于所述第一电源引脚远离所述多个第二焊盘的一 侧，所述第四电源引脚位于第三电源引脚远离所述多个第二焊盘的一侧。
  12. 根据权利要求11所述的显示基板，其特征在于，所述第一电源引脚、所述第二电源引脚、所述第三电源引脚和所述第四电源引脚被配置为在面板测试阶段与外接电学测试电路电连接，且被配置为与电路板绑定，在显示阶段将所述电路板的电信号传输至所述显示区。
  13. 根据权利要求11所述的显示基板，其特征在于，所述多个第一子焊盘位于所述第一电源引脚和所述第三电源引脚之间，所述多个第二子焊盘位于所述第二电源引脚和所述第四电源引脚之间。
  14. 根据权利要求11所述的显示基板，其特征在于，所述多个第一子焊盘位于所述第三电源引脚远离所述第一电源引脚的一侧，所述多个第二子焊盘位于所述第四电源引脚远离所述第二电源引脚的一侧。
  15. 根据权利要求11所述的显示基板，其特征在于，所述第一电源线为正电压电源线，所述第二电源线为负电压电源线。
  16. 根据权利要求11所述的显示基板，其特征在于，所述第一电源引脚、所述第二电源引脚、所述第三电源引脚和所述第四电源引脚中的至少一个在所述第一方向的宽度大于所述多个第一焊盘或所述多个第二焊盘在所述第一方向的宽度。
  17. 根据权利要求1所述的显示基板，其特征在于，所述第一焊盘被配置为传输栅极驱动信号，多路复用器信号、电学测试信号中的至少一项。
  18. 根据权利要求7所述的显示基板，其特征在于，所述第三子焊盘和所述第四子焊盘分别被配置为传输高电平信号和低电平信号，所述第五子焊盘被配置为传输数据信号。
  19. 根据权利要求1-18任一项所述的显示基板，其特征在于，还包括多个输入引脚和多个输出引脚，所述多个输入引脚和所述多个输出引脚位于所述显示区和所述多个第二焊盘之间，所述多个输入引脚位于所述多个输出引脚远离所述显示区的一侧；
    所述多个输入引脚和所述多个输出引脚被配置为与驱动IC绑定；
    所述多个输入引脚通过导线与所述多个第二焊盘连接。
  20. 一种显示装置，其特征在于，包括如权利要求1-19中任一项所述的显示基板，所述显示装置还包括电路板，所述多个第一焊盘和所述多个第二焊盘与所述电路板绑定。
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