WO2020124897A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2020124897A1
WO2020124897A1 PCT/CN2019/083143 CN2019083143W WO2020124897A1 WO 2020124897 A1 WO2020124897 A1 WO 2020124897A1 CN 2019083143 W CN2019083143 W CN 2019083143W WO 2020124897 A1 WO2020124897 A1 WO 2020124897A1
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WO
WIPO (PCT)
Prior art keywords
metal
test
flip
display panel
traces
Prior art date
Application number
PCT/CN2019/083143
Other languages
English (en)
French (fr)
Inventor
明星
陈彩琴
王一伊
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/644,511 priority Critical patent/US11145561B2/en
Publication of WO2020124897A1 publication Critical patent/WO2020124897A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present application relates to the field of display, and in particular to a display panel and a manufacturing method thereof.
  • the display panel includes a display area and a non-display area.
  • the display area has a thin film transistor array, and a phase staggered array composed of spaced data lines and gate lines;
  • the non-display area is disposed outside the display area, and has an array test circuit and a flip-chip film for electrically testing the array substrate (COF) and test points (Test Pad).
  • COF array substrate
  • Test Pad test points
  • an array test (Array test) circuit needs to be provided on the display panel to perform array test after the array substrate is completed.
  • the array test circuit is located between the test pad (Test Pad) and the flip chip (COF).
  • the test signal is written by the test point (Test Pad), and transmitted into the display area through the test circuit to test the array substrate.
  • the control device in the test circuit is turned off.
  • the test signal is provided by a flexible circuit board (FPC) bonded on a flip chip (COF).
  • test circuit in the display panel not only complicates the structure of the display panel, but also increases the incidence of electrostatic damage, but cutting off the test circuit can cause the exposed portions of metal traces to be eroded. Therefore, there is an urgent need for a display panel and its manufacturing method to solve the above-mentioned problems.
  • the present application provides a display panel and a method for manufacturing the same, to solve the problem that part of the metal traces are exposed and eroded after the test structure is cut off in the display panel, thereby affecting the quality of the display panel.
  • This application proposes a method for manufacturing a display panel, including the following steps:
  • Step S10 Provide a substrate, the substrate including a display area and a non-display area provided outside the display area, and a flip chip and a test structure are provided in the non-display area;
  • the test structure includes:
  • a test circuit between the test point and the flip chip includes a signal trace connecting the flip chip and the test point, and the signal trace includes non-metal traces and metal traces connected to each other Line, the signal line is provided with a cutting line;
  • Step S20 Test the display area of the substrate through the test structure
  • Step S30 Remove the test points along the cutting line to form the display panel.
  • the signal traces include metal traces at both ends and non-metal traces in the middle, and the metal traces include first metal traces connected to the flip chip The second metal trace connected to the connection point of the test point, the cutting line is located within the range of the non-metal trace.
  • the cutting line intersects the non-metallic trace, and the distance from the cutting line to both ends of the non-metallic trace is greater than or equal to 100 microns.
  • the cutting line intersects the second metal trace, and the length of the non-metal trace is 100 ⁇ m to 150 ⁇ m.
  • the substrate includes a stacked substrate, a polysilicon layer, a buffer layer, and a metal layer;
  • the non-metal traces are located in the polysilicon layer, the metal traces are located in the metal layer, the buffer layer is provided with vias, and the non-metal traces pass through the vias and the metal traces Electrically connect to form signal traces.
  • the substrate further includes a planarization layer, a groove exists in the planarization layer, and the flip chip and the test point are disposed in the groove.
  • the preparation material of the non-metal traces includes polysilicon, and the metal traces are one of gate traces, source-drain traces, and transparent metal traces.
  • the step S30 includes removing the test points along the cutting line by laser cutting to form a display panel.
  • m adjacent flip-chip films form a flip-chip film group
  • the test points correspond one-to-one with the flip-chip film group
  • m is an integer greater than or equal to 1;
  • the test circuit includes the same number of transistors as the flip-chip film, the transistors correspond to the flip-chip film in one-to-one correspondence, and the transistor is electrically connected to the second metal trace;
  • the transistors corresponding to the flip-chip films with the same serial number from left to right are electrically connected to each other to form a transistor group, and the test circuit controls the transistors by switching and closing the transistor group Display area test.
  • a display panel including: a display area and a non-display area surrounding the display area;
  • the display area includes:
  • a metal layer disposed on the buffer layer includes metal traces, the metal traces are electrically connected to the non-metal traces through the vias, and the metal traces are located in the grooves Inside;
  • the non-display area includes a flip chip and a non-metal trace that prevents the metal trace from being eroded.
  • the flip chip is electrically connected to one of the non-metal trace and the metal trace.
  • a method for manufacturing a display panel includes the following steps:
  • Step S10 Provide a substrate, the substrate including a display area and a non-display area provided outside the display area, and a flip chip and a test structure are provided in the non-display area;
  • the test structure includes:
  • test point located on a side of the flip-chip film away from the display area, where the test points correspond to the flip-chip film one-to-one;
  • a test circuit between the test point and the flip chip includes a signal trace connecting the flip chip and the test point, and the signal trace includes non-metal traces and metal traces connected to each other Line, the signal line is provided with a cutting line;
  • Step S20 Test the display area of the substrate through the test structure
  • Step S30 Remove the test points along the cutting line to form the display panel.
  • the signal traces include metal traces at both ends and non-metal traces in the middle, and the metal traces include first metal traces connected to the flip chip The second metal trace connected to the connection point of the test point, the cutting line is located within the range of the non-metal trace.
  • the cutting line intersects the non-metallic trace, and the distance from the cutting line to both ends of the non-metallic trace is greater than or equal to 100 microns.
  • the cutting line intersects the second metal trace, and the length of the non-metal trace is 100 ⁇ m to 150 ⁇ m.
  • the substrate includes a stacked substrate, a polysilicon layer, a buffer layer, and a metal layer;
  • the non-metal traces are located in the polysilicon layer, the metal traces are located in the metal layer, the buffer layer is provided with vias, and the non-metal traces pass through the vias and the metal traces Electrically connect to form signal traces.
  • the substrate further includes a planarization layer, a groove exists in the planarization layer, and the flip chip and the test point are disposed in the groove.
  • the preparation material of the non-metal traces includes polysilicon, and the metal traces are one of gate traces, source-drain traces, and transparent metal traces.
  • the step S30 includes removing the test points along the cutting line by laser cutting to form a display panel.
  • m adjacent flip-chip films form a flip-chip film group
  • the test points correspond one-to-one with the flip-chip film group
  • m is an integer greater than or equal to 1;
  • the test circuit includes the same number of transistors as the flip-chip film, the transistors correspond to the flip-chip film in one-to-one correspondence, and the transistor is electrically connected to the second metal trace;
  • the transistors corresponding to the flip-chip films with the same serial number from left to right are electrically connected to each other to form a transistor group, and the test circuit controls the transistors by switching and closing the transistor group Display area test.
  • the test points can be removed without eroding the metal traces, thereby simplifying the structure of the display panel and reducing the incidence of electrostatic damage.
  • FIG. 1 is a schematic structural diagram of a test structure of a display panel in the prior art
  • Figure 2 is a schematic flowchart of a method of manufacturing a display panel in an embodiment of the present application
  • FIG. 3 is a schematic structural view of a test structure in a display panel before being cut in an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a display panel in an embodiment of this application.
  • FIG. 5 is a schematic structural diagram of a display panel in another embodiment of this application.
  • FIG. 6 is a schematic structural diagram of a test structure in a display panel before being cut in another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel in another embodiment of this application.
  • FIG. 8 is a schematic structural diagram of a test structure in a display panel before being cut in yet another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a test structure in a display panel before being cut in yet another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a partial structure of a display panel in this application.
  • the present application provides a test structure of a display panel, to solve the problem that the metal traces in the display panel are eroded after the test structure is cut off, thereby affecting the quality of the display panel.
  • This embodiment can improve the defect.
  • FIG. 2 is a schematic flowchart of a method of manufacturing a display panel in an embodiment of the present application.
  • This application provides a method for manufacturing a display panel, including:
  • FIG. 3 is a schematic structural diagram of a test panel in a display panel before being cut according to an embodiment of the present application.
  • Step S10 a substrate 2 is provided, the substrate 2 includes a display area 21 and a non-display area 22 disposed outside the display area 21, and a flip chip 221 and a test structure are provided in the non-display area 22;
  • the flip chip 221 is used to generate a test signal.
  • the flip chip 221 includes a substrate and a flexible circuit board disposed on the substrate, and the test signal is generated on the flexible circuit board.
  • the test structure includes:
  • Test point 223 and test circuit 222
  • the test point 223 is used to receive the test signal and transmit the test signal to the display area 21.
  • the test point 223 is located on the side of the flip chip 221 away from the display area 21.
  • the test point 223 is used to test the display area. After the display area is tested, the test point 223 can be removed to simplify the structure of the display panel.
  • the test circuit is disposed between the test point 223 and the flip chip 221, and includes a signal trace 222 connecting the flip chip 221 and the test point 223;
  • the signal trace 222 includes a non-metal trace 222 a and a metal trace 222 b connected to each other, and the signal trace 222 is provided with a cutting line 23.
  • the signal traces by setting the signal traces to be a mixture of metal traces 222a and non-metal traces 222b, after cutting the test points, a section can be left in the signal traces 222 to prevent metal
  • the non-metallic trace 222b corroded by water and oxygen in the air to improve the durability of the display panel.
  • the test structure further includes a cutting line 23, which is used to cut along the cutting line 23 to remove the test point 223 after the test structure tests the display panel.
  • the non-display area 22 of the display panel includes a reserved area and a cutting area, the reserved area and the cutting area are defined by the cutting line 23, and the area where the test point 223 is located is the cutting area.
  • the cutting method of the cutting line 23 is laser cutting.
  • Step S20 Test the display area 21 of the substrate through the test structure
  • Step S30 Remove the test point 223 along the cutting line 23 to form a display panel
  • FIG. 4 is a schematic structural diagram of a display panel in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a display panel in another embodiment of the present application.
  • the signal wiring 222 When testing the display area 21, the signal wiring 222 needs to be used for signal transmission. Therefore, while ensuring the water and oxygen resistance of the non-metallic trace 222b, it is also necessary to ensure its conductivity to reduce the impedance of the non-metallic trace 222b.
  • the non-metallic trace 222b it is necessary to make the non-metallic trace 222b as short as possible; but due to the consideration of the cutting accuracy when cutting according to the cutting line 23, the length of the non-metallic trace 222b is designed at Within a reasonable range.
  • the cutting line 23 intersects the non-metallic trace 222b, and the distance between the cutting line 23 and both ends of the non-metallic trace 222b is greater than or equal to 100 microns, that is, when the cutting When the line 23 is located in the middle of the non-metallic trace 222b, the minimum length of the non-metallic trace 222b is 200 microns.
  • the cutting line 23 is provided on the non-metallic trace 222b.
  • the cutting line 23 is provided on the second metal trace. The advantage of this design is that it can shorten the length of the non-metallic trace 222b. The length reduces the impedance of the signal trace 222 when testing the display area 21.
  • FIG. 6 is a schematic structural diagram of a test structure of a display panel in another embodiment of this application.
  • the cutting line 23 intersects the second metal trace, and the length of the non-metal trace 222b is 100 ⁇ m to 150 ⁇ m.
  • FIG. 7 is a schematic structural diagram of a test point in a test structure of a display panel in another embodiment of the present application with the test points removed.
  • the substrate may include a substrate, a polysilicon layer, a buffer layer, and a metal layer that are stacked.
  • the non-metal trace 222b is located in the polysilicon layer, the metal trace 222a is located in the metal layer, the buffer layer is provided with a via, and the non-metal trace 222b passes through The via is electrically connected to the metal trace 222a to form a signal trace 222.
  • the same photomask is used to prepare the non-metallic traces 222b while preparing the polysilicon layer, the same photomask is used to prepare the metal traces when the metal layer is prepared, and the same photomask is used to prepare the via holes when the buffer layer is prepared, thereby eliminating the need for The additional process to prepare the signal traces greatly reduces the manufacturing cost of the test structure.
  • the technical solution of the present application is not limited to preparing vias in the buffer layer to connect the metal trace 222a and the non-metal trace 222b. When the metal layer and the polysilicon layer further include other film layers, The vias also penetrate the other layer structures accordingly to connect the metal trace 222a and the non-metal trace 222b.
  • the substrate further includes a planarization layer, a groove exists in the planarization layer, the flip chip 2221 and the test point 223 are disposed in the groove, so that display is performed During the preparation of the panel, the protrusion of the flip-chip film 2221 and the test point 223 can prevent the problem that the positions thereof are not fixed well.
  • the material for preparing the non-metal trace 222b includes polysilicon, and the metal trace 222a is one of a gate trace, a source-drain trace, and a transparent metal trace.
  • the metal wiring in the application is not limited to the above example, as long as it is the metal layer structure of the display panel, it may be considered to prepare the metal wiring 222a in this application simultaneously.
  • the polysilicon in order to improve the conductive performance of the non-metal trace 222b, is doped with at least one of boron and phosphorus.
  • test points 223 correspond to the flip-chip films 221 one-to-one; however, the relationship between the flip-chip films 221 and the test points 223 in this application is not limited to one-to-one correspondence. There is a case where one test point 223 corresponds to multiple flip-chip films 221.
  • FIG. 8 is a schematic structural diagram of a test structure in a display panel before being cut in yet another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a test structure in a display panel before being cut in yet another embodiment of the present application.
  • m adjacent flip-chip films 221 form a flip-chip film group
  • the test points 223 correspond to the flip-chip film groups one by one
  • m is an integer greater than or equal to 1;
  • the test circuit includes the same number of transistors 24a as the flip-chip film 223, the transistor 24a corresponds to the flip-chip film 223 one-to-one, and the transistor 24a is electrically connected to the second metal trace;
  • the transistors corresponding to the flip-chip films with the same serial number from left to right are electrically connected to each other to form a transistor group, and the test circuit controls the transistors by switching and closing the transistor group Display area 21 test.
  • the test circuit controls the transistors by switching and closing the transistor group Display area 21 test.
  • the testing of the display area includes array testing.
  • test point and part of the test circuit will be removed after the test of the display area 21 is completed, this part does not require a packaging structure, so the test of the display area can also be performed at the end of the preparation process.
  • the length of the non-metal traces is controllable, the impedance from the test circuit to the flip-chip film can be reduced; finally, since the bare traces after cutting include non-metal traces, water and oxygen can be reduced The erosion of the signal wiring, thereby improving product yield.
  • a display panel including: a display area 21 and a non-display area 22 surrounding the display area;
  • the display area 21 includes:
  • the non-display area 22 includes a flip-chip film 221 and a non-metal trace 222b to prevent the metal trace 222a from being eroded.
  • the flip-chip film 221 and the non-metal trace 222b and the metal trace 222a One of them is electrically connected.
  • the working principle of the display panel is similar to the working principle of the manufacturing method of the display panel.
  • the working principle of the display panel please refer to the working principle of the manufacturing method of the display panel, which will not be repeated here.
  • the test points can be removed without eroding the metal lines, thereby simplifying the structure of the display panel and reducing the incidence of electrostatic damage .

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Abstract

本申请提供了一种显示面板及其制作方法，所述制作方法包括：提供一包括显示区域和非显示区域的基板，非显示区域内设置有测试点和测试电路，测试电路包括具有相互连接的非金属走线和金属走线的信号走线，信号走线上设置有切割线；通过测试结构对基板的显示区域进行测试；将所述测试点除掉。

Description

显示面板及其制作方法 技术领域
本申请涉及显示领域，具体涉及一种显示面板及其制作方法。
 背景技术
在现有的显示面板中，显示面板包括显示区域和非显示区域。显示区域具有薄膜晶体管阵列，以及相间隔的数据线与栅极线所组成的相交错阵列；非显示区域设置于显示区域的外侧，具有对阵列基板进行电性测试的阵列测试电路、覆晶薄膜(COF)以及测试点（Test Pad）。
如图1所示，在显示面板的生产过程中，需要在显示面板上设置阵列测试（Array测试）电路以在阵列基板完成后对进行阵列测试。阵列测试电路位于测试点（Test Pad）和覆晶薄膜(COF)之间。对阵列基板进行测试时，测试信号由测试点（Test Pad）写入，经过测试电路传输入显示区域对阵列基板进行测试。在阵列测试结束后，将测试电路中的控制器件关闭。测试信号由邦定在覆晶薄膜(COF)上的柔性电路板（FPC）提供。显示面板中由于测试电路的存在，不仅复杂了显示面板的结构，而且会提高静电损伤发生率，但是切除了所述测试电路会导致金属走线裸露部分被侵蚀。因此，目前亟需一种显示面板及其制作方法以解决上述问题。
 技术问题
本申请提供了一种显示面板及其制作方法，以解决显示面板中由于测试结构被切除后部分金属走线裸露被侵蚀，进而影响显示面板品质的问题。
 技术解决方案
本申请提出了一种显示面板的制作方法，包括如下步骤：
步骤S10、提供一基板，所述基板包括显示区域和设置在所述显示区域外侧的非显示区域，所述非显示区域内设置有覆晶薄膜和测试结构；
所述测试结构包括：
位于所述覆晶薄膜远离所述显示区域的一侧的测试点；
位于所述测试点与所述覆晶薄膜之间的测试电路，包括连接所述覆晶薄膜和所述测试点的信号走线，所述信号走线包括相互连接的非金属走线和金属走线，所述信号走线上设置有切割线；
步骤S20、通过所述测试结构对所述基板的显示区域进行测试；
步骤S30、沿着所述切割线将所述测试点除掉，形成所述显示面板。
根据本申请一实施例，在步骤S10中，所述信号走线包括两端的金属走线和中间的非金属走线，所述金属走线包括与所述覆晶薄膜连接的第一金属走线和与所述测试点连接点相连的第二金属走线，所述切割线位于所述非金属走线范围内。
根据本申请一实施例，所述切割线与所述非金属走线相交，所述切割线至所述非金属走线两端的距离均大于或等于100微米。
根据本申请一实施例，所述切割线与所述第二金属走线相交，所述非金属走线的长度为100微米至150微米。
根据本申请一实施例，所述基板包括层叠设置的衬底、多晶硅层、缓冲层和金属层；
所述非金属走线位于所述多晶硅层，所述金属走线位于所述金属层，所述缓冲层上设置有过孔，所述非金属走线通过所述过孔与所述金属走线电连接以形成信号走线。
根据本申请一实施例，所述基板还包括平坦化层，所述平坦化层中存在凹槽，所述覆晶薄膜和所述测试点设置于所述凹槽中。
根据本申请一实施例，所述非金属走线的制备材料包括多晶硅，所述金属走线为栅极走线、源漏极走线和透明金属走线中的其中一者。
根据本申请一实施例，所述步骤S30包括采用镭射切割的方式沿着所述切割线将所述测试点除掉，形成显示面板。
根据本申请一实施例，m个相邻的所述覆晶薄膜形成一个覆晶薄膜组，所述测试点与所述覆晶薄膜组一一对应，m为大于或等于1的整数；
所述测试电路包括与所述覆晶薄膜数目相同的晶体管，所述晶体管与所述覆晶薄膜一一对应，所述晶体管与所述第二金属走线电连接；
在所述覆晶薄膜组中，从左往右数序号相同的所述覆晶薄膜所对应的晶体管相互电连接以形成晶体管组，所述测试电路通过所述晶体管组的开关和闭合控制所述显示区域的测试。
根据本申请的另一个方面，还提供了一种显示面板，包括：显示区域和包围所述显示区域的非显示区域；
所述显示区域包括：
衬底；
设置在所述衬底上的多晶硅层，所述多晶硅层包括非金属走线；
设置在所述多晶硅层上的缓冲层，所述缓冲层内设置有过孔；
设置在所述缓冲层上的平坦化层，所述平坦化层设置有凹槽；
设置在所述缓冲层上的金属层，所述金属层包括金属走线，所述金属走线通过所述过孔与所述非金属走线电连接，所述金属走线位于所述凹槽内；
所述非显示区域包括覆晶薄膜和避免所述金属走线被侵蚀的非金属走线，所述覆晶薄膜与所述非金属走线和所述金属走线的其中一者电连接。
根据本申请的有一个方面，还提供了一种显示面板的制作方法，其包括如下步骤：
步骤S10、提供一基板，所述基板包括显示区域和设置在所述显示区域外侧的非显示区域，所述非显示区域内设置有覆晶薄膜和测试结构；
所述测试结构包括：
位于所述覆晶薄膜远离所述显示区域的一侧的测试点，所述测试点与所述覆晶薄膜一一对应；
位于所述测试点与所述覆晶薄膜之间的测试电路，包括连接所述覆晶薄膜和所述测试点的信号走线，所述信号走线包括相互连接的非金属走线和金属走线，所述信号走线上设置有切割线；
步骤S20、通过所述测试结构对所述基板的显示区域进行测试；
步骤S30、沿着所述切割线将所述测试点除掉，形成所述显示面板。
根据本申请一实施例，在步骤S10中，所述信号走线包括两端的金属走线和中间的非金属走线，所述金属走线包括与所述覆晶薄膜连接的第一金属走线和与所述测试点连接点相连的第二金属走线，所述切割线位于所述非金属走线范围内。
根据本申请一实施例，所述切割线与所述非金属走线相交，所述切割线至所述非金属走线两端的距离均大于或等于100微米。
根据本申请一实施例，所述切割线与所述第二金属走线相交，所述非金属走线的长度为100微米至150微米。
根据本申请一实施例，所述基板包括层叠设置的衬底、多晶硅层、缓冲层和金属层；
所述非金属走线位于所述多晶硅层，所述金属走线位于所述金属层，所述缓冲层上设置有过孔，所述非金属走线通过所述过孔与所述金属走线电连接以形成信号走线。
根据本申请一实施例，所述基板还包括平坦化层，所述平坦化层中存在凹槽，所述覆晶薄膜和所述测试点设置于所述凹槽中。
根据本申请一实施例，所述非金属走线的制备材料包括多晶硅，所述金属走线为栅极走线、源漏极走线和透明金属走线中的其中一者。
根据本申请一实施例，所述步骤S30包括采用镭射切割的方式沿着所述切割线将所述测试点除掉，形成显示面板。
根据本申请一实施例，m个相邻的所述覆晶薄膜形成一个覆晶薄膜组，所述测试点与所述覆晶薄膜组一一对应，m为大于或等于1的整数；
所述测试电路包括与所述覆晶薄膜数目相同的晶体管，所述晶体管与所述覆晶薄膜一一对应，所述晶体管与所述第二金属走线电连接；
在所述覆晶薄膜组中，从左往右数序号相同的所述覆晶薄膜所对应的晶体管相互电连接以形成晶体管组，所述测试电路通过所述晶体管组的开关和闭合控制所述显示区域的测试。
 有益效果
通过将信号走线设置为金属走线和非金属走线相结合的方式，能够在不侵蚀金属线路的前提下将测试点去掉，进而简化显示面板的结构，降低静电损伤的发生率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中显示面板的测试结构的结构示意图；
图2为本申请实施例中显示面板制作方法的流程示意图;
图3为本申请实施例中显示面板中测试结构被切割前的结构示意图；
图4为本申请实施例中显示面板的结构示意图；
图5为本申请另一实施例中显示面板的结构示意图；,
图6为本申请中另一实施例中显示面板中测试结构被切割前的结构示意图；
图7为本申请中另一实施例中显示面板的结构示意图；
图8在本申请中又一实施例中显示面板中测试结构被切割前的结构示意图；
图9在本申请中又一实施例中显示面板中测试结构被切割前的结构示意图；
图10为本申请中显示面板的部分结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供了一种显示面板的测试结构，以解决显示面板中由于测试结构被切除后部分金属走线裸露被侵蚀，进而影响显示面板品质的问题，本实施例能够改善该缺陷。
下面结合附图和具体实施例对本申请做进一步的说明：
请参阅图2，图2为本申请实施例中显示面板制作方法的流程示意图。
本申请提供了一种显示面板的制作方法，包括：
请参阅图3，图3为本申请实施例中显示面板中测试结构被切割前的结构示意图。
步骤S10、提供一基板2，所述基板2包括显示区域21和设置在所述显示区域21外侧的非显示区域22，所述非显示区域22内设置有覆晶薄膜221和测试结构；
所述覆晶薄膜221，用于生成测试信号。
在一种实施例中，所述覆晶薄膜221包括：衬底和设置在衬底上的柔性电路板，所述测试信号在柔性电路板上生成。
所述测试结构包括：
测试点223和测试电路222；
所述测试点223用于接收所述测试信号并将所述将测试信号传输到所述显示区域21。
在一种实施例中，所述测试点223位于所述覆晶薄膜221远离所述显示区域21的一侧。其中，测试点223用来测试显示区域，在对显示区域测试后，所述测试点223可以被去掉，以简化显示面板的结构。
所述测试电路，设置于所述测试点223与所述覆晶薄膜221之间，包括连接所述覆晶薄膜221和所述测试点223的信号走线222；
其中，所述信号走线222包括相互连接的非金属走线222a和金属走线222b，所述信号走线222上设置有切割线23。
在一种实施例中，通过将信号走线设置为金属走线222a和非金属走线222b相混合的方式，在切割完测试点后，能够在信号走线222中留出一段用于防止金属走线222a被空气中水氧侵蚀的非金属走线222b，以提高显示面板的耐用性。
在一种实施例中，所述测试结构还包括一切割线23，在所述测试结构对所述显示面板测试完成后，用于按切割线23切割以除去所述测试点223。
在一种实施例中，显示面板的非显示区域22包括保留区和切割区，所述保留区和所述切割区由所述切割线23界定，所述测试点223所在的区域为切割区。
在一种实施例中，所述切割线23的切割方法为镭射切割。
步骤S20、通过所述测试结构对所述基板的显示区域21进行测试；
步骤S30、沿着所述切割线23将所述测试点223除掉，形成显示面板；
请参阅图4，图4为本申请实施例中显示面板的结构示意图。
请参阅图5，图5为本申请另一实施例中显示面板的结构示意图。
由于在对所述显示区域21进行测试时，需要采用信号走线222进行信号传输。因此，所述非金属走线222b在保证其抗水氧性的同时，还需要保证其导电性，以减少所述非金属走线222b的阻抗。在进行非金属走线222b设计的时候，需要使得非金属走线222b尽可能的短；但是由于考虑在对按所述切割线23进行切割时的切割精度，非金属走线222b的长度设计在合理的范围内。
在一种实施例中，所述切割线23与所述非金属走线222b相交，所述切割线23与所述非金属走线222b两端的距离均大于或等于100微米,即当所述切割线23位于所述非金属走线222b居中位置时，所述非金属走线222b的最小长度为200微米。此时是切割线23设置在所述非金属走线222b上，还有一种实施例是切割线23设置在所述第二金属走线上，这样设计的好处在于能够缩短非金属走线222b的长度，降低信号走线222的在对显示区域21测试时的阻抗。
请参与图图6，,图6为本申请中另一实施例中显示面板的测试结构的结构示意图。
在一种实施例中，所述切割线23与所述第二金属走线相交，所述非金属走线222b的长度为100微米至150微米。
请参阅图7，如图7所示为本申请中另一实施例中显示面板的测试结构中测试点被去掉的结构示意图。
在一种实施例中，所述基板可以包括层叠设置的衬底、多晶硅层、缓冲层和金属层。
在一种实施例中，所述非金属走线222b位于所述多晶硅层，所述金属走线222a位于所述金属层，所述缓冲层上设置有过孔，所述非金属走线222b通过所述过孔与所述金属走线222a电连接以形成信号走线222。
本申请通过在制备多晶硅层的同时采用同一光罩制备非金属走线222b，在制备金属层时采用同一光罩制备金属走线，在制备缓冲层时采用同一光罩制备过孔，进而不需要额外的工艺来制备信号走线，大大将低了测试结构的制作成本。本申请的技术方案并不仅限于在缓冲层中制备过孔以将所述金属走线222a和非金属走线222b连接，当所述金属层和所述多晶硅层中还包括其他膜层结构时，所述过孔也相应的贯穿其他层膜结构以达到连接金属走线222a和非金属走线222b的作用。
在一种实施例中，所述基板还包括平坦化层，所述平坦化层中存在凹槽，所述覆晶薄膜2221和所述测试点223设置与所述凹槽中，这样在进行显示面板的制备时，可以防止所述覆晶薄膜2221和所述测试点223的突出使其位置不好固定的问题。
在一种实施例中，所述非金属走线222b的制备材料包括多晶硅，所述金属走线222a为栅极走线、源漏极走线和透明金属走线中的其中一者，当然本申请中的金属走线并不仅限于上述举例，只要是显示面板的金属层结构，均可以考虑同步制备本申请中的金属走线222a。
在一种实施例中，为了提高非金属走线222b的导电性能，所述多晶硅中掺杂有硼和磷中的至少一者。
在一种实施例中，所述测试点223与所述覆晶薄膜221一一对应；但是本申请中所述覆晶薄膜221和所述测试点223的关系并不仅限于一一对应，也可以存在一个测试点223对应多个覆晶薄膜221的情况。
请参阅图8，图8在本申请中又一实施例中显示面板中测试结构被切割前的结构示意图。
请参阅图9，图9在本申请中又一实施例中显示面板中测试结构被切割前的结构示意图。
在一种实施例中，m个相邻的所述覆晶薄膜221形成一个覆晶薄膜组，所述测试点223与所述覆晶薄膜组一一对应，m为大于或等于1的整数；
所述测试电路包括与所述覆晶薄膜223数目相同的晶体管24a，所述晶体管24a与所述覆晶薄膜223一一对应，所述晶体管24a与所述第二金属走线电连接；
在所述覆晶薄膜组中，从左往右数序号相同的所述覆晶薄膜所对应的晶体管相互电连接以形成晶体管组，所述测试电路通过所述晶体管组的开关和闭合控制所述显示区域21的测试。通过晶体管的引用，可以实现1个测试点221连接多个覆晶薄膜，进而简化显示面板的测试结构的制备工艺。
在一种实施例中，对所述显示区域的测试包括阵列测试。
本申请中由于所述测试点及部分测试电路在完成显示区域21的测试后会被去掉，这一部分不需要封装结构，因此显示区域的测试也可以放在制备工艺的最后进行。
在一种实施例中，由于非金属走线的长度可控，因此能够减小测试电路到覆晶薄膜的阻抗；最后，由于切割后的裸露走线包括非金属走线，因此可以减少水氧对信号走线的侵蚀，进而提升产品良率。
根据本申请的另一个方面，请参阅图4、图5和图10所示，还提供了一种显示面板，包括：显示区域21和包围所述显示区域的非显示区域22；
所述显示区域21包括：
衬底31；
设置在所述衬底上的多晶硅层，所述多晶硅层包括非金属走线222b；
设置在所述多晶硅层上的缓冲层32，所述缓冲层内设置有过孔；
设置在所述缓冲层上的平坦化层33，所述平坦化层设置有凹槽；
设置在所述缓冲层32上的金属层，所述金属层包括金属走线222a，所述金属走线222a通过所述过孔与所述非金属222b走线电连接，所述金属走线222a位于所述凹槽内；
所述非显示区域22包括覆晶薄膜221和避免所述金属走线222a被侵蚀的非金属走线222b，所述覆晶薄膜221与所述非金属走线222b和所述金属走线222a的其中一者电连接。
所述显示面板的工作原理与所述显示面板的制作方法的工作原理相似，所述显示面板的工作原理具体可以参考所述显示面板的制作方法的工作原理，这里不再赘述。
有益效果：通过将信号走线设置为金属走线和非金属走线相结合的方式，能够在不侵蚀金属线路的前提下将测试点去掉，进而简化显示面板的结构，降低静电损伤的发生率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种显示面板的制作方法，其包括如下步骤：
    步骤S10、提供一基板，所述基板包括显示区域和设置在所述显示区域外侧的非显示区域，所述非显示区域内设置有覆晶薄膜和测试结构；
    所述测试结构包括：
    位于所述覆晶薄膜远离所述显示区域的一侧的测试点；
    位于所述测试点与所述覆晶薄膜之间的测试电路，包括连接所述覆晶薄膜和所述测试点的信号走线，所述信号走线包括相互连接的非金属走线和金属走线，所述信号走线上设置有切割线；
    步骤S20、通过所述测试结构对所述基板的显示区域进行测试；
    步骤S30、沿着所述切割线将所述测试点除掉，形成显示面板。
  2. 根据权利要求1所述的显示面板的制作方法，其中，在步骤S10中，所述信号走线包括两端的金属走线和中间的非金属走线，所述金属走线包括与所述覆晶薄膜连接的第一金属走线和与所述测试点连接点相连的第二金属走线，所述切割线位于所述非金属走线范围内。
  3. 根据权利要求2所述的显示面板的制作方法，其中，所述切割线与所述非金属走线相交，所述切割线至所述非金属走线两端的距离均大于或等于100微米。
  4. 根据权利要求2所述的显示面板的制作方法，其中，所述切割线与所述第二金属走线相交，所述非金属走线的长度为100微米至150微米。
  5. 根据权利要求1所述的显示面板的制作方法，其中，所述基板包括层叠设置的衬底、多晶硅层、缓冲层和金属层；
    所述非金属走线位于所述多晶硅层，所述金属走线位于所述金属层，所述缓冲层上设置有过孔，所述非金属走线通过所述过孔与所述金属走线电连接以形成信号走线。
  6. 根据权利要求5所述的显示面板的制作方法，其中，所述基板还包括平坦化层，所述平坦化层中存在凹槽，所述覆晶薄膜和所述测试点设置于所述凹槽中。
  7. 根据权利要求1所述的显示面板的制作方法，其中，所述非金属走线的制备材料包括多晶硅，所述金属走线为栅极走线、源漏极走线和透明金属走线中的其中一者。
  8. 根据权利要求1所述的显示面板的制作方法，其中，所述步骤S30包括采用镭射切割的方式沿着所述切割线将所述测试点除掉，形成所述显示面板。
  9. 根据权利要求1所述的显示面板的制作方法，其中，m个相邻的所述覆晶薄膜形成一个覆晶薄膜组，所述测试点与所述覆晶薄膜组一一对应，m为大于或等于1的整数；
    所述测试电路包括与所述覆晶薄膜数目相同的晶体管，所述晶体管与所述覆晶薄膜一一对应，所述晶体管与所述第二金属走线电连接；
    在所述覆晶薄膜组中，从左往右数序号相同的所述覆晶薄膜所对应的晶体管相互电连接以形成晶体管组，所述测试电路通过所述晶体管组的开关和闭合控制所述显示区域的测试。
  10. 一种显示面板，其包括：显示区域和包围所述显示区域的非显示区域；
    所述显示区域包括：
    衬底；
    设置在所述衬底上的多晶硅层，所述多晶硅层包括非金属走线；
    设置在所述多晶硅层上的缓冲层，所述缓冲层内设置有过孔；
    设置在所述缓冲层上的平坦化层，所述平坦化层设置有凹槽；
    设置在所述缓冲层上的金属层，所述金属层包括金属走线，所述金属走线通过所述过孔与所述非金属走线电连接，所述金属走线位于所述凹槽内；
    所述非显示区域包括覆晶薄膜和避免所述金属走线被侵蚀的非金属走线，所述覆晶薄膜与所述非金属走线和所述金属走线的其中一者电连接。
  11. 一种显示面板的制作方法，其包括如下步骤：
    步骤S10、提供一基板，所述基板包括显示区域和设置在所述显示区域外侧的非显示区域，所述非显示区域内设置有覆晶薄膜和测试结构；
    所述测试结构包括：
    位于所述覆晶薄膜远离所述显示区域的一侧的测试点，所述测试点与所述覆晶薄膜一一对应；
    位于所述测试点与所述覆晶薄膜之间的测试电路，包括连接所述覆晶薄膜和所述测试点的信号走线，所述信号走线包括相互连接的非金属走线和金属走线，所述信号走线上设置有切割线；
    步骤S20、通过所述测试结构对所述基板的显示区域进行测试；
    步骤S30、沿着所述切割线将所述测试点除掉，形成显示面板。
  12. 根据权利要求11所述的显示面板的制作方法，其中，在步骤S10中，所述信号走线包括两端的金属走线和中间的非金属走线，所述金属走线包括与所述覆晶薄膜连接的第一金属走线和与所述测试点连接点相连的第二金属走线，所述切割线位于所述非金属走线范围内。
  13. 根据权利要求12所述的显示面板的制作方法，其中，所述切割线与所述非金属走线相交，所述切割线至所述非金属走线两端的距离均大于或等于100微米。
  14. 根据权利要求12所述的显示面板的制作方法，其中，所述切割线与所述第二金属走线相交，所述非金属走线的长度为100微米至150微米。
  15. 根据权利要求11所述的显示面板的制作方法，其中，所述基板包括层叠设置的衬底、多晶硅层、缓冲层和金属层；
    所述非金属走线位于所述多晶硅层，所述金属走线位于所述金属层，所述缓冲层上设置有过孔，所述非金属走线通过所述过孔与所述金属走线电连接以形成信号走线。
  16. 根据权利要求15所述的显示面板的制作方法，其中，所述基板还包括平坦化层，所述平坦化层中存在凹槽，所述覆晶薄膜和所述测试点设置于所述凹槽中。
  17. 根据权利要求11所述的显示面板的制作方法，其中，所述非金属走线的制备材料包括多晶硅，所述金属走线为栅极走线、源漏极走线和透明金属走线中的其中一者。
  18. 根据权利要求11所述的显示面板的制作方法，其中，所述步骤S30包括采用镭射切割的方式沿着所述切割线将所述测试点除掉，形成所述显示面板。
  19. 根据权利要求11所述的显示面板的制作方法，其中，m个相邻的所述覆晶薄膜形成一个覆晶薄膜组，所述测试点与所述覆晶薄膜组一一对应，m为大于或等于1的整数；
    所述测试电路包括与所述覆晶薄膜数目相同的晶体管，所述晶体管与所述覆晶薄膜一一对应，所述晶体管与所述第二金属走线电连接；
    在所述覆晶薄膜组中，从左往右数序号相同的所述覆晶薄膜所对应的晶体管相互电连接以形成晶体管组，所述测试电路通过所述晶体管组的开关和闭合控制所述显示区域的测试。
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