WO2020019908A1 - 静电保护电路、阵列基板及显示装置 - Google Patents

静电保护电路、阵列基板及显示装置 Download PDF

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Publication number
WO2020019908A1
WO2020019908A1 PCT/CN2019/091913 CN2019091913W WO2020019908A1 WO 2020019908 A1 WO2020019908 A1 WO 2020019908A1 CN 2019091913 W CN2019091913 W CN 2019091913W WO 2020019908 A1 WO2020019908 A1 WO 2020019908A1
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Prior art keywords
thin film
film transistor
electrostatic protection
line
gate
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PCT/CN2019/091913
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English (en)
French (fr)
Inventor
龙春平
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京东方科技集团股份有限公司
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Priority to US16/638,968 priority Critical patent/US11296074B2/en
Publication of WO2020019908A1 publication Critical patent/WO2020019908A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an electrostatic protection circuit, an array substrate, and a display device.
  • an electrostatic protection device connected to the signal lines is provided on the array substrate.
  • This electrostatic protection device is also commonly referred to as an Electro-Static Discharge (ESD) device.
  • the electrostatic protection device in the related art generally includes a thin film transistor and an electrostatic protection line.
  • the source of the thin film transistor can be connected to the signal line, and the gate and the drain can be connected to the electrostatic protection line.
  • the thin film transistor can release the static electricity generated on the signal line to the electrostatic protection line in time.
  • the present disclosure provides an electrostatic protection circuit, an array substrate, and a display device.
  • the technical solution is as follows:
  • an electrostatic protection circuit which includes: a first thin film transistor, a second thin film transistor, and an electrostatic protection line;
  • the gate and the second pole of the first thin film transistor are both connected to a signal line, and the first pole of the first thin film transistor is connected to the electrostatic protection line;
  • a gate and a second pole of the second thin film transistor are both connected to the electrostatic protection line, and a first pole of the second thin film transistor is connected to a signal line;
  • Each thin film transistor is an oxide thin film transistor, and an aspect ratio of a channel of each thin film transistor is greater than or equal to an aspect ratio threshold, and the aspect ratio threshold is greater than 1.
  • the aspect ratio threshold is 5.
  • a length direction of a channel of each thin film transistor is parallel to an extending direction of the signal line.
  • a gate of each thin film transistor is a strip structure, and a length direction of the strip structure is parallel to an extending direction of the signal line.
  • an arrangement direction of the first thin film transistor and the second thin film transistor is parallel to an extending direction of the signal line.
  • the signal line is a data line extending in a first direction
  • the electrostatic protection line includes: a first discharge line and a second discharge line extending in a second direction and parallel to each other, and used to connect the A connection line between a first discharge line and the second discharge line, wherein the second direction intersects the first direction;
  • the first thin film transistor and the second thin film transistor are disposed between the first discharge line and the second discharge line, and a first pole of the first thin film transistor is connected to the first discharge line
  • the gate and the second electrode of the second thin film transistor are connected to the second discharge line.
  • the second pole of the first thin film transistor and the first pole of the second thin film transistor are integrated, and the gate of the first thin film transistor is connected to the integrated structure through a via.
  • the signal line is a gate line extending in a second direction
  • the electrostatic protection line extends in a first direction
  • the second direction intersects the first direction
  • the electrostatic protection circuit further includes: a third thin film transistor and a fourth thin film transistor;
  • the gate and the second pole of the third thin film transistor are both connected to the first pole of the first thin film transistor, and the first pole of the third thin film transistor is connected to the electrostatic protection line;
  • the fourth thin film The gate and the second pole of the transistor are both connected to the first pole of the first thin film transistor, and the first pole of the fourth thin film transistor is connected to the signal line;
  • the first thin film transistor and the second thin film transistor are arranged along a first axis
  • the third thin film transistor and the fourth thin film transistor are arranged along a second axis
  • the first axis and the second axis are both Intersects the second direction and is not collinear.
  • first axis and the second axis are both parallel to the second direction.
  • the first pole of the first thin film transistor, the first pole of the second thin film transistor, the second pole of the third thin film transistor, and the second pole of the fourth thin film transistor have an integrated structure
  • the gate of the third thin film transistor and the gate of the fourth thin film transistor are connected to the integrated structure through a via.
  • the gates of the third thin film transistor and the fourth thin film transistor are integrated structures.
  • the second direction is perpendicular to the first direction.
  • the electrostatic protection circuit further includes: at least one of a third thin film transistor and a fourth thin film transistor;
  • the gate and the second electrode of the third thin film transistor are both connected to the first electrode of the first thin film transistor, and the first electrode of the third thin film transistor is connected to the electrostatic protection line;
  • the gate and the second electrode of the fourth thin film transistor are both connected to the first electrode of the first thin film transistor, and the first electrode of the fourth thin film transistor is connected to the signal line.
  • a channel of each thin film transistor is in a serpentine shape, a zigzag shape, or an arc shape.
  • an array substrate in another aspect, includes:
  • a signal line, and the electrostatic protection circuit according to the above aspect connected to the signal line.
  • the signal line is a data line extending in a first direction
  • the array substrate includes a plurality of data lines
  • the electrostatic protection line includes: three discharge lines extending in a second direction and arranged in parallel, and A connection line for connecting the three discharge lines, the second direction intersects the first direction;
  • Each ESD protection circuit connected to each data line is in the same column as the ESD protection circuit connected to an adjacent data line;
  • one of the electrostatic protection circuits is located between the first discharge line and the second discharge line of the three discharge lines, and the other electrostatic protection circuit is located at the first of the three discharge lines.
  • the gate and the second electrode of the second thin film transistor in the two electrostatic protection circuits located in the same column between the two discharge lines and the third discharge line are connected to the second discharge line.
  • the signal line is a gate line extending in a second direction
  • the array substrate includes a plurality of gate lines
  • the electrostatic protection line extends in a first direction
  • the second direction is perpendicular to the first direction.
  • An electrostatic protection circuit connected to one of the plurality of gate lines is disposed between two adjacent gate lines.
  • a display device in another aspect, includes the array substrate according to the above aspect.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a variation of an on-current of a thin film transistor with a gate voltage according to an embodiment of the present disclosure
  • FIG. 4 is an equivalent circuit diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional view in the AA direction of FIG. 1;
  • FIG. 6 is a schematic structural diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view taken along the BB direction of FIG. 6;
  • FIG. 8 is a cross-sectional view in the CC direction of FIG. 6;
  • FIG. 9 is a schematic diagram of an optional shape of a channel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a cross-sectional view in the AA direction of FIG. 11;
  • FIG. 13 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a gate pattern according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a gate insulation layer, an active layer, and an etch barrier layer according to an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of a source-drain metal pattern provided by an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be all thin film transistors. According to the function in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Because the source and drain of the switching transistor used here are symmetrical, the source and drain of the switching transistor are interchangeable.
  • the source electrode may be referred to as a first electrode and the drain electrode may be referred to as a second electrode; or the source electrode may be referred to as a second electrode and the drain electrode may be referred to as a first electrode.
  • the middle end of the transistor is specified as the gate, the signal input end is used as the source, and the signal output end is used as the drain.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • the electrostatic protection circuit may include a first thin film transistor M1, a second thin film transistor M2, and an electrostatic protection line L.
  • the gate g and the second electrode d2 of the first thin film transistor M1 may both be connected to the signal line S, and the first electrode d1 of the first thin film transistor M1 is connected to the electrostatic protection line L.
  • the first electrode d1 of the first thin film transistor M1 may be directly connected to the electrostatic protection line L.
  • the gate g and the second electrode d2 of the second thin film transistor M2 are both connected to the electrostatic protection line L, and the first electrode d1 of the second thin film transistor M2 is connected to the signal line S.
  • the first electrode d1 of the second thin film transistor M2 may be directly connected to the signal line S.
  • each thin film transistor may be an oxide thin film transistor, that is, the active layer of the thin film transistor is made of an oxide material, for example, it may be indium gallium zinc oxide (IGZO) or zinc oxide (ZnO ) And other oxide materials.
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • the aspect ratio of the channel ACT (ie, the active layer) of each thin film transistor is greater than or equal to the aspect ratio threshold, and the aspect ratio threshold may be greater than 1.
  • the embodiment of the present disclosure provides an electrostatic protection circuit.
  • the thin film transistor included in the electrostatic protection circuit is an oxide thin film transistor, and the aspect ratio of the channel of each thin film transistor is greater than or equal to the aspect ratio Threshold value, and the aspect ratio threshold value is greater than 1, thereby effectively reducing the on-current of the transistor and preventing the transistor from being burned out when the signal line generates a transient high voltage.
  • the aspect ratio threshold may be 5, that is, the aspect ratio W / L ⁇ 0.2 of the channel ACT of each thin film transistor.
  • oxide thin film transistors are generally simpler to manufacture, so oxide thin film transistors are generally used to make electrostatic protection circuits.
  • the on-current of the oxide thin film transistor is relatively high, which is about 5 times that of the LTPS thin film transistor. Since the oxide thin film transistor has strong conductivity and large on-current, when the voltage of static electricity generated on the signal line is high, the oxide thin film transistor is relatively easy to burn.
  • V GS is the gate-source voltage difference of the thin film transistor
  • V TH is the threshold voltage of the thin film transistor
  • V DS is the source-drain voltage difference of the thin film transistor.
  • FIG. 3 is a schematic diagram of a variation of an on-current of a thin film transistor with a gate voltage according to an embodiment of the present disclosure.
  • the channel W / L of the thin film transistor can ensure the safe and effective operation of the thin film transistor.
  • the length direction of the channel ACT of each thin film transistor may be parallel to the extending direction of the signal line S.
  • the length of the channel of each transistor is long, so that the length direction of the channel is parallel to the extending direction of the signal line, which can effectively reduce the occupied space of the electrostatic protection circuit.
  • the signal line S may be any signal line on the array substrate, and may be, for example, a data line, a gate line, or a clock signal line of a gate driving circuit, which is used to drive a display device.
  • the signal line may also be a test line or a maintenance line in the array substrate.
  • the electrostatic protection line L may be a discharge line for providing a reference power signal.
  • the electrostatic protection line L may be a common electrode (Vcom) line, and the common electrode line is used to provide a common electrode signal with a voltage of 0 volts (V) or about 0V.
  • the first thin film transistor M1 or the second thin film transistor M2 can be turned on, so that the signal line S can be communicated with the electrostatic protection line L, so that the static electricity generated on the signal line S can be discharged in time.
  • the electrostatic protection line L To the electrostatic protection line L.
  • the electrostatic protection circuit provided by the embodiment of the present disclosure may further include at least one of a third thin film transistor M3 and a fourth thin film transistor M4.
  • FIG. 4 is an equivalent circuit diagram of another electrostatic protection circuit provided by an embodiment of the present disclosure. As shown in FIG. 4, the electrostatic protection circuit further includes a third thin film transistor M3 and a fourth thin film transistor M4.
  • the gate and the second pole of the third thin film transistor M3 may both be connected to the first pole of the first thin film transistor M1, and the first pole of the third thin film transistor M3 is connected to the electrostatic protection line L.
  • the gate and the second pole of the fourth thin film transistor M4 are both connected to the first pole of the first thin film transistor M1, and the first pole of the fourth thin film transistor M4 is connected to the signal line S.
  • the first pole of the first thin film transistor M1 may be connected to the electrostatic protection line L through the third thin film transistor M3.
  • the first pole of the second thin film transistor M2 may be connected to the signal line S through the fourth thin film transistor M4.
  • the first pole of the first thin film transistor M1 is directly connected to the electrostatic protection line L
  • the first pole of the second thin film transistor M2 is directly connected to the signal line S.
  • the resistance between the first pole of the first thin film transistor M1 and the electrostatic protection line L can be increased, so that the magnitude of the current flowing through the first thin film transistor M1 can be effectively reduced, and the first A thin film transistor M1.
  • the resistance between the first electrode of the second thin film transistor M2 and the signal line S can be increased, thereby effectively reducing the amount of current flowing through the second thin film transistor M2 and avoiding burning Defective second thin film transistor M2.
  • the gate g of each thin film transistor in the electrostatic protection circuit may be a strip structure, and a length direction of the strip structure is parallel to an extending direction of the signal line S. This can reduce the footprint of the thin film transistor.
  • the arrangement direction of the first thin film transistor M1 and the second thin film transistor M2 may also be parallel to the extending direction of the signal line S, so as to minimize the space occupied by the electrostatic protection circuit.
  • the signal line S may be a data line extending along the first direction X.
  • the electrostatic protection line L may include a first discharge line L1 and a second discharge line L2 extending in the second direction Y and being parallel to each other, and a connection line for connecting the first discharge line L1 and the second discharge line L2. L0.
  • the second direction Y may intersect the first direction X.
  • the connecting line L0 may extend along the first direction X.
  • the second direction Y may be perpendicular to the first direction X.
  • FIG. 5 is a cross-sectional view in the AA direction of FIG. 1. It can be seen from FIG. 1 and FIG. 5 that the first thin film transistor M1 and the second thin film transistor M2 may both be disposed between the first discharge line L1 and the second discharge line L2. In addition, a first electrode d1 of the first thin film transistor M1 may be connected to the first discharge line L1, and a gate g and a second electrode d2 of the second thin film transistor M2 may be connected to the second discharge line L2.
  • the first pole d1 and the second pole d2 of each thin film transistor may be disposed on the same layer as the signal line S, and the gate g of each thin film transistor It can be set on the same layer as the electrostatic protection line L. Therefore, it can be seen from FIG. 1 and FIG. 5 that the first electrode d1 of the first thin film transistor M1 can be connected to the first discharge line L1 through a via hole.
  • the second electrode d2 of the second thin film transistor M2 may be connected to the second discharge line L2 through a via.
  • the gate g of the second thin film transistor M2 may be directly connected to the second discharge line L2.
  • the gate g of the second thin film transistor M2 and the second discharge line L2 may be an integrated structure.
  • the space between data lines is usually narrow in the array substrate, by setting two parallel discharge lines and making each thin film transistor connected to one discharge line, the space occupied by the electrostatic protection circuit can be effectively reduced. Achieve reasonable wiring.
  • the second pole d2 of the first thin film transistor M1 and the first pole d1 of the second thin film transistor M2 may be an integrated structure, and the integrated structure may be directly connected to the signal line S. connection. That is, the second electrode d2 of the first thin film transistor M1, the first electrode d1 of the second thin film transistor M2, and the signal line S may be formed by a patterning process.
  • the gate g of the first thin film transistor M1 may be connected to the integrated structure through a via (such as a square via in FIG. 1).
  • Designing the electrodes connected to the signal line S in the two thin film transistors as an integrated structure can not only reduce the space occupied by the electrostatic protection circuit, but also simplify the manufacturing process of the electrostatic protection circuit.
  • the signal line S may also be a gate line extending in the second direction Y
  • the electrostatic protection line L may extend in the first direction X
  • the second The direction Y intersects the first direction X.
  • the second direction Y is perpendicular to the first direction X.
  • the electrostatic protection circuit may further include a third thin film transistor M3 and a fourth thin film transistor M4.
  • the gate g and the second electrode d2 of the third thin film transistor M3 may both be connected to the first electrode d1 of the first thin film transistor M1, and the first electrode d1 of the third thin film transistor M3 may be connected to the electrostatic protection line L.
  • the gate g and the second electrode d2 of the fourth thin film transistor M4 may both be connected to the first electrode d1 of the first thin film transistor M1, and the first electrode d1 of the fourth thin film transistor M4 may be connected to the signal line S.
  • the first thin film transistor M1 and the second thin film transistor M2 may be arranged along a first axis
  • the third thin film transistor M3 and the fourth thin film transistor M4 may be arranged along a second axis.
  • the first axis and the The second axis may both intersect the first direction X, and the two axes are not collinear.
  • the first axis and the second axis may each be parallel to the second direction Y.
  • the first pole d1 of the first thin film transistor M1, the first pole d1 of the second thin film transistor M2, the second pole d2 of the third thin film transistor M3, and the fourth thin film transistor M4 may be an integrated structure.
  • the gate g of the third thin film transistor M3 and the gate g of the fourth thin film transistor M4 may be connected to the integrated structure through a via (such as a square via in FIG. 6).
  • each of the four thin film transistors has an electrode located closer to the electrodes of other thin film transistors.
  • FIG. 7 is a cross-sectional view in FIG. 6 in the BB direction
  • FIG. 8 is a cross-sectional view in FIG. 6 in the CC direction.
  • the signal line S is a gate line
  • the gates of the thin film transistors can be disposed on the same layer as the signal line S, and the first and second electrodes of each thin film transistor can be connected to the same layer.
  • the electrostatic protection line L is provided on the same layer. Therefore, the gate g and the second electrode d2 of the first thin film transistor M1 and the first electrode d1 of the fourth thin film transistor M4 may be connected to the signal line S through vias, respectively.
  • the gate g of the second thin film transistor M2 may be connected to the electrostatic protection line L through a via, and the second pole d2 of the second thin film transistor M2 and the first pole d1 of the third thin film transistor M3 may be directly connected to the electrostatic protection line.
  • L Connect For example, as shown in FIG. 6 and FIG. 7, the second electrode d2 of the second thin film transistor M2 and the electrostatic protection line L may be an integrated structure. As shown in FIGS. 6 and 8, the first electrode of the third thin film transistor M3 d1 and the electrostatic protection line L may be integrated.
  • the gates g of the third thin film transistor M3 and the fourth thin film transistor M4 may be an integrated structure. This can simplify the manufacturing process and further save the space occupied by the electrostatic protection circuit.
  • FIG. 9 is a schematic diagram of an optional shape of a channel provided by an embodiment of the present disclosure.
  • the channel ACT of each thin film transistor in the electrostatic protection circuit may have a rectangular shape, a snake shape, a zigzag shape, or an arc shape.
  • the serpentine, zigzag or arc-shaped channel By designing the serpentine, zigzag or arc-shaped channel, the aspect ratio of the channel can be maximized in a limited space.
  • the shape of the channel may refer to a shape of an orthographic projection of the channel on the base substrate.
  • the electrostatic protection circuit can be disposed on the substrate substrate 00.
  • the gate g of the thin film transistor is provided with a gate insulating layer (GI) 01 on a side remote from the base substrate 00, and an active layer ACT of the thin film transistor may be provided on a side of the gate insulating layer 01 remote from the base substrate 00. .
  • An etch stop layer (ESL) 02 is further provided on the side of the active layer ACT far from the substrate 00.
  • the first electrode d1 and the second electrode d2 of the thin film transistor may be disposed on the etch stop layer 02. The side far from the base substrate 00.
  • the first electrode d1 and the second electrode d2 of the thin film transistor may further be provided with a passivation layer (PVX) 03 on a side far from the substrate 00.
  • PVX passivation layer
  • the etch stop layer 02 may be made of silicon oxide (SiOx) material
  • the gate insulating layer 01 may be made of SiOx
  • an oxide insulating material such as aluminum oxide (Al 2 O 3 )
  • the passivation layer 03 may be Made of insulating materials such as silicon nitride, silicon oxynitride, polyimide, or acrylic.
  • the embodiment of the present disclosure provides an electrostatic protection circuit.
  • the thin film transistor included in the electrostatic protection circuit is an oxide thin film transistor, and the aspect ratio of the channel of each thin film transistor is greater than or equal to the aspect ratio. Threshold, and the aspect ratio threshold is greater than 1, so the on-current of the transistor can be effectively reduced to prevent the transistor from being burned out when the signal line generates a transient high voltage.
  • the length of the channel of each transistor is longer, the length direction of the channel is parallel to the extending direction of the signal line, which can effectively reduce the occupied space of the electrostatic protection circuit.
  • FIG. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate may include a signal line S and an electrostatic protection circuit 100 connected to the signal line S.
  • the electrostatic protection circuit 100 may be a circuit as shown in any one of FIGS. 1, 2 and 4 to 8.
  • the array substrate may include a plurality of signal lines S, and each of the signal lines S may be connected to an electrostatic protection circuit 100.
  • the ESD protection circuits 100 connected to each signal line S may be located in a non-display area around the array substrate.
  • FIG. 11 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the signal line S may be a data line extending along the first direction X
  • the array substrate includes a plurality of data lines.
  • the ESD protection line L may include three discharge lines extending in the second direction Y and arranged in parallel, and a connection line L0 for connecting the three discharge lines.
  • the second direction Y intersects the first direction X
  • the connecting line L0 may extend along the first direction X.
  • the second direction Y may be perpendicular to the first direction X.
  • the ESD protection circuit 100 connected to each data line may be located in the same column as the ESD protection circuit 100 connected to an adjacent data line. That is, two adjacent ESD protection circuits 100 are connected between two adjacent data lines, or no ESD protection circuit is provided.
  • the electrostatic protection circuit 100 connected to the first data line and the electrostatic protection circuit 100 connected to the second data are located in the same column. That is, they are located between the two data lines.
  • the electrostatic protection circuits connected to the third data line and the fourth data line are also located between the two data lines.
  • each ESD protection circuit 100 connected to each data line By placing the ESD protection circuit 100 connected to each data line in the same column as the ESD protection circuit 100 connected to an adjacent data line, the space occupied by each ESD protection circuit can be effectively reduced, which is conducive to narrow border display. Implementation of the panel.
  • FIG. 12 is a cross-sectional view of FIG. 11 in the direction of AA. It can also be seen with reference to FIGS. 11 and 12 that among the two electrostatic protection circuits 100 located in the same column, one of the electrostatic protection circuits 100 may be located first among the three discharge lines. Between one discharge line and the second discharge line, another electrostatic protection circuit may be located between the second discharge line and the third discharge line of the three discharge lines. Moreover, the gate g and the second electrode d2 of the second thin film transistor M2 in the two electrostatic protection circuits 100 are both connected to the second discharge line (that is, the discharge line located in the middle).
  • the first discharge line and the second discharge line may serve as the first discharge line L1 and the second discharge line L2 of the one electrostatic protection circuit, respectively.
  • the third discharge line and the second discharge line can be used as the first discharge line L1 and the second discharge line L2 of the other electrostatic protection circuit, respectively.
  • the gate g of the second thin film transistor M2 in the two electrostatic protection circuits located in the same column is connected to the second discharge line L2
  • the two The gate g of the second thin film transistor M2 and the second discharge line may be an integrated structure, that is, they may be manufactured through a single patterning process. This can effectively reduce the occupied space of the electrostatic protection circuit and simplify the manufacturing process of the electrostatic protection circuit.
  • FIG. 13 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the signal line S may be a gate line extending along the second direction Y, and the array substrate may include a plurality of gate lines.
  • the electrostatic protection line L may extend along a first direction X, and the second direction Y intersects the first direction X.
  • the ESD protection line L may be disposed in parallel with the data lines in the array substrate.
  • the second direction Y is perpendicular to the first direction X.
  • An electrostatic protection circuit 100 connected to one of the plurality of gate lines may be disposed between two adjacent gate lines.
  • each gate line is located in a non-display area around the array substrate, and each gate line is connected to a gate line lead.
  • the display area of the array substrate is provided with a plurality of pixel units arranged in an array.
  • Each pixel unit may include a driving transistor M0 and a pixel electrode P connected to the driving transistor M0.
  • the gate of each driving transistor M0 is connected to the gate line, the first electrode is connected to the data line, and the second electrode is connected to the pixel electrode P.
  • Each driving transistor M0 can provide a driving voltage or a driving current to the pixel electrode P under the driving of the gate line and the data line.
  • the width direction refers to the second direction Y and the height direction refers to the first direction X. Therefore, in the array substrate, the interval between the gate lines extending in the second direction Y and arranged in the first direction X is relatively large, so an electrostatic protection circuit 100 can be provided between every two adjacent gate lines. The distance between the data lines extending along the first direction X and arranged along the second direction Y is relatively small, so two electrostatic protections arranged along the first direction X can be set between two adjacent data lines Circuit 100. Therefore, a reasonable layout of the electrostatic protection circuit is realized, and the occupied space of the electrostatic protection circuit is reduced.
  • the embodiment of the present disclosure also provides a method for manufacturing an electrostatic protection circuit, which can be used to manufacture the electrostatic protection circuit provided by the above embodiments.
  • the method may include:
  • Step 101 forming a first thin film transistor, a second thin film transistor, and an electrostatic protection line on a base substrate.
  • the gate and the second electrode of the first thin film transistor are both connected to a signal line, the first electrode of the first thin film transistor is connected to the electrostatic protection line, and the gate and the second electrode of the second thin film transistor are both connected to the static electricity
  • the protection line is connected, and the first pole of the second thin film transistor is connected to the signal line.
  • Each thin film transistor is an oxide thin film transistor, and an aspect ratio of a channel of each thin film transistor is greater than or equal to an aspect ratio threshold, and the aspect ratio threshold is greater than 1.
  • the aspect ratio threshold may be equal to 5.
  • a length direction of a channel of each thin film transistor is parallel to an extending direction of the signal line.
  • the ESD protection provided by the embodiment of the present disclosure may be formed in a non-display area around the substrate, and may be formed together with the signal line and the pixel unit in the display area.
  • At least one thin film transistor of the third thin film transistor and the fourth thin film transistor may be formed on the base substrate.
  • the gate and the second electrode of the third thin film transistor are both connected to the first electrode of the first thin film transistor, and the first electrode of the third thin film transistor is connected to the electrostatic protection line; the gate of the fourth thin film transistor is Both the pole and the second pole are connected to the first pole of the first thin film transistor, and the first pole of the fourth thin film transistor is connected to the signal line.
  • the gate of each thin film transistor formed in the above step 101 may be a strip structure, and a length direction of the strip structure is parallel to an extending direction of the signal line.
  • an arrangement direction of the first thin film transistor and the second thin film transistor may be parallel to an extending direction of the signal line.
  • the signal line may be a data line extending in a first direction;
  • the electrostatic protection line may include: a first discharge line and a second discharge line extending in a second direction and parallel to each other, and A connection line for connecting the first discharge line and the second discharge line, the second direction intersects the first direction.
  • the first thin film transistor and the second thin film transistor may be formed between the first discharge line and the second discharge line.
  • a first electrode of the first thin film transistor is connected to the first discharge line
  • a gate and a second electrode of the second thin film transistor are connected to the second discharge line.
  • the second pole of the first thin film transistor and the first pole of the second thin film transistor may be an integrated structure formed by one patterning process, and the gate of the first thin film transistor may be integrated with the one through a via. Structural connection.
  • the signal line may be a gate line extending in a second direction, and the electrostatic protection line extends in a first direction.
  • the first thin film transistor and the second thin film transistor may be aligned along a first axis, and the third thin film transistor and the The fourth thin film transistor may be arranged along a second axis, and the first axis and the second axis both intersect the first direction and are not collinear.
  • the first axis and the second axis may each be parallel to the second direction.
  • the first pole of the first thin film transistor, the first pole of the second thin film transistor, the second pole of the third thin film transistor, and the second pole of the fourth thin film transistor may be formed by a single patterning process.
  • the gate of the third thin film transistor and the gate of the fourth thin film transistor may be connected to the integrated structure through vias.
  • the gates of the third thin film transistor and the fourth thin film transistor may also be integrated structures formed through a single patterning process.
  • the second direction may be perpendicular to the first direction.
  • the method may include:
  • Step S1a a gate metal thin film is formed on the base substrate.
  • the base substrate may be a transparent glass substrate, and the gate metal thin film may be prepared by a method such as magnetron sputtering or evaporation.
  • the gate metal thin film may be a film layer formed of a low-resistance metal material, and may be, for example, molybdenum (Mo), aluminum (Al), aluminum-nickel alloy, chromium (Cr) or copper (Cu), titanium (Ti), or A single-layer metal thin film formed of a material such as AlNd or a multilayer metal thin film formed of Mo / Al / Mo or Ti / Al / Ti.
  • Step S2a performing a patterning process on the gate metal thin film to form a gate pattern.
  • the first metal mask may be patterned by a photolithography process to form a gate pattern
  • the gate pattern may include the gate of each thin film transistor in the electrostatic protection circuit and the static electricity. Protection line.
  • the gate pattern may further include a gate line and a gate of each driving transistor.
  • the photolithography process may include steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • the gate pattern formed in the non-display area of the base substrate may include a gate g of the first thin film transistor M1, a gate g of the second thin film transistor M2, a first discharge line L1, a first Two discharge lines L2 and a connection line L0 (not shown in the figure).
  • the gate g of M2 and the second discharge line L2 may be an integrated structure.
  • Step S3a a gate insulating layer, an active layer, and an etch stop layer are sequentially formed on the base substrate on which the gate pattern is formed.
  • the substrate with the gate insulating layer 01, the active layer ACT, and the etch barrier layer 02 formed thereon can be as shown in FIG. 15.
  • the gate insulating layer may be formed of an oxide insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.
  • the active layer may be formed of an oxide semiconductor material.
  • the etch stop layer may be made of a silicon oxide (SiOx) material.
  • a plurality of via holes can also be formed on the base substrate.
  • Part of the plurality of vias may expose a gate pattern for connecting the gate pattern and the source-drain metal pattern; part of the vias may expose an active layer for connecting the active layer and the source. Leaked metal pattern.
  • Step S4a forming a source-drain metal thin film on the base substrate on which the etch barrier layer is formed.
  • the source and drain metal thin films can be formed by using the same materials and processes as the gate metal thin films, and are not repeated here.
  • Step S5a Graphically process the source-drain metal thin film to form a source-drain metal pattern.
  • the source and drain metal thin film may be patterned by a photolithography process using a second mask plate to obtain a source and drain metal pattern.
  • the source and drain metal pattern may include: a first electrode and a first electrode of each thin film transistor. Dipole. Since the electrostatic protection circuit can be formed in synchronization with the pixel unit of the display area, the source-drain metal pattern may further include a data line and first and second electrodes of each driving transistor.
  • the source-drain metal pattern formed in the non-display area of the base substrate may include first and second electrodes d1 and d2 of the first thin film transistor M1 and first electrode d1 of the second thin film transistor M2. And the second pole d2 and the data line S.
  • the second pole d2 of the M1 and the first pole d1 of the M2 and the data line S may be an integrated structure.
  • Step S6a A passivation layer is formed on the base substrate on which the active drain metal pattern is formed.
  • an insulating material may be used to form a passivation protection film, and then a third mask plate may be used to define the pattern of the passivation protection film to form a passivation layer.
  • the passivation layer 03 may completely cover the source-drain metal pattern, and in a display area of the base substrate, the passivation layer 03 partially covers the source-drain metal. pattern. That is, a via hole is formed in the passivation layer 03 for connecting the pixel electrode and the drain of the driving transistor.
  • etching etching
  • different etching methods, etching liquids and etching gases need to be used to ensure the selection ratio of different materials, control of slope angle (Profile) and critical dimension (CD).
  • profile angle slope angle
  • CD critical dimension
  • the gate insulating layer and the active layer can be removed using a similar method, that is, plasma etching or reactive ion etching.
  • plasma etching or reactive ion etching By adjusting the etching gas and etching conditions, they can be in the same device. Achieve corrosion of multilayer films.
  • the above different films can be etched in the same equipment.
  • gases such as sulfur hexafluoride, chlorine, oxygen, and helium
  • sulfur hexafluoride, chlorine, and helium can be used to etch semiconductor films
  • sulfur hexafluoride, oxygen, and helium can be used to etch insulating films
  • chlorine and oxygen can be used to etch metal films.
  • the corrosion conditions of different films such as plasma power, air pressure, and electrode spacing are different.
  • the corrosion of semiconductor thin films is generally performed in a plasma chamber with a lower pressure and a higher power to ensure a strong effect of ion bombardment and sputtering corrosion.
  • Insulation films and metal films are generally carried out in a plasma chamber with a higher pressure and a lower power to ensure a strong chemical reaction ion corrosion effect.
  • the semiconductor film can be efficiently etched and removed under the environment of more than several kilowatts of power and several tens of millitorr pressure.
  • Another example is to pass hundreds of sccm of sulfur hexafluoride and hundreds of sccm of chlorine gas to the equipment.
  • the insulating film can be efficiently removed by etching.
  • the source-drain metal film may be removed by a chemical etching solution etching method according to the source-drain metal material, or a plasma etching or reactive ion etching method may be used.
  • a chemical etching solution etching method according to the source-drain metal material
  • a plasma etching or reactive ion etching method may be used.
  • the metal film can be efficiently etched and removed under the environment of thousands of power and hundreds of millitorr pressure.
  • the gate pattern and the active layer are formed, the source and drain metal thin film and the doped semiconductor layer are continuously etched and removed in the same equipment using the method of plasma etching or reactive ion etching and the conditions described above. .
  • Wet etching can be used for the removal of metal thin films.
  • a mixed solution of nitric acid, hydrochloric acid and acetic acid with a certain concentration ratio is used for immersion and spraying at a temperature of tens of degrees.
  • the method may include:
  • Step S1b a buffer layer is formed on the base substrate.
  • a plasma enhanced chemical vapor deposition can be used to sequentially deposit a silicon nitride (SiN) film and a silicon dioxide (SiO2) film on the entire substrate to obtain a buffer layer.
  • PECVD plasma enhanced chemical vapor deposition
  • Step S2b forming an active layer on the base substrate on which the buffer layer is formed.
  • sputtering thermal evaporation
  • PECVD Low Pressure Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • APCVD Atmospheric Pressure Chemical Vapor Deposition
  • Electrode electron cyclotron resonance chemical vapor deposition
  • ECR-CVD Cyclotron Resonance Chemical Vapor Deposition
  • other processes deposit an oxide semiconductor thin film on the surface of the substrate, and pattern the oxide semiconductor thin film to obtain an active layer.
  • the oxide semiconductor thin film can be patterned by photolithography and etching processes.
  • the etching process generally uses wet etching, and the etching solution used may be sulfuric acid (H 2 SO 4 ), phosphoric acid (H 3 PO 4 ), or hydrogen peroxide (H 2 O 2 ).
  • the etching solution used may be sulfuric acid (H 2 SO 4 ), phosphoric acid (H 3 PO 4 ), or hydrogen peroxide (H 2 O 2 ).
  • H 2 SO 4 sulfuric acid
  • phosphoric acid H 3 PO 4
  • hydrogen peroxide H 2 O 2
  • different etching solutions can be selected.
  • an etching barrier layer may be deposited on the surface of the active layer by using a PECVD, LPCVD, APCVD, ECR-CVD, or sputtering process.
  • the oxide semiconductor material such as IGZO has a very fast corrosion rate in the traditional etching solution for etching source and drain metal patterns.
  • An etch stop layer is added on the source layer.
  • the material forming the oxide semiconductor thin film may be an amorphous or polycrystalline metal oxide semiconductor material, and the amorphous or polycrystalline metal oxide semiconductor material may include: indium (In), gallium (Ga), zinc ( Zn), hafnium (Hf), tin (Sn), and Al, one or more metal elements.
  • the oxide semiconductor material may be: ZnO, InZnO (referred to as IZO), ZnSnO (referred to as ZTO), InSnZnO (referred to as ITZO), GaZnO (referred to as GZO), InGaZnO (referred to as IGZO), HfInZnO (referred to as HIZO), SnInO (Referred to as ITO) or AlInZnO (referred to as AIZO).
  • the material forming the oxide semiconductor thin film may also be a material formed by doping one or more metal ions or non-metal ions on the metal oxide semiconductor material, for example, it may be ZnO: Ga (that is, doped in ZnO). (HeteroGa ion), ZnO: Li, IGZO: Li, IGZO: N, ZnON and other materials.
  • the thickness of the oxide semiconductor thin film may be in a range of 40 nanometers (nm) to 50 nm, and the oxygen content during deposition is 15% to 30%.
  • Step S3b a gate insulating layer is formed on the base substrate on which the active layer is formed.
  • the photoresist on the polysilicon active layer can be removed by a photoresist stripping process, and a SiO2 film or a composite film of SiO2 and SiN can be deposited using PECVD to form a gate insulating layer on the active layer and the entire buffer layer.
  • Step S4b forming a gate metal pattern on the base substrate on which the gate insulating layer is formed.
  • one or more low-resistance metal material films can be deposited on the gate insulating layer by a physical vapor deposition method such as magnetron sputtering, and a gate metal pattern is formed by a photolithography process.
  • the pattern may include a gate and a gate line of each thin film transistor.
  • the gate metal thin film may be a single-layer metal thin film formed of materials such as Al, Cu, Mo, Ti, or AlNd, or may be a multilayer metal thin film formed of materials such as Mo / Al / Mo or Ti / Al / Ti.
  • Step S4b An interlayer insulating layer is formed on the base substrate on which the gate metal pattern is formed.
  • a SiO2 film and a SiN film are sequentially deposited using PECVD to form an interlayer insulating layer, and the interlayer insulating layer is etched through a mask and an etching process. A first contact hole and a second contact hole are formed.
  • Step S5b a source-drain metal pattern is formed on the base substrate on which the interlayer insulating layer is formed.
  • a source-drain metal film containing one or more low-resistance materials may be deposited on the interlayer insulating layer by a magnetron sputtering process, and a source-drain metal pattern may be formed through a mask and an etching process.
  • the source-drain metal pattern may include First and second electrodes of each thin film transistor, and data lines.
  • the first pole may be in contact with the active layer through the first contact hole, and the second pole may be in contact with the active layer through the second contact.
  • the material forming the source-drain metal thin film may include any one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, and copper.
  • the source-drain metal thin film may have a thickness ranging from 20 to 30 nm. It should be noted here that the source / drain metal film can be a single metal film layer, a double-layer metal film layer of buffer metal / metal, or a three-layer metal film layer of buffer metal / metal / buffer metal. .
  • the base substrate that has completed the above steps may be annealed at an annealing temperature of 30 to 320 ° C. and an annealing duration of 30 minutes (min).
  • this step not only the metal atoms in the metal material of the first pole and the second pole of the transistor can be diffused to the active layer, but also chemically react with the oxygen atoms in the oxide semiconductor material forming the active layer, so that The material of the active layer at this location loses oxygen, that is, the number of oxygen vacancies increases, and the number of free electrons also increases, so that the semiconductor material at this location exhibits a metallization (semiconductor) trend.
  • This can increase the ohmic contact between the first and second electrodes of the transistor and the active layer; at the same time, the stability of the channel region of the active layer can be enhanced, so that the performance of the oxide thin film transistor is better.
  • Step S6b a passivation layer is formed on the base substrate on which the active drain metal pattern is formed.
  • a SiN film can be deposited on the entire surface of the base substrate forming the active drain metal pattern using PECVD, and a passivation layer including vias can be formed through a mask and an etching process. Then use rapid thermal annealing or heat treatment furnace annealing to perform the hydrogenation process to repair defects in the interior and interface of the polysilicon active layer.
  • the via hole may be a via hole located in a display area of the base substrate and used to connect the second electrode of the driving transistor and the pixel electrode. This completes the manufacture of the electrostatic protection circuit.
  • an organic planarization layer having the same vias as the vias of the passivation layer may be formed on the passivation layer again through a mask process to fill the surface of the device.
  • the depressions form a flat surface.
  • a transparent conductive film is deposited on the organic planarization layer and the via hole by using magnetron sputtering, and the transparent conductive film is etched by a photolithography process, thereby forming a pixel region on the via hole and a part of the organic planarization layer.
  • the transparent conductive film may be a single-layer oxide conductive film, such as ITO (indium tin oxide) or IZO (indium zinc oxide), etc., or it may be ITO (indium tin oxide) / Ag / ITO, IZO (indium oxide Zinc) / Ag and other composite films.
  • An embodiment of the present disclosure further provides a display device, which may include an array substrate as shown in any one of FIGS. 10 to 13.
  • the display device may be any liquid crystal panel, electronic paper, OLED panel, AMOLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator and any other product or component with a display function.

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Abstract

提供了一种静电保护电路、阵列基板及显示装置，属于显示领域。该静电保护电路包括：第一薄膜晶体管、第二薄膜晶体管和静电防护线；第一薄膜晶体管的栅极和第二极均与信号线连接，第一薄膜晶体管的第一极与静电防护线连接；第二薄膜晶体管的栅极和第二极均与静电防护线连接，第二薄膜晶体管的第一极与信号线连接；每个薄膜晶体管均为氧化物薄膜晶体管，每个薄膜晶体管的沟道的长宽比大于或等于长宽比阈值，且该长宽比阈值大于1，由此可有效减小晶体管的导通电流，避免晶体管在信号线产生瞬时高压时被烧坏。

Description

静电保护电路、阵列基板及显示装置
本公开要求于2018年7月25日提交的申请号为201821189406.9、发明名称为“静电保护电路、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种静电保护电路、阵列基板及显示装置。
背景技术
在阵列基板制造过程，由于等离子体沉积、膜层刻蚀和摩擦等工艺容易产生静电，因此阵列基板上形成的信号线可能发生静电击穿和静电损伤，导致阵列基板不良。为了保证各种信号线的正常工作，阵列基板上会设置与信号线连接的静电保护器件。该静电保护器件通常也称为静电释放(Electro-Static discharge，ESD)器件。
相关技术中的静电保护器件一般包括薄膜晶体管和静电防护线，该薄膜晶体管的源极可以与信号线连接，栅极和漏极可以均与静电防护线连接。该薄膜晶体管可以将信号线上产生的静电及时释放至该静电防护线。
实用新型内容
本公开提供了一种静电保护电路、阵列基板及显示装置。所述技术方案如下：
一方面，提供了一种静电保护电路，所述静电保护电路包括：第一薄膜晶体管、第二薄膜晶体管和静电防护线；
所述第一薄膜晶体管的栅极和第二极均与信号线连接，所述第一薄膜晶体管的第一极与所述静电防护线连接；
所述第二薄膜晶体管的栅极和第二极均与所述静电防护线连接，所述第二薄膜晶体管的第一极与信号线连接；
其中，每个薄膜晶体管均为氧化物薄膜晶体管，每个薄膜晶体管的沟道的长宽比大于或等于长宽比阈值，所述长宽比阈值大于1。
可选的，所述长宽比阈值为5。
可选的，每个薄膜晶体管的沟道的长度方向平行于所述信号线的延伸方向。
可选的，每个薄膜晶体管的栅极均为条状结构，且所述条状结构的长度方向平行于所述信号线的延伸方向。
可选的，所述第一薄膜晶体管和所述第二薄膜晶体管的排列方向平行于所述信号线的延伸方向。
可选的，所述信号线为沿第一方向延伸的数据线；所述静电防护线包括：沿第二方向延伸且相互平行的第一放电线和第二放电线，以及用于连接所述第一放电线和所述第二放电线的连接线，所述第二方向与所述第一方向相交；
所述第一薄膜晶体管和所述第二薄膜晶体管设置在所述第一放电线和所述第二放电线之间，且所述第一薄膜晶体管的第一极与所述第一放电线连接，所述第二薄膜晶体管的栅极和第二极与所述第二放电线连接。
可选的，所述第一薄膜晶体管的第二极和所述第二薄膜晶体管的第一极为一体结构，且所述第一薄膜晶体管的栅极通过过孔与所述一体结构连接。
可选的，所述信号线为沿第二方向延伸的栅线，所述静电防护线沿第一方向延伸，且所述第二方向与所述第一方向相交。
可选的，所述静电保护电路还包括：第三薄膜晶体管和第四薄膜晶体管；
所述第三薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第三薄膜晶体管的第一极与所述静电防护线连接；所述第四薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第四薄膜晶体管的第一极与所述信号线连接；
所述第一薄膜晶体管和所述第二薄膜晶体管沿第一轴线排列，所述第三薄膜晶体管和所述第四薄膜晶体管沿第二轴线排列，所述第一轴线与所述第二轴线均与所述第二方向相交，且不共线。
可选的，所述第一轴线与所述第二轴线均平行于所述第二方向。
可选的，所述第一薄膜晶体管的第一极、所述第二薄膜晶体管的第一极、所述第三薄膜晶体管的第二极以及所述第四薄膜晶体管的第二极为一体结构，且所述第三薄膜晶体管的栅极和所述第四薄膜晶体管的栅极通过过孔与所述一 体结构连接。
可选的，所述第三薄膜晶体管和所述第四薄膜晶体管的栅极为一体结构。
可选的，所述第二方向垂直于所述第一方向。
可选的，所述静电保护电路还包括：第三薄膜晶体管和第四薄膜晶体管中的至少一个；
所述第三薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第三薄膜晶体管的第一极与所述静电防护线连接；
所述第四薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第四薄膜晶体管的第一极与所述信号线连接。
可选的，每个薄膜晶体管的沟道呈蛇形、锯齿形或者弧形。
另一方面，提供了一种阵列基板，所述阵列基板包括：
信号线，以及与所述信号线连接的如上述方面所述的静电保护电路。
可选的，所述信号线为沿第一方向延伸的数据线，且所述阵列基板包括多条数据线；所述静电防护线包括：沿第二方向延伸且平行排列的三条放电线，以及用于连接所述三条放电线的连接线，所述第二方向与所述第一方向相交；
每条数据线所连接的静电保护电路，均与相邻一条数据线所连接的静电保护电路位于同一列；
位于同一列的两个静电保护电路中，其中一个静电保护电路位于所述三条放电线中第一条放电线和第二条放电线之间，另一个静电保护电路位于所述三条放电线中第二条放电线和第三条放电线之间，且位于同一列的两个静电保护电路中第二薄膜晶体管的栅极和第二极均与所述第二条放电线连接。
可选的，所述信号线为沿第二方向延伸的栅线，且所述阵列基板包括多条栅线；所述静电防护线沿第一方向延伸，所述第二方向垂直于所述第一方向；
所述多条栅线中每相邻两条栅线之间设置有其中一条栅线所连接的静电保护电路。
又一方面，提供了一种显示装置，所述显示装置包括：如上述方面所述的阵列基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种静电保护电路的结构示意图；
图2是本公开实施例提供的一种静电保护电路的等效电路图；
图3是本公开实施例提供的一种薄膜晶体管的导通电流随栅极电压变化的示意图；
图4是本公开实施例提供的另一种静电保护电路的等效电路图；
图5是图1在AA方向的截面图；
图6是本公开实施例提供的另一种静电保护电路的结构示意图；
图7是图6在BB方向的截面图；
图8是图6在CC方向的截面图；
图9是本公开实施例提供的一种沟道的可选形状的示意图；
图10是本公开实施例提供的一种阵列基板的结构示意图；
图11是本公开实施例提供的另一种阵列基板的结构示意图；
图12是图11在AA方向的截面图；
图13是本公开实施例提供的另一种阵列基板的结构示意图；
图14是本公开实施例提供的一种栅极图案的结构示意图；
图15是本公开实施例提供的一种栅绝缘层、有源层和刻蚀阻挡层的结构示意图；
图16是本公开实施例提供的一种源漏金属图案的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例中采用的晶体管可以均为薄膜晶体管，根据在电路中的作用本公开实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，可以将其中源极称为第一极，漏极称为第二极；或者也可以将其中源极称为第二极，漏极称为第一极。按附图中的形态规定晶体管的中间端为栅极、信号输 入端为源极、信号输出端为漏极。
图1是本公开实施例提供的一种静电保护电路的结构示意图，图2是本公开实施例提供的一种静电保护电路的等效电路图。参考图1和图2，该静电保护电路可以包括：第一薄膜晶体管M1、第二薄膜晶体管M2和静电防护线L。
其中，该第一薄膜晶体管M1的栅极g和第二极d2可以均与信号线S连接，该第一薄膜晶体管M1的第一极d1与该静电防护线L连接。例如，该第一薄膜晶体管M1的第一极d1可以与静电防护线L直接连接。
该第二薄膜晶体管M2的栅极g和第二极d2均与该静电防护线L连接，该第二薄膜晶体管M2的第一极d1与信号线S连接。例如，该第二薄膜晶体管M2的第一极d1可以与信号线S直接连接。
其中，每个薄膜晶体管可以均为氧化物薄膜晶体管，即该薄膜晶体管的有源层由氧化物材料制成，例如可以由铟镓锌氧化物(indium gallium zinc oxide，IGZO)或者氧化锌(ZnO)等氧化物材料制成。每个薄膜晶体管的沟道ACT(即有源层)的长宽比大于或等于长宽比阈值，该长宽比阈值可以大于1。
综上所述，本公开实施例提供了一种静电保护电路，该静电保护电路中包括的薄膜晶体管为氧化物薄膜晶体管，且每个薄膜晶体管的沟道的长宽比大于或等于长宽比阈值，且该长宽比阈值大于1，由此可以有效减小晶体管的导通电流，避免晶体管在信号线产生瞬时高压时被烧坏。
在本公开实施例中，该长宽比阈值可以为5，即每个薄膜晶体管的沟道ACT的宽长比W/L≤0.2。
相比于低温多晶硅(Low Temperature Poly-silicon，LTPS)薄膜晶体管，由于氧化物薄膜晶体管的制造工艺较为简单，因此目前一般采用氧化物薄膜晶体管制作静电保护电路。但是，氧化物薄膜晶体管的导通电流较高，约为LTPS薄膜晶体管的5倍。由于该氧化物薄膜晶体管的导电能力较强，导通电流较大，因此当信号线上产生的静电的电压较高时，该氧化物薄膜晶体管比较容易烧毁。
根据薄膜晶体管的导通电流I的计算公式：
Figure PCTCN2019091913-appb-000001
可以看出，该导通电流I的大小与薄膜晶体管的宽长比W/L正相关。上述公式中，V GS为薄膜晶体管的栅源电压差，V TH为薄膜晶体管的阈值电压，V DS为薄膜 晶体管的源漏电压差。
图3是本公开实施例提供的一种薄膜晶体管的导通电流随栅极电压变化的示意图。图3以薄膜晶体管的沟道的宽长比W/L＝1，源漏电压差VDS＝15V为例。从图3可以看出，当薄膜晶体管的栅极电压V G达到10V时，薄膜晶体管的导通电流即可达到10 -5A。但是，若设计薄膜晶体管的沟道的宽长比W/L≤0.2，则薄膜晶体管的栅极电压V G需达到50V时，薄膜晶体管的导通电流即可达到10 -5A。又由于信号线上产生的静电的电压一般在50V以下，因此设计薄膜晶体管的沟道的W/L小于等于0.2(即长宽比大于等于5)可以保证薄膜晶体管的安全有效运行。
可选的，从图1还可以看出，每个薄膜晶体管的沟道ACT的长度方向可以平行于该信号线S的延伸方向。由于在本公开实施例中，每个晶体管的沟道的长度较长，使得该沟道的长度方向平行于信号线的延伸方向，可以有效减小静电保护电路的占用空间。
在本公开实施例中，信号线S可以为阵列基板上的任一条信号线，例如可以为数据线、栅线或栅极驱动电路的时钟信号线等任一用于驱动显示装置的信号线。或者，该信号线还可以为阵列基板中的测试线或维修线等。该静电防护线L可以为用于提供基准电源信号的放电线。例如该静电防护线L可以为公共电极(Vcom)线，该公共电极线用于提供电压为0伏特(V)或0V左右的公共电极信号。当该信号线S上产生静电时，该第一薄膜晶体管M1或第二薄膜晶体管M2可以开启，从而可以将该信号线S与静电防护线L连通，使得信号线S上产生的静电能够及时释放至静电防护线L上。
可选的，本公开实施例提供的静电保护电路还可以包括：第三薄膜晶体管M3和第四薄膜晶体管M4中的至少一个。示例的，图4是本公开实施例提供的另一种静电保护电路的等效电路图，如图4所示，该静电保护电路还包括第三薄膜晶体管M3和第四薄膜晶体管M4。
参考图4，该第三薄膜晶体管M3的栅极和第二极可以均与该第一薄膜晶体管M1的第一极连接，该第三薄膜晶体管M3的第一极与该静电防护线L连接。该第四薄膜晶体管M4的栅极和第二极均与该第一薄膜晶体管M1的第一极连接，该第四薄膜晶体管M4的第一极与该信号线S连接。
在图4所示的电路结构中，第一薄膜晶体管M1的第一极可以通过第三薄膜 晶体管M3与静电防护线L连接。第二薄膜晶体管M2的第一极可以通过第四薄膜晶体管M4与信号线S连接。而在图1和图2所示的电路结构中，第一薄膜晶体管M1的第一极与静电防护线L直接连接，第二薄膜晶体管M2的第一极与信号线S直接连接。
通过设置第三薄膜晶体管M3，可以增大第一薄膜晶体管M1的第一极与静电防护线L之间的电阻，从而可以有效降低流过第一薄膜晶体管M1的电流的大小，避免烧坏第一薄膜晶体管M1。同理，通过设置第四薄膜晶体管M4，可以增大第二薄膜晶体管M2的第一极与信号线S之间的电阻，从而可以有效降低流过第二薄膜晶体管M2的电流的大小，避免烧坏第二薄膜晶体管M2。
可选的，如图1所示，该静电保护电路中的每个薄膜晶体管的栅极g可以均为条状结构，且该条状结构的长度方向平行于该信号线S的延伸方向。由此可以减小薄膜晶体管的占用空间。
参考图1还可以看出，该第一薄膜晶体管M1和该第二薄膜晶体管M2的排列方向也可以平行于该信号线S的延伸方向，以尽量减小该静电保护电路的占用空间。
作为一种可选的实现方式，参考图1，该信号线S可以为沿第一方向X延伸的数据线。该静电防护线L可以包括：沿第二方向Y延伸且相互平行的第一放电线L1和第二放电线L2，以及用于连接该第一放电线L1和该第二放电线L2的连接线L0。其中，该第二方向Y可以与该第一方向X相交。
可选的，该连接线L0可以沿第一方向X延伸。该第二方向Y可以垂直于该第一方向X。
图5是图1在AA方向的截面图。结合图1和图5可以看出，该第一薄膜晶体管M1和该第二薄膜晶体管M2可以均设置在该第一放电线L1和该第二放电线L2之间。并且，该第一薄膜晶体管M1的第一极d1可以与该第一放电线L1连接，该第二薄膜晶体管M2的栅极g和第二极d2可以与该第二放电线L2连接。
示例的，如图5所示，当该信号线S为数据线时，各薄膜晶体管的第一极d1和第二极d2可以均与该信号线S同层设置，各薄膜晶体管的栅极g可以与该静电防护线L同层设置。因此，结合图1和图5可以看出，该第一薄膜晶体管M1的第一极d1可以通过过孔与该第一放电线L1连接。该第二薄膜晶体管M2 的第二极d2可以通过过孔与该第二放电线L2连接。该第二薄膜晶体管M2的栅极g可以直接与该第二放电线L2连接。例如图5所示，该第二薄膜晶体管M2的栅极g与该第二放电线L2可以为一体结构。
由于在阵列基板中，数据线之间的间隔通常较窄，因此通过设置两条平行的放电线，并使得每个薄膜晶体管分别与一条放电线连接，可以有效减小静电保护电路的占用空间，实现合理布线。
可选的，如图1和图5所示，该第一薄膜晶体管M1的第二极d2和该第二薄膜晶体管M2的第一极d1可以为一体结构，该一体结构可以直接与信号线S连接。也即是，该第一薄膜晶体管M1的第二极d2、该第二薄膜晶体管M2的第一极d1和信号线S可以通过一次构图工艺形成。该第一薄膜晶体管M1的栅极g可以通过过孔(例如图1中的方形过孔)与该一体结构连接。
将两个薄膜晶体管中与信号线S连接的电极设计为一体结构，不仅可以减小静电保护电路的占用空间，并且可以简化静电保护电路的制造工艺。
作为另一种可选的实现方式，如图6所示，该信号线S还可以为沿第二方向Y延伸的栅线，该静电防护线L可以沿第一方向X延伸，且该第二方向Y与该第一方向X相交。例如，该第二方向Y垂直于该第一方向X。
继续参考图6，该静电保护电路还可以包括：第三薄膜晶体管M3和第四薄膜晶体管M4。该第三薄膜晶体管M3的栅极g和第二极d2可以均与该第一薄膜晶体管M1的第一极d1连接，该第三薄膜晶体管M3的第一极d1可以与该静电防护线L连接。该第四薄膜晶体管M4的栅极g和第二极d2可以均与该第一薄膜晶体管M1的第一极d1连接，该第四薄膜晶体管M4的第一极d1可以与该信号线S连接。
如图6所示，该第一薄膜晶体管M1和第二薄膜晶体管M2可以沿第一轴线排列，该第三薄膜晶体管M3和第四薄膜晶体管M4可以沿第二轴线排列，该第一轴线和该第二轴线可以均与该第一方向X相交，且该两个轴线不共线。例如，该第一轴线和该第二轴线可以均平行于该第二方向Y。
参考图6可以看出，该第一薄膜晶体管M1的第一极d1、该第二薄膜晶体管M2的第一极d1、该第三薄膜晶体管M3的第二极d2以及该第四薄膜晶体管M4的第二极d2可以为一体结构。并且，第三薄膜晶体管M3的栅极g和第四薄膜晶体管M4的栅极g可以通过过孔(例如图6中的方形过孔)与该一体结构 连接。
由于该四个薄膜晶体管分两行平行设置，因此该四个薄膜晶体管中，每个薄膜晶体管均各有一个电极与其他薄膜晶体管的电极的位置较为接近。通过设计一体结构作为四个薄膜晶体管共用的电极，可以有效节约布线空间，减小静电保护电路的占用空间，以及简化其制造工艺。
图7是图6在BB方向的截面图，图8是图6在CC方向的截面图。结合图6至图8可以看出，当该信号线S为栅线时，各薄膜晶体管的栅极可以与该信号线S同层设置，各薄膜晶体管的第一极和第二极可以均与该静电防护线L同层设置。因此，该第一薄膜晶体管M1的栅极g和第二极d2，以及第四薄膜晶体管M4的第一极d1可以分别通过过孔与该信号线S连接。
该第二薄膜晶体管M2的栅极g可以通过过孔与静电防护线L连接，第二薄膜晶体管M2的第二极d2，以及第三薄膜晶体管M3的第一极d1可以直接与该静电防护线L连接。例如图6和图7所示，该第二薄膜晶体管M2的第二极d2与该静电防护线L可以为一体结构，如图6和图8所示，该第三薄膜晶体管M3的第一极d1与该静电防护线L也可以为一体结构。
可选的，如图6和图8所示，该第三薄膜晶体管M3和该第四薄膜晶体管M4的栅极g可以为一体结构。由此可以简化制造工艺，进一步节省该静电保护电路的占用空间。
图9是本公开实施例提供的一种沟道的可选形状的示意图。参考图9，该静电保护电路中每个薄膜晶体管的沟道ACT除了可以呈矩形，还可以呈蛇形、锯齿形或者弧形等形状。通过设计该蛇形、锯齿形或者弧形的沟道，可以在有限空间内尽量增大沟道的长宽比。其中，沟道的形状可以是指沟道在衬底基板上的正投影的形状。
参考图5、图7以及图8还可以看出，该静电保护电路可以设置在衬底基板00上。薄膜晶体管的栅极g远离衬底基板00的一侧设置有栅绝缘层(gate insulator，GI)01，薄膜晶体管的有源层ACT可以设置在该栅绝缘层01远离衬底基板00的一侧。该有源层ACT远离衬底基板00的一侧还设置有刻蚀阻挡层(Etch Stop Layer，ESL)02，薄膜晶体管的第一极d1和第二极d2可以设置在该刻蚀阻挡层02远离衬底基板00的一侧。该薄膜晶体管的第一极d1和第二极d2远离衬底基板00的一侧还可以设置有钝化层(Passivation，PVX)03。
其中，该刻蚀阻挡层02可以由氧化硅(SiOx)材料制成，该栅绝缘层01可以由SiOx，或者氧化铝(Al 2O 3)等氧化物绝缘材料制成，钝化层03可以由氮化硅、氮氧化硅、聚酰亚胺或亚克力等绝缘材料制成。
综上所述，本公开实施例提供了一种静电保护电路，该静电保护电路中包括的薄膜晶体管为氧化物薄膜晶体管，且每个薄膜晶体管的沟道的长宽比大于或等于长宽比阈值，且该长宽比阈值大于1，因此可以有效减小晶体管的导通电流，避免晶体管在信号线产生瞬时高压时被烧坏。并且，由于每个晶体管的沟道的长度较长，使得该沟道的长度方向平行于信号线的延伸方向，可以有效减小静电保护电路的占用空间。
图10是本公开实施例提供的一种阵列基板的结构示意图，参考图10，该阵列基板可以包括：信号线S，以及与该信号线S连接的静电保护电路100。该静电保护电路100可以为如图1、图2以及图4至图8任一所示的电路。
可选的，如图10所示，该阵列基板可以包括多条信号线S，其中每条信号线S均可以连接有一个静电保护电路100。并且，各个信号线S所连接的静电保护电路100可以均位于阵列基板周边的非显示区域内。
图11是本公开实施例提供的另一种阵列基板的结构示意图。如图11所示，该信号线S可以为沿第一方向X延伸的数据线，且该阵列基板包括多条数据线。该静电防护线L可以包括：沿第二方向Y延伸且平行排列的三条放电线，以及用于连接该三条放电线的连接线L0。其中，该第二方向Y与该第一方向X相交，该连接线L0可以沿该第一方向X延伸。例如，该第二方向Y可以垂直于该第一方向X。
如图11所示，该多条数据线中，每条数据线所连接的静电保护电路100，可以均与相邻一条数据线所连接的静电保护电路100位于同一列。也即是，每相邻两条数据线之间设置有该两条数据线所连接的两个静电保护电路100，或者未设置静电保护电路。
示例的，在图11所示的结构中，按照从左至右的顺序，第一条数据线所连接的静电保护电路100，与第二条数据所连接的静电保护电路100均位于同一列，即均位于该两条数据线之间。第三条数据线和第四条数据线所连接的静电保护电路也均位于该两条数据线之间。
通过将每条数据线所连接的静电保护电路100，与相邻一条数据线所连接的 静电保护电路100设置在同一列，可以有效减小各静电保护电路所占用的空间，有利于窄边框显示面板的实现。
图12是图11在AA方向的截面图，参考图11和图12还可以看出，位于同一列的两个静电保护电路100中，其中一个静电保护电路100可以位于该三条放电线中第一条放电线和第二条放电线之间，另一个静电保护电路则可以位于该三条放电线中第二条放电线和第三条放电线之间。并且，该两个静电保护电路100中第二薄膜晶体管M2的栅极g和第二极d2均与该第二条放电线(即位于中间的放电线)连接。
也即是，如图11和图12所示，该第一条放电线和第二条放电线可以分别作为该一个静电保护电路的第一放电线L1和第二放电线L2。该第三条放电线和第二条放电线则可以分别作为该另一个静电保护电路的第一放电线L1和第二放电线L2。
可选的，参考图11和图12还可以看出，由于位于同一列的两个静电保护电路中的第二薄膜晶体管M2的栅极g均与第二条放电线L2连接，因此该两个第二薄膜晶体管M2的栅极g与该第二条放电线可以为一体结构，即可以通过一次构图工艺制造得到。由此可以有效减小静电保护电路的占用空间，以及简化静电保护电路的制造工艺。
图13是本公开实施例提供的另一种阵列基板的结构示意图。如图13所示，该信号线S可以为沿第二方向Y延伸的栅线，且该阵列基板可以包括多条栅线。该静电防护线L可以沿第一方向X延伸，该第二方向Y与该第一方向X相交。示例的，如图13所示，该静电防护线L可以与阵列基板中的数据线平行设置。该第二方向Y垂直于该第一方向X。
该多条栅线中每相邻两条栅线之间可以设置有其中一条栅线所连接的静电保护电路100。
参考图13还可以看出，各条栅线所连接的静电保护电路100均位于阵列基板周边的非显示区域，每条栅线与栅线引线连接。阵列基板的显示区域设置有阵列排布的多个像素单元，每个像素单元可以包括驱动晶体管M0，以及与该驱动晶体管M0连接的像素电极P。从图13可以看出，每个驱动晶体管M0的栅极与栅线连接，第一极与数据线连接，第二极与像素电极P连接。该每个驱动晶体管M0可以在栅线和数据线的驱动下，为像素电极P提供驱动电压或者驱 动电流。
由于每个像素单元的宽度与高度的比值一般为1:3，其中，宽度方向是指该第二方向Y，高度方向是指第一方向X。因此在阵列基板中，沿第二方向Y延伸，并沿第一方向X排列的栅线之间的间距相对较大，因此可以在每相邻两条栅线之间设置一个静电保护电路100。而沿第一方向X延伸，并沿第二方向Y排列的数据线之间的间距相对较小，因此可以在相邻两条数据线之间设置沿该第一方向X排列的两个静电保护电路100。由此实现了静电保护电路的合理布局，减小了静电保护电路的占用空间。
本公开实施例还提供了一种静电保护电路的制造方法，该方法可以用于制造上述实施例所提供的静电保护电路。该方法可以包括：
步骤101、在衬底基板上形成第一薄膜晶体管、第二薄膜晶体管和静电防护线。
该第一薄膜晶体管的栅极和第二极均与信号线连接，该第一薄膜晶体管的第一极与该静电防护线连接；该第二薄膜晶体管的栅极和第二极均与该静电防护线连接，该第二薄膜晶体管的第一极与信号线连接。
其中，每个薄膜晶体管均为氧化物薄膜晶体管，每个薄膜晶体管的沟道的长宽比大于或等于长宽比阈值，该长宽比阈值大于1。示例的，该长宽比阈值可以等于5。
可选的，每个薄膜晶体管的沟道的长度方向平行于该信号线的延伸方向。
需要说明的是，本公开实施例提供的静电保护电可以形成在衬底基板周边的非显示区域，并可以与显示区域的信号线和像素单元一同形成。
可选的，在上述步骤101中，在形成第一薄膜晶体管和第二薄膜晶体管的同时，还可以在该衬底基板上形成第三薄膜晶体管和第四薄膜晶体管中的至少一个薄膜晶体管。
其中，该第三薄膜晶体管的栅极和第二极均与该第一薄膜晶体管的第一极连接，该第三薄膜晶体管的第一极与该静电防护线连接；该第四薄膜晶体管的栅极和第二极均与该第一薄膜晶体管的第一极连接，该第四薄膜晶体管的第一极与该信号线连接。
可选的，上述步骤101中形成的每个薄膜晶体管的栅极可以均为条状结构，且该条状结构的长度方向平行于该信号线的延伸方向。并且，该第一薄膜晶体 管和该第二薄膜晶体管的排列方向可以平行于该信号线的延伸方向。
作为一种可选的实现方式，该信号线可以为沿第一方向延伸的数据线；该静电防护线可以包括：沿第二方向延伸且相互平行的第一放电线和第二放电线，以及用于连接该第一放电线和该第二放电线的连接线，该第二方向与该第一方向相交。
相应的，该第一薄膜晶体管和该第二薄膜晶体管可以形成在该第一放电线和该第二放电线之间。并且，该第一薄膜晶体管的第一极与该第一放电线连接，该第二薄膜晶体管的栅极和第二极与该第二放电线连接。
可选的，该第一薄膜晶体管的第二极和该第二薄膜晶体管的第一极可以为通过一次构图工艺形成的一体结构，且该第一薄膜晶体管的栅极可以通过过孔与该一体结构连接。
作为另一种可选的实现方式，该信号线可以为沿第二方向延伸的栅线，该静电防护线沿第一方向延伸。
若在上述步骤101中还在衬底基板上形成了第三薄膜晶体管和第四薄膜晶体管，则该第一薄膜晶体管和该第二薄膜晶体管可以沿第一轴线排列，该第三薄膜晶体管和该第四薄膜晶体管可以沿第二轴线排列，该第一轴线和该第二轴线均与该第一方向相交，且不共线。例如，该第一轴线和该第二轴线可以均平行于第二方向。
可选的，该第一薄膜晶体管的第一极、该第二薄膜晶体管的第一极、该第三薄膜晶体管的第二极以及该第四薄膜晶体管的第二极可以为通过一次构图工艺形成的一体结构，且该第三薄膜晶体管的栅极和该第四薄膜晶体管的栅极可以通过过孔与该一体结构连接。该第三薄膜晶体管和该第四薄膜晶体管的栅极也可以为通过一次构图工艺形成的一体结构。
可选的，在本公开实施例中，该第二方向可以垂直于该第一方向。
以图1和图5所示的静电保护电路为例，并以静电保护电路中的薄膜晶体管为底栅结构为例，介绍本公开实施例提供的静电保护电路的制造方法，该方法可以包括：
步骤S1a、在衬底基板上形成一层栅金属薄膜。
其中，该衬底基板可以为透明的玻璃基板，该栅金属薄膜可以采用磁控溅射或蒸发等方法制备。该栅金属薄膜可以是由低电阻金属材料形成的膜层，例 如可以是由钼(Mo)、铝(Al)、铝镍合金、铬(Cr)或、铜(Cu)、钛(Ti)或AlNd等材料形成的单层金属薄膜，或者也可以是Mo/Al/Mo或Ti/Al/Ti形成的多层金属薄膜。
步骤S2a、对该栅金属薄膜进行图形化处理，形成栅极图案。
可选的，可以采用第一个掩膜版通过光刻工艺对该栅金属薄膜进行图形化处理，以形成栅极图案，该栅极图案可以包括静电保护电路中各薄膜晶体管的栅极以及静电防护线。当然，由于该静电保护电路可以与显示区域的像素单元同步形成，因此该栅极图案还可以包括栅线以及各驱动晶体管的栅极。该光刻工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等步骤。
示例的，如图14所示，衬底基板非显示区域内形成的栅极图案可以包括第一薄膜晶体管M1的栅极g、第二薄膜晶体管M2的栅极g、第一放电线L1、第二放电线L2以及连接线L0(图中未示出)。该M2的栅极g与第二放电线L2可以为一体结构。
步骤S3a、在形成有栅极图案的衬底基板上依次形成栅绝缘层、有源层和刻蚀阻挡层。
该形成有栅绝缘层01、有源层ACT以及刻蚀阻挡层02的衬底基板可以如图15所示。其中，栅绝缘层可以由氧化硅、氮化硅、氮氧化硅或氧化铝等氧化物绝缘材料形成。有源层可以由氧化物半导体材料形成。刻蚀阻挡层可以由氧化硅(SiOx)材料制成。
参考图15还可以看出，在形成刻蚀阻挡层02之后，还可以在该衬底基板上形成多个过孔。该多个过孔中的部分过孔可以暴露出栅极图案，以用于连接栅极图案和源漏金属图案；部分过孔则可以暴露出有源层，以用于连接有源层和源漏金属图案。
步骤S4a、在形成有刻蚀阻挡层的衬底基板上形成源漏金属薄膜。
其中，源漏金属薄膜可以采用与栅金属薄膜相同的材料和工艺形成，此处不再赘述。
步骤S5a、对该源漏金属薄膜进行图形化处理，形成源漏金属图案。
可选的，可以采用第二个掩膜版通过光刻工艺对该源漏金属薄膜进行图形化处理，得到源漏金属图案，该源漏金属图案可以包括：各个薄膜晶体管的第一极和第二极。由于该静电保护电路可以与显示区域的像素单元同步形成，因 此该源漏金属图案还可以包括数据线以及各驱动晶体管的第一极和第二极。
示例的，如图16所示，衬底基板非显示区域内形成的源漏金属图案可以包括第一薄膜晶体管M1的第一极d1和第二极d2、第二薄膜晶体管M2的第一极d1和第二极d2以及数据线S。该M1的第二极d2、M2的第一极d1与该数据线S可以为一体结构。
步骤S6a、在形成有源漏金属图案的衬底基板上形成钝化层。
可选的，可以采用绝缘材料形成钝化保护膜，之后可以采用第三个掩膜版定义钝化保护膜的图案，形成钝化层。参考图5，在衬底基板的非显示区域内，该钝化层03可以完全覆盖在源漏金属图案上，而在衬底基板的显示区域内，该钝化层03部分覆盖该源漏金属图案。即该钝化层03中形成有用于连接像素电极和驱动晶体管的漏极的过孔。
由此，即可完成静电保护电路的制造。进一步的，对于衬底基板的显示区域，还需继续在钝化层上形成一层透明导电薄膜，然后通过第四个掩膜版形成像素电极，该像素电极可以通过钝化层中的过孔与驱动晶体管的漏极连接。
在上述工艺的腐蚀(即刻蚀)过程中，需要使用不同的腐蚀方法、腐蚀液和腐蚀气体，保证实现不同材料的选择比、坡度角(Profile)和关键尺寸(CD)的控制。比如在形成源漏金属图案的过程中，栅绝缘层和有源层可以使用类似的方法去除，即等离子刻蚀或反应离子刻蚀，通过调整刻蚀气体和刻蚀条件，可以在同一设备中实现多层薄膜的腐蚀。如从六氟化硫、氯气、氧气和氦气等气体中选择不同的腐蚀气体组合和不同的气体流量，即可在同一设备里实现上述不同薄膜的腐蚀。如可以采用六氟化硫、氯气和氦气刻蚀半导体薄膜；采用六氟化硫、氧气和氦气刻蚀绝缘薄膜；采用氯气和氧气腐蚀金属薄膜。
为了达成器件结构的优化和工艺的高效率，不同薄膜的腐蚀条件如等离子功率、气压和电极间距等有所区别。半导体薄膜的腐蚀一般在较低气压和较大功率的等离子腔室里进行，以确保具有较强的离子轰击和溅射腐蚀的效果。绝缘薄膜和金属薄膜一般在较高气压和稍低功率的等离子腔室里进行，以确保具有较强的化学反应离子腐蚀效果。如向设备通入数十体积流量(sccm)的六氟化硫和数千sccm的氯气，在数千瓦功率以上和数十毫托气压的环境下，可以高效刻蚀去除半导体薄膜。又如向设备通入数百sccm的六氟化硫和数百sccm的氯气，在数千瓦功率以下和数百毫托气压的环境下，可以高效刻蚀去除绝缘薄 膜。
又比如在形成源漏金属图案的过程中，根据源漏金属材料可以采用化学腐蚀液刻蚀的方法去除源漏金属薄膜，也可以采用等离子刻蚀或反应离子刻蚀的方法。如向干法腐蚀设备通入数百至数千sccm的氯气和数千sccm的氧气，在数千功率以下和数百毫托气压的环境下，可以高效刻蚀去除金属薄膜。在形成栅极图案和有源层时，使用等离子刻蚀或反应离子刻蚀的方法和如前所述的条件，在同一设备中对源漏金属薄膜和掺杂半导体层进行连续地腐蚀而去除。湿法腐蚀可以用于金属薄膜的去除，一般使用一定浓度比例的硝酸、盐酸和醋酸的混合液，在数十度的温度下通过浸入和喷洒的方式进行。
以图1和图5所示的静电保护电路为例，并以静电保护电路中的薄膜晶体管为顶栅结构为例，介绍本公开实施例提供的静电保护电路的制造方法，该方法可以包括：
步骤S1b、在衬底基板上形成缓冲层。
示例的，可以采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)在整个衬底基板上依次沉积氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜，得到缓冲层。
步骤S2b、在形成有缓冲层的衬底基板上形成有源层。
可选的，可以采用溅射、热蒸发、PECVD、低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)、大气压化学气相沉积(Atmospheric Pressure Chemical Vapor Deposition，APCVD)或电子回旋谐振化学气相沉积(Electron Cyclotron Resonance ChemicalVapor Deposition，ECR-CVD)等工艺在衬底基板的表面沉积氧化物半导体薄膜，并对该氧化物半导体薄膜进行图形化处理，得到有源层。例如，可以采用光刻和刻蚀工艺对该氧化物半导体薄膜进行图形化处理。其中刻蚀工艺一般采用湿法刻蚀，使用的刻蚀液可以是硫酸(H 2SO 4)、磷酸(H 3PO 4)或者过氧化氢(H 2O 2)等。根据有源层所采用的氧化物半导体材料，以及源漏金属薄膜的材料，可以选择不同的刻蚀液。
进一步的，还可以采用PECVD、LPCVD、APCVD、ECR-CVD或溅射工艺在该有源层的表面沉积刻蚀阻挡层。由于IGZO等氧化物半导体材料在传统的刻蚀源漏金属图案的刻蚀液中的腐蚀速率极快，同时由于氧化物半导体对水和氧的较为敏感，因此为了保护有源层，需要在有源层上增加一层刻蚀阻挡层。
其中，形成该氧化物半导体薄膜的材料可以为非晶或多晶金属氧化物半导体材料，该非晶或多晶金属氧化物半导体材料中可以包括：铟(In)、镓(Ga)、锌(Zn)、铪(Hf)、锡(Sn)和Al等金属元素中一种或多种金属元素。示例的，该氧化物半导体材料可以为：ZnO，InZnO(简称IZO)，ZnSnO(简称ZTO)，InSnZnO(简称ITZO)，GaZnO(简称GZO)，InGaZnO(简称IGZO)，HfInZnO(简称HIZO)，SnInO(简称ITO)或AlInZnO(简称AIZO)等。或者，形成该氧化物半导体薄膜的材料还可以是对上述金属氧化物半导体材料进行一种或多种金属离子或非金属离子掺杂形成的材料，例如可以为ZnO:Ga(即在ZnO中掺杂Ga离子)，ZnO:Li，IGZO:Li，IGZO:N，ZnON等材料。
可选的，该氧化物半导体薄膜的厚度范围可以为40纳米(nm)至50nm，沉积时的含氧量为15％至30％。
步骤S3b、在形成有有源层的衬底基板上形成栅绝缘层。
进一步的，可以通过光刻胶剥离工艺去除多晶硅有源层上的光刻胶，使用PECVD沉积SiO2薄膜或SiO2与SiN的复合薄膜，在有源层以及整个缓冲层上形成栅绝缘层。
步骤S4b、在形成有栅绝缘层的衬底基板上形成栅极金属图案。
在本公开实施例中，可以通过磁控溅射等物理气相沉积方法在栅绝缘层上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成栅极金属图案，该栅极金属图案可以包括各薄膜晶体管的栅极以及栅线。该栅金属薄膜可以是Al、Cu、Mo、Ti或AlNd等材料形成的单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等材料形成的多层金属薄膜。
步骤S4b、在形成有栅极金属图案的衬底基板上形成层间绝缘层。
进一步的，可以在形成有栅极金属图案的衬底基板的整个表面，使用PECVD依次沉积SiO2薄膜和SiN薄膜，以形成层间绝缘层，并通过掩模和刻蚀工艺刻蚀层间绝缘层而形成第一接触孔和第二接触孔。
步骤S5b、在形成有层间绝缘层的衬底基板上形成源漏金属图案。
可以采用磁控溅射工艺在层间绝缘层上沉积包含一种或多种低电阻材料的源漏金属薄膜，并通过掩模和刻蚀工艺形成源漏金属图案，该源漏金属图案可以包括各薄膜晶体管的第一极和第二极，以及数据线。其中，第一极可以通过第一接触孔与有源层接触，第二极可以通过第二接触与有源层接触。
形成该源漏金属薄膜的材料可以包括钼、钼铌合金、铝、铝钕合金、钛和铜中的任意一种。源漏金属薄膜的厚度范围可以为20至30nm。在此需要说明的是，源漏金属薄膜可以为单层金属膜层，也可以为缓冲金属/金属的双层金属膜层，或者还可以为缓冲金属/金属/缓冲金属的三层金属膜层。
进一步的，可以对完成上述步骤的衬底基板进行退火，退火温度为30至320℃，退火时长为30分钟(min)。在该步骤中，不仅可以使得晶体管的第一极和第二极的金属材料中的金属原子向有源层扩散，与形成有源层的氧化物半导体材料中的氧原子发生化学反应，以使该位置处的有源层材料失氧，即氧空位增多，同时自由电子也随之增多，从而使得该位置处的半导体材料呈现金属化(半导体)趋势。由此可增加晶体管的第一极和第二极与有源层之间的欧姆接触；同时还可以增强有源层沟道区的稳定性，使得氧化物薄膜晶体管的性能更好。
步骤S6b、在形成有源漏金属图案的衬底基板上形成钝化层。
最后，可以使用PECVD在形成有源漏金属图案的衬底基板的整个表面沉积一层SiN薄膜，通过掩模和刻蚀工艺形成包含过孔的钝化层。然后使用快速热退火或热处理炉退火进行氢化工艺，修复多晶硅有源层内部和界面的缺陷。其中，该过孔可以为位于衬底基板的显示区域内，用于连接驱动晶体管的第二极和像素电极的过孔。由此，即可完成静电保护电路的制造。
进一步的，对于衬底基板的显示区域，还可以再一次通过掩模工艺，在钝化层之上形成具有与该钝化层的过孔相同的过孔的有机平坦化层，填充器件表面的低凹形成平坦表面。之后，使用磁控溅射在有机平坦化层和过孔之上沉积一层透明导电薄膜，通过光刻工艺刻蚀该透明导电薄膜，从而在过孔及部分有机平坦化层之上形成像素区域的像素电极。然后在有机平坦化层及像素电极上涂覆一层与有机平坦化层类似的光敏有机材料，通过一道掩模工艺暴露出像素电极的部分区域，形成像素定义层，像素定义层覆盖有机平坦化层及部分的像素电极区域。其中，该透明导电薄膜可以是单层的氧化物导电薄膜，如ITO(氧化铟锡)或IZO(氧化铟锌)等，也可以是ITO(氧化铟锡)/Ag/ITO、IZO(氧化铟锌)/Ag等复合薄膜。
本公开实施例还提供一种显示装置，该显示装置可以包括如图10至图13任一所示的阵列基板。该显示装置可以为：液晶面板、电子纸、OLED面板、 AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (19)

  1. 一种静电保护电路，所述静电保护电路包括：第一薄膜晶体管、第二薄膜晶体管和静电防护线；
    所述第一薄膜晶体管的栅极和第二极均与信号线连接，所述第一薄膜晶体管的第一极与所述静电防护线连接；
    所述第二薄膜晶体管的栅极和第二极均与所述静电防护线连接，所述第二薄膜晶体管的第一极与信号线连接；
    其中，每个薄膜晶体管均为氧化物薄膜晶体管，每个薄膜晶体管的沟道的长宽比大于或等于长宽比阈值，所述长宽比阈值大于1。
  2. 根据权利要求1所述的静电保护电路，所述长宽比阈值为5。
  3. 根据权利要求1或2所述的静电保护电路，每个薄膜晶体管的沟道的长度方向平行于所述信号线的延伸方向。
  4. 根据权利要求1至3任一所述的静电保护电路，
    每个薄膜晶体管的栅极均为条状结构，且所述条状结构的长度方向平行于所述信号线的延伸方向。
  5. 根据权利要求1至4任一所述的静电保护电路，
    所述第一薄膜晶体管和所述第二薄膜晶体管的排列方向平行于所述信号线的延伸方向。
  6. 根据权利要求1至5任一所述的静电保护电路，所述信号线为沿第一方向延伸的数据线；所述静电防护线包括：沿第二方向延伸且相互平行的第一放电线和第二放电线，以及用于连接所述第一放电线和所述第二放电线的连接线，所述第二方向与所述第一方向相交；
    所述第一薄膜晶体管和所述第二薄膜晶体管设置在所述第一放电线和所述第二放电线之间，且所述第一薄膜晶体管的第一极与所述第一放电线连接，所 述第二薄膜晶体管的栅极和第二极与所述第二放电线连接。
  7. 根据权利要求6所述的静电保护电路，所述第一薄膜晶体管的第二极和所述第二薄膜晶体管的第一极为一体结构，且所述第一薄膜晶体管的栅极通过过孔与所述一体结构连接。
  8. 根据权利要求1至5任一所述的静电保护电路，所述信号线为沿第二方向延伸的栅线，所述静电防护线沿第一方向延伸，且所述第二方向与所述第一方向相交。
  9. 根据权利要求8所述的静电保护电路，所述静电保护电路还包括：第三薄膜晶体管和第四薄膜晶体管；
    所述第三薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第三薄膜晶体管的第一极与所述静电防护线连接；所述第四薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第四薄膜晶体管的第一极与所述信号线连接；
    所述第一薄膜晶体管和所述第二薄膜晶体管沿第一轴线排列，所述第三薄膜晶体管和所述第四薄膜晶体管沿第二轴线排列，所述第一轴线与所述第二轴线均与所述第一方向相交，且不共线。
  10. 根据权利要求9所述的静电保护电路，所述第一轴线与所述第二轴线均平行于所述第二方向。
  11. 根据权利要求9或10所述的静电保护电路，
    所述第一薄膜晶体管的第一极、所述第二薄膜晶体管的第一极、所述第三薄膜晶体管的第二极以及所述第四薄膜晶体管的第二极为一体结构，且所述第三薄膜晶体管的栅极和所述第四薄膜晶体管的栅极通过过孔与所述一体结构连接。
  12. 根据权利要求9至11任一所述的静电保护电路，
    所述第三薄膜晶体管和所述第四薄膜晶体管的栅极为一体结构。
  13. 根据权利要求6至12任一所述的静电保护电路，所述第二方向垂直于所述第一方向。
  14. 根据权利要求1至8任一所述的静电保护电路，所述静电保护电路还包括：第三薄膜晶体管和第四薄膜晶体管中的至少一个；
    所述第三薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第三薄膜晶体管的第一极与所述静电防护线连接；
    所述第四薄膜晶体管的栅极和第二极均与所述第一薄膜晶体管的第一极连接，所述第四薄膜晶体管的第一极与所述信号线连接。
  15. 根据权利要求1至15任一所述的静电保护电路，
    每个薄膜晶体管的沟道呈蛇形、锯齿形或者弧形。
  16. 一种阵列基板，所述阵列基板包括：
    信号线，以及与所述信号线连接的如权利要求1至15任一所述的静电保护电路。
  17. 根据权利要求16所述的阵列基板，所述信号线为沿第一方向延伸的数据线，且所述阵列基板包括多条数据线；所述静电防护线包括：沿第二方向延伸且平行排列的三条放电线，以及用于连接所述三条放电线的连接线，所述第二方向与所述第一方向相交；
    每条数据线所连接的静电保护电路，均与相邻一条数据线所连接的静电保护电路位于同一列；
    位于同一列的两个静电保护电路中，其中一个静电保护电路位于所述三条放电线中第一条放电线和第二条放电线之间，另一个静电保护电路位于所述三条放电线中第二条放电线和第三条放电线之间，且位于同一列的两个静电保护电路中第二薄膜晶体管的栅极和第二极均与所述第二条放电线连接。
  18. 根据权利要求16所述的阵列基板，所述信号线为沿第二方向延伸的栅线，且所述阵列基板包括多条栅线；所述静电防护线沿第一方向延伸，所述第二方向垂直于所述第一方向；
    所述多条栅线中每相邻两条栅线之间设置有其中一条栅线所连接的静电保护电路。
  19. 一种显示装置，所述显示装置包括：如权利要求16至18任一所述的阵列基板。
PCT/CN2019/091913 2018-07-25 2019-06-19 静电保护电路、阵列基板及显示装置 WO2020019908A1 (zh)

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