WO2020164438A1 - 触控显示面板和显示装置 - Google Patents

触控显示面板和显示装置 Download PDF

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Publication number
WO2020164438A1
WO2020164438A1 PCT/CN2020/074481 CN2020074481W WO2020164438A1 WO 2020164438 A1 WO2020164438 A1 WO 2020164438A1 CN 2020074481 W CN2020074481 W CN 2020074481W WO 2020164438 A1 WO2020164438 A1 WO 2020164438A1
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WIPO (PCT)
Prior art keywords
touch
test switch
test
data
switch
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PCT/CN2020/074481
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English (en)
French (fr)
Inventor
龙春平
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京东方科技集团股份有限公司
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Priority to US16/963,723 priority Critical patent/US11366548B2/en
Publication of WO2020164438A1 publication Critical patent/WO2020164438A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to a touch display panel and a display device.
  • the in-cell touch screen has been used more and more widely due to its simple structure, fast response speed and high sensitivity, etc., especially in occasions with stricter volume requirements such as portable mobile devices.
  • a plurality of small blocks divided into the common electrode layer in the touch operation area are generally used to form a touch electrode matrix.
  • test signal lines In the test structure of the self-capacitance in-cell touch screen, multiple test signal lines, odd-type touch electrodes and even-type touch electrodes are provided. Among them, the test signal lines are used to provide different types of thin film transistors during the test. Test voltage value, part of the test signal line provides a higher test voltage value for the odd-type touch electrode (for example, the higher test voltage value is 5V), and the other part of the test signal line provides a lower test voltage value for the even-type touch electrode ( For example, the lower test voltage value is 1V), so as to adjust the voltage difference between different test signal lines and clearly distinguish between bright and dark areas.
  • the touch electrode is the common electrode of the display area
  • applying a voltage to the touch electrode can change the liquid crystal deflection state of the corresponding display area and thus change the light transmittance of the area.
  • the higher the applied voltage the higher the brightness of the display area, and the lower the application.
  • the voltage value is the opposite.
  • the display area is divided into a contrasting darker display area and a brighter display area for detection, and short-circuit/open-circuit defects can be judged based on the pattern.
  • the present disclosure provides a touch display panel, including a base substrate, a plurality of first touch electrodes, a plurality of second touch electrodes, a plurality of first leads, and a plurality of A second lead, a number of first data lines, and a number of second data lines, each of the first leads is connected to one of the first touch electrodes, and each of the second leads is connected to one of the second touch electrodes,
  • the base substrate includes a display area and a non-display area
  • the touch display panel further includes: a plurality of first touch test switches, a plurality of second touch test switches, and a first test signal line located in the non-display area , The second test signal line, one or two test control gate lines, a number of first data test switches, and a number of second data test switches;
  • first lead and the first data line share the first test signal line
  • second lead and the second data line share the second test signal line
  • the first touch test switch used to control the first lead and the first data test switch used to control the first data line are not turned on at the same time, and are used to control all of the second lead
  • the second touch test switch and the second data test switch for controlling the second data line are not turned on at the same time.
  • the two test control gate lines include a first test control gate line and a second test control gate line;
  • the first end of the first touch test switch is electrically connected to the first lead, the second end of the first touch test switch is electrically connected to the first test signal line, and the first touch The control terminal of the test switch is electrically connected to the first test control gate line;
  • the first end of the second touch test switch is electrically connected to the second lead, the second end of the second touch test switch is electrically connected to the second test signal line, and the second touch The control terminal of the test switch is electrically connected to the first test control gate line;
  • the first end of the first data test switch is electrically connected to the first data line
  • the second end of the first data test switch is electrically connected to the first test signal line
  • the first data test switch The control terminal is electrically connected to the second test control gate line
  • the first end of the second data test switch is electrically connected to the second data line
  • the second end of the second data test switch is electrically connected to the second test signal line
  • the second data test switch The control terminal of is electrically connected to the second test control gate line.
  • the first touch electrodes and the second touch electrodes are alternately arranged along a first direction, and the first touch electrodes and the second touch electrodes are perpendicular to the The first direction and the second direction are alternately arranged.
  • the display area includes a plurality of common electrodes arranged in blocks, and a plurality of sub-pixel units arranged in an array, and each of the sub-pixel units includes a thin film transistor;
  • the first touch electrode multiplexes part of the common electrode, and the second touch electrode multiplexes the remaining portion of the common electrode.
  • the gates of the first touch test switch, the second touch test switch, the first data test switch and the second data test switch and the gate of the thin film transistor is located on the same layer;
  • the sources of the first touch test switch, the second touch test switch, the first data test switch, and the second data test switch are located on the same layer as the source of the thin film transistor;
  • the drains of the first touch test switch, the second touch test switch, the first data test switch and the second data test switch are located on the same layer as the drain of the thin film transistor.
  • the touch display panel includes a test control gate line
  • the first end of the first touch test switch is electrically connected to the first lead, the second end of the first touch test switch is electrically connected to the first test signal line, and the first touch The control terminal of the test switch is electrically connected to the test control grid line;
  • the first end of the second touch test switch is electrically connected to the second lead, the second end of the second touch test switch is electrically connected to the second test signal line, and the second touch The control terminal of the test switch is electrically connected to the test control grid line;
  • the first end of the first data test switch is electrically connected to the first data line
  • the second end of the first data test switch is electrically connected to the first test signal line
  • the first data test switch The control terminal is electrically connected to the test control grid line
  • the first end of the second data test switch is electrically connected to the second data line
  • the second end of the second data test switch is electrically connected to the second test signal line
  • the second data test switch The control terminal is electrically connected to the test control grid line
  • the first data test switch and the second data test switch are in the test Closed under the control of the control gate line; or, when the first touch test switch and the second touch test switch are closed under the control of the test control gate line, the first data test switch and the The second data test switch is turned on under the control of the test control gate line.
  • the first touch test switch and the second touch test switch are N-type thin film transistors, and the first data test switch and the second data test switch are P-type thin film transistors. Transistor; or
  • the first touch test switch and the second touch test switch are P-type thin film transistors, and the first data test switch and the second data test switch are N-type thin film transistors.
  • the touch display panel further includes: a plurality of first auxiliary touch test switches, a plurality of second auxiliary touch test switches, auxiliary test control gate lines, a plurality of first auxiliary data test switches, and Several second auxiliary data test switches, of which,
  • the control terminals of the first auxiliary touch test switch, the second auxiliary touch test switch, the first auxiliary data test switch, and the second auxiliary data test switch are electrically connected to the auxiliary test control gate line ;
  • the first auxiliary touch test switch and the first touch test switch are connected in series, and the first end of the first auxiliary touch test switch and the first touch test switch connected in series are electrically connected to The first lead, the second end of the first auxiliary touch test switch and the first touch test switch connected in series are electrically connected to the first test signal line;
  • the second auxiliary touch test switch and the second touch test switch are connected in series, and the first end of the second auxiliary touch test switch and the second touch test switch connected in series are electrically connected to The second lead, the second end of the second auxiliary touch test switch and the second touch test switch connected in series are electrically connected to the second test signal line;
  • the first auxiliary data test switch is connected in series with the first data test switch, and the first end of the first auxiliary data test switch and the first data test switch connected in series are electrically connected to the first A data line, the second end of the first auxiliary data test switch and the first data test switch connected in series are electrically connected to the first test signal line;
  • the second auxiliary data test switch is connected in series with the second data test switch, and the first end of the second auxiliary data test switch and the second data test switch connected in series is electrically connected to the second A data line, the second end of the second auxiliary data test switch and the second data test switch connected in series are electrically connected to the second test signal line.
  • the first touch electrodes and the second touch electrodes are alternately arranged along a first direction, and the first touch electrodes and the second touch electrodes are perpendicular to the The first direction and the second direction are alternately arranged.
  • the display area includes a plurality of common electrodes arranged in blocks, and a plurality of sub-pixel units arranged in an array, each of the sub-pixel units includes a thin film transistor;
  • the first touch electrode multiplexes part of the common electrode, and the second touch electrode multiplexes the remaining portion of the common electrode.
  • the gates of the first touch test switch, the second touch test switch, the first data test switch and the second data test switch and the gate of the thin film transistor is located on the same layer;
  • the sources of the first touch test switch, the second touch test switch, the first data test switch, and the second data test switch are located on the same layer as the source of the thin film transistor;
  • the drains of the first touch test switch, the second touch test switch, the first data test switch and the second data test switch are located on the same layer as the drain of the thin film transistor.
  • the present disclosure provides a display device including the touch display panel described in the first aspect.
  • FIG. 1 is a schematic diagram of the structure of odd-type touch electrodes and even-type touch electrodes in a touch display panel in the related art
  • FIG. 2 is a schematic diagram of the structure of a test circuit in a touch display panel in the related art
  • FIG. 3 is a test circuit diagram in the touch display panel of an embodiment of the disclosure.
  • FIG. 4 is a diagram of a test circuit in the touch display panel of an embodiment of the disclosure.
  • FIG. 5 is a test circuit diagram in the touch display panel of an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of the structure of fabricating a buffer layer, a polysilicon storage capacitor layer and an active layer on an insulating substrate;
  • FIG. 7 is a schematic diagram of the structure of fabricating photoresist on the substrate of FIG. 6;
  • FIG. 8 is a schematic diagram of the structure of fabricating a gate insulating layer and a gate electrode on the substrate of FIG. 7;
  • FIG. 9 is a schematic diagram of the structure of fabricating an interlayer insulating layer on the substrate of FIG. 8;
  • FIG. 10 is a schematic diagram of the structure of fabricating source and drain electrodes on the substrate of FIG. 9;
  • FIG. 11 is a schematic diagram of the structure of forming a passivation layer and a planarization layer on the substrate of FIG. 10;
  • FIG. 12 is a schematic diagram of the structure of fabricating pixel electrodes on the substrate of FIG. 11;
  • FIG. 13 is a schematic diagram of the structure of fabricating a pixel definition layer on the substrate of FIG. 12.
  • the present disclosure provides a touch display panel and a display device to solve the problem of large wiring space in the non-display area in the prior art and the inability to achieve a narrow frame.
  • the technical solutions provided in the present disclosure have at least the following advantages:
  • first touch test switches, second touch test switches, first data test switches, and second data test switches in the non-display area
  • the first touch test switch and the second touch test switch Share the same first test control gate line
  • the first data test switch and the second data test switch share the same second test control gate line
  • the first touch test switch and the first data test switch share the same first test signal line
  • the two touch test switches and the second data test switch share the same second test signal line, therefore, it is possible to save wiring space and achieve the technical purpose of a narrow frame; in addition, the above structure also reduces input signals and reduces power consumption.
  • FIGS. 1 and 2 show schematic diagrams of the structure of a touch test circuit in a touch display panel in the related art.
  • the touch display panel includes first touch electrodes 1 (also called odd-type touch electrodes) and second touch electrodes 2 (also called even-type touch electrodes) arranged alternately with each other.
  • a touch electrode 1 and a second touch electrode 2 multiplex the common electrode of the touch display panel, and each of the first touch electrode 1 and the second touch electrode 2 is connected with a touch electrode lead 3.
  • a higher test voltage value is provided to the first touch electrode 1, while a lower test voltage value is provided to the second touch electrode 2 to adjust the touch electrode lead 3
  • the voltage difference clearly distinguishes light and dark areas.
  • the voltage value for providing a lower test voltage value to the second touch electrode 2 is 1V
  • the voltage value for providing a higher test voltage value to the first touch electrode 1 is 5V. Since the first touch electrode 1 and the second touch electrode 2 are the common electrodes of the display area, applying a voltage to the touch electrodes can change the liquid crystal state of the corresponding display area, thereby changing the light transmittance of the area.
  • Applying a lower voltage value corresponds to a higher brightness of the display area.
  • the display area is divided into a darker area and a brighter area with sharp contrast for detection. According to the pattern, short circuits and open circuits can be judged.
  • embodiments of the present disclosure provide a touch display panel.
  • some of the reference signs in the following embodiments are the same as those in FIGS. 1 and 2.
  • the touch display panel in this embodiment includes a base substrate 200, a number of first touch electrodes 1, a number of second touch electrodes 2, a number of first leads 31, and A number of second leads 32, a number of first data lines 9 and a number of second data lines 10, each first lead 31 is connected to a first touch electrode 1, and each second lead 32 is connected to a second touch electrode 2,
  • the base substrate 200 includes a display area 201 and a non-display area 202.
  • the arrangement of the display area 201 and the non-display area 202 is the same as that of the prior art, which will not be repeated here.
  • the touch display panel further includes: a plurality of first touch test switches 4, a plurality of second touch test switches 5, a first test signal line 6, and a second test signal line located in the non-display area 202 7.
  • the first test control gate line 8 the second test control gate line 13, a number of first data test switches 11, and a number of second data test switches 12.
  • first lead 31 and the first data line 9 share the first test signal line 6, the second lead 32 and the second data line 10 share the second test signal line 7; and the first contact for controlling the first lead 31
  • the control test switch 4 and the first data test switch 11 for controlling the first data line 9 are not turned on at the same time, the second touch test switch 5 for controlling the second lead 32 and the second touch test switch 5 for controlling the second data line 10
  • the second data test switch 12 is not turned on at the same time.
  • the first end of the first touch test switch 4 is electrically connected to the first lead 31, the second end is electrically connected to the first test signal line 6, and the control end is electrically connected to the first test control gate line 8.
  • the first end of the second touch test switch 5 is electrically connected to the second lead 32, the second end is electrically connected to the second test signal line 7, and the control end is electrically connected to the first test control gate line 8.
  • the first end of the first data test switch 11 is electrically connected to the first data line 9, the second end is electrically connected to the first test signal line 6, and the control end is electrically connected to the second test control gate line 13.
  • the first end of the second data test switch 12 is electrically connected to the second data line 10, the second end is electrically connected to the second test signal line 7, and the control end is electrically connected to the second test control gate line 13.
  • this embodiment is provided with a number of first touch test switches, second touch test switches, first data test switches, and second data test switches in the non-display area, and the first touch test switch and the second touch test switch
  • the switches share the same first test control gate line
  • the first data test switch and the second data test switch share the same second test control gate line
  • the first touch test switch and the first data test switch share the same first test signal line
  • the second touch test switch and the second data test switch share the same second test signal line. Therefore, it is possible to save wiring space and achieve the technical purpose of a narrow frame; in addition, the above structure also reduces input signals and reduces power consumption.
  • the first touch test switch 4 and the second touch test switch 5 are N-type thin film transistors; the first data test switch 11 and the second data test switch 12 are P-type thin film transistors.
  • the voltage signal input by the control gate line 8 is 0V
  • the first touch test switch 4 and the second touch test switch 5 are all turned off.
  • the voltage signal input by the second test control gate line 13 is 0V
  • the first data test switch 11 and the second data test switch 12 are all turned off.
  • the first touch test switch 4 and the second touch test switch 5 are turned on; when the voltage input by the first test control gate line 8 When the signal is -5V, the first touch test switch 4 and the second touch test switch 5 are turned off.
  • the first data test switch 11 and the second data test switch 12 are turned on; when the voltage input by the second test control gate line 13 When the signal is 5V, the first data test switch 11 and the second data test switch 12 are turned off.
  • the first touch test switch 4 and the second touch test switch 5 used to detect touch and the first data test switch 11 and the second data test switch 12 used to detect data lines can be arbitrarily selected from P-type thin film transistors and N Type thin film transistors reduce the manufacturing cost and difficulty.
  • the first touch electrodes 1 and the second touch electrodes 2 are alternately arranged along the first direction, and the first touch electrodes 1 and the second touch electrodes 2 are also arranged along the first direction perpendicular to the first direction.
  • the two directions are set alternately.
  • the first direction may be a horizontal direction and the second direction may be a vertical direction; or the first direction may be a vertical direction and the second direction may be a horizontal direction.
  • first touch electrodes 1 and the second touch electrodes 2 are alternately arranged in different directions, when different voltages are applied to the first touch electrodes 1 and the second touch electrodes 2, touch detection can be performed on the display panel.
  • the display area includes several common electrodes arranged in blocks, and several sub-pixel units (not shown in the figure) arranged in an array, and each sub-pixel unit includes a thin film transistor (not shown in the figure). ).
  • the first touch electrode multiplexes part of the common electrode, and the second touch electrode multiplexes the rest of the common electrode.
  • the gates of the first touch test switch 4, the second touch test switch 5, the first data test switch 11, and the second data test switch 12 and the gates of the thin film transistors included in the sub-pixel unit The poles are located on the same floor.
  • the sources of the first touch test switch 4, the second touch test switch 5, the first data test switch 11, and the second data test switch 12 are located on the same layer as the source of the thin film transistor included in the sub-pixel unit.
  • the drains of the first touch test switch 4, the second touch test switch 5, the first data test switch 11, and the second data test switch 12 are located on the same layer as the drains of the thin film transistors included in the sub-pixel unit. Can save production costs.
  • FIG. 4 also discloses another touch display panel of the present disclosure, including a base substrate 200, a plurality of first touch electrodes 1, a plurality of second touch electrodes 2, and a plurality of A first lead 31, a number of second leads 32, a number of first data lines 9 and a number of second data lines 10, each first lead 31 is connected to a first touch electrode 1, and each second lead 32 is connected to a second
  • the base substrate 200 includes a display area 201 and a non-display area 202.
  • the arrangement of the display area 201 and the non-display area 202 is the same as that of the prior art, and will not be repeated here.
  • the touch display panel further includes: a plurality of first touch test switches 4, a plurality of second touch test switches 5, a first test signal line 6, and a second test signal line located in the non-display area 202 7.
  • a test control gate line 15, a plurality of first data test switches 11 and a plurality of second data test switches 12.
  • first lead 31 and the first data line 9 share the first test signal line 6, the second lead 32 and the second data line 10 share the second test signal line 7; and the first contact for controlling the first lead 31
  • the control test switch 4 and the first data test switch 11 for controlling the first data line 9 are not turned on at the same time, the second touch test switch 5 for controlling the second lead 32 and the second touch test switch 5 for controlling the second data line 10
  • the second data test switch 12 is not turned on at the same time.
  • the first end of the first touch test switch 4 is electrically connected to the first lead 31, the second end is electrically connected to the first test signal line 6, and the control end is electrically connected to the test control gate line 15.
  • the first end of the second touch test switch 5 is electrically connected to the second lead 32, the second end is electrically connected to the second test signal line 7, and the control end is electrically connected to the test control gate line 15.
  • the first end of the first data test switch 11 is electrically connected to the first data line 9, the second end is electrically connected to the first test signal line 6, and the control end is electrically connected to the test control gate line 15.
  • the first end of the second data test switch 12 is electrically connected to the second data line 10, the second end is electrically connected to the second test signal line 7, and the control end is electrically connected to the test control gate line 15.
  • the first touch test switch 4 and the second touch test switch 5 are turned on under the control of the test control gate line 15
  • the first data test switch 11 and the second data test switch 12 are connected to the test control gate line 15. Closed under control; or, when the first touch test switch 4 and the second touch test switch 5 are closed under the control of the test control gate line 15, the first data test switch 11 and the second data test switch 12 are in the test control gate Line 15 is turned on under the control.
  • the first touch test switch 4 and the second touch test switch 5 are N-type thin film transistors, and the first data test switch 11 and the second data test switch 12 are P-type thin film transistors.
  • the first touch test switch 4 and the second touch test switch 5 are P-type thin film transistors, and the first data test switch 11 and the second data test switch 12 are N-type thin film transistors.
  • the first touch test switch 4 and the second touch test switch 5 are N-type thin film transistors; the first data test switch 11 and the second data test switch 12 are P-type thin film transistors.
  • the voltage signal input from the line 15 is 0V
  • the first touch test switch 4 and the second touch test switch 5 are all turned off
  • the first data test switch 11 and the second data test switch 12 are all turned off.
  • the voltage signal input by the test control gate line 15 is 5V, turn on the first touch test switch 4 and the second touch test switch 5; when the voltage signal input by the test control gate line 15 is -5V, turn off the first The touch test switch 4 and the second touch test switch 5.
  • test control gate line 15 When the voltage signal input by the test control gate line 15 is -5V, turn on the first data test switch 11 and the second data test switch 12; when the voltage signal input by the test control gate line 15 is 5V, turn off the first data test Switch 11 and the second data test switch 12.
  • the touch display panel of the embodiment of the present disclosure further includes: a plurality of first auxiliary touch test switches 41, a plurality of second auxiliary touch test switches 51, and an auxiliary test control grid Line 14, a number of first auxiliary data test switches 111 and a number of second auxiliary data test switches 121.
  • the control ends of the first auxiliary touch test switch 41, the second auxiliary touch test switch 51, the first auxiliary data test switch 111 and the second auxiliary data test switch 121 are electrically connected to the auxiliary test control gate line 14.
  • the first auxiliary touch test switch 41 is connected in series with the first touch test switch 4, the first terminal connected in series is electrically connected to the first lead 31, and the second terminal is electrically connected to the first test signal line 6.
  • the second auxiliary touch test switch 51 and the second touch test switch 5 are connected in series, the first end of the series connection is electrically connected to the second lead 32, and the second end is electrically connected to the second test signal line 7.
  • the first auxiliary data test switch 111 is connected in series with the first data test switch 11, the first terminal connected in series is electrically connected to the first data line 9, and the second terminal is electrically connected to the first test signal line 6.
  • the second auxiliary data test switch 121 is connected in series with the second data test switch 12, the first terminal connected in series is electrically connected to the second data line 10, and the second terminal is electrically connected to the second test signal line 7.
  • the first touch test switch 4 is connected in series with a first auxiliary touch test switch 41
  • the second touch test switch 5 is connected in series with a second auxiliary touch test switch 51
  • the first data test switch 11 is connected in series with a first auxiliary touch test switch.
  • Auxiliary data test switch 111, second data test switch 12 is connected in series with a second auxiliary data test switch 121, first auxiliary touch test switch 41, second auxiliary touch test switch 51, first auxiliary data test switch 111 and second auxiliary data test switch
  • the auxiliary data test switch 121 can be an N-type thin film transistor or a P-type thin film transistor.
  • the auxiliary test control gate line 14 is used to completely turn off the first auxiliary touch test switch 41 and the second auxiliary touch test when not testing.
  • the switch 51, the first auxiliary data test switch 111 and the second auxiliary data test switch 121 prevent the leakage current from increasing. That is, the auxiliary test control gate line signal of the N-type thin film transistor is completely turned off when the signal is -5V, and the auxiliary test control gate line signal of the P-type thin film transistor is completely turned off when the signal is 5V, which is relative to the 0V turn-off voltage of the test control gate line. Turning off both the N-type thin film transistor and the P-type thin film transistor at the same time has lower leakage current.
  • auxiliary test control gate line 14 is also provided in the display panel, it is used to completely turn off the first auxiliary touch test switch 41, the second auxiliary touch test switch 51, the first auxiliary data test switch 111 and the second auxiliary touch test switch when not testing.
  • the second auxiliary data test switch 121 prevents the leakage current from increasing.
  • the first auxiliary touch test switch 41, the second auxiliary touch test switch 51, the first auxiliary data test switch 111, and the second auxiliary data test switch 121 are N-type thin film transistors.
  • the first auxiliary touch test switch 41, the second auxiliary touch test switch 51, the first auxiliary data test switch 111, and the second auxiliary data test switch 121 are P-type thin film transistors.
  • the first touch electrodes 1 and the second touch electrodes 2 are alternately arranged along the first direction, and the first touch electrodes 1 and the second touch electrodes 2 are also arranged along the first direction perpendicular to the first direction.
  • the two directions are set alternately.
  • the first direction may be a horizontal direction and the second direction may be a vertical direction; or the first direction may be a vertical direction and the second direction may be a horizontal direction.
  • first touch electrodes 1 and the second touch electrodes 2 are alternately arranged in different directions, different voltages can be applied to the first touch electrodes 1 and the second touch electrodes 2, thereby enabling touch detection on the display panel.
  • the display area includes several common electrodes arranged in blocks, and several sub-pixel units (not shown in the figure) arranged in an array, and each sub-pixel unit includes a thin film transistor (not shown in the figure). ).
  • the first touch electrode 1 multiplexes part of the common electrode, and the second touch electrode 2 multiplexes the rest of the common electrode.
  • the gates of the first touch test switch 4, the second touch test switch 5, the first data test switch 11, and the second data test switch 12 and the gates of the thin film transistors included in the sub-pixel unit The poles are located on the same floor.
  • the sources of the first touch test switch 4, the second touch test switch 5, the first data test switch 11, and the second data test switch 12 are located on the same layer as the source of the thin film transistor included in the sub-pixel unit.
  • embodiments of the present disclosure provide a display device, including the touch display panel of the first aspect. Since the display device in the second aspect includes the touch display panel in the first aspect, so that the display device has similar beneficial effects as the touch display panel, the details will not be repeated.
  • a silicon nitride (SiN) film and a silicon dioxide (SiO2) film are sequentially deposited on the entire insulating substrate 100 by plasma enhanced chemical vapor deposition (PECVD) to form silicon nitride and A buffer layer 101 made of silicon dioxide.
  • the insulating substrate 100 may be glass or a flexible substrate such as PI.
  • an amorphous silicon (a-Si) film is formed on the buffer layer 101 by using PECVD or other chemical or physical vapor deposition methods. Through laser annealing (ELA) or solid phase crystallization (SPC) methods, the a-Si is crystallized into a polysilicon film.
  • the polysilicon film that is not protected by the photoresist layer is etched by plasma to form the active polysilicon film.
  • the transistor channel in the active layer 103 is doped with low-concentration ions using an ion implantation process, and a conductive channel required by the thin film transistor is formed in the active layer 103.
  • a photoresist 104 composed of a photoresist material is formed on the active layer 103 by a mask process to protect the active layer 103 from ion implantation.
  • a high concentration ion implantation process is performed on the polysilicon storage capacitor layer 102 that is not protected by the photoresist 104 to convert the polysilicon storage capacitor layer 102 into a low-resistance doped polysilicon film.
  • FIGS. 8 to 13 since only the second plate of the capacitor composed of the gate insulating layer and the gate metal film is formed on the polysilicon storage capacitor layer 102, in FIGS. 8 to 13 The only subsequent photolithography process for the polysilicon storage capacitor layer 102 is no longer shown, that is, the photolithography process for forming the second plate of the capacitor.
  • the photoresist 104 on the active layer 103 is removed by a photoresist stripping process, and a SiO2 film or a composite film of SiO2 and SiN is deposited by PECVD.
  • the polysilicon storage capacitor layer 102, the active layer 103 and A gate insulating layer 105 is formed on the entire buffer layer 101.
  • one or more low-resistance metal material films are deposited on the gate insulating layer 105 by a physical vapor deposition method such as magnetron sputtering, and the gate 106 is formed by a photolithography process.
  • the gate metal film can be a single-layer metal film such as Al, Cu, Mo, Ti or AlNd, or a multi-layer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • the gate 106 is used as an ion implantation blocking layer, and the active layer 103 is ion-doped to form low-impedance source and drain electrode contact regions in the active layer 103 area not blocked by the gate.
  • a SiO2 film and a SiN film are sequentially deposited using PECVD to form an interlayer insulating layer 107, and the interlayer insulating layer 107 is etched through a mask and etching process to form a source electrode and Drain electrode contact hole.
  • one or more low-resistance metal films are deposited on the interlayer insulating layer 107 and the source and drain contact holes using magnetron sputtering, and the source 108 and the drain are formed by masking and etching processes.
  • the drain 113, the source 108 and the drain 113 form an ohmic contact with the active layer 103 through the contact hole.
  • rapid thermal annealing or thermal annealing furnace to activate the doped ions in the active layer 103, an effective conductive channel is formed in the active layer 103 under the gate 106.
  • the source/drain metal film can be a single-layer metal film such as Al, Cu, Mo, Ti or AlNd, or a multilayer metal film such as Mo/Al/Mo or Ti/Al/Ti.
  • a layer of SiN film is deposited on the entire surface including the source electrode 108 and the drain electrode 113 using PECVD, and a passivation layer 109 including via holes is formed through a mask and etching process.
  • the hydrogenation process is performed using rapid thermal annealing or heat treatment furnace annealing to repair defects in the interior and interface of the active layer 103.
  • an organic planarization layer 110 having the same via holes as the via holes is formed on the SiN passivation layer 109, and the depressions on the device surface are filled to form a flat surface.
  • the transparent conductive film can be a single-layer oxide conductive film, such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), etc., or it can be ITO (Indium Tin Oxide)/Ag /ITO, IZO (Indium Zinc Oxide)/Ag and other composite films.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • a layer of photosensitive organic material similar to the planarization layer 110 is coated on the planarization layer 110 and the pixel electrode 112, and a part of the pixel electrode 112 is exposed through the last mask process to form the pixel definition shown in FIG. 13 ⁇ 116.
  • the pixel definition layer 116 covers the planarization layer 110 and part of the pixel electrode 112 area.
  • Table 1 respectively shows the materials and corresponding thicknesses of the main coatings in the touch display panel in this embodiment. However, for those skilled in the art, other suitable materials and thicknesses can be selected according to actual needs.
  • Thickness (Angstrom) Insulating substrate PI 90000 The buffer layer SiNx/SiOx 5000 Gate insulating layer SiOx 1200 Grid Mo 2500 Interlayer insulation SiNx/SiOx 4500 Source drain Ti/Al/Ti 8000 Passivation layer SiNx 2500 Planarization layer PI 12000 Pixel electrode ITO/Ag/ITO 1000
  • this embodiment is provided with a number of first touch test switches, second touch test switches, first data test switches, and second data test switches in the non-display area, and the first touch test switch and the second touch test switch
  • the switches share the same first test control gate line
  • the first data test switch and the second data test switch share the same second test control gate line
  • the first touch test switch and the first data test switch share the same first test signal line
  • the second touch test switch and the second data test switch share the same second test signal line. Therefore, it is possible to save wiring space and achieve the technical purpose of a narrow frame; in addition, the above structure also reduces input signals and reduces power consumption.

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Abstract

一种触控显示面板，其包括传统触控显示面板的部件外，还包括：第一引线（31）和第一数据线（9）共用第一测试信号线（6），第二引线（32）和第二数据线（10）共用第二测试信号线（7）；以及用于控制第一引线（31）的第一触控测试开关（4）和用于控制第一数据线（9）的第一数据测试开关（11）不同时接通，用于控制第二引线（32）的第二触控测试开关（5）和用于控制第二数据线（10）的第二数据测试开关（12）不同时接通。

Description

触控显示面板和显示装置
相关申请的交叉引用
本申请要求于2019年2月14日提交的中国专利申请第201920200963.4号的优先权，该申请的公开通过引用被全部合并于此。
技术领域
本公开涉及触控显示面板和显示装置。
背景技术
目前，内嵌式触摸屏因其具有结构简单、响应速度快以及灵敏度高等优点而获得了越来越广泛的应用，特别是在便携式移动设备等对体积要求较严格的场合中。为了进一步缩小便携设备的尺寸，现有技术中一般利用触控操作区域内的公共电极层分割成的多个小区块来形成触摸电极矩阵。
在自电容内嵌式触摸屏的测试结构中，设置了多条测试信号线、奇型触摸电极和偶型触摸电极，其中，测试信号线用于在测试过程中分别向相对应的薄膜晶体管提供不同测试电压值，一部分测试信号线为奇型触控电极提供较高测试电压值(例如，较高测试电压值为5V)，另一部分测试信号线为偶型触控电极提供较低测试电压值(例如，较低测试电压值为1V)，从而调整不同测试信号线间的电压差，明显区分明暗区域。由于触摸电极是显示区域的公共电极，对触摸电极施以电压可改变对应显示区域液晶偏转状态进而改变该区域的透光率，施以电压值越高对应显示区域亮度越高，施以较低电压值则相反，显示区域分为对比鲜明的较暗显示区与较亮显示区以供检测，根据图案即可判断短路/断路等不良。
发明内容
本公开主要提供如下技术方案：
在第一方面中，本公开提供了一种触控显示面板，包括衬底基板，位于所述衬底基板上方的若干第一触控电极、若干第二触控电极、若干第一引线、若干第二引线、若干第一数据线和若干第二数据线，每一所述第一引线连接一所述第一触控电极，每一所述第二引线连接一所述第二触控电极，所述衬底基板包括显示区和非显示区，其 中，触控显示面板还包括：位于所述非显示区的若干第一触控测试开关、若干第二触控测试开关、第一测试信号线、第二测试信号线、一条或两条测试控制栅线、若干第一数据测试开关、若干第二数据测试开关；
其中，所述第一引线和所述第一数据线共用所述第一测试信号线，所述第二引线和所述第二数据线共用所述第二测试信号线；以及
用于控制所述第一引线的所述第一触控测试开关和用于控制所述第一数据线的所述第一数据测试开关不同时接通，用于控制所述第二引线的所述第二触控测试开关和用于控制所述第二数据线的所述第二数据测试开关不同时接通。
根据本公开的一些实施例，在所述触控显示面板包括两条测试控制栅线的情况下，所述两条测试控制栅线包括第一测试控制栅线和第二测试控制栅线；
所述第一触控测试开关的第一端电连接至所述第一引线，所述第一触控测试开关的第二端电连接至所述第一测试信号线，所述第一触控测试开关的控制端电连接至所述第一测试控制栅线；
所述第二触控测试开关的第一端电连接至所述第二引线，所述第二触控测试开关的第二端电连接至所述第二测试信号线，所述第二触控测试开关的控制端电连接至所述第一测试控制栅线；
所述第一数据测试开关的第一端电连接至所述第一数据线，所述第一数据测试开关的第二端电连接至所述第一测试信号线，所述第一数据测试开关的控制端电连接至所述第二测试控制栅线；
所述第二数据测试开关的第一端电连接至所述第二数据线，所述第二数据测试开关的第二端电连接至所述第二测试信号线，所述第二数据测试开关的控制端电连接至所述第二测试控制栅线。
根据本公开的一些实施例，所述第一触控电极和所述第二触控电极沿第一方向交替设置，所述第一触控电极和所述第二触控电极沿垂直于所述第一方向的第二方向交替设置。
根据本公开的一些实施例，所述显示区包括分块设置的若干公共电极，以及阵列排列的若干亚像素单元，每一所述亚像素单元包括一薄膜晶体管；
所述第一触控电极复用部分所述公共电极，所述第二触控电极复用其余部分所述公共电极。
根据本公开的一些实施例，所述第一触控测试开关、所述第二触控测试开关、所 述第一数据测试开关和所述第二数据测试开关的栅极与所述薄膜晶体管的栅极位于同一层；
所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的源极与所述薄膜晶体管的源极位于同一层；
所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的漏极与所述薄膜晶体管的漏极位于同一层。
根据本公开的一些实施例，所述触控显示面板包括一条测试控制栅线；
所述第一触控测试开关的第一端电连接至所述第一引线，所述第一触控测试开关的第二端电连接至所述第一测试信号线，所述第一触控测试开关的控制端电连接至所述测试控制栅线；
所述第二触控测试开关的第一端电连接至所述第二引线，所述第二触控测试开关的第二端电连接至所述第二测试信号线，所述第二触控测试开关的控制端电连接至所述测试控制栅线；
所述第一数据测试开关的第一端电连接至所述第一数据线，所述第一数据测试开关的第二端电连接至所述第一测试信号线，所述第一数据测试开关的控制端电连接至所述测试控制栅线；
所述第二数据测试开关的第一端电连接至所述第二数据线，所述第二数据测试开关的第二端电连接至所述第二测试信号线，所述第二数据测试开关的控制端电连接至所述测试控制栅线；
所述第一触控测试开关和所述第二触控测试开关在所述测试控制栅线的控制下导通时，所述第一数据测试开关和所述第二数据测试开关在所述测试控制栅线的控制下闭合；或，所述第一触控测试开关和所述第二触控测试开关在所述测试控制栅线的控制下闭合时，所述第一数据测试开关和所述第二数据测试开关在所述测试控制栅线的控制下导通。
根据本公开的一些实施例，所述第一触控测试开关和所述第二触控测试开关为N型薄膜晶体管，所述第一数据测试开关和所述第二数据测试开关为P型薄膜晶体管；或者
所述第一触控测试开关和所述第二触控测试开关为P型薄膜晶体管，所述第一数据测试开关和所述第二数据测试开关为N型薄膜晶体管。
根据本公开的一些实施例，所述触控显示面板还包括：若干第一辅助触控测试开 关、若干第二辅助触控测试开关、辅助测试控制栅线、若干第一辅助数据测试开关、以及若干第二辅助数据测试开关，其中，
所述第一辅助触控测试开关、所述第二辅助触控测试开关、所述第一辅助数据测试开关和所述第二辅助数据测试开关的控制端电连接至所述辅助测试控制栅线；
所述第一辅助触控测试开关与所述第一触控测试开关串联连接，串联连接后的所述第一辅助触控测试开关和所述第一触控测试开关的第一端电连接至所述第一引线，串联连接后的所述第一辅助触控测试开关和所述第一触控测试开关的第二端电连接至所述第一测试信号线；
所述第二辅助触控测试开关与所述第二触控测试开关串联连接，串联连接后的所述第二辅助触控测试开关和所述第二触控测试开关的第一端电连接至所述第二引线，串联连接后的所述第二辅助触控测试开关和所述第二触控测试开关的第二端电连接至所述第二测试信号线；
所述第一辅助数据测试开关与所述第一数据测试开关串联连接，串联连接后的所述第一辅助数据测试开关和所述第一数据测试开关的第一端电连接至所述第一数据线，串联连接后的所述第一辅助数据测试开关和所述第一数据测试开关的第二端电连接至所述第一测试信号线；
所述第二辅助数据测试开关与所述第二数据测试开关串联连接，串联连接后的所述第二辅助数据测试开关和所述第二数据测试开关的第一端电连接至所述第二数据线，串联连接后的所述第二辅助数据测试开关和所述第二数据测试开关的第二端电连接至所述第二测试信号线。
根据本公开的一些实施例，所述第一触控电极和所述第二触控电极沿第一方向交替设置，所述第一触控电极和所述第二触控电极沿垂直于所述第一方向的第二方向交替设置。
根据本公开的一些实施例，所述显示区包括分块设置的若干公共电极，以及若干阵列排列的亚像素单元，每一所述亚像素单元包括一薄膜晶体管；
所述第一触控电极复用部分所述公共电极，所述第二触控电极复用其余部分所述公共电极。
根据本公开的一些实施例，所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的栅极与所述薄膜晶体管的栅极位于同一层；
所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的源极与所述薄膜晶体管的源极位于同一层；
所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的漏极与所述薄膜晶体管的漏极位于同一层。
在第二方面中，本公开提供了一种显示装置，包括：第一方面所述的触控显示面板。
上述说明仅是本公开中的技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
通过阅读下文可选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出可选实施方式的目的，而并不认为是对本公开的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1为相关技术中触控显示面板中奇型触控电极和偶型触控电极的结构示意图；
图2为相关技术中触控显示面板中测试电路的结构示意图；
图3为本公开实施例的触控显示面板中的测试电路图；
图4为本公开实施例的触控显示面板中的测试电路图；
图5为本公开实施例的触控显示面板中的测试电路图；
图6为在绝缘基板上制作缓冲层、多晶硅存储电容层和有源层的结构示意图；
图7为在图6的基板上制作光刻胶的结构示意图；
图8为在图7的基板上制作栅极绝缘层和栅极的结构示意图；
图9为在图8的基板上制作层间绝缘层的结构示意图；
图10为在图9的基板上制作源极和漏极的结构示意图；
图11为在图10的基板上制作钝化层和平坦化层的结构示意图；
图12为在图11的基板上制作像素电极的结构示意图；
图13为在图12的基板上制作像素定义层的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开 的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
申请人发现，在同时进行触控测试和数据测试时，分别需要使用两条不同的测试信号线和两条不同的测试控制线来进行测试，在非显示区外占据了较大的布线空间，不利于窄边框的设计。
有鉴于此，本公开提供一种触控显示面板和显示装置，解决现有技术中非显示区域的布线空间大，无法实现窄边框的问题。
借由本公开中的技术方案，本公开提供的技术方案至少具有下列优点：
由于本公开在非显示区设置了若干第一触控测试开关、第二触控测试开关、第一数据测试开关和第二数据测试开关，且第一触控测试开关和第二触控测试开关共用同一第一测试控制栅线，第一数据测试开关和第二数据测试开关共用同一第二测试控制栅线，第一触控测试开关和第一数据测试开关共用同一第一测试信号线，第二触控测试开关和第二数据测试开关共用同一第二测试信号线，因此，能够节省布线空间，实现窄边框的技术目的；另外，上述结构还减少了输入信号，降低功耗。
图1和图2示出了相关技术中触控显示面板中触控测试电路的结构示意图。如图1和图2所示，触控显示面板包括彼此交替设置的第一触控电极1(也称奇型触控电极)和第二触控电极2(也称偶型触控电极)，第一触控电极1和第二触控电极2复用触控显示面板的公共电极，并且每个第一触控电极1和第二触控电极2均连接有触控电极引线3。
如图1和图2所示，在触控测试中，向第一触控电极1提供较高测试电压值，同时向第二触控电极2提供较低测试电压值，调整触控电极引线3的电压差，明显区分明暗区域。例如，向第二触控电极2提供较低测试电压值的电压值为1V，向第一触控电极1提供较高测试电压值的电压值为5V。由于第一触控电极1和第二触摸电极2是显示区域的公共电极，对触摸电极施以电压可改变对应显示区域液晶状态，进而可改变该区域的透光率。例如，根据不同的设计要求，施以电压值越高则对应显示区域亮度越高，施以较低电压值则对应显示区域亮度越低；或者，施以电压值越高对应显示区域亮度越低，施以较低电压值则对应显示区域亮度越高。显示区域分为对比鲜明的较暗区与较亮区以供检测。根据图案即可判断短路，以及断路等不良。
但是，本申请的发明人发现，现有技术当同时对显示面板进行触控测试和数据线 测试时，需要分别使用两条不同的测试信号线和两条不同的测试控制线，在非显示区占据较大的布线空间，不利于窄边框的设计。
为了解决上述技术问题，本公开实施例提供了一种触控显示面板。为了方便描述，以下实施例中的部分附图标记与图1和图2中的部分附图标记相同。
如图3所示，本实施例中的触控显示面板包括衬底基板200，位于衬底基板200上方的若干第一触控电极1、若干第二触控电极2、若干第一引线31、若干第二引线32、若干第一数据线9和若干第二数据线10，每一第一引线31连接一第一触控电极1，每一第二引线32连接一第二触控电极2，衬底基板200包括显示区201和非显示区202，显示区201和非显示区202的设置与现有技术相同，这里不再赘述。
如图3所示，该触控显示面板还包括：位于非显示区202的若干第一触控测试开关4、若干第二触控测试开关5、第一测试信号线6、第二测试信号线7、第一测试控制栅线8、第二测试控制栅线13、若干第一数据测试开关11、若干第二数据测试开关12。例如，第一引线31和第一数据线9共用第一测试信号线6，第二引线32和第二数据线10共用第二测试信号线7；以及用于控制第一引线31的第一触控测试开关4和用于控制第一数据线9的第一数据测试开关11不同时接通，用于控制第二引线32的第二触控测试开关5和用于控制第二数据线10的第二数据测试开关12不同时接通。
例如，第一触控测试开关4的第一端电连接至第一引线31，第二端电连接至第一测试信号线6，控制端电连接至第一测试控制栅线8。第二触控测试开关5的第一端电连接至第二引线32，第二端电连接至第二测试信号线7，控制端电连接至第一测试控制栅线8。第一数据测试开关11的第一端电连接至第一数据线9，第二端电连接至第一测试信号线6，控制端电连接至第二测试控制栅线13。第二数据测试开关12的第一端电连接至第二数据线10，第二端电连接至第二测试信号线7，控制端电连接至第二测试控制栅线13。
由于本实施例在非显示区设置了若干第一触控测试开关、第二触控测试开关、第一数据测试开关和第二数据测试开关，且第一触控测试开关和第二触控测试开关共用同一第一测试控制栅线，第一数据测试开关和第二数据测试开关共用同一第二测试控制栅线，第一触控测试开关和第一数据测试开关共用同一第一测试信号线，第二触控测试开关和第二数据测试开关共用同一第二测试信号线，因此，能够节省布线空间，实现窄边框的技术目的；另外，上述结构还减少了输入信号，降低功耗。
在本实施例中，第一触控测试开关4和第二触控测试开关5为N型薄膜晶体管； 第一数据测试开关11和第二数据测试开关12为P型薄膜晶体管，当第一测试控制栅线8输入的电压信号为0V时，第一触控测试开关4和第二触控测试开关5全关断。当第二测试控制栅线13输入的电压信号为0V时，第一数据测试开关11和第二数据测试开关12全关断。在一个实施例中，当第一测试控制栅线8输入的电压信号为5V时，打开第一触控测试开关4和第二触控测试开关5；当第一测试控制栅线8输入的电压信号为-5V时，关断第一触控测试开关4和第二触控测试开关5。在另一个实施例中，当第二测试控制栅线13输入的电压信号为-5V时，打开第一数据测试开关11和第二数据测试开关12；当第二测试控制栅线13输入的电压信号为5V时，关断第一数据测试开关11和第二数据测试开关12。
用于检测触控的第一触控测试开关4和第二触控测试开关5以及用于检测数据线的第一数据测试开关11和第二数据测试开关12可以任意选择P型薄膜晶体管和N型薄膜晶体管，降低了制造成本和难度。
根据本公开的一些实施例，第一触控电极1和第二触控电极2沿第一方向交替设置，第一触控电极1和第二触控电极2还沿垂直于第一方向的第二方向交替设置。具体地，第一方向可以为水平方向，第二方向可以为竖直方向；或者第一方向可以为竖直方向，第二方向可以为水平方向。
由于第一触控电极1和第二触控电极2沿不同方向交替设置，当对第一触控电极1和第二触控电极2施加不同的电压时，能够对显示面板进行触控检测。
根据本公开的一些实施例，显示区包括分块设置的若干公共电极，以及阵列排列的若干亚像素单元(图中未示出)，每一亚像素单元包括一薄膜晶体管(图中未示出)。第一触控电极复用部分公共电极，第二触控电极复用其余部分公共电极。
根据本公开的一些实施例，第一触控测试开关4、第二触控测试开关5、第一数据测试开关11和第二数据测试开关12的栅极与亚像素单元包括的薄膜晶体管的栅极位于同一层。第一触控测试开关4、第二触控测试开关5、第一数据测试开关11和第二数据测试开关12的源极与亚像素单元包括的薄膜晶体管的源极位于同一层。并且，第一触控测试开关4、第二触控测试开关5、第一数据测试开关11和第二数据测试开关12的漏极与亚像素单元包括的薄膜晶体管的漏极位于同一层，这样能够节省生产成本。
基于同一构思，图4还公开了本公开的另一种触控显示面板，包括衬底基板200， 位于衬底基板200上方的若干第一触控电极1、若干第二触控电极2、若干第一引线31、若干第二引线32、若干第一数据线9和若干第二数据线10，每一第一引线31连接一第一触控电极1，每一第二引线32连接一第二触控电极2，衬底基板200包括显示区201和非显示区202，显示区201和非显示区202的设置与现有技术相同，这里不再赘述。
如图4所示，该触控显示面板还包括：位于非显示区202的若干第一触控测试开关4、若干第二触控测试开关5、第一测试信号线6、第二测试信号线7、一条测试控制栅线15、若干第一数据测试开关11和若干第二数据测试开关12。例如，第一引线31和第一数据线9共用第一测试信号线6，第二引线32和第二数据线10共用第二测试信号线7；以及用于控制第一引线31的第一触控测试开关4和用于控制第一数据线9的第一数据测试开关11不同时接通，用于控制第二引线32的第二触控测试开关5和用于控制第二数据线10的第二数据测试开关12不同时接通。
例如，第一触控测试开关4的第一端电连接至第一引线31，第二端电连接至第一测试信号线6，控制端电连接至测试控制栅线15。第二触控测试开关5的第一端电连接至第二引线32，第二端电连接至第二测试信号线7，控制端电连接至测试控制栅线15。第一数据测试开关11的第一端电连接至第一数据线9，第二端电连接至第一测试信号线6，控制端电连接至测试控制栅线15。第二数据测试开关12的第一端电连接至第二数据线10，第二端电连接至第二测试信号线7，控制端电连接至测试控制栅线15。
并且，第一触控测试开关4和第二触控测试开关5在测试控制栅线15的控制下导通时，第一数据测试开关11和第二数据测试开关12在测试控制栅线15的控制下闭合；或，第一触控测试开关4和第二触控测试开关5在测试控制栅线15的控制下闭合时，第一数据测试开关11和第二数据测试开关12在测试控制栅线15的控制下导通。
根据本公开的一些实施例，第一触控测试开关4和第二触控测试开关5为N型薄膜晶体管，第一数据测试开关11和第二数据测试开关12为P型薄膜晶体管。在另一个实施例中，第一触控测试开关4和第二触控测试开关5为P型薄膜晶体管，第一数据测试开关11和第二数据测试开关12为N型薄膜晶体管。
如图4所示，第一触控测试开关4和第二触控测试开关5为N型薄膜晶体管；第一数据测试开关11和第二数据测试开关12为P型薄膜晶体管，当测试控制栅线15 输入的电压信号为0V时，第一触控测试开关4、第二触控测试开关5全关断、第一数据测试开关11和第二数据测试开关12全关断。当测试控制栅线15输入的电压信号为5V时，打开第一触控测试开关4和第二触控测试开关5；当测试控制栅线15输入的电压信号为-5V时，关断第一触控测试开关4和第二触控测试开关5。当测试控制栅线15输入的电压信号为-5V时，打开第一数据测试开关11和第二数据测试开关12；当测试控制栅线15输入的电压信号为5V时，关断第一数据测试开关11和第二数据测试开关12。
根据本公开的一些实施例，如图5所示，本公开实施例的触控显示面板还包括：若干第一辅助触控测试开关41、若干第二辅助触控测试开关51、辅助测试控制栅线14、若干第一辅助数据测试开关111和若干第二辅助数据测试开关121。第一辅助触控测试开关41、第二辅助触控测试开关51、第一辅助数据测试开关111和第二辅助数据测试开关121的控制端电连接至辅助测试控制栅线14。第一辅助触控测试开关41与第一触控测试开关4串联连接，串联连接后的第一端电连接至第一引线31，第二端电连接至第一测试信号线6。第二辅助触控测试开关51与第二触控测试开关5串联连接，串联连接后的第一端电连接至第二引线32，第二端电连接至第二测试信号线7。第一辅助数据测试开关111与第一数据测试开关11串联连接，串联连接后的第一端电连接至第一数据线9，第二端电连接至第一测试信号线6。第二辅助数据测试开关121与第二数据测试开关12串联连接，串联连接后的第一端电连接至第二数据线10，第二端电连接至第二测试信号线7。
图5中，第一触控测试开关4串联一第一辅助触控测试开关41，第二触控测试开关5串联一第二辅助触控测试开关51，第一数据测试开关11串联一第一辅助数据测试开关111，第二数据测试开关12串联一第二辅助数据测试开关121，第一辅助触控测试开关41、第二辅助触控测试开关51、第一辅助数据测试开关111和第二辅助数据测试开关121可以是N型薄膜晶体管，也可以是P型薄膜晶体管，辅助测试控制栅线14用于在不测试时完全关断第一辅助触控测试开关41、第二辅助触控测试开关51、第一辅助数据测试开关111和第二辅助数据测试开关121，防止漏电流增大。即N型薄膜晶体管的辅助测试控制栅线信号是-5V时完全关断，而P型薄膜晶体管的辅助测试控制栅线信号是5V时完全关断，相对于测试控制栅线的0V关断电压同时关断N型薄膜晶体管和P型薄膜晶体管，具有更低的漏电流。
由于显示面板中还设置了辅助测试控制栅线14，用于在不测试时完全关断第一辅 助触控测试开关41、第二辅助触控测试开关51、第一辅助数据测试开关111和第二辅助数据测试开关121，防止漏电流增大。
在一个实施例中，第一辅助触控测试开关41、第二辅助触控测试开关51、第一辅助数据测试开关111和第二辅助数据测试开关121为N型薄膜晶体管。或者在另一个实施例中，第一辅助触控测试开关41、第二辅助触控测试开关51、第一辅助数据测试开关111和第二辅助数据测试开关121为P型薄膜晶体管。
根据本公开的一些实施例，第一触控电极1和第二触控电极2沿第一方向交替设置，第一触控电极1和第二触控电极2还沿垂直于第一方向的第二方向交替设置。具体地，第一方向可以为水平方向，第二方向可以为竖直方向；或者第一方向可以为竖直方向，第二方向可以为水平方向。
由于第一触控电极1和第二触控电极2沿不同方向交替设置，能够对第一触控电极1和第二触控电极2施加不同的电压，从而能够对显示面板进行触控检测。
根据本公开的一些实施例，显示区包括分块设置的若干公共电极，以及阵列排列的若干亚像素单元(图中未示出)，每一亚像素单元包括一薄膜晶体管(图中未示出)。第一触控电极1复用部分公共电极，第二触控电极2复用其余部分公共电极。
根据本公开的一些实施例，第一触控测试开关4、第二触控测试开关5、第一数据测试开关11和第二数据测试开关12的栅极与亚像素单元包括的薄膜晶体管的栅极位于同一层。第一触控测试开关4、第二触控测试开关5、第一数据测试开关11和第二数据测试开关12的源极与亚像素单元包括的薄膜晶体管的源极位于同一层。在另一个实施例中，第一触控测试开关4、第二触控测试开关5、第一数据测试开关11和第二数据测试开关12的漏极与亚像素单元包括的薄膜晶体管的漏极位于同一层，这样能够节省生产成本。
基于同一构思，在第二方面中，本公开实施例提供了一种显示装置，包括：第一方面的触控显示面板。由于第二方面中的显示装置包括了第一方面中的触控显示面板，使得显示装置具有与触控显示面板类似的有益效果，因此不再重复赘述。
以下通过图6至图12来更清楚地描述本公开实施例的触控显示面板。
例如，如图6所示，首先，通过等离子体增强化学气相沉积(PECVD)，在整个绝缘基板100上依次沉积氮化硅(SiN)薄膜和二氧化硅(SiO2)薄膜，形成氮化硅和二氧化 硅构成的缓冲层101。绝缘基板100可以是玻璃，或PI等柔性基板。接着，利用PECVD或者其它化学或物理气相沉积方法在缓冲层101上形成非晶硅(a-Si)薄膜。通过激光退火(ELA)或者固相结晶(SPC)方法，使得a-Si结晶成为多晶硅薄膜。然后采用传统掩模工艺在多晶硅薄膜上形成光刻胶层的图案，以光刻胶层为刻蚀阻挡层，通过等离子体刻蚀没有被光刻胶层保护的多晶硅薄膜，形成多晶硅的有源层103和多晶硅存储电容层102。利用离子注入工艺对有源层103中的晶体管沟道进行低浓度离子掺杂，在有源层103中形成薄膜晶体管要求的导电沟道。
如图7所示，通过掩模工艺在有源层103上形成光阻材料组成的光刻胶104，以保护有源层103不被离子注入。对没有光刻胶104保护的多晶硅存储电容层102进行高浓度离子注入工艺，将多晶硅存储电容层102转化为低电阻的掺杂多晶硅薄膜。在图8至图13所示的后续工艺过程中，由于只在多晶硅存储电容层102上形成栅极绝缘层和栅极金属薄膜构成的电容的第二极板，因此在图8至图13中不再显示多晶硅存储电容层102后续仅有的一次光刻工艺，即形成电容的第二极板的光刻工艺。
如图8所示，通过光刻胶剥离工艺去除有源层103上的光刻胶104，使用PECVD沉积SiO2薄膜或SiO2与SiN的复合薄膜，可以在多晶硅存储电容层102、有源层103以及整个缓冲层101上形成栅极绝缘层105。
如图9所示，通过磁控溅射等物理气相沉积方法在栅极绝缘层105上沉积一种或者多种低电阻的金属材料薄膜，利用光刻工艺形成栅极106。该栅金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。使用栅极106作为离子注入阻挡层，对有源层103进行离子掺杂，在未被栅极阻挡的有源层103区域形成低阻抗的源极和漏极电极接触区。
如图9所示，在包含栅极106的整个表面，使用PECVD依次沉积SiO2薄膜和SiN薄膜形成层间绝缘层107，通过掩模和刻蚀工艺刻蚀层间绝缘层107而形成源电极和漏电极接触孔。
如图10所示，使用磁控溅射在层间绝缘层107及源极和漏极接触孔上沉积一种或多种低电阻的金属薄膜，通过掩模和刻蚀工艺形成源极108和漏极113，源极108和漏极113通过接触孔与有源层103形成欧姆接触。使用快速热退火或热处理炉退火，激活有源层103中掺杂的离子，在栅极106之下的有源层103中形成有效的导电沟道。该源漏金属薄膜可以是Al、Cu、Mo、Ti或AlNd等单层金属薄膜，也可以是Mo/Al/Mo或Ti/Al/Ti等多层金属薄膜。
如图11所示，使用PECVD在包含源极108和漏极113的整个表面沉积一层SiN薄膜，通过掩模和刻蚀工艺形成包含过孔的钝化层109。使用快速热退火或热处理炉退火进行氢化工艺，修复有源层103内部和界面的缺陷。再一次通过掩模工艺，在SiN钝化层109之上形成具有与过孔相同的过孔的有机平坦化层110，填充器件表面的低凹形成平坦表面。
如图12所示，使用磁控溅射在有机平坦化层110和过孔之上沉积一层透明导电薄膜，通过光刻工艺刻蚀该透明导电薄膜，在过孔及部分平坦化层110之上形成像素区域的像素电极112，该透明导电薄膜可以是单层的氧化物导电薄膜，如ITO(氧化铟锡)或IZO(氧化铟锌)等，也可以是ITO(氧化铟锡)/Ag/ITO、IZO(氧化铟锌)/Ag等复合薄膜。
然后在平坦化层110及像素电极112上涂覆一层与平坦化层110类似的光敏有机材料，通过最后一道掩模工艺暴露出像素电极112的部分区域，形成图13中所示的像素定义层116。像素定义层116覆盖平坦化层110及部分的像素电极112区域。
表1分别示出了本实施例中触控显示面板中主要涂层的材料以及相应的厚度，但是，对于本领域技术人员而言，可以根据实际需要选择其他合适的材料和厚度。
涂层 材料 厚度(埃)
绝缘基板 PI 90000
缓冲层 SiNx/SiOx 5000
栅极绝缘层 SiOx 1200
栅极 Mo 2500
层间绝缘层 SiNx/SiOx 4500
源漏极 Ti/Al/Ti 8000
钝化层 SiNx 2500
平坦化层 PI 12000
像素电极 ITO/Ag/ITO 1000
表1
应用本公开实施例所获得的有益效果包括：
由于本实施例在非显示区设置了若干第一触控测试开关、第二触控测试开关、第 一数据测试开关和第二数据测试开关，且第一触控测试开关和第二触控测试开关共用同一第一测试控制栅线，第一数据测试开关和第二数据测试开关共用同一第二测试控制栅线，第一触控测试开关和第一数据测试开关共用同一第一测试信号线，第二触控测试开关和第二数据测试开关共用同一第二测试信号线，因此，能够节省布线空间，实现窄边框的技术目的；另外，上述结构还减少了输入信号，降低功耗。
以上仅是本公开的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开的原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (12)

  1. 一种触控显示面板，包括衬底基板，位于所述衬底基板上方的若干第一触控电极、若干第二触控电极、若干第一引线、若干第二引线、若干第一数据线和若干第二数据线，每一所述第一引线连接一所述第一触控电极，每一所述第二引线连接一所述第二触控电极，所述衬底基板包括显示区和非显示区，其中，所述触控显示面板还包括：位于所述非显示区的若干第一触控测试开关、若干第二触控测试开关、第一测试信号线、第二测试信号线、一条或两条测试控制栅线、若干第一数据测试开关、若干第二数据测试开关；
    其中，所述第一引线和所述第一数据线共用所述第一测试信号线，所述第二引线和所述第二数据线共用所述第二测试信号线；以及
    用于控制所述第一引线的所述第一触控测试开关和用于控制所述第一数据线的所述第一数据测试开关不同时接通，用于控制所述第二引线的所述第二触控测试开关和用于控制所述第二数据线的所述第二数据测试开关不同时接通。
  2. 根据权利要求1所述的触控显示面板，其中，在所述触控显示面板包括两条测试控制栅线的情况下，所述两条测试控制栅线包括第一测试控制栅线和第二测试控制栅线；
    所述第一触控测试开关的第一端电连接至所述第一引线，所述第一触控测试开关的第二端电连接至所述第一测试信号线，所述第一触控测试开关的控制端电连接至所述第一测试控制栅线；
    所述第二触控测试开关的第一端电连接至所述第二引线，所述第二触控测试开关的第二端电连接至所述第二测试信号线，所述第二触控测试开关的控制端电连接至所述第一测试控制栅线；
    所述第一数据测试开关的第一端电连接至所述第一数据线，所述第一数据测试开关的第二端电连接至所述第一测试信号线，所述第一数据测试开关的控制端电连接至所述第二测试控制栅线；
    所述第二数据测试开关的第一端电连接至所述第二数据线，所述第二数据测试开关的第二端电连接至所述第二测试信号线，所述第二数据测试开关的控制端电连接至所述第二测试控制栅线。
  3. 如权利要求2所述的触控显示面板，其中，所述第一触控电极和所述第二触控电极沿第一方向交替设置，所述第一触控电极和所述第二触控电极还沿垂直于所述第一方向的第二方向交替设置。
  4. 如权利要求3所述的触控显示面板，其中，所述显示区包括分块设置的若干公共电极，以及阵列排列的若干亚像素单元，每一所述亚像素单元包括一薄膜晶体管；
    所述第一触控电极复用部分所述公共电极，所述第二触控电极复用其余部分所述公共电极。
  5. 如权利要求3所述的触控显示面板，其中，所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的栅极与所述薄膜晶体管的栅极位于同一层；
    所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的源极与所述薄膜晶体管的源极位于同一层；
    所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的漏极与所述薄膜晶体管的漏极位于同一层。
  6. 如权利要求1所述的触控显示面板，其中，所述触控显示面板包括一条测试控制栅线；
    所述第一触控测试开关的第一端电连接至所述第一引线，所述第一触控测试开关的第二端电连接至所述第一测试信号线，所述第一触控测试开关的控制端电连接至所述测试控制栅线；
    所述第二触控测试开关的第一端电连接至所述第二引线，所述第二触控测试开关的第二端电连接至所述第二测试信号线，所述第二触控测试开关的控制端电连接至所述测试控制栅线；
    所述第一数据测试开关的第一端电连接至所述第一数据线，所述第一数据测试开关的第二端电连接至所述第一测试信号线，所述第一数据测试开关的控制端电连接至所述测试控制栅线；
    所述第二数据测试开关的第一端电连接至所述第二数据线，所述第二数据测试开关的第二端电连接至所述第二测试信号线，所述第二数据测试开关的控制端电连接至 所述测试控制栅线；
    所述第一触控测试开关和所述第二触控测试开关在所述测试控制栅线的控制下导通时，所述第一数据测试开关和所述第二数据测试开关在所述测试控制栅线的控制下闭合；或，所述第一触控测试开关和所述第二触控测试开关在所述测试控制栅线的控制下闭合时，所述第一数据测试开关和所述第二数据测试开关在所述测试控制栅线的控制下导通。
  7. 如权利要求6所述的触控显示面板，其中，所述第一触控测试开关和所述第二触控测试开关为N型薄膜晶体管，所述第一数据测试开关和所述第二数据测试开关为P型薄膜晶体管；或者
    所述第一触控测试开关和所述第二触控测试开关为P型薄膜晶体管，所述第一数据测试开关和所述第二数据测试开关为N型薄膜晶体管。
  8. 如权利要求6所述的触控显示面板，其中，所述触控显示面板还包括：若干第一辅助触控测试开关、若干第二辅助触控测试开关、辅助测试控制栅线、若干第一辅助数据测试开关、以及若干第二辅助数据测试开关，其中，
    所述第一辅助触控测试开关、所述第二辅助触控测试开关、所述第一辅助数据测试开关和所述第二辅助数据测试开关的控制端电连接至所述辅助测试控制栅线；
    所述第一辅助触控测试开关与所述第一触控测试开关串联连接，串联连接后的所述第一辅助触控测试开关和所述第一触控测试开关的第一端电连接至所述第一引线，串联连接后的所述第一辅助触控测试开关和所述第一触控测试开关的第二端电连接至所述第一测试信号线；
    所述第二辅助触控测试开关与所述第二触控测试开关串联连接，串联连接后的所述第二辅助触控测试开关和所述第二触控测试开关的第一端电连接至所述第二引线，串联连接后的所述第二辅助触控测试开关和所述第二触控测试开关的第二端电连接至所述第二测试信号线；
    所述第一辅助数据测试开关与所述第一数据测试开关串联连接，串联连接后的所述第一辅助数据测试开关和所述第一数据测试开关的第一端电连接至所述第一数据线，串联连接后的所述第一辅助数据测试开关和所述第一数据测试开关的第二端电连接至所述第一测试信号线；
    所述第二辅助数据测试开关与所述第二数据测试开关串联连接，串联连接后的所述第二辅助数据测试开关和所述第二数据测试开关的第一端电连接至所述第二数据线，串联连接后的所述第二辅助数据测试开关和所述第二数据测试开关的第二端电连接至所述第二测试信号线。
  9. 如权利要求6-8任一项所述的触控显示面板，其中，所述第一触控电极和所述第二触控电极沿第一方向交替设置，所述第一触控电极和所述第二触控电极还沿垂直于所述第一方向的第二方向交替设置。
  10. 如权利要求9所述的触控显示面板，其中，所述显示区包括分块设置的若干公共电极，以及阵列排列的若干亚像素单元，每一所述亚像素单元包括一薄膜晶体管；
    所述第一触控电极复用部分所述公共电极，所述第二触控电极复用其余部分所述公共电极。
  11. 如权利要求10所述的触控显示面板，其中，所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的栅极与所述薄膜晶体管的栅极位于同一层；
    所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的源极与所述薄膜晶体管的源极位于同一层；
    所述第一触控测试开关、所述第二触控测试开关、所述第一数据测试开关和所述第二数据测试开关的漏极与所述薄膜晶体管的漏极位于同一层。
  12. 一种显示装置，包括：如权利要求1-11任一项所述的触控显示面板。
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