WO2019223755A1 - 阵列基板及其制造方法、显示面板 - Google Patents

阵列基板及其制造方法、显示面板 Download PDF

Info

Publication number
WO2019223755A1
WO2019223755A1 PCT/CN2019/088100 CN2019088100W WO2019223755A1 WO 2019223755 A1 WO2019223755 A1 WO 2019223755A1 CN 2019088100 W CN2019088100 W CN 2019088100W WO 2019223755 A1 WO2019223755 A1 WO 2019223755A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
sub
insulating layer
gate
base substrate
Prior art date
Application number
PCT/CN2019/088100
Other languages
English (en)
French (fr)
Inventor
田宏伟
牛亚男
赵梦
王雷
刘政
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/641,372 priority Critical patent/US11296122B2/en
Publication of WO2019223755A1 publication Critical patent/WO2019223755A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a method for manufacturing an array substrate, an array substrate, and a display panel.
  • the display panel generally includes an array substrate and various display structures provided on the array substrate.
  • the flexible display panel is a current development trend, but various inorganic films in the array substrate have limited the flexibility of the display panel due to its own material.
  • An aspect of the present disclosure provides an array substrate including: a base substrate; an active layer on the base substrate; a first gate insulating layer on the active layer; and a first gate A first gate on the insulating layer; and a second gate insulating layer on the first gate.
  • the second gate insulating layer includes a first sub-insulating layer and a second sub-insulating layer disposed in a direction away from the active layer, and a hydrogen content of the first sub-insulating layer is greater than that of the second sub-insulating layer. Hydrogen content.
  • a density of the first sub-insulation layer is smaller than that of the second sub-insulation layer.
  • a hydrogen content of the first sub-insulation layer decreases in a direction away from the active layer, and the first sub-insulation layer is on a surface facing the second sub-insulation layer The hydrogen content at is greater than the hydrogen content of the second sub-insulation layer at a surface facing the first sub-insulation layer.
  • a hydrogen content of the second sub-insulation layer decreases in a direction away from the active layer, and the first sub-insulation layer is on a surface facing the second sub-insulation layer The hydrogen content at is greater than the hydrogen content of the second sub-insulation layer at a surface facing the first sub-insulation layer.
  • a hydrogen content of at least one of the first sub-insulation layer and the second sub-insulation layer is constant in a direction away from the active layer.
  • a hydrogen content of the first sub-insulating layer is between about 30% and 45%.
  • the above-mentioned array substrate further includes a recess penetrating the second gate insulating layer and extending into the first gate insulating layer, and the recess on the base substrate
  • the orthographic projection is located around the orthographic projection of the active layer on the base substrate.
  • the second gate insulating layer includes a first region and a second region, a thickness of the first region is greater than a thickness of the second region, and the active layer is located in the A first region is in an orthographic projection on the base substrate, and the second region is a region of the second gate insulating layer other than the first region.
  • the above-mentioned array substrate further includes: a second gate on the second gate insulating layer; and a source penetrating the second gate insulating layer and the first gate insulating layer A drain via, and the active layer is exposed through the source-drain via.
  • the above-mentioned array substrate further includes an intermediate dielectric layer on the second gate.
  • the array substrate includes a plurality of sub-pixels arranged in a matrix, and the second gate insulating layer further includes a trench disposed between each of the sub-pixels.
  • Another aspect of the present disclosure provides a display panel including any one of the above-mentioned array substrates.
  • Another aspect of the present disclosure provides a method for manufacturing an array substrate, including: sequentially forming an active layer, a first gate insulating layer, and a first gate on a base substrate; and forming a substrate on which the first gate is formed.
  • a second gate insulating layer is formed on the base substrate, and the second gate insulating layer includes a first sub-insulating layer and a second sub-insulating layer disposed in a direction away from the active layer, wherein the The hydrogen content is greater than the hydrogen content of the second sub-insulation layer; and the active layer is hydrogenated.
  • the forming a second gate insulating layer on a base substrate on which the first gate is formed includes: forming a second gate insulating layer on the base substrate on which the first gate is formed; Depositing the first sub-insulating layer at a first deposition rate; and depositing the second sub-insulating layer at a second deposition rate on a base substrate on which the first sub-insulating layer is formed; The second deposition rate is less than the first deposition rate.
  • the method before subjecting the active layer to a hydrogenation treatment, the method further includes: forming a second gate on a substrate substrate on which the second gate insulating layer is formed; and A source-drain via is formed on the base substrate on which the second gate is formed, and the active layer is exposed through the source-drain via.
  • the method before the active layer is hydrogenated, the method further includes: forming a groove on the base substrate on which the second gate insulating layer is formed, and the concave The bottom of the groove is located in the first gate insulating layer, and the orthographic projection of the groove on the base substrate is located around the orthographic projection of the active layer on the base substrate.
  • the hydrogenating the active layer includes: setting a base substrate having the grooves formed in a hydrogen atmosphere to hydrogenate the active layer.
  • the method before subjecting the active layer to a hydrogenation treatment, the method further includes: forming a second gate on a substrate substrate on which the second gate insulating layer is formed; and Coating the silicon-based organic material layer on the base substrate on which the second gate is formed; baking the silicon-based organic material layer; and processing the silicon-based organic material layer into an intermediate dielectric layer.
  • the step of forming a second gate insulating layer on a base substrate on which the first gate is formed includes: using a gray mask process to form the first gate on the base substrate.
  • the second gate insulating layer is formed on a base substrate.
  • the second gate insulating layer includes a first region and a second region. The thickness of the first region is greater than the thickness of the second region.
  • the active layer is located in the first region on the base substrate.
  • the second region is a region of the second gate insulating layer other than the first region.
  • the array substrate includes a plurality of sub-pixels arranged in a matrix
  • the method further includes: forming a trench between each of the sub-pixels in the second gate insulating layer.
  • the active layer includes one or more of low temperature polysilicon and microcrystalline silicon.
  • FIG. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a base substrate in the manufacturing method shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of another base substrate in the manufacturing method shown in FIG. 2;
  • FIG. 5 is a schematic structural diagram of another substrate in the manufacturing method shown in FIG. 2;
  • FIG. 6 is a schematic structural diagram of another base substrate in the manufacturing method shown in FIG. 2;
  • FIG. 7 is a schematic structural diagram of another base substrate in the manufacturing method shown in FIG. 2;
  • FIG. 8 is a cross-sectional view of the base substrate shown in FIG. 7;
  • FIG. 9 is a schematic structural diagram of another base substrate in the manufacturing method shown in FIG. 2;
  • FIG. 10 is a schematic structural diagram of an array substrate in the manufacturing method shown in FIG. 2;
  • FIG. 11 is a flowchart of another method of manufacturing an array substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a base substrate in the manufacturing method shown in FIG. 11;
  • FIG. 13 is a schematic structural diagram of another base substrate in the manufacturing method shown in FIG. 11;
  • FIG. 14 is a flowchart of a subsequent manufacturing process in the manufacturing method shown in FIG. 11;
  • FIG. 16 is a schematic structural diagram of an array substrate in the manufacturing method shown in FIG. 11.
  • a typical method of manufacturing a flexible array substrate may include the following steps: sequentially forming an active layer made of low temperature polysilicon (English: Low Temperature Poly-silicon (LTPS)), a first gate insulating layer, a first A gate, a second gate insulating layer, and a second gate; the active layer in the base substrate on which the second gate is formed is hydrogenated by a solid-state diffusion method to improve the electrical performance of the active layer;
  • An intermediate dielectric layer (English: inter-layerdielectric; ILD for short) made of an organic material is formed on the base substrate having the second gate to improve the flexibility of the array substrate. Because organic materials are less resistant to high temperatures than inorganic materials, the active layer needs to be hydrogenated before ILD is formed to avoid damage to the ILD.
  • Hydrogen treatment can fill the unbonded or unsaturated bonds of the silicon atoms in the LTPS (or microcrystalline silicon) constituting the active layer with hydrogen atoms, thereby improving the electrical performance of the LTPS (or microcrystalline silicon).
  • the temperature required for effective hydrogenation of the active layer is usually higher than the withstand temperature of the organic film, so that the organic film will limit the hydrogenation of the active layer. It has been proposed to hydrogenate the active layer before forming the ILD.
  • embodiments of the present disclosure provide an improved manufacturing method of an array substrate, an array substrate, and a display panel.
  • FIG. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • an active layer, a first gate insulating layer, and a first gate are sequentially formed on a base substrate, where the active layer includes low-temperature polysilicon.
  • a second gate insulating layer is formed on the base substrate on which the first gate is formed, and the second gate insulating layer includes a first sub-insulating layer and a second sub-layer disposed in a direction away from the active layer.
  • the insulating layer wherein a hydrogen content of the first sub-insulating layer is greater than a hydrogen content of the second sub-insulating layer.
  • step 103 the active layer is hydrogenated.
  • the first sub-insulation layer can serve as a hydrogen source
  • the second sub-insulation layer can serve as a hydrogen barrier layer, so that hydrogen can diffuse to the direction of the active layer better, thereby increasing the hydrogen concentration gradient toward the active layer. Distribution to improve the hydrogenation of the active layer, thereby avoiding insufficient hydrogenation of the active layer, thereby causing problems affecting the electrical performance of the active layer, and achieving the effect of improving the electrical performance of the active layer.
  • FIG. 2 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present disclosure.
  • an active layer, a first gate insulating layer, and a first gate are sequentially formed on a base substrate, where the active layer includes low temperature polysilicon and / or microcrystalline silicon.
  • Low-temperature polysilicon or microcrystalline silicon has a higher electron mobility, so an active layer including LTPS or microcrystalline silicon can improve the response speed of a thin film transistor (English: Thin Film Transistor; TFT for short).
  • the structure of the base substrate may be as shown in FIG. 3.
  • the base substrate 11 is provided with an active layer 12, a first gate insulating layer 13 and a first gate 14 in this order.
  • the material of the first gate insulating layer 13 may include materials such as silicon nitride.
  • the first gate electrode 14 may include a metal or other conductive material, which is not limited in the embodiment of the present disclosure.
  • the active layer is composed of LTPS
  • the process of forming the active layer composed of LTPS may include the following steps:
  • amorphous silicon (a-si) is subjected to a dehydrogenation treatment.
  • a dehydrogenation treatment can be performed on the amorphous silicon first.
  • the hydrogen content in the amorphous silicon can be made less than 2% by a dehydrogenation treatment.
  • amorphous silicon layer is then formed on the base substrate by amorphous silicon. Then, the amorphous silicon layer is annealed at a low temperature to transform the amorphous silicon layer into a polysilicon layer. Specifically, the low-temperature annealing process may be performed by a laser annealing technique. Finally, the polysilicon layer is patterned through a patterning process to form an active layer.
  • the active layer may include an active layer pattern in a plurality of TFTs on a base substrate.
  • the patterning process may include steps of coating the photoresist, exposing the photoresist, developing the photoresist, etching, and stripping the photoresist.
  • the base substrate may be a flexible base substrate, and the base substrate may be composed of a polyimide substrate or a composite film layer including a polyimide substrate.
  • the base substrate may include polyimide and A spacer layer, a polyimide substrate, and a buffer layer are sequentially disposed on the polyimide.
  • a first sub-insulation layer is formed on the base substrate on which the first gate is formed at a first deposition rate, and the hydrogen content of the first sub-insulation layer is increased.
  • the first deposition speed may be a speed at which a conventional second gate insulating layer is formed in the related art.
  • the first sub-insulation layer may be formed by a chemical vapor deposition (English: Chemical Vapor Deposition; CVD for short) technology, and the hydrogen content of the first sub-insulation layer may be increased by increasing the flow rate of the reaction gas containing hydrogen.
  • the reaction gas may include ammonia gas (chemical formula: NH 3 ) and silane (chemical formula: SiH 4 ). Accordingly, the flow rate of NH 3 can be increased to 1.1 times to 1.5 times the normal level to increase the hydrogen content of the first sub-insulation layer to 1.1 times to 1.5 times.
  • the hydrogen content (atomic ratio) in the first sub-insulating layer can be about 30% to 45%.
  • the first sub-insulation layer may have a uniform hydrogen content.
  • the hydrogen content of the first sub-insulation layer decreases in a direction away from the active layer. That is, the first sub-insulating layer has the highest hydrogen content at the interface between the first sub-insulating layer and the first gate insulating layer, and the hydrogen content gradually decreases in a direction away from the active layer. In this way, the ability of the hydrogen atoms to diffuse into the active layer can be improved, and the possibility of the hydrogen in the film layer under the first sub-insulation layer to diffuse into the first sub-insulation layer can be avoided.
  • the hydrogen content of the first sub-insulating layer may also start from the side far from the active layer, and increase in a thickness range of 100 to 300 angstroms in a direction close to the active layer. In this way, the ability of the hydrogen atoms to diffuse into the active layer can be improved, and the possibility of the hydrogen in the film layer under the first sub-insulation layer to diffuse into the first sub-insulation layer can be avoided.
  • the term “thickness” refers to a dimension in a direction perpendicular to the base substrate.
  • the structure of the base substrate may be as shown in FIG. 4, and the first sub-insulating layer 151 is formed on the base substrate 11 on which the first gate electrode 14 is formed.
  • the first sub-insulating layer 151 is formed on the base substrate 11 on which the first gate electrode 14 is formed.
  • a second sub-insulation layer is formed at a second deposition rate, where the second deposition rate is less than the first deposition rate.
  • the density of the second sub-insulation layer can be increased, and the second sub-insulation layer can be made denser than the first sub-insulation layer.
  • the blocking effect of the second sub-insulation layer on hydrogen can be improved, so that hydrogen in the film layer below the second sub-insulation layer can hardly diffuse out through the second sub-insulation layer, thereby further improving the active layer. Effect of hydrogenation.
  • the deposition speed of the second sub-insulation layer may be the same as the deposition speed of the first sub-insulation layer, which is not limited in the embodiment of the present disclosure.
  • the first and second sub-insulation layers may each have a uniform hydrogen content, and the hydrogen content of the first sub-insulation layer is greater than the hydrogen content of the second sub-insulation layer.
  • the first sub-insulation layer has a decreasing hydrogen content in a direction away from the active layer
  • the second sub-insulation layer has a uniform hydrogen content
  • the hydrogen content of the second sub-insulation layer is less than the minimum of the first sub-insulation layer.
  • the hydrogen content makes it possible to improve the ability of the hydrogen atoms to diffuse into the active layer, and to avoid the possibility of the hydrogen in the film layer under the second sub-insulation layer to diffuse outward through the second sub-insulation layer.
  • the first sub-insulation layer has a uniform hydrogen content
  • the second sub-insulation layer has a decreasing hydrogen content in a direction away from the first sub-insulation layer
  • the hydrogen content of the first sub-insulation layer is greater than the second sub-insulation layer
  • the maximum hydrogen content of the silicon oxide layer can increase the ability of hydrogen atoms to diffuse into the active layer, and can avoid the possibility of hydrogen in the film layer under the second sub-insulation layer to diffuse outward through the second sub-insulation layer.
  • the hydrogen content (atomic ratio) in the second sub-insulating layer may be about 15% to 30%.
  • the thickness ratio between the second sub-insulation layer and the first sub-insulation layer may be between 1: 0.5 and 1: 2.
  • the structure of the base substrate may be as shown in FIG. 5, wherein a second sub-insulation layer 152 is formed on the base substrate 11 on which the first sub-insulation layer 151 is formed, and the first sub-insulation layer 151 And the second sub-insulation layer 152 constitutes the second insulation layer 15.
  • a second sub-insulation layer 152 is formed on the base substrate 11 on which the first sub-insulation layer 151 is formed, and the first sub-insulation layer 151 And the second sub-insulation layer 152 constitutes the second insulation layer 15.
  • the first sub-insulation layer and the second sub-insulation layer may be different portions (different portions in the thickness direction) of the same film layer formed in one chemical vapor deposition, or two film layers formed separately.
  • first sub-insulation layer and the second sub-insulation layer are different parts of the same film layer, compared with the case where the first sub-insulation layer and the second sub-insulation layer are different film layers, the stress between the film layers is reduced, The risk of film breakage is thus reduced.
  • a second gate is formed on the base substrate on which the second gate insulating layer is formed.
  • the second gate can form a capacitor with the first gate to improve the capacity of the capacitor in the TFT, thereby enhancing the display effect of the display structure.
  • the structure of the base substrate may be as shown in FIG. 6, wherein a second gate electrode 16 is formed on the base substrate 11 on which the second gate insulating layer 15 is formed.
  • a second gate electrode 16 is formed on the base substrate 11 on which the second gate insulating layer 15 is formed.
  • the active layer may be activated by heating the base substrate on which each film layer is formed. During heating, the temperature can be slowly raised, so that the stress variation between the film layers can be carried out relatively slowly, so as to avoid the problem of film cracking caused by the stress mismatch between the various film layers.
  • a source-drain via is formed on the base substrate on which the second gate is formed, so that the active layer is exposed from the source-drain via.
  • Step 205 may be performed at any stage after step 204 and before step 209, for example, source-drain vias may be formed after the active layer is hydrogenated, or source-drain vias may be formed after the intermediate dielectric layer is formed. In an exemplary embodiment, source-drain vias are formed before the active layer is hydrogenated, so that the hydrogenation effect on the active layer can be improved to a certain extent.
  • step 205 the structure of the base substrate can be as shown in FIG. 7, where the active layer 12 is exposed in the source-drain via hole k, so the subsequently formed source and drain electrodes can pass through the via k and Active layer contact.
  • FIG. 7 For the meanings of other marks in FIG. 7, refer to FIG. 3, and details are not described herein again.
  • a groove is formed on the base substrate on which the second gate insulation layer is formed, the bottom of the groove is located in the first gate insulation layer, and the orthographic projection of the groove on the base substrate is located on the active layer. around.
  • the groove is used to improve the hydrogenation of the active layer, and the area of the groove's orthographic projection on the base substrate is not greater than the area of the orthographic projection of the source / drain vias on the substrate.
  • the structure of the base substrate may be as shown in FIG. 8, and it is a cross-sectional view of the base substrate at P-P shown in FIG. 7.
  • the groove c passes through the second insulating layer 15, the bottom thereof is located in the first insulating layer 13, and the orthographic projection of the groove c on the base substrate 11 is located around the active layer 12.
  • FIG. 8 refers to FIG. 3, and details are not described herein again.
  • the base substrate on which the groove is formed is placed in a hydrogen atmosphere to hydrogenate the active layer.
  • the hydrogen concentration in the external environment is high, so it is difficult for the hydrogen in each film layer on the base substrate to overflow into the external environment, and the The concentration can form a gradual decrease in the direction of the active layer along the external environment, thereby facilitating the movement of hydrogen into the active layer.
  • the hydrogen will fill the groove c, which makes the high-concentration hydrogen closer to the active layer 12, thereby further facilitating the movement of hydrogen into the active layer.
  • the hydrogen atmosphere may include only hydrogen, and may also include hydrogen and nitrogen, wherein the partial pressure of hydrogen is not less than 200 mTorr (English: mTorr).
  • an intermediate dielectric layer is formed on the grooved base substrate.
  • the intermediate dielectric layer may be composed of an organic insulating material.
  • an organic insulating material layer may be first formed on a base substrate having a groove formed thereon, and then the organic insulating material layer may be patterned into an intermediate dielectric layer by a patterning process. If the source and drain vias have been formed before the intermediate dielectric layer is formed, the organic insulating material in the source and drain vias needs to be etched away to expose the active layer in the source and drain vias.
  • the grooves can be filled with an organic insulating material layer to improve the flatness of each film layer on the base substrate.
  • the intermediate dielectric layer may be composed of a photoresist material.
  • a photoresist material layer may be first formed on the base substrate having the grooves formed therein, for example, the thickness is between 0.2 ⁇ m and 0.3 ⁇ m, and then an intermediate dielectric layer is formed by an exposure process and a development process. If the source and drain vias have been formed before the intermediate dielectric layer is formed, the photoresist material in the source and drain vias needs to be exposed and developed to remove the photoresist material in the source and drain vias, so that The active layer in the source-drain via is exposed.
  • the groove can be filled by the photoresist material, and the photoresist material in the groove is retained after exposure and development, so as to improve the base substrate.
  • the structure of the base substrate may be as shown in FIG. 9, wherein the intermediate dielectric layer 17 is formed on the base substrate on which the second gate electrode 16 is formed, and the source and drain vias k also pass through the middle. Dielectric layer 17.
  • a source and a drain are formed on the base substrate on which the intermediate dielectric layer is formed.
  • the structure of the base substrate may be as shown in FIG. 10, where the source and drain electrodes 18 are in contact with the active layer 12 through source and drain vias.
  • the active in the manufacturing method of the array substrate provided by the embodiments of the present disclosure, by forming a first sub-insulation layer including a large hydrogen content and a second sub-insulation layer with a small hydrogen content, the active During the hydrogenation process of the layer, the first sub-insulating layer acts as a hydrogen source, and the second sub-insulating layer serves as a hydrogen barrier layer, so hydrogen can better diffuse toward the active layer, thereby increasing the hydrogen concentration gradient to the active layer.
  • the directional distribution improves the hydrogenation of the active layer. In this way, insufficient hydrogenation of the active layer can be avoided, which in turn causes problems that affect the electrical performance of the active layer, and improves the electrical performance of the active layer.
  • FIG. 11 is a flowchart of another method of manufacturing an array substrate according to an embodiment of the present disclosure.
  • an active layer, a first gate insulating layer, and a first gate are sequentially formed on a base substrate, where the active layer may include low-temperature polysilicon.
  • step 201 For this step, reference may be made to step 201 in the foregoing embodiment, and details are not described herein again.
  • a second gate insulating layer is formed on the base substrate on which the first gate is formed by a gray mask process.
  • the second gate insulating layer includes a first region and a second region.
  • the thickness of the first region is greater than the thickness of the second region.
  • the active layer is located in an orthographic projection of the first region on the substrate (the orthographic projection).
  • the distance between the edge and the edge of the nearest active layer may be between 1 micrometer and 5 micrometers)
  • the second region is a region other than the first region in the second gate insulating layer. Because the insulating layer in the first region directly above the active layer is thick, it can provide more hydrogen in the subsequent hydrogenation process, which is beneficial to the hydrogenation of the active layer.
  • the thickness of the first region may be 1.1 to 1.3 times the thickness of the second region.
  • the second gate insulating layer is further provided with a trench between each sub-pixel in the array substrate.
  • the groove can reduce continuous abrasion stress and avoid damage to the film layer.
  • the thickness of the second insulating layer at the trench may be, for example, 0.1 to 0.5 times the thickness of the second region.
  • trenches may be provided at the positions of the second gates between the sub-pixels.
  • a gray mask process is a process of exposing through a gray mask, and a gray mask is a mask that can have different light transmittance in different regions. By using such a mask, patterns with different thicknesses in different regions can be formed.
  • a second gate insulating layer having different thicknesses in different regions may be formed by a gray mask process.
  • the second insulating layer may include The first sub-insulation layer with a higher hydrogen content and the second sub-insulation layer with a lower hydrogen content are arranged in this order in order to further improve the hydrogenation effect on the active layer.
  • the structure of the base substrate may be as shown in FIG. 12, wherein the thickness of the first region q1 is greater than the thickness of the second region q2, and a groove g is provided between the sub-pixel and the sub-pixel.
  • a second gate is formed on the base substrate on which the second gate insulating layer is formed.
  • the second gate is formed, since the insulating layer in the second region is thinner, a larger capacitance can be formed between the second gate and the first gate at the second region, thereby improving the electrical performance of the TFT.
  • the structure of the base substrate may be as shown in FIG. 13, wherein the second insulating layer 15 between the first gate 14 and the second gate 16 is thin, so the first gate 14 and the first gate 14 A larger capacitance can be formed between the two gates 16.
  • a source-drain via is formed on the base substrate on which the second gate is formed, so that the active layer is exposed in the source-drain via.
  • the source-drain vias reference may be made to the source-drain vias k in FIG. 7, and details are not described herein again.
  • step 305 the active layer is hydrogenated.
  • step 207 in the foregoing embodiment, and details are not described herein again.
  • grooves c as shown in FIG. 8 may also be formed on each film layer on the base substrate.
  • step 306 an intermediate dielectric layer is formed on the base substrate on which the second gate is formed.
  • step 208 reference may be made to step 208 in the foregoing embodiment, and details are not described herein again.
  • step 307 a source-drain is formed on the base substrate on which the active-drain vias are formed.
  • step 209 for this step, reference may be made to step 209 in the foregoing embodiment, and details are not described herein again.
  • step 303 after step 303 is completed, as shown in FIG. 15, subsequent steps different from FIG. 14 may be performed.
  • a silicon-based organic material layer is coated on the base substrate on which the second gate is formed.
  • the silicon-based organic material is an organic material with a strong resistance to temperature, so the silicon-based organic material layer can be coated before the hydrogenation treatment in order to maintain reliability during the subsequent temperature rise process.
  • step 309 the silicon-based organic material layer is baked. Baking can remove the moisture and other solvents mixed in the silicon-based organic material, increase the density of the silicon-based organic material layer, and further improve the hydrogen-blocking ability of the silicon-based organic material layer.
  • the active layer can be activated while baking the silicon-based organic material layer.
  • the silicon-based organic material layer is processed into an intermediate dielectric layer.
  • the intermediate dielectric layer can be formed in different ways. For this step, reference may be made to step 208 in the foregoing embodiment, and details are not described herein again.
  • the active layer is hydrogenated.
  • an intermediate dielectric layer composed of a silicon-based organic material can be used to prevent hydrogen of each film layer on the substrate from overflowing to the outside to improve the hydrogenation effect on the active layer.
  • step 312 source-drain vias are formed on the base substrate on which the intermediate dielectric layer is formed.
  • step 312 may also be performed before step 311, that is, source-drain vias may be formed before the hydrogenation treatment, which is not limited in the embodiment of the present disclosure.
  • a source-drain is formed on the base substrate on which the active-drain vias are formed.
  • step 209 for this step, reference may be made to step 209 in the foregoing embodiment, and details are not described herein again.
  • the structure of the base substrate can be as shown in FIG. 16, wherein the intermediate dielectric layer 17 is formed on the base substrate on which the second gate electrode 16 is formed, and the base substrate on which the intermediate dielectric layer 17 is formed An active drain 18 is formed thereon, and the source and drain 18 are in contact with the active layer 12 through source and drain vias.
  • the manufacturing method of the above-mentioned array substrate provided by the embodiment of the present disclosure, by forming a first sub-insulation layer including a large hydrogen content and a second sub-insulation layer with a small hydrogen content, the first sub-insulating layer acts as a hydrogen source, and the second sub-insulating layer serves as a barrier layer, so that the hydrogen can diffuse better in the direction of the active layer and increase the hydrogen concentration gradient toward the active layer. Distribution to improve the hydrogenation of the active layer. In this way, insufficient hydrogenation of the active layer can be avoided, which in turn causes problems that affect the electrical performance of the active layer, and improves the electrical performance of the active layer.
  • An embodiment of the present disclosure further provides an array substrate.
  • the array substrate is an array substrate manufactured by any of the methods described above, such as the array substrate shown in FIG. 10 or the array substrate shown in FIG. 16.
  • the array substrate includes: a base substrate 11; an active layer 12 on the base substrate 11; a first gate insulating layer 13 on the active layer 12; and a first gate insulating layer 13 And a second gate insulating layer 15 on the first gate 14.
  • the second gate insulation layer 15 includes a first sub-insulation layer 151 and a second sub-insulation layer 152 disposed in a direction away from the active layer 12, and the hydrogen content of the first sub-insulation layer 151 is greater than that of the second sub-insulation layer 152. content.
  • An embodiment of the present disclosure further provides a display panel including any of the foregoing array substrates.
  • the display panel may be an organic light emitting diode (English: Organic Light-Emitting Diode; OLED for short) display panel or a liquid crystal display panel.
  • first and second are used for descriptive purposes only and are not to be construed to indicate or imply relative importance.
  • plurality refers to two or more, unless explicitly defined otherwise.
  • the program may be stored in a computer-readable storage medium.
  • the storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板，包括：衬底基板（11）；位于所述衬底基板（11）上的有源层（12）；位于所述有源层（12）上的第一栅绝缘层（13）；位于所述第一栅绝缘层（13）上的第一栅极（14）；以及位于所述第一栅极（14）上的第二栅绝缘层（15）。所述第二栅绝缘层（15）包括沿远离所述有源层（12）的方向设置的第一子绝缘层（151）和第二子绝缘层（152），并且所述第一子绝缘层（151）的氢含量大于所述第二子绝缘层（152）的氢含量。还提供了该阵列基板的制造方法和包括该阵列基板的显示面板。

Description

阵列基板及其制造方法、显示面板
相关申请
本申请要求享有2018年5月24日提交的中国专利申请No.201810508747.6的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板的制造方法、阵列基板和显示面板。
背景技术
显示面板通常包括阵列基板以及设置在该阵列基板上的各种显示结构。柔性的显示面板是目前的一种发展趋势，但阵列基板中的各种无机膜由于其本身材质的原因，对显示面板的柔性造成了限制。
发明内容
本公开的一方面提供了一种阵列基板，包括：衬底基板；位于所述衬底基板上的有源层；位于所述有源层上的第一栅绝缘层；位于所述第一栅绝缘层上的第一栅极；以及位于所述第一栅极上的第二栅绝缘层。所述第二栅绝缘层包括沿远离所述有源层的方向设置的第一子绝缘层和第二子绝缘层，并且所述第一子绝缘层的氢含量大于所述第二子绝缘层的氢含量。
根据本公开的一些示例性实施例，所述第一子绝缘层的密度小于所述第二子绝缘层。
根据本公开的一些示例性实施例，所述第一子绝缘层的氢含量沿远离所述有源层的方向递减，并且所述第一子绝缘层在面向所述第二子绝缘层的表面处的氢含量大于所述第二子绝缘层在面向所述第一子绝缘层的表面处的氢含量。
根据本公开的一些示例性实施例，所述第二子绝缘层的氢含量沿远离所述有源层的方向递减，并且所述第一子绝缘层在面向所述第二子绝缘层的表面处的氢含量大于所述第二子绝缘层在面向所述第一子绝缘层的表面处的氢含量。
根据本公开的一些示例性实施例，所述第一子绝缘层和所述第二子绝缘层中的至少一个的氢含量沿远离所述有源层的方向是恒定的。
根据本公开的一些示例性实施例，所述第一子绝缘层的氢含量在大约30％-45％之间。
根据本公开的一些示例性实施例，上述阵列基板还包括贯穿所述第二栅绝缘层并且延伸到所述第一栅绝缘层中的凹槽，所述凹槽在所述衬底基板上的正投影位于所述有源层在所述衬底基板上的正投影的周围。
根据本公开的一些示例性实施例，所述第二栅绝缘层包括第一区域和第二区域，所述第一区域的厚度大于所述第二区域的厚度，所述有源层位于所述第一区域在所述衬底基板上的正投影中，并且所述第二区域为所述第二栅绝缘层中除所述第一区域外的区域。
根据本公开的一些示例性实施例，上述阵列基板还包括：位于所述第二栅绝缘层上的第二栅极；以及贯穿所述第二栅绝缘层和所述第一栅绝缘层的源漏极过孔，所述有源层通过所述源漏极过孔中露出。
根据本公开的一些示例性实施例，上述阵列基板还包括位于所述第二栅极上的中间介电层。
根据本公开的一些示例性实施例，所述阵列基板包括矩阵布置的多个子像素，并且所述第二栅绝缘层还包括设置在每个子像素之间的沟槽。
本公开的另一方面提供了一种显示面板，包括上述任一种阵列基板。
本公开另外的方面提供了一种制造阵列基板的方法，包括：在衬底基板上依次形成有源层、第一栅绝缘层和第一栅极；在形成有所述第一栅极的衬底基板上形成第二栅绝缘层，所述第二栅绝缘层包括沿远离所述有源层的方向设置的第一子绝缘层和第二子绝缘层，其中所述第一子绝缘层的氢含量大于所述第二子绝缘层的氢含量；以及对所述有源层进行氢化处理。
根据本公开的一些示例性实施例，所述在形成有所述第一栅极的衬底基板上形成第二栅绝缘层，包括：在形成有所述第一栅极的衬底基板上以第一沉积速度沉积形成所述第一子绝缘层；以及在形成由所述第一子绝缘层的衬底基板上以第二沉积速度沉积形成所述第二子绝 缘层，其中，所述第二沉积速度小于所述第一沉积速度。
根据本公开的一些示例性实施例，在对所述有源层进行氢化处理之前，所述方法还包括：在形成有所述第二栅绝缘层的衬底基板上形成第二栅极；在形成有所述第二栅极的衬底基板上形成源漏极过孔，所述有源层通过所述源漏极过孔中露出。
根据本公开的一些示例性实施例，在对所述有源层进行氢化处理之前，所述方法还包括：在形成有所述第二栅绝缘层的衬底基板上形成凹槽，所述凹槽的底部位于所述第一栅绝缘层中，并且所述凹槽在所述衬底基板上的正投影位于所述有源层在所述衬底基板上的正投影的周围。所述对所述有源层进行氢化处理，包括：将形成有所述凹槽的衬底基板设置在氢气氛围中，以对所述有源层进行氢化。
根据本公开的一些示例性实施例，在对所述有源层进行氢化处理之前，所述方法还包括：在形成有所述第二栅绝缘层的衬底基板上形成第二栅极；在形成有所述第二栅极的衬底基板上涂布硅基有机材料层；对所述硅基有机材料层进行烘烤；以及将所述硅基有机材料层处理为中间介电层。
根据本公开的一些示例性实施例，所述在形成有所述第一栅极的衬底基板上形成第二栅绝缘层，包括：通过灰度掩模工艺在形成有所述第一栅极的衬底基板上形成所述第二栅绝缘层。所述第二栅绝缘层包括第一区域和第二区域，所述第一区域的厚度大于所述第二区域的厚度，所述有源层位于所述第一区域在所述衬底基板上的正投影中，并且所述第二区域为所述第二栅绝缘层中除所述第一区域外的区域。
根据本公开的一些示例性实施例，所述阵列基板包括矩阵布置的多个子像素，所述方法还包括：在所述第二栅绝缘层中形成位于每个子像素之间的沟槽。
根据本公开的一些示例性实施例，所述有源层包括低温多晶硅和微晶硅中的一种或多种。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在 不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种阵列基板的制造方法的流程图；
图2是本公开实施例提供的另一种阵列基板的制造方法的流程图；
图3是图2所示的制造方法中一种衬底基板的结构示意图；
图4是图2所示的制造方法中另一种衬底基板的结构示意图；
图5是图2所示的制造方法中另一种衬底基板的结构示意图；
图6是图2所示的制造方法中另一种衬底基板的结构示意图；
图7是图2所示的制造方法中另一种衬底基板的结构示意图；
图8是图7所示的衬底基板的剖面图；
图9是图2所示的制造方法中另一种衬底基板的结构示意图；
图10是图2所示的制造方法中一种阵列基板的结构示意图；
图11是本公开实施例提供的另一种阵列基板的制造方法的流程图；
图12是图11所示的制造方法中一种衬底基板的结构示意图；
图13是图11所示的制造方法中另一种衬底基板的结构示意图；
图14是图11所示的制造方法中一种后续制造流程的流程图；
图15是图11所示的制造方法中另一种后续制造流程的流程图；以及
图16是图11所示的制造方法中一种阵列基板的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
随着柔性显示面板的发展，对显示面板的要求从可弯曲(英文：Bendable)，可弯折(英文：Foldable)，逐步过渡到具有弹性柔性(英文：Stretchable)。目前的柔性显示面板的阵列基板中，存在多层无机膜。当显示面板发生较为剧烈的形变时，阵列基板中的无机膜较容易发生碰撞和分离等现象，使得无机膜在碰撞和分离的过程中可能产生微小破损，该微小破损可以扩大为较大的裂纹，并影响显示面板的正 常运行。因此提出采用有机膜代替现有的无机膜层。
典型的柔性阵列基板的制造方法可以包括以下步骤：在衬底基板上依次形成由低温多晶硅(英文：Low Temperature Poly-silicon；简称：LTPS)制成的有源层、第一栅绝缘层、第一栅极、第二栅绝缘层和第二栅极；通过固态扩散法对形成有第二栅极的衬底基板中的有源层进行氢化处理，以提高有源层的电学性能；在形成有第二栅极的衬底基板上形成由有机材料构成的中间介电层(英文：inter-layer dielectric；简称：ILD)以提高阵列基板的柔性。由于有机材料相较于无机材料对于高温的耐受能力较差，因而需要在形成ILD之前对有源层进行氢化处理，以避免对ILD造成损坏。
氢化处理能够通过氢原子填补构成有源层的LTPS(或微晶硅)中的硅原子的未结合键或未饱和键，从而提高LTPS(或微晶硅)的电学性能。但是，对有源层进行有效的氢化处理所需的温度通常高于有机膜的耐受温度，使得有机膜会对有源层的氢化造成限制。已经提出在形成ILD之前对有源层进行氢化处理。然而，在这样的方案中，由于在未形成ILD时，衬底基板上的膜层中的氢含量较少，并且没有膜层阻挡氢从衬底基板中溢出，因此衬底基板上的膜层对于有源层的氢化能力不足，从而可能导致有源层的电学性能的降低。
有鉴于此，本公开实施例提供了一种改进的阵列基板的制造方法、阵列基板和显示面板。
图1是本公开实施例提供的一种阵列基板的制造方法的流程图
如图1所示，在步骤101处，在衬底基板上依次形成有源层、第一栅绝缘层和第一栅极，其中有源层包括低温多晶硅。
然后，在步骤102处，在形成有第一栅极的衬底基板上形成第二栅绝缘层，第二栅绝缘层包括沿远离有源层的方向设置的第一子绝缘层和第二子绝缘层，其中第一子绝缘层的氢含量大于第二子绝缘层的氢含量。
接着，在步骤103处，对有源层进行氢化处理。
在本公开实施例提供的上述阵列基板的制造方法中，通过形成包括氢含量较大的第一子绝缘层以及氢含量较小的第二子绝缘层的第二栅绝缘层，使得在氢化处理的过程中，第一子绝缘层可以充当氢源，而第二子绝缘层可以充当氢阻挡层，使得氢能够更好地向有源层的方 向扩散，从而提高氢浓度梯度向有源层方向的分布，以提高对于有源层的氢化作用因此避免了对于有源层的氢化不足，进而导致影响有源层的电学性能的问题，达到了提高有源层的电学性能的效果。
图2是本公开实施例提供的另一种阵列基板的制造方法的流程图。
如图2所示，在步骤201处，在衬底基板上依次形成有源层、第一栅绝缘层和第一栅极，其中有源层包括低温多晶硅和/或微晶硅。低温多晶硅或微晶硅的电子迁移率较高，因此包括LTPS或微晶硅的有源层能够提高薄膜晶体管(英文：Thin Film Transistor；简称：TFT)的响应速度。
在完成步骤201时，衬底基板的结构可以如图3所示，其中，衬底基板11上依次设置有有源层12、第一栅绝缘层13和第一栅极14。第一栅绝缘层13的材料可以包括氮化硅等材料。第一栅极14可以包括金属或其他导电材料，本公开实施例不进行限制。
在示例性实施例中，有源层由LTPS构成，并且形成由LTPS构成的有源层的过程可以包括以下步骤：
首先，对非晶硅(a-si)进行脱氢处理。当非晶硅中的氢含量过多时，由该非晶硅形成的多晶硅的质量会下降。因而，可以首先对非晶硅进行脱氢处理。可选地，可以通过脱氢处理使非晶硅中的含氢量小于2％。
接着通过非晶硅在衬底基板上形成非晶硅层。然后，对该非晶硅层进行低温退火，使非晶硅层转变为多晶硅层。具体地，可以通过激光退火技术来实施低温退火工艺。最后，通过构图工艺图案化多晶硅层，以形成有源层。该有源层可以包括衬底基板上的多个TFT中的有源层图案。典型地，构图工艺可以包括光刻胶的涂覆、对光刻胶的曝光、对光刻胶的显影、刻蚀和对光刻胶的剥离等步骤。
如本领域技术人员所知的，形成由微晶硅构成的有源层的过程可以参考以上所描述的形成由LTPS构成的有源层的过程以及相关技术，在此不再赘述。
可选地，衬底基板可以为柔性衬底基板，该衬底基板可以由聚酰亚胺基底或包括聚酰亚胺基底的复合膜层构成，例如，衬底基板可以包括聚酰亚胺以及依次设置在聚酰亚胺上的间隔层、聚酰亚胺基底和缓冲层。
返回到图2，在步骤202处，在形成有第一栅极的衬底基板上以第一沉积速度沉积形成第一子绝缘层，并增加第一子绝缘层的氢含量。特别地，第一沉积速度可以是相关技术中形成常规的第二栅绝缘层的速度。
可选地，可以通过化学气相沉积(英文：Chemical Vapor Deposition；简称：CVD)技术来形成第一子绝缘层，并且可以通过增加含氢的反应气体的流量来增加第一子绝缘层的氢含量。例如，若第一子绝缘层由氮化硅构成，则反应气体可以包括氨气(化学式：NH 3)和硅烷(化学式：SiH 4)。相应地，可以提高NH 3的流量至正常水平的1.1倍至1.5倍，以将第一子绝缘层的氢含量提高至1.1倍至1.5倍。经过该过程，第一子绝缘层中的氢含量(原子比例)可以在30％至45％左右。
第一子绝缘层可以具有均匀的氢含量。可替换地，在示例性实施例中，第一子绝缘层的氢含量沿远离有源层的方向递减。也就是说，第一子绝缘层在第一子绝缘层和第一栅绝缘层的交界面处的氢含量是最高的，并且沿远离有源层的方向氢含量逐渐递减。以此方式能够提高氢原子向有源层扩散的能力，且能够避免第一子绝缘层下方膜层中的氢向第一子绝缘层扩散的可能性。
可替换地，第一子绝缘层的氢含量也可以从远离有源层的一侧开始，沿靠近有源层的方向在100埃至300埃的厚度范围内递增。以此方式能够提高氢原子向有源层扩散的能力，且能够避免第一子绝缘层下方膜层中的氢向第一子绝缘层扩散的可能性。
如本文中所使用的，术语“厚度”是指沿垂直于衬底基板的方向上的尺寸。
当完成步骤202时，衬底基板的结构可以如图4所示，其中形成有第一栅极14的衬底基板11上形成有第一子绝缘层151。图4中其他标记的含义可以参考图3，在此不再赘述。
在步骤203处，以第二沉积速度沉积形成第二子绝缘层，其中第二沉积速度小于第一沉积速度。
通过降低第二子绝缘层的沉积速度，能够提高第二子绝缘层的密度，使第二子绝缘层比第一子绝缘层更加致密。以此方式，能够提高第二子绝缘层对于氢的阻挡作用，使得第二子绝缘层下方膜层中的氢难以穿过第二子绝缘层而向外扩散，从而进一步提高了对于有源层的 氢化效果。
可替换地，第二子绝缘层的沉积速度也可以和第一子绝缘层的沉积速度相同，本公开实施例不进行限制。
在示例性实施例中，第一子绝缘层和第二子绝缘层可以均具有均匀的氢含量，且第一子绝缘层的氢含量大于第二子绝缘层的氢含量。可替换地，第一子绝缘层具有沿远离有源层的方向递减的氢含量，第二子绝缘层具有均匀的氢含量，并且第二子绝缘层的氢含量小于第一子绝缘层的最小氢含量，以使得能够提高氢原子向有源层扩散的能力，且能够避免第二子绝缘层下方膜层中的氢通过第二子绝缘层向外扩散的可能性。可替换地，第一子绝缘层具有均匀的氢含量，第二子绝缘层具有沿远离第一子绝缘层的方向递减的氢含量，并且第一子绝缘层的氢含量大于第二子绝缘层的最大氢含量，以使得能够提高氢原子向有源层扩散的能力，且能够避免第二子绝缘层下方膜层中的氢通过第二子绝缘层向外扩散的可能性。在上述实施例中，第二子绝缘层中的氢含量(原子比例)可以在15％至30％左右。
可选地，第二子绝缘层和第一子绝缘层之间的厚度比可以在1∶0.5到1∶2之间。
在完成步骤203时，衬底基板的结构可以如图5所示，其中，形成有第一子绝缘层151的衬底基板11上形成有第二子绝缘层152，并且第一子绝缘层151和第二子绝缘层152构成第二绝缘层15。图5中其他标记的含义可以参考图3，在此不再赘述。
第一子绝缘层和第二子绝缘层可以是在一次化学气相沉积中形成的同一膜层的不同部分(沿厚度方向的不同部分)，也可以是分别形成的两个膜层。当第一子绝缘层和第二子绝缘层为同一膜层的不同部分时，相较于第一子绝缘层和第二子绝缘层为不同膜层的情况，膜层间的应力减小，因而降低了膜层破损的风险。
在步骤204处，在形成有第二栅绝缘层的衬底基板上形成第二栅极。该第二栅极能够与第一栅极形成电容，以提高TFT中电容的保持能力，进而增强显示结构的显示效果。
在完成步骤204时，衬底基板的结构可以如图6所示，其中，形成有第二栅绝缘层15的衬底基板11上形成有第二栅极16。图6中其他标记的含义可以参考图3，在此不再赘述。
在形成第二栅极后，可以通过加热形成有各个膜层的衬底基板以对有源层进行活化工艺。在加热时，可以缓慢提升温度，使得膜层之间的应力变动可以较和缓地进行，以避免各个膜层之间的应力不匹配导致的膜层破裂问题。
在步骤205处，在形成有第二栅极的衬底基板上形成源漏极过孔，使得有源层从该源漏极过孔中露出。
步骤205可以在步骤204之后且在步骤209之前的任何阶段执行，例如可以在对有源层氢化之后形成源漏极过孔，或在形成中间介电层之后形成源漏极过孔。在示例性实施例中，在对有源层氢化前形成源漏极过孔，从而能够在一定程度上提高对有源层的氢化效果。
在完成步骤205时，衬底基板的结构可以如图7所示，其中，有源层12在源漏极过孔k中露出，因此后续形成的源极和漏极可以通过该过孔k与有源层接触。图7中其他标记的含义可以参考图3，在此不再赘述。
在步骤206处，在形成有第二栅绝缘层的衬底基板上形成凹槽，凹槽的底部位于第一栅绝缘层中，并且凹槽在衬底基板上的正投影位于有源层的周围。该凹槽用于提高对于有源层的氢化作用，并且该凹槽在衬底基板上的正投影的面积不大于源漏极过孔在衬底基板上的正投影的面积。
在完成步骤206时，衬底基板的结构可以如图8所示，并且其为图7所示的衬底基板在P-P处的剖面图。凹槽c穿过第二绝缘层15，其底部位于第一绝缘层13中，且凹槽c在衬底基板11上的正投影位于有源层12的周围。图8中其他标记的含义可以参考图3，在此不再赘述。
在步骤207处，将形成有所述凹槽的衬底基板置于氢气氛围中，以对所述有源层进行氢化。
在将形成有所述凹槽的衬底基板设置在氢气氛围中后，由于外界环境中氢的浓度较高，因而衬底基板上各个膜层中的氢难以溢出到外界环境中，且氢的浓度能够形成沿外界环境向有源层方向逐渐下降的趋势，从而有利于氢气向有源层中的移动。此外，如图8所示，在氢气氛围中，氢气会充满凹槽c，这使得高浓度的氢气与有源层12的距离较近，从而进一步有利于氢向有源层中的移动。
可选地，氢气氛围可以仅包括氢气，也可以包括氢气和氮气，其中，氢气的分压不小于200毫托(英文：mTorr)。
在步骤208处，在形成有凹槽的衬底基板上形成中间介电层。中间介电层可以由有机绝缘材料构成。在具体实施时，可以首先在形成有凹槽的衬底基板上形成有机绝缘材料层，之后通过构图工艺将有机绝缘材料层图案化为中间介电层。如果在形成中间介电层之前源漏极过孔已经形成，则需要刻蚀掉源漏极过孔中的有机绝缘材料，使源漏极过孔中的有源层露出。此外，若衬底基板的膜层上形成有凹槽，则可以通过有机绝缘材料层填充该凹槽，以提高衬底基板上各个膜层的平整度。
特别地，中间介电层可以由光刻胶材料构成。在具体实施时，可以首先在形成有凹槽的衬底基板上形成光刻胶材料层，例如厚度在0.2微米至0.3微米之间，之后通过曝光工艺和显影工艺形成中间介电层。若在形成中间介电层之前源漏极过孔已经形成，则需要对源漏极过孔中的光刻胶材料进行曝光和显影，以去除源漏极过孔中的光刻胶材料，使源漏极过孔中的有源层露出。此外，若衬底基板的膜层上形成有凹槽，则可以通过该光刻胶材料填充该凹槽，并在曝光显影后保留该凹槽中的光刻胶材料，以提高衬底基板上各个膜层的平整度。
在完成步骤208时，衬底基板的结构可以如图9所示，其中，中间介电层17形成在形成有第二栅极16的衬底基板上，并且源漏极过孔k同样贯穿中间介电层17。
在步骤209处，在形成有中间介电层的衬底基板上形成源漏极。
在完成步骤209时，衬底基板的结构可以如图10所示，其中，源漏极18通过源漏极过孔与有源层12接触。
综上所述，在本公开实施例提供的阵列基板的制造方法中，通过形成包括氢含量较大的第一子绝缘层以及氢含量较小的第二子绝缘层，可以使得在对有源层进行氢化处理的过程中，第一子绝缘层充当氢源，第二子绝缘层充当氢阻挡层，因而氢能够更好地向有源层的方向扩散，从而提高氢浓度梯度向有源层方向的分布，提高对于有源层的氢化作用。以此方式，可以避免对于有源层的氢化不足，进而导致影响有源层的电学性能的问题，提高了有源层的电学性能。
图11是本公开实施例提供的另一种阵列基板的制造方法的流程图。
如图11所示，在步骤301处，在衬底基板上依次形成有源层、第一栅绝缘层和第一栅极，其中有源层可以包括低温多晶硅。
本步骤可以参考上述实施例中的步骤201，在此不再赘述。
在步骤302处，通过灰度掩模工艺在形成有第一栅极的衬底基板上形成第二栅绝缘层。特别地，第二栅绝缘层包括第一区域和第二区域，第一区域的厚度大于第二区域的厚度，有源层位于第一区域在衬底基板上的正投影中(该正投影的边缘与最近的有源层的边缘的距离可以在1微米至5微米之间)，并且第二区域为第二栅绝缘层中除第一区域外的区域。由于位于有源层正上方的第一区域的绝缘层较厚，因而能够在后续的氢化处理过程中提供较多的氢，从而有利于对于有源层的氢化。示例性的，第一区域的厚度可以为第二区域的厚度的1.1倍至1.3倍。
可选地，第二栅绝缘层在该阵列基板中的每个子像素之间还设置有沟槽。该沟槽能够减小连续磨蹭应力，避免膜层的损坏。该沟槽处的第二绝缘层的厚度例如可以为第二区域的厚度的0.1倍至0.5倍。此外，在子像素之间的第二栅极的走线位置也可以设置有沟槽。
如本文中所使用的，灰度掩模工艺是一种通过灰度掩模板进行曝光的工艺，而灰度掩模板是一种在不同区域可以具有不同光透过率的掩模板。通过使用此种掩模板，能够形成不同区域厚度不同的图案。在步骤302中，可以通过灰度掩模工艺形成在不同区域厚度不同的第二栅绝缘层。
可选地，本公开实施例通过灰度掩模工艺形成的第二栅绝缘层的结构还可以参考上述实施例中步骤202和步骤203，即该第二绝缘层可以包括沿远离有源层的方向上依次布置的含氢量较高的第一子绝缘层和含氢量较低的第二子绝缘层，从而进一步提高对于有源层的氢化效果。
在完成步骤302时，衬底基板的结构可以如图12所示，其中第一区域q1的厚度大于第二区域q2的厚度，并且在子像素和子像素之间设置有沟槽g。
在步骤303处，在形成有第二栅绝缘层的衬底基板上形成第二栅极。本步骤可以参考上述实施例中的步骤204，在此不再赘述。在形成第二栅极之后，由于第二区域的绝缘层较薄，因而在第二区域处第二 栅极和第一栅极之间能够形成更大的电容，从而提高了TFT的电学性能。
在完成步骤303时，衬底基板的结构可以如图13所示，其中，第一栅极14和第二栅极16之间的第二绝缘层15较薄，因而第一栅极14和第二栅极16之间能够形成较大的电容。
之后，如图14所示，在步骤304处，在形成有第二栅极的衬底基板上形成源漏极过孔，使得有源层在源漏极过孔中露出。该源漏极过孔的结构可以参考图7中的源漏极过孔k，在此不再赘述。
然后，在步骤305处，对有源层进行氢化处理。本步骤可以参考上述实施例中的步骤207，在此不再赘述。
此外，本公开实施例在对有源层进行氢化前，也可以在衬底基板上的各个膜层上形成如图8中所示的凹槽c。该过程可以参考上述实施例中的步骤206，在此不再赘述。
在步骤306处，在形成有第二栅极的衬底基板上形成中间介电层。本步骤可以参考上述实施例中的步骤208，在此不再赘述。
最后，在步骤307处，在形成有源漏极过孔的衬底基板上形成源漏极。本步骤可以参考上述实施例中的步骤209，在此不再赘述。
在可替换的实施例中，在完成步骤303之后，如图15所示，可以进行与图14不同的后续步骤。
在步骤308处，在形成有第二栅极的衬底基板上涂布硅基有机材料层。
硅基有机材料为对于温度的耐受能力较强的一种有机材料，因而可以在氢化处理前涂布硅基有机材料层以便在后续的升温过程中保持可靠性。
接着，在步骤309处，对硅基有机材料层进行烘烤。烘烤能够去除硅基有机材料中混入的水分以及一些其它溶剂，提高硅基有机材料层的密度，进而能够提高硅基有机材料层对于氢的阻挡能力。另外，对硅基有机材料层进行烘烤的同时能够对有源层进行活化。
然后，在步骤310处，将硅基有机材料层处理为中间介电层。
可以通过不同的方式来形成中间介电层，本步骤可以参考上述实施例中的步骤208，在此不再赘述。
在步骤311处，对有源层进行氢化处理。在氢化处理时，可以使 用由硅基有机材料构成的中间介电层来阻挡衬底基板上各膜层的氢向外部溢出，以提高对于有源层的氢化效果。本步骤可以参考上述实施例中的步骤207，在此不再赘述。
接着，在步骤312处，在形成有中间介电层的衬底基板上形成源漏极过孔。当然，步骤312还可以在步骤311之前执行，即可以在氢化处理之前形成源漏极过孔，本公开实施例对此不进行限制。
在步骤313处，在形成有源漏极过孔的衬底基板上形成源漏极。本步骤可以参考上述实施例中的步骤209，在此不再赘述。
当完成步骤313时，衬底基板的结构可以如图16所示，其中中间介电层17形成于形成有第二栅极16的衬底基板上，形成有中间介电层17的衬底基板上形成有源漏极18，源漏极18通过源漏极过孔与有源层12接触。
综上所述，在本公开实施例提供的上述阵列基板的制造方法中，通过形成包括氢含量较大的第一子绝缘层以及氢含量较小的第二子绝缘层，可以使得在对有源层氢化处理的过程中，第一子绝缘层充当氢源，第二子绝缘层充当阻挡层，进而使得氢能够更好地向有源层的方向扩散，提高氢浓度梯度向有源层方向的分布，提高对于有源层的氢化作用。以此方式，可以避免对于有源层的氢化不足，进而导致影响有源层的电学性能的问题，提高了有源层的电学性能。
本公开实施例还提供了一种阵列基板，该阵列基板是通过上述任一种方法制造的阵列基板，例如图10所示的阵列基板或图16所示的阵列基板。
如图10和16所示，阵列基板包括：衬底基板11；位于衬底基板11上的有源层12；位于有源层12上的第一栅绝缘层13；位于第一栅绝缘层13上的第一栅极14；以及位于第一栅极14上的第二栅绝缘层15。第二栅绝缘层15包括沿远离有源层12的方向设置的第一子绝缘层151和第二子绝缘层152，并且第一子绝缘层151的氢含量大于第二子绝缘层152的氢含量。
上述阵列基板的其他示例性实施例可以参照上述阵列基板的制造方法的描述，在此不再赘述。
本公开实施例还提供了一种显示面板，该显示面板包括上述任一种阵列基板。该显示面板可以为有机发光二极管(英文：Organic  Light-Emitting Diode；简称：OLED)显示面板或液晶显示面板。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
进一步地，在本文中，尽管采用某种顺序描述了方法的实施例，但是该描述的顺序并不构成对该方法实施例的执行顺序的限制。本领域技术人员鉴于本公开中的教导，可以适应性地调整各个方法步骤的执行顺序。
在本公开中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板上的有源层；
    位于所述有源层上的第一栅绝缘层；
    位于所述第一栅绝缘层上的第一栅极；以及
    位于所述第一栅极上的第二栅绝缘层，
    其中，所述第二栅绝缘层包括沿远离所述有源层的方向设置的第一子绝缘层和第二子绝缘层，并且所述第一子绝缘层的氢含量大于所述第二子绝缘层的氢含量。
  2. 根据权利要求1所述的阵列基板，其中，所述第一子绝缘层的密度小于所述第二子绝缘层。
  3. 根据权利要求1所述的阵列基板，其中，所述第一子绝缘层的氢含量沿远离所述有源层的方向递减，并且所述第一子绝缘层在面向所述第二子绝缘层的表面处的氢含量大于所述第二子绝缘层在面向所述第一子绝缘层的表面处的氢含量。
  4. 根据权利要求1所述的阵列基板，其中，所述第二子绝缘层的氢含量沿远离所述有源层的方向递减，并且所述第一子绝缘层在面向所述第二子绝缘层的表面处的氢含量大于所述第二子绝缘层在面向所述第一子绝缘层的表面处的氢含量。
  5. 根据权利要求1所述的阵列基板，其中，所述第一子绝缘层和所述第二子绝缘层中的至少一个的氢含量沿远离所述有源层的方向是恒定的。
  6. 根据权利要求1所述的阵列基板，其中，所述第一子绝缘层的氢含量在大约30％-45％之间。
  7. 根据权利要求1所述的阵列基板，还包括贯穿所述第二栅绝缘层并且延伸到所述第一栅绝缘层中的凹槽，所述凹槽在所述衬底基板上的正投影位于所述有源层在所述衬底基板上的正投影的周围。
  8. 根据权利要求1所述的阵列基板，其中，
    所述第二栅绝缘层包括第一区域和第二区域，
    所述第一区域的厚度大于所述第二区域的厚度，
    所述有源层位于所述第一区域在所述衬底基板上的正投影中，并且
    所述第二区域为所述第二栅绝缘层中除所述第一区域外的区域。
  9. 根据权利要求1所述的阵列基板，还包括：
    位于所述第二栅绝缘层上的第二栅极；以及
    贯穿所述第二栅绝缘层和所述第一栅绝缘层的源漏极过孔，所述有源层通过所述源漏极过孔中露出。
  10. 根据权利要求1所述的阵列基板，还包括位于所述第二栅极上的中间介电层。
  11. 根据权利要求1所述的阵列基板，其中所述阵列基板包括矩阵布置的多个子像素，并且所述第二栅绝缘层还包括设置在每个子像素之间的沟槽。
  12. 一种显示面板，包括权利要求1-11中任一项所述的阵列基板。
  13. 一种制造阵列基板的方法，包括：
    在衬底基板上依次形成有源层、第一栅绝缘层和第一栅极；
    在形成有所述第一栅极的衬底基板上形成第二栅绝缘层，所述第二栅绝缘层包括沿远离所述有源层的方向设置的第一子绝缘层和第二子绝缘层，其中所述第一子绝缘层的氢含量大于所述第二子绝缘层的氢含量；以及
    对所述有源层进行氢化处理。
  14. 根据权利要求13所述的方法，其中，所述在形成有所述第一栅极的衬底基板上形成第二栅绝缘层，包括：
    在形成有所述第一栅极的衬底基板上以第一沉积速度沉积形成所述第一子绝缘层；以及
    在形成由所述第一子绝缘层的衬底基板上以第二沉积速度沉积形成所述第二子绝缘层，
    其中，所述第二沉积速度小于所述第一沉积速度。
  15. 根据权利要求13所述的方法，其中，在对所述有源层进行氢化处理之前，所述方法还包括：
    在形成有所述第二栅绝缘层的衬底基板上形成第二栅极；
    在形成有所述第二栅极的衬底基板上形成源漏极过孔，所述有源层通过所述源漏极过孔中露出。
  16. 根据权利要求13所述的方法，其中，在对所述有源层进行氢化处理之前，所述方法还包括：
    在形成有所述第二栅绝缘层的衬底基板上形成凹槽，所述凹槽的底部位于所述第一栅绝缘层中，并且所述凹槽在所述衬底基板上的正投影位于所述有源层在所述衬底基板上的正投影的周围，并且
    所述对所述有源层进行氢化处理，包括：
    将形成有所述凹槽的衬底基板设置在氢气氛围中，以对所述有源层进行氢化。
  17. 根据权利要求13所述的方法，其中，在对所述有源层进行氢化处理之前，所述方法还包括：
    在形成有所述第二栅绝缘层的衬底基板上形成第二栅极；
    在形成有所述第二栅极的衬底基板上涂布硅基有机材料层；
    对所述硅基有机材料层进行烘烤；以及
    将所述硅基有机材料层处理为中间介电层。
  18. 根据权利要求13所述的方法，其中，所述在形成有所述第一栅极的衬底基板上形成第二栅绝缘层，包括：
    通过灰度掩模工艺在形成有所述第一栅极的衬底基板上形成所述第二栅绝缘层，
    其中，所述第二栅绝缘层包括第一区域和第二区域，所述第一区域的厚度大于所述第二区域的厚度，所述有源层位于所述第一区域在所述衬底基板上的正投影中，并且所述第二区域为所述第二栅绝缘层中除所述第一区域外的区域。
  19. 根据权利要求13所述的方法，其中，所述阵列基板包括矩阵布置的多个子像素，所述方法还包括：
    在所述第二栅绝缘层中形成位于每个子像素之间的沟槽。
  20. 根据权利要求13所述的方法，其中，所述有源层包括低温多晶硅和微晶硅中的一种或多种。
PCT/CN2019/088100 2018-05-24 2019-05-23 阵列基板及其制造方法、显示面板 WO2019223755A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/641,372 US11296122B2 (en) 2018-05-24 2019-05-23 Array substrate, method for fabricating the same and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810508747.6 2018-05-24
CN201810508747.6A CN108598093B (zh) 2018-05-24 2018-05-24 阵列基板的制造方法、阵列基板和显示面板

Publications (1)

Publication Number Publication Date
WO2019223755A1 true WO2019223755A1 (zh) 2019-11-28

Family

ID=63629011

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/088100 WO2019223755A1 (zh) 2018-05-24 2019-05-23 阵列基板及其制造方法、显示面板

Country Status (3)

Country Link
US (1) US11296122B2 (zh)
CN (1) CN108598093B (zh)
WO (1) WO2019223755A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598093B (zh) 2018-05-24 2021-01-15 京东方科技集团股份有限公司 阵列基板的制造方法、阵列基板和显示面板
CN109148596B (zh) * 2018-08-17 2021-06-04 武汉华星光电半导体显示技术有限公司 低温多晶硅薄膜晶体管及其制作方法
CN111081714B (zh) * 2018-10-19 2022-11-04 京东方科技集团股份有限公司 柔性阵列基板及其制备方法、显示面板
CN109786440A (zh) * 2018-12-25 2019-05-21 惠科股份有限公司 阵列基板的制造方法、装置及阵列基板
CN110176397B (zh) * 2019-04-18 2021-03-02 京东方科技集团股份有限公司 一种有源层接触孔的刻蚀方法及阵列基板的电路检测方法
KR102704437B1 (ko) * 2019-06-13 2024-09-09 삼성디스플레이 주식회사 박막트랜지스터 기판 및 이를 구비한 디스플레이 장치
US20230035664A1 (en) * 2019-12-13 2023-02-02 Huawei Technologies Co., Ltd. Display and electronic device
CN111308850A (zh) * 2020-02-21 2020-06-19 京东方科技集团股份有限公司 掩膜板、tft的制备方法、tft及阵列基板
CN112768470A (zh) * 2020-12-30 2021-05-07 厦门天马微电子有限公司 一种显示面板及显示装置
CN113985667B (zh) * 2021-10-12 2023-08-01 Tcl华星光电技术有限公司 阵列基板及其制备方法、液晶显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1445862A (zh) * 2002-03-11 2003-10-01 三洋电机株式会社 顶栅型薄膜晶体管
CN105655353A (zh) * 2016-01-21 2016-06-08 武汉华星光电技术有限公司 Tft阵列基板结构及其制作方法
CN106783628A (zh) * 2017-02-27 2017-05-31 武汉华星光电技术有限公司 薄膜晶体管的制作方法、薄膜晶体管及显示器
CN107068771A (zh) * 2017-06-01 2017-08-18 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管及其制造方法
CN107819021A (zh) * 2017-11-06 2018-03-20 武汉华星光电半导体显示技术有限公司 一种柔性oled显示面板的制备方法及柔性oled显示面板
CN108598093A (zh) * 2018-05-24 2018-09-28 京东方科技集团股份有限公司 阵列基板的制造方法、阵列基板和显示面板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102645811B (zh) * 2011-11-23 2014-07-02 京东方科技集团股份有限公司 电子纸有源基板及其制造方法和电子纸显示屏
CN103022147A (zh) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 阵列基板及其制备方法、薄膜晶体管及显示装置
CN103985637B (zh) 2014-04-30 2017-02-01 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及其制作方法和显示装置
US9985082B2 (en) * 2016-07-06 2018-05-29 Lg Display Co., Ltd. Organic light emitting display device comprising multi-type thin film transistor and method of manufacturing the same
US10490756B2 (en) 2017-11-06 2019-11-26 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Method for fabricating flexible OLED panel and flexible OLED panel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1445862A (zh) * 2002-03-11 2003-10-01 三洋电机株式会社 顶栅型薄膜晶体管
CN105655353A (zh) * 2016-01-21 2016-06-08 武汉华星光电技术有限公司 Tft阵列基板结构及其制作方法
CN106783628A (zh) * 2017-02-27 2017-05-31 武汉华星光电技术有限公司 薄膜晶体管的制作方法、薄膜晶体管及显示器
CN107068771A (zh) * 2017-06-01 2017-08-18 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管及其制造方法
CN107819021A (zh) * 2017-11-06 2018-03-20 武汉华星光电半导体显示技术有限公司 一种柔性oled显示面板的制备方法及柔性oled显示面板
CN108598093A (zh) * 2018-05-24 2018-09-28 京东方科技集团股份有限公司 阵列基板的制造方法、阵列基板和显示面板

Also Published As

Publication number Publication date
CN108598093B (zh) 2021-01-15
US11296122B2 (en) 2022-04-05
CN108598093A (zh) 2018-09-28
US20210375952A1 (en) 2021-12-02

Similar Documents

Publication Publication Date Title
WO2019223755A1 (zh) 阵列基板及其制造方法、显示面板
CN107302032B (zh) 一种薄膜晶体管及其制作方法、阵列基板、显示面板
WO2018214727A1 (zh) 柔性显示基板及其制作方法、显示装置
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
CN107425044B (zh) 一种柔性显示面板、其制作方法及显示装置
WO2018157601A1 (zh) 过孔的制备方法、阵列基板的制备方法及阵列基板
CN105304722B (zh) 一种薄膜晶体管及其制备方法、显示基板、显示装置
JP2017508275A (ja) 低温ポリシリコン薄膜トランジスタ及びその製造方法
WO2017202057A1 (zh) 电子器件、薄膜晶体管、以及阵列基板及其制作方法
JP2020520557A (ja) Ｏｌｅｄ表示パネルおよびその製造方法
US10361261B2 (en) Manufacturing method of TFT substrate, TFT substrate, and OLED display panel
US7923312B2 (en) Fabricating method of thin film transistor
WO2016065780A1 (zh) 显示基板及其制作方法、显示装置
WO2016090807A1 (zh) 阵列基板及其制作方法、显示装置
US20200219955A1 (en) Array substrate and manufacturing method thereof
US10115745B2 (en) TFT array substrate and method of forming the same
US20210225877A1 (en) Display substrate and manufacturing method thereof, display device
US10249654B1 (en) Manufacturing method of top-gate TFT and top-gate TFT
JP2014229709A (ja) 薄膜トランジスタの製造方法及び薄膜トランジスタ
WO2019119584A1 (zh) 阵列基板及其制造方法
WO2017143636A1 (zh) 一种薄膜晶体管及其制备方法
US10825930B2 (en) Thin film transistor and manufacture method thereof
US20070264597A1 (en) Method for manufacturing transflective liquid crystal display
US10714504B2 (en) Low temperature poly-silicon thin film transistor array substrate and method of producing the same
US20200403102A1 (en) Electrode structure and manufacturing method thereof, thin film transistor, and array substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19808209

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 26/04/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19808209

Country of ref document: EP

Kind code of ref document: A1