WO2018157601A1 - 过孔的制备方法、阵列基板的制备方法及阵列基板 - Google Patents
过孔的制备方法、阵列基板的制备方法及阵列基板 Download PDFInfo
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- WO2018157601A1 WO2018157601A1 PCT/CN2017/105380 CN2017105380W WO2018157601A1 WO 2018157601 A1 WO2018157601 A1 WO 2018157601A1 CN 2017105380 W CN2017105380 W CN 2017105380W WO 2018157601 A1 WO2018157601 A1 WO 2018157601A1
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- insulating layer
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- insulator layer
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- H01L21/31155—Doping the insulating layers by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Definitions
- Embodiments of the present disclosure relate to a method of fabricating a via, a method of fabricating an array substrate, and an array substrate.
- the quality of the display substrate is important, and in the preparation method for preparing the display substrate, it is necessary to deposit an insulating layer on the display substrate on which the thin film transistor has been formed, using The dry etching technique etches on the insulating layer to form via holes, and then forms a pixel electrode on the insulating layer, through which the pixel electrode can be electrically connected to the thin film transistor for data transmission.
- the dry etching technique etches on the insulating layer to form via holes, and then forms a pixel electrode on the insulating layer, through which the pixel electrode can be electrically connected to the thin film transistor for data transmission.
- the insulating layer has a multi-layered insulator layer structure, and the etching rates of the respective insulator layers are different.
- the etching rate of the bottommost insulator layer is greater than the etching rate of the insulator layer above it, resulting in the etching of the bottommost insulator layer too fast, and the via forms an internal stepped barb angle at the bottom of the insulating layer, resulting in poor undercut .
- the poor undercut causes the contact between the pixel electrode and the source/drain electrode layer of the thin film transistor to cross, which causes the display device to display abnormality or display, reducing the quality and yield of the display device.
- At least one embodiment of the present disclosure provides a method of fabricating a via, comprising: providing a substrate; forming an insulating layer on the substrate; etching the insulating layer by a first etching process to Forming a recess in the insulating layer; ion-implanting a portion of the insulating layer exposed by the recess to form an ion implantation region; etching the insulating layer in the ion implantation region by a second etching process A via hole penetrating the insulating layer is formed.
- At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including the method for preparing the via.
- At least one embodiment of the present disclosure provides an array substrate including: a substrate substrate; an insulating layer disposed on the substrate; and a via penetrating the insulating layer.
- the insulating layer includes a first insulator layer and a second insulator layer sequentially disposed on the base substrate, the first insulator layer including a first portion adjacent to the via and a second portion away from the via The density of the first portion is greater than the density of the second portion.
- At least one embodiment of the present disclosure provides a method of fabricating a via, a method of fabricating an array substrate, and an array substrate.
- the method for preparing the via hole utilizes an ion implantation process to perform ion implantation on the insulating layer to increase the density of the insulating layer in the ion implantation region, thereby avoiding the undercut chamfering caused by severe lateral etching, and improving the via hole.
- the quality ensures the effectiveness of the via hole, improves or eliminates the problem that the contact between the pixel electrode and the source/drain electrode layer electrically connected by the via hole is broken, and improves the electric power between the pixel electrode and the source/drain electrode layer.
- the stability of the connection improves the quality and yield of the product.
- 1 is a schematic structural view of a via of an insulating layer
- FIG. 2 is a flow chart of a method for preparing a via hole according to an embodiment of the present disclosure
- 3a-3f are process diagrams of a method for fabricating vias according to an embodiment of the present disclosure.
- 4a-4c are process diagrams of a method of fabricating an array substrate according to an embodiment of the present disclosure.
- FIG. 1 is a schematic structural view of a via of an insulating layer.
- an insulating layer needs to be deposited on the thin film transistor, and then a via hole is formed on the insulating layer by a dry etching technique, and finally a pixel electrode is formed on the surface of the insulating layer, and the pixel electrode passes through
- the via is electrically connected to a source or a drain of the thin film transistor.
- an insulating layer and a pixel electrode 66 are sequentially disposed on the base substrate 60.
- the insulating layer includes a via hole 73 penetrating the insulating layer, and the pixel electrode 66 can pass through the via hole 73 and be disposed on the base substrate 60.
- the upper source and drain electrode layers (not shown) are electrically connected.
- the insulating layer may include a transition layer 70, a body layer 71, and a top layer 72, which are generally etched at a higher rate than the body layer 71 and the top layer 72.
- the transition layer 70 may cause lateral etching, thereby causing the via 73 to form an inner stepped barb angle 75 at the bottom of the transition layer 70, resulting in Poor undercut, poor undercut will cause the pixel electrode 66 to break at the barb angle 75, causing contact between the pixel electrode 66 and the source/drain electrode layer to break, resulting in abnormal display or display, reducing product yield and quality.
- At least one embodiment of the present disclosure provides a method of fabricating a via, a method of fabricating an array substrate, and an array substrate.
- the method for preparing the via hole comprises: providing a substrate; forming an insulating layer on the substrate; etching the insulating layer by a first etching process to form a recess in the insulating layer; The portion of the insulating layer exposed by the recess is ion-implanted to form an ion implantation region; the second etching process is used to etch the insulating layer in the ion implantation region to form a via hole penetrating the insulating layer .
- the method for preparing the via hole utilizes an ion implantation process to perform ion implantation on the insulating layer to increase the density of the insulating layer in the ion implantation region, thereby avoiding the undercut chamfering caused by severe lateral etching, and improving the via hole.
- the quality ensures the effectiveness of the via hole, improves or eliminates the problem that the contact between the pixel electrode and the source/drain electrode layer electrically connected by the via hole is broken, and improves the electric power between the pixel electrode and the source/drain electrode layer.
- the stability of the connection improves product yield and quality.
- At least one embodiment of the present disclosure provides a method of preparing a via.
- 2 is a flow chart showing a method of preparing a via hole provided by an embodiment of the present disclosure
- FIGS. 3a-3f are process diagrams showing a method of fabricating a via hole provided by an embodiment of the present disclosure.
- Figures 3a-3f show only a portion of the related structure for clarity of illustration.
- a method for preparing a via hole provided by an embodiment of the present disclosure includes the following steps:
- S05 etching the insulating layer of the ion implantation region by using a second etching process to form a via hole penetrating the insulating layer.
- the method for preparing the via hole utilizes an ion implantation process to ion-implant the portion of the insulating layer exposed by the groove to increase the density of the insulating layer in the ion implantation region, thereby preventing the undercut chamfer from being severely laterally etched. Improves the quality of the vias and ensures the effectiveness of the vias.
- a base substrate 10 is provided, an insulating layer 2 is deposited on the base substrate 10, and a layer of photoresist 32 is coated on the insulating layer 2.
- depositing the insulating layer 2 may include sequentially depositing a first insulating sub-layer 21, a second insulating sub-layer 22, and a third insulating sub-layer 23 on the base substrate 10.
- the deposition process parameters of the deposition insulating layer 2 may be controlled such that the first insulator layer 21, the second insulator layer 22, and the third insulator layer 23 have different densities, and the deposition process parameters may include, for example, power, deposition time, or gas flow rate. Wait. For example, when the power and gas flow rates are small and the deposition time is short, the density of the formed insulating layer is also small.
- the density of the first insulator layer 21 may be, for example, smaller than the density of the second insulator layer 22.
- the base substrate 10 may be a metal substrate or a non-metal substrate.
- the non-metal substrate may be, for example, a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, or a silica gel substrate.
- the non-metal substrate may be a panel in which a functional member is formed, such as a liquid crystal display panel or an OLED display panel.
- the metal substrate may be, for example, an electrogalvanized steel sheet, a hot dip galvanized steel sheet, an galvanized steel sheet or a copper plate.
- the coating of the photoresist 32 may be by spin coating, blade coating or roll coating.
- the deposition insulating layer 2 may be formed by chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like, or may be physical vapor deposition (PVD) or the like.
- CVD chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- PVD physical vapor deposition
- the material of the insulating layer 2 may be silicon nitride (SiNx) or other suitable material.
- the photoresist coated on the insulating layer 2 is exposed and developed to form a photoresist pattern 33.
- the insulating layer 2 is subjected to a first etching process using the photoresist pattern 33 as an etch mask to form the recess 30 in the insulating layer 2.
- the first etching process can be dry etching.
- the dry etching may be performed by reactive ion etching (RIE), ion beam etching (IBE), and inductively coupled plasma (ICP) etching.
- RIE reactive ion etching
- IBE ion beam etching
- ICP inductively coupled plasma
- the first etching process can be etched by ICP etching technology, and the ICP etching has the characteristics of small DC offset (DC Bias) damage, high etching rate, controllable ion density and ion energy, thereby shortening the engraving.
- the etch time can also precisely control the etched topography.
- the first etching process may be performed using an ICP etching technique and etching with a mixed gas of SF 6 and O 2 as an etching gas.
- the etch rate of SF 6 and O 2 is faster, which can shorten the production time; in addition, SF 6 and O 2 can react with the insulating layer to form a volatile gas, which can be discharged by the vacuum system in time, so that it can be removed in time. Residual foreign matter generated during the etching process prevents residual foreign matter from affecting subsequent etching, and also ensures that the insulating layer is not contaminated by residual foreign matter.
- the sidewalls of the recess 30 can be smoothed and the slope is gentle by adjusting the etching parameters.
- the etching parameters may be the working pressure, power, etching gas flow rate, and composition ratio of the etching gas of the ICP etching apparatus.
- the first etching process can use the etching parameters in a conventional etching process.
- the upper electrode power may be 7200-8800W
- the lower electrode power may be 1800-2200W
- the pressure value may be 900-1100mT
- the SF 6 gas flow rate may be 1000-1400Sccm
- the O 2 gas flow rate may be 1200-1700Sccm.
- the etching parameter may be: the upper electrode power is 8000 W, the lower electrode power is 2000 W, the pressure value may be 1000 mT
- the SF 6 gas flow rate is 1200 sccm
- the O 2 gas flow rate is 1500 sccm.
- the density of the third insulator layer 23 may also be smaller than the density of the second insulator layer 22, so that when the active plasma is used for etching, the looser third insulator layer 23 is relatively easy to enter the plasma to achieve etching. purpose.
- the third insulator layer 23 can also serve as a buffer layer for etching.
- the groove 30 may include a portion away from the side of the base substrate 10 and a portion close to the side of the base substrate 10, and a portion of the groove 30 away from the side of the base substrate 10 has a larger diameter than the side closer to the substrate 10
- the aperture of the portion, i.e., the recess 30, may be formed in an inverted trapezoidal shape such that the recess 30 has a gentle slope angle.
- a portion away from the side of the base substrate 10 may be a portion in which the groove 30 is located in the third insulating sub-layer 23, and a portion near the side of the substrate substrate 10 may be a portion in which the groove 30 is located in the second insulating sub-layer 22.
- the third insulating sub-layer 23 and the second insulating sub-layer 22 are sequentially etched, and etching is stopped when etching to the first insulating sub-layer 21, thereby forming
- the groove 30 penetrating the second insulator layer 22 and the third insulator layer 23, and the groove 30 may expose the first insulator layer 21.
- the etching process can be monitored in real time using an etch endpoint detector (EPD) in an ICP device.
- EPD etch endpoint detector
- the etch endpoint detector EPD
- an etch endpoint detector can detect parameters such as the refractive index of the insulating layer 2. Since the first insulator layer 21, the second insulator layer 22, and the third insulator layer 23 have different densities, the refractive indices thereof are also different, for example, in the etching end point detector (EPD) before etching.
- the refractive index of the first insulating sub-layer 21 is pre-recorded.
- the ICP device When the etching end point detector (EPD) detects that the refractive index of the material to be etched is the same as the refractive index of the first insulating sub-layer 21, the ICP device is automatically controlled to stop etching. It should be noted that the etching end point can also be monitored by other methods (for example, by detecting the depth of the etching), thereby controlling the ICP device to stop etching. The disclosure does not limit this.
- the portion of the first insulator layer 21 exposed by the recess 30 is ion-injected using the photoresist pattern 33 as a mask to form an ion implantation region.
- the photoresist layer 33 is continuously used as an etch mask, and the insulating layer formed with the ion implantation region is subjected to a second etching process, and then the remaining photoresist is removed by a lift-off process.
- a via 31 penetrating the insulating layer is formed in the insulating layer.
- the first insulator layer 21 may include a first portion 210 in the ion implantation region and a second portion 211 outside the ion implantation region, and after ion 24 implantation, the density of the first portion 210 may be greater than The density of the two parts 211.
- the density of the first portion 210 increases, the insulating layer becomes denser, and the etching rate of the first portion 210 can be slowed down, thereby avoiding or reducing the excessive reaction of the first portion 210 with the active fluorine (F) ions and causing excessive transition to both sides.
- the indentation forms an undercut chamfer.
- the density of the first portion 210 is increased to allow the via 31 to be in the second insulator layer 22 and A smooth slope is formed at the junction of the first insulator layer 21.
- the density of the first portion 210 can also be greater than the density of the second insulator layer 22. Therefore, the etching rate of the first portion 210 is smaller than the etching rate of the second insulating sub-layer 22, further preventing lateral etching of the first portion 210, improving the quality of the via 31, and ensuring the effectiveness of the via 31.
- the density of the first portion 210 increases, and the etching rate is slowed, so that the first portion 210 may not be completely etched, for example, after the via 31 is formed, during the second etching process.
- the first portion 210 can be partially retained.
- the ions 24 can be nitrogen ions, oxygen ions, or other suitable ions.
- nitrogen (N 2 ) is introduced into the surface of the exposed first insulator layer 21 to obtain N ions, and the N ions are controlled to be in direct contact with the first insulator layer 21 .
- N ions are implanted into the first insulator layer 21 under high temperature and high pressure, so that N ions replace some silicon (Si) ions, or N ions are combined with some free Si ions to form Si-N bonds, so that the original silicon is rich. Part or all of the Si-Si bond remaining in the silicon nitride is replaced by a Si-N bond.
- the Si-N bond has a shorter bond length than the Si-Si bond, the bond energy is high, and an increase in the Si-N bond content can promote the tightness of the first insulator layer 21 and increase the density of the first insulator layer 21.
- the Si-Si bond in the silicon nitride is one of the main factors causing defects of the silicon nitride film, the ion can be increased to some extent by injecting N ions into the first insulator layer 21 exposed by the groove 30.
- the density of the first insulator layer 21 in the implantation region enhances the fluorine (F) ion etch resistance of the first insulator layer 21 in the ion implantation region, so that the etching rate is slowed, thereby preventing the first insulator layer 21 from being severely damaged. Lateral etching produces an undercut chamfer.
- the first insulator layer 21 exposed by the recess 30 becomes the first portion 210 having a higher density, and the density of the second portion 211 not implanted with the N ions is constant.
- the second etch process can be etched using the same etch technique and the same etch parameters as the first etch process.
- the second etching process is also etched using ICP etching.
- the second etching process can also be performed by using an etching technique different from that of the first etching process and different etching parameters.
- the second etch process can be etched using an IBE etch technique.
- first etching process and the second etching process may also adopt other suitable etching equipment and other suitable etching gases (for example, a mixed gas of CF 4 and O 2 is used as an etching gas).
- suitable etching equipment and other suitable etching gases for example, a mixed gas of CF 4 and O 2 is used as an etching gas.
- FIGS. 4a-4c are process diagrams illustrating a method of fabricating an array substrate provided by an embodiment of the present disclosure. Figures 4a-4c still only show a portion of the related structure for clarity of illustration.
- Embodiments of the present disclosure also provide a method of fabricating an array substrate.
- the method of preparing the array substrate of the embodiment of the present disclosure may include the method of preparing the via hole in the above embodiment.
- a base substrate 100 is provided, and a gate electrode 12, a gate insulating layer 16, an active layer 15, a source/drain electrode layer, and a passivation layer are sequentially formed on the base substrate 100 by a patterning process. 17 and the common electrode 18.
- the base substrate 100 may be a transparent insulating substrate.
- the base substrate 100 may be a glass substrate, a quartz substrate, a plastic substrate, or other suitable substrate.
- the source/drain electrode layer may include the first electrode 13 and the second electrode 14.
- the first electrode 13 can be, for example, a source or a drain
- the second electrode 14 can be a drain or a source.
- the first electrode 13, the active layer 15, the second electrode 14, the gate electrode 12, and the gate insulating layer 16 constitute a thin film transistor which can serve as a switching element of a pixel region of the array substrate.
- the material of the first electrode 13 and the second electrode 14 may include a copper-based metal, an aluminum-based metal, a nickel-based metal, or the like.
- the copper-based metal may be a copper-based metal alloy having stable properties such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi), or copper-zinc-nickel alloy (CuZnNi).
- the copper-based metal has the characteristics of low resistivity and good electrical conductivity, thereby improving the signal transmission rate of the source and the drain and improving the display quality.
- the material of the gate electrode 12 may be copper (Cu), copper-molybdenum alloy (Cu/Mo), or may be a chromium-based metal, such as chromium-molybdenum alloy (Cr/Mo), chrome-titanium alloy (Cr/Ti), and It can be aluminum, aluminum alloy or other suitable material.
- the active layer 15 may be an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer.
- the polycrystalline silicon may be high temperature polycrystalline silicon or low temperature polycrystalline silicon
- the oxide semiconductor may be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO).
- the material of the common electrode 18 may be a transparent conductive material, a metal material or other suitable materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) or Carbon nanotubes, etc.
- ITO indium tin oxide
- IZO indium zinc oxide
- IGO indium gallium oxide
- GZO gallium zinc oxide
- Carbon nanotubes etc.
- the common electrode 18 may be a plate electrode or a slit electrode.
- the material of the gate insulating layer 16 and the passivation layer 17 may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy), or other suitable materials such as an organic resin material or the like.
- the gate insulating layer 16 and the passivation layer 17 may be a single layer structure or a multilayer structure composed of one or more of the above materials.
- an insulating layer is deposited on the common electrode 18, and then patterned by a patterning process.
- the via electrode 31 penetrates the insulating layer, and the common electrode 18 is in direct contact with the insulating layer.
- depositing the insulating layer includes sequentially depositing the first insulating sub-layer 21, the second insulating sub-layer 22, and the third insulating sub-layer 23 on the common electrode 18, and the common electrode 18 may be in direct contact with the first insulating sub-layer 21, for example.
- the density of the first insulator layer 21 is made smaller than the density of the second insulator layer 22 by controlling the deposition process parameters.
- the second insulator layer 22 having a higher density is rich in silane, so that the concentration of hydrogen (H + ) radicals in the second insulator layer 22 is high, and hydrogen (H + ) radicals easily cause metal ions in the common electrode 18 to be generated.
- the reduction reaction forms an opaque metal or metal complex to form black spots in the common electrode 18.
- a high concentration of hydrogen (H + ) radicals also has a strong trapping ability for oxygen ions in the common electrode 18, thereby affecting the properties of the common electrode 18 and reducing the display quality.
- the first insulator layer 21 can prevent the second insulator layer 22 having a larger density from directly contacting the common electrode 18, thereby reducing or eliminating metal black spots and improving display quality.
- the via hole 31 can be prepared by the method for preparing the via hole described in the above embodiment, so that the via hole 31 does not cause undercut chamfering, improves the quality of the via hole 31, and ensures the effectiveness of the via hole 31. .
- the first portion 210 of the first insulator layer 21 may be partially retained, for example.
- the via 31 may expose the first electrode 13 or the second electrode 14 in the source/drain electrode layer. As shown in FIG. 4b, in one example, the via 31 exposes the second electrode 14 in the source-drain electrode layer.
- the material of the insulating layer may be silicon nitride, and the first insulating sub-layer 21, the second insulating sub-layer 22, and the third insulating sub-layer 23 are formed of silicon nitride having different densities.
- Silicon nitride has excellent ability to isolate ions. While insulating, it can also effectively prevent oxygen and water vapor in the air from entering the array substrate and affecting the performance of the thin film transistor, thereby improving the quality of the array substrate and improving the product of the array substrate. Yield.
- the pixel electrode 19 is formed on the insulating layer on which the via hole 31 is formed by a patterning process.
- the pixel electrode 19 may be electrically connected to the first electrode 13 or the second electrode 14 via the via 31 to receive a data signal transmitted through the thin film transistor.
- the material of the pixel electrode 19 may include a transparent conductive material, a metal material, or other suitable materials.
- the material of the pixel electrode 19 may be indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
- the pixel electrode 19 may be a plate electrode or a slit electrode.
- a plurality of branches parallel to each other and spaced apart from each other can be formed by a patterning process, thereby forming slit-shaped pixel electrodes 19.
- the density of the third insulator layer 23 may also be smaller than the density of the second insulator layer 22, so that the etching rate of the third insulator layer 23 may be greater than the etching rate of the second insulator layer 22, and thus, when the via 31 is etched.
- the via 31 can be formed to have a certain gentle slope angle.
- the pixel electrode 19 can be smoothly joined to the sidewall of the insulating layer to prevent the pixel electrode 19 from being broken at the step formed by the via 31 on the surface of the third insulator layer 23, thereby improving display quality and improving product yield.
- the method for fabricating the array substrate provided by the embodiment of the present disclosure is described by taking a bottom gate type thin film transistor as an example, but is not limited thereto, and the method for preparing the array substrate provided by the embodiment of the present disclosure may also be applied to a top gate type. Thin film transistor.
- An embodiment of the present disclosure also provides an array substrate.
- the array substrate provided by the embodiment of the present disclosure includes a base substrate 100, an insulating layer disposed on the base substrate 100, and the insulating layer includes a via 31.
- the insulating layer may include a first insulating sub-layer 21 and a second insulating sub-layer 22 which are sequentially disposed on the base substrate 100, and the first insulating sub-layer 21 may include a first portion 210 close to the via 31 and a second away from the via 31 Portion 211, and the density of the first portion 210 is greater than the density of the second portion 211.
- the first portion 210 having a larger density can ensure that the via 31 does not form an internal stepped barb angle, improve the quality of the via 31, and ensure the effectiveness of the via 31.
- the density of the first portion 210 can also be greater than the density of the second insulator layer 22.
- the insulating layer may further include a third insulating layer 23 disposed on the second insulating sub-layer 22, and the density of the third insulating layer 23 may be smaller than the density of the second insulating sub-layer 22.
- the array substrate further includes a gate electrode 12, a gate insulating layer 16, an active layer 15, and a source/drain electrode layer disposed between the base substrate 100 and the insulating layer (for example, may include the first The electrode 13 and the second electrode 14), the passivation layer 17, and the common electrode 18.
- the common electrode 18 may be in direct contact with the first insulator layer 21.
- the array substrate further includes a pixel electrode 19 disposed on the insulating layer.
- the pixel electrode 19 can be electrically connected to the first electrode 13 or the second electrode 14 via the via 31.
- the via hole 31 has a gentle slope angle and has no internal stepped barb angle, so that the problem of contact breakage between the pixel electrode 19 and the source/drain electrode layer can be improved or eliminated, and the pixel electrode 19 and the source/drain electrode layer are improved.
- the stability of the electrical connection between the two to improve product yield and improve product quality.
- the pixel electrode 19 and the common electrode 18 are formed on different layers, Therefore, the array substrate can be used, for example, in an Advanced Super Dimension Switch (ADS) type liquid crystal panel. It should be noted that the pixel electrode 19 and the common electrode 18 may also be formed on the same layer, which is not limited in the embodiment of the present disclosure.
- ADS Advanced Super Dimension Switch
- the array substrate can be applied to any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
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Abstract
Description
Claims (15)
- 一种过孔的制备方法,包括:提供衬底基板;在所述衬底基板上形成绝缘层;采用第一次刻蚀工艺刻蚀所述绝缘层以在所述绝缘层中形成凹槽;对所述绝缘层的由所述凹槽暴露的部分进行离子注入,以形成离子注入区;采用第二次刻蚀工艺刻蚀所述离子注入区内的绝缘层以形成贯穿所述绝缘层的过孔。
- 根据权利要求1所述的过孔的制备方法,其中,所述在所述衬底基板上形成绝缘层包括:在所述衬底基板上依次形成第一绝缘子层和第二绝缘子层,进行所述离子注入前,所述第一绝缘子层的密度小于所述第二绝缘子层。
- 根据权利要求2所述的过孔的制备方法,其中,所述采用第一次刻蚀工艺刻蚀所述绝缘层以形成凹槽包括:对所述第二绝缘子层进行刻蚀,并且在所述凹槽暴露出所述第一绝缘子层时停止刻蚀。
- 根据权利要求3所述的过孔的制备方法,其中,在所述离子注入中,对所述第一绝缘子层的由所述凹槽暴露的部分进行所述离子注入。
- 根据权利要求4所述的过孔的制备方法,其中,进行所述离子注入后,所述离子注入区内的第一绝缘子层的密度变大。
- 根据权利要求4或5所述的过孔的制备方法,其中,进行所述离子注入后,所述离子注入区内的第一绝缘子层的密度大于所述第二绝缘子层的密度。
- 根据权利要求2-6任一项所述的过孔的制备方法,其中,形成所述绝缘层还包括:在所述第二绝缘子层上形成第三绝缘子层,所述第三绝缘子层的密度小于所述第二绝缘子层的密度。
- 根据权利要求1-7任一项所述的过孔的制备方法,其中,所述离子为氮离子或氧离子。
- 根据权利要求1-8任一项所述的过孔的制备方法,其中,所述绝缘层的材料为氮化硅。
- 根据权利要求1-9任一项所述的过孔的制备方法,其中,在进行所述第一次刻蚀工艺之前,所述方法还包括:在所述绝缘层上涂覆光刻胶,并对所述光刻胶进行曝光和显影以形成光刻胶图案,所述第一次刻蚀工艺以所述光刻胶图案为掩模进行。
- 一种阵列基板的制备方法,包括权利要求1-10任一项所述的过孔的制备方法。
- 根据权利要求11所述的阵列基板的制备方法,还包括:在所述衬底基板上形成栅极、栅极绝缘层、有源层、源漏电极层和公共电极;其中,所述绝缘层形成在所述公共电极上且与所述公共电极直接接触,所述过孔暴露所述源漏电极层中的源极或漏极。
- 根据权利要求12所述的阵列基板的制备方法,还包括:在形成有所述过孔的绝缘层上形成像素电极,其中,所述像素电极通过所述过孔与所述源极或漏极电连接。
- 一种阵列基板,包括:衬底基板;设置在所述衬底基板上的绝缘层;贯穿所述绝缘层的过孔;其中,所述绝缘层包括依次设置在所述衬底基板上的第一绝缘子层和第二绝缘子层,所述第一绝缘子层包括靠近所述过孔的第一部分和远离所述过孔的第二部分,所述第一部分的密度大于所述第二部分的密度。
- 根据权利要求14所述的阵列基板,还包括:设置在所述衬底基板和所述绝缘层之间的栅极、栅极绝缘层、有源层、源漏电极层和公共电极;设置在所述绝缘层上的像素电极,其中,所述绝缘层与所述公共电极直接接触,所述像素电极通过所述过孔与所述源漏电极层中的源极或漏极电连接。
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US11037959B2 (en) * | 2017-03-24 | 2021-06-15 | Boe Technology Group Co., Ltd. | Method of producing array substrate, array substrate, and display apparatus |
US11163204B2 (en) * | 2019-11-22 | 2021-11-02 | Ordos Yuansheng Optoelectronics Co., Ltd. | Array substrate, display panel including the same, and display device |
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CN106707649B (zh) | 2017-03-01 | 2019-09-03 | 合肥京东方光电科技有限公司 | 过孔的制备方法、阵列基板的制备方法及阵列基板 |
CN108320668A (zh) * | 2018-01-19 | 2018-07-24 | 昆山国显光电有限公司 | 柔性显示基板及其制备方法 |
CN113394235B (zh) * | 2021-05-20 | 2022-10-21 | 北海惠科光电技术有限公司 | 阵列基板及阵列基板的制造方法 |
CN114045512A (zh) * | 2021-06-24 | 2022-02-15 | 有研工程技术研究院有限公司 | 多孔高比表面积电解水制氢一体化电极材料及其制备方法 |
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