WO2017128555A1 - 薄膜晶体管基板及其制造方法 - Google Patents

薄膜晶体管基板及其制造方法 Download PDF

Info

Publication number
WO2017128555A1
WO2017128555A1 PCT/CN2016/081783 CN2016081783W WO2017128555A1 WO 2017128555 A1 WO2017128555 A1 WO 2017128555A1 CN 2016081783 W CN2016081783 W CN 2016081783W WO 2017128555 A1 WO2017128555 A1 WO 2017128555A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
semiconductor layer
drain electrode
forming
Prior art date
Application number
PCT/CN2016/081783
Other languages
English (en)
French (fr)
Inventor
李金明
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/113,822 priority Critical patent/US20180069022A1/en
Publication of WO2017128555A1 publication Critical patent/WO2017128555A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the invention belongs to the field of wafer fabrication and flat panel display technology.
  • it relates to a thin film transistor (TFT) substrate and a method of fabricating the same.
  • TFT thin film transistor
  • a semiconductor layer in a thin film transistor is composed of a metal oxide film, and a metal oxide film is very sensitive to an acid, and even a weak acid can quickly etch the oxide semiconductor layer to etch on the oxide semiconductor layer.
  • the oxide semiconductor layer itself is easily destroyed when the metal source electrode and the drain electrode are used.
  • the oxide semiconductor layer is thin (generally between 30 nm and 50 nm), even in hydrofluoric acid (HF) diluted at a concentration of 500:1, the oxide semiconductor layer can be etched in only a few seconds.
  • an etching barrier layer ESL is usually added between the oxide semiconductor layer and the source electrode and the drain to protect the bottom oxide semiconductor layer from etching for forming the source electrode and the drain electrode.
  • a lithography process includes film formation, exposure, development, etching, stripping, etc., which greatly increases production costs and reduces production. rate.
  • the present invention provides a thin film transistor substrate which does not require an additional etching barrier layer and a method of fabricating the same.
  • a method of manufacturing a thin film transistor substrate comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate to cover the gate electrode; forming a semiconductor on the gate insulating layer a layer; a semiconductor layer is plasma-formed to form an ohmic contact layer having a predetermined thickness; a metal layer is formed on the gate insulating layer to cover the ohmic contact layer; and the metal layer and the ohmic contact layer are patterned to form a source electrode and Leaking the electrode and exposing a region of the semiconductor layer between the source electrode and the drain electrode; forming a passivation layer on the source electrode, the drain electrode, and the exposed semiconductor layer; in the passivation layer A contact hole for exposing the drain electrode is formed; a pixel electrode is formed on the passivation layer, and the pixel electrode is connected to the drain electrode through the contact hole.
  • the step of plasmaizing the semiconductor layer may include: activating the semiconductor layer under conditions of 250 ° C to 500 ° C; and plasma-treating the surface of the semiconductor layer with argon/nitrogen ions, To form an ohmic contact layer having a predetermined thickness.
  • the step of patterning the metal layer and the ohmic contact layer may include etching a portion of the metal layer by dry etching, and then using the etching liquid containing H 2 O 2 to treat the remaining metal
  • the layer and the ohmic contact layer are etched to obtain a source electrode and a drain electrode and expose a region of the semiconductor layer between the source electrode and the drain electrode.
  • the metal layer may include at least one of Mo and Al.
  • the gate electrode may include at least one of Mo and Al.
  • the gate insulating layer may include a silicon oxide layer or a composite layer of a silicon oxide layer and a silicon nitride layer.
  • the passivation layer may include a silicon oxide layer, or a composite layer of a silicon oxide layer and a silicon nitride layer stacked in order from bottom to top.
  • the pixel electrode may include ITO.
  • the semiconductor layer may include indium gallium zinc oxide.
  • a thin film transistor substrate including: a gate electrode formed on a substrate; a gate insulating layer formed on the substrate to cover the gate electrode; and a semiconductor layer formed on the gate On the pole insulating layer; the source electrode and the drain electrode are formed on both sides of the semiconductor layer; the ohmic contact layer is formed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer; and the passivation layer is formed on the semiconductor layer And a source electrode and a drain electrode; a pixel electrode formed on the passivation layer and connected to the drain electrode.
  • etching stopper layer between the semiconductor layer and the source electrode and the drain electrode, thereby reducing production cost and simplifying the manufacturing process. Furthermore, according to the method of the present invention, etching of the metal oxide by the metal etching solution can be avoided. Furthermore, according to the method of the present invention, a good ohmic contact can be formed between the semiconductor layer and the source and drain electrodes.
  • 1 to 6 illustrate a flow chart of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
  • 1 to 6 illustrate a flow chart of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.
  • a gate electrode 110 is formed on a substrate 100.
  • the substrate 100 may be formed of a transparent glass material containing SiO 2 as a main component, but is not limited thereto.
  • the gate electrode 110 is formed on the substrate 100 by a physical vapor deposition (PVD) method. Specifically, a metal oxide is deposited on the substrate 100 by a PVD method, and then a yellow light process and an etching process are performed to form a gate electrode 110 having a predetermined pattern.
  • PVD physical vapor deposition
  • the gate electrode 110 may include at least one of Al and Mo, however, the present invention is not limited thereto, and other suitable metal materials may also be included. In an exemplary embodiment of the present invention, the gate electrode 110 may have a thickness of 2000 ⁇ to 5500 ⁇ .
  • a gate insulating layer 120 is formed on the substrate 100 to cover the gate electrode 110.
  • a metal layer is deposited on the substrate 100 by plasma enhanced chemical vapor deposition, followed by a yellow light process and an etching process to obtain the gate insulating layer 120.
  • the gate insulating layer 120 may be formed of silicon oxide (SiO x) is a single layer or a silicon oxide (SiO x) and silicon nitride (SiN x) of the composite layer.
  • the thickness of the gate insulating layer 120 may be 1500 angstroms to 4000 angstroms, however, the invention is not limited thereto.
  • a semiconductor layer 130 and an ohmic contact layer 140 are formed on the gate insulating layer 120.
  • a metal oxide is first deposited on the gate insulating layer 120, and then a yellow light process and an etching process are performed to obtain a semiconductor layer 130 having a predetermined pattern, and then in an air or oxidizing environment at 250 ° C to 500
  • the surface of the semiconductor layer 130 is activated at a temperature of ° C, and then the surface of the semiconductor layer 130 is plasmaized by dry etching (Dry Etch) or a CVD machine using argon (Ar) / nitrogen (N 2 ) ions (Plasma). Processing thereby converting a portion of the semiconductor layer 130 into an ohmic contact layer 140 having a predetermined thickness.
  • the semiconductor layer 130 may include indium gallium zinc oxide (IGZO), however, the present invention is not limited thereto, and any suitable metal oxide may be selected.
  • the semiconductor layer 110 may have a thickness of 400 angstroms to 1500 angstroms; and the ohmic contact layer may have a thickness of 10 angstroms to 300 angstroms.
  • a metal layer is formed on the gate insulating layer 120 to cover the ohmic contact layer 140, and then the metal layer is patterned to form the source electrode S and the drain electrode D and expose the semiconductor layer 130. A region between the source electrode S and the drain electrode D.
  • a metal layer is deposited on the gate insulating layer 120, and then a portion of the metal layer is dry etched (Dry Etch), and then the remaining portion of the metal layer is contacted with ohmic using an etching solution containing H 2 O 2 . The layer is etched to form the source electrode S and the drain electrode D and expose a region of the semiconductor layer 130 between the source electrode S and the drain electrode D.
  • the end point monitoring (EPD) mode is employed to control the degree of dry etching to improve the fabrication accuracy.
  • the metal layer includes at least one of Al and Mo.
  • the metal layer preferably includes Al and Mo, and Mo contacts the ohmic contact layer.
  • the surface of the semiconductor layer is plasma-treated by argon/nitrogen ions, and the argon/nitrogen ions bombard the oxygen of the surface of the semiconductor layer under the action of energy to cause an increase in the content of indium in the semiconductor layer, so that the semiconductor layer is The surface resistance is lowered to obtain a relatively ohmic contact layer, and then the metal layer formed on the ohmic contact layer is etched by dry etching, and the remaining metal layer and the ohmic contact layer are etched by using an etching solution containing hydrogen peroxide. Thereby, source and drain electrodes and an active layer with fewer defects are obtained.
  • a passivation layer 150 is formed on the source electrode S, the drain electrode D, and the exposed semiconductor layer, and a contact hole H is formed in the passivation layer 150.
  • a passivation layer 150 is formed on the source electrode S, the drain electrode D, and the exposed semiconductor layer by plasma enhanced chemical vapor deposition, and then a yellow light process and an etching process are performed to form a contact hole H in the passivation layer 150. .
  • the passivation layer includes a silicon oxide layer or a composite layer including a silicon nitride layer and a silicon oxide layer, and when a composite layer including a silicon nitride layer and a silicon oxide layer, a silicon oxide layer Contact with the semiconductor layer 130.
  • the passivation layer may have a thickness of 1500 angstroms to 4000 angstroms, although the invention is not limited thereto.
  • the pixel electrode 160 is formed on the passivation layer 150, and the pixel electrode 160 is turned on.
  • the contact hole H is connected to the drain electrode D.
  • the pixel electrode 160 may be formed by depositing ITO by a PVD method, and then performing a yellow light process and an etching process.
  • the pixel electrode is not limited to ITO, and may be other transparent conductors.
  • the pixel electrode 160 may have a thickness of 300 angstroms to 1000 angstroms, however, the invention is not limited thereto.
  • etching stopper layer between the semiconductor layer and the source electrode and the drain electrode, thereby reducing production cost and simplifying the manufacturing process.
  • etching of the metal oxide by the metal etching solution can be avoided.
  • a good ohmic contact can be formed between the semiconductor layer and the source and drain electrodes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种制造薄膜晶体管基板的方法，包括：在基底(100)上形成栅电极(110)；在基底(100)上形成栅极绝缘层(120)以覆盖栅电极(110)；在栅极绝缘层(120)上形成半导体层(130)；对半导体层(130)进行等离子化，以形成具有预定厚度的欧姆接触层(140)；在栅极绝缘层(120)上形成金属层以覆盖欧姆接触层(140)；对金属层和欧姆接触层(140)进行图案化，以形成源电极(S)和漏电极(D)并且暴露半导体层(130)的在源电极(S)和漏电极(D)之间的区域；在源电极(S)、漏电极(D)和暴露的半导体层(130)上形成钝化层(150)；在钝化层(150)中形成用于暴露漏电极(D)的接触孔(H)；在钝化层(150)上形成像素电极(160)，像素电极(160)通过接触孔(H)连接到漏电极(D)。上述制造薄膜晶体管基板的方法，不需要在半导体层(130)与源电极(S)和漏电极(D)之间增设蚀刻阻挡层，因此降低了生产成本，简化了制造工艺。还提供了一种薄膜晶体管基板。

Description

[根据细则37.2由ISA制定的发明名称]　薄膜晶体管基板及其制造方法 技术领域
本发明属于晶圆制造和平板显示技术领域。具体地讲，涉及一种薄膜晶体管(TFT)基板及其制造方法。
背景技术
通常，薄膜晶体管(TFT)中的半导体层由金属氧化物薄膜构成，而金属氧化物薄膜对酸非常敏感，即便是弱酸也能够快速地腐蚀氧化物半导体层，从而在氧化物半导体层上刻蚀金属源电极和漏电极时很容易破坏氧化物半导体层本身。
此外，由于氧化物半导体层较薄(通常在30nm至50nm之间)，即使采用浓度在500:1稀释的氢氟酸(HF)中，只需几秒钟就能够刻蚀氧化物半导体层。在现有技术中，通常会在氧化物半导体层与源电极和漏极之间增设一层蚀刻阻挡层(ESL)来保护底部的氧化物半导体层免受用来形成源电极和漏电极的蚀刻液的影响，但是额外制作一层蚀刻阻挡层需要额外增加一道光刻制程，一道光刻制程包括成膜、曝光、显影、蚀刻、剥离等工序，因而会大大增加了生产成本，降低了生产良率。
发明内容
为了解决上述现有技术的不足，本发明提供一种不需要额外增加蚀刻阻挡层的薄膜晶体管基板及其制造方法。
根据本发明的一方面，提供一种制造薄膜晶体管基板的方法，所述方法包括：在基底上形成栅电极；在基底上形成栅极绝缘层以覆盖栅电极；在栅极绝缘层上形成半导体层；对半导体层进行等离子化，以形成具有预定厚度的欧姆接触层；在栅极绝缘层上形成金属层以覆盖欧姆接触层；对金属层和欧姆接触层进行图案化，以形成源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域；在源电极、漏电极和暴露的半导体层上形成钝化层；在钝化层中 形成用于暴露漏电极的接触孔；在钝化层上形成像素电极，像素电极通过接触孔连接到漏电极。
根据本发明的示例性实施例，对半导体层进行等离子化的步骤可以包括：在250℃至500℃的条件下对半导体层进行活化；利用氩/氮离子对半导体层的表面进行等离子化处理，以形成具有预定厚度的欧姆接触层。
根据本发明的示例性实施例，对金属层和欧姆接触层进行图案化的步骤可以包括：采用干蚀刻法对金属层的一部分进行蚀刻，之后利用含有H2O2的蚀刻液对剩余的金属层和欧姆接触层进行蚀刻，从而得到源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域。
根据本发明的示例性实施例，金属层可以包括Mo和Al中的至少一种。
根据本发明的示例性实施例，栅电极可以包括Mo和Al中的至少一种。
根据本发明的示例性实施例，栅极绝缘层可以包括氧化硅层或氧化硅层与氮化硅层的复合层。
根据本发明的示例性实施例，钝化层可以包括氧化硅层，或者以从下到上的顺序堆叠的氧化硅层和氮化硅层的复合层。
根据本发明的示例性实施例，像素电极可以包括ITO。
根据本发明的示例性实施例，半导体层可以包括氧化铟镓锌。
根据本发明的另一方面，提供一种薄膜晶体管基板，所述薄膜晶体管基板包括：栅电极，形成在基底上；栅极绝缘层，形成在基底上以覆盖栅电极；半导体层，形成在栅极绝缘层上；源电极和漏电极，形成在半导体层的两侧上；欧姆接触层，形成在源电极与半导体层之间以及漏电极与半导体层之间；钝化层，形成在半导体层、源电极和漏电极上；像素电极，形成在钝化层上并连接到漏电极。
根据本发明的制造薄膜晶体管基板的方法，不需要在半导体层与源电极和漏电极之间增设蚀刻阻挡层，因此降低了生产成本，简化了制造工艺。此外，根据本发明的方法，能够避免金属刻蚀液对金属氧化物的刻蚀。此外，根据本发明的方法，能够在半导体层与源电极和漏电极之间形成良好的欧姆接触。
附图说明
图1至图6示出了根据本发明的示例性实施例的制造薄膜晶体管基板的流程示意图。
具体实施方式
下面将参照附图详细地描述本发明的示例性实施例。
以下将结合附图来详细描述本发明的示例性实施例，然而，附图只是示意性地示出了本发明的具体示例，且不具有限制作用。然而，本领域技术人员应理解的是，在不脱离本发明的权利要求所限定的保护范围的情况下，可以对其进行各种修改和变形。
在下文中，将通过参照附图解释本发明的示例性实施例来详细描述本发明。
图1至图6示出了根据本发明的示例性实施例的制造薄膜晶体管基板的流程示意图。
如图1中所示，在基底100上形成栅电极110。基底100可以由含有SiO2作为主要成分的透明玻璃材料形成，但是不限于此。
通常，通过物理气相沉积(PVD)法在基底100上形成栅电极110。具体地讲，采用PVD法在基底100上沉积金属氧化物，之后执行黄光工艺和刻蚀工艺来形成具有预定图案的栅电极110。
栅电极110可以包括Al和Mo中的至少一种，然而，本发明并不限于此，也可以包括其它适合的金属材料。在本发明的一个示例性实施例中，栅电极110的厚度可以为2000埃至5500埃。
接着，如图2中所示，在基底100上形成栅极绝缘层120以覆盖栅电极110。具体地讲，通过等离子增强化学气相沉积法在基底100上沉积金属层，接着执行黄光工艺和刻蚀工艺来得到栅极绝缘层120。在本发明的示例性实施例中，栅极绝缘层120可以形成为氧化硅(SiOx)的单层或者氧化硅(SiOx)和氮化硅(SiNx)的复合层。此外，在本发明的非限制性实施例中，栅极绝缘层120的厚度可以为1500埃至4000埃，然而，本发明不限于此。
然后，如图3中所示，在栅极绝缘层120上形成半导体层130和欧姆接触层140。具体地讲，首先在栅极绝缘层120上沉积金属氧化物，然后执行黄光工艺和刻蚀工艺来得到具有预定图案的半导体层130，之后在空气或氧化的环境下，在250℃～500℃的温度下对半导体层130的表面进行活化，接着通过干蚀刻 法(Dry Etch)或CVD机台使用氩(Ar)/氮(N2)离子对半导体层130的表面进行等离子化(Plasma)处理，从而将半导体层130的一部分转化为具有预定厚度的欧姆接触层140。
在本发明的示例性实施例中，半导体层130可以包括氧化铟镓锌(IGZO)，然而，本发明不限于此，可以选用任何适合的金属氧化物。在本发明的一个示例性实施例中，半导体层110的厚度可以为400埃至1500埃；欧姆接触层的厚度可以为10埃至300埃。
接着，如图4中所示，在栅极绝缘层120上形成金属层以覆盖欧姆接触层140，接着对金属层进行图案化，来形成源电极S和漏电极D并且暴露半导体层130的在源电极S和漏电极D之间的区域。具体地讲，首先，在栅极绝缘层120上沉积金属层，然后对金属层的一部分进行干蚀刻(Dry Etch)，之后利用含有H2O2的蚀刻液对金属层的剩余部分和欧姆接触层进行蚀刻，以形成源电极S和漏电极D并且暴露半导体层130的在源电极S和漏电极D之间的区域。
在本发明中，采用终点监控(EPD)模式控制干蚀刻的程度，以提高制作精度。在本发明的示例性实施例中，金属层包括Al和Mo中的至少一种。在本发明中，金属层优选地包括Al和Mo，并且Mo接触欧姆接触层。
在本发明中，通过氩/氮离子对半导体层的表面进行等离子化处理，氩/氮离子在能量的作用下轰击半导体层的表面的氧导致半导体层中的铟的含量增加，使得半导体层的表面的电阻降低，得到相对的欧姆接触层，之后利用干蚀刻对形成在欧姆接触层上的金属层进行蚀刻，再利用含有过氧化氢的蚀刻液对剩余的金属层以及欧姆接触层进行蚀刻，从而得到源电极和漏电极以及缺陷较少的有源层。
然后，参照图5，在源电极S、漏电极D和暴露的半导体层上形成钝化层150，并且在钝化层150中形成接触孔H。具体地讲，通过等离子增强化学气相沉积法在源电极S、漏电极D和暴露的半导体层上形成钝化层150，之后执行黄光工艺和刻蚀工艺在钝化层150中形成接触孔H。在本发明的示例性实施例中，钝化层包括氧化硅层或者包括氮化硅层和氧化硅层的复合层，并且在包括氮化硅层和氧化硅层的复合层时，氧化硅层与半导体层130接触。在本发明的非限制性实施例中，钝化层的厚度可以为1500埃至4000埃，然而本发明不限于此。
然后，参照图6，在钝化层150上形成像素电极160，并且像素电极160通 过接触孔H连接到漏电极D。在本发明中，可以通过PVD法沉积ITO，然后执行黄光工艺和刻蚀工艺来形成像素电极160。在本发明中，像素电极不限于ITO，也可以是其它透明导体。在本发明的示例性实施例中，像素电极160的厚度可以为300埃至1000埃，然而，本发明不限于此。
根据本发明的制造薄膜晶体管基板的方法，不需要在半导体层与源电极和漏电极之间增设蚀刻阻挡层，因此降低了生产成本，简化了制造工艺。
此外，根据本发明的方法，能够避免金属刻蚀液对金属氧化物的刻蚀。
此外，根据本发明的方法，能够在半导体层与源电极和漏电极之间形成良好的欧姆接触。
以上描述了根据本发明的示例性实施例的制造薄膜晶体管的方法，但本发明的保护范围并不限制于上述特定实施例。

Claims (10)

  1. 一种制造薄膜晶体管基板的方法，其中，所述方法包括如下步骤：
    在基底上形成栅电极；
    在基底上形成栅极绝缘层以覆盖栅电极；
    在栅极绝缘层上形成半导体层；
    对半导体层进行等离子化，以形成具有预定厚度的欧姆接触层；
    在栅极绝缘层上形成金属层以覆盖欧姆接触层；
    对金属层和欧姆接触层进行图案化，以形成源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域；
    在源电极、漏电极和暴露的半导体层上形成钝化层；
    在钝化层中形成用于暴露漏电极的接触孔；
    在钝化层上形成像素电极，像素电极通过接触孔连接到漏电极。
  2. 根据权利要求1所述的方法，其中，对半导体层进行等离子化的步骤包括：
    在250℃至500℃的条件下对半导体层进行活化；
    利用氩/氮离子对半导体层的表面进行等离子化处理，以形成具有预定厚度的欧姆接触层。
  3. 根据权利要求1所述的方法，其中，对金属层和欧姆接触层进行图案化的步骤包括：采用干蚀刻法对金属层的一部分进行蚀刻，之后利用含有H2O2的蚀刻液对剩余的金属层和欧姆接触层进行蚀刻，从而得到源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域。
  4. 根据权利要求1所述的方法，其中，金属层包括Mo和Al中的至少一种。
  5. 根据权利要求1所述的方法，其中，栅电极包括Mo和Al中的至少一种。
  6. 根据权利要求1所述的方法，其中，栅极绝缘层包括氧化硅层或氧化硅层与氮化硅层的复合层。
  7. 根据权利要求1所述的方法，其中，钝化层包括氧化硅层，或者以从下到上的顺序堆叠的氧化硅层和氮化硅层的复合层。
  8. 根据权利要求1所述的方法，其中，像素电极包括ITO。
  9. 根据权利要求1所述的方法，其中，半导体层包括氧化铟镓锌。
  10. 一种薄膜晶体管基板，所述薄膜晶体管基板包括：
    栅电极，形成在基底上；
    栅极绝缘层，形成在基底上以覆盖栅电极；
    半导体层，形成在栅极绝缘层上；
    源电极和漏电极，形成在半导体层的两侧上；
    欧姆接触层，形成在源电极与半导体层之间以及漏电极与半导体层之间；
    钝化层，形成在半导体层、源电极和漏电极上；
    像素电极，形成在钝化层上并连接到漏电极。
PCT/CN2016/081783 2016-01-28 2016-05-12 薄膜晶体管基板及其制造方法 WO2017128555A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/113,822 US20180069022A1 (en) 2016-01-28 2016-05-12 Thin-film transistor and method of fabricating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610061597.XA CN105448938B (zh) 2016-01-28 2016-01-28 薄膜晶体管基板及其制造方法
CN201610061597.X 2016-01-28

Publications (1)

Publication Number Publication Date
WO2017128555A1 true WO2017128555A1 (zh) 2017-08-03

Family

ID=55558950

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/081783 WO2017128555A1 (zh) 2016-01-28 2016-05-12 薄膜晶体管基板及其制造方法

Country Status (3)

Country Link
US (1) US20180069022A1 (zh)
CN (1) CN105448938B (zh)
WO (1) WO2017128555A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448938B (zh) * 2016-01-28 2019-06-25 深圳市华星光电技术有限公司 薄膜晶体管基板及其制造方法
US10121710B2 (en) * 2016-06-14 2018-11-06 Innolux Corporation Methods for manufacturing a display device
CN106684037B (zh) * 2017-03-22 2019-09-24 深圳市华星光电半导体显示技术有限公司 优化4m制程的tft阵列制备方法
CN106684038B (zh) * 2017-03-22 2019-12-24 深圳市华星光电半导体显示技术有限公司 用于4m制程制备tft的光罩及4m制程tft阵列制备方法
CN107527870B (zh) * 2017-08-29 2023-08-25 惠科股份有限公司 一种阵列基板的制作方法及其制作设备
CN107658345B (zh) * 2017-09-22 2020-12-01 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110183463A1 (en) * 2007-04-18 2011-07-28 Samsung Electronics Co., Ltd. Thin film transitor substrate and method of manufacturing the same
CN102646634A (zh) * 2011-04-29 2012-08-22 京东方科技集团股份有限公司 Tft-lcd阵列基板制造方法
CN102646715A (zh) * 2011-12-29 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法
CN103000692A (zh) * 2011-09-14 2013-03-27 鸿富锦精密工业（深圳）有限公司 薄膜晶体管结构及其制造方法
CN105448938A (zh) * 2016-01-28 2016-03-30 深圳市华星光电技术有限公司 薄膜晶体管基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001324725A (ja) * 2000-05-12 2001-11-22 Hitachi Ltd 液晶表示装置およびその製造方法
TWI413260B (zh) * 2008-07-31 2013-10-21 Semiconductor Energy Lab 半導體裝置及其製造方法
CN102881598B (zh) * 2012-09-17 2015-08-12 京东方科技集团股份有限公司 薄膜晶体管的制造方法、阵列基板的制造方法及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110183463A1 (en) * 2007-04-18 2011-07-28 Samsung Electronics Co., Ltd. Thin film transitor substrate and method of manufacturing the same
CN102646634A (zh) * 2011-04-29 2012-08-22 京东方科技集团股份有限公司 Tft-lcd阵列基板制造方法
CN103000692A (zh) * 2011-09-14 2013-03-27 鸿富锦精密工业（深圳）有限公司 薄膜晶体管结构及其制造方法
CN102646715A (zh) * 2011-12-29 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法
CN105448938A (zh) * 2016-01-28 2016-03-30 深圳市华星光电技术有限公司 薄膜晶体管基板及其制造方法

Also Published As

Publication number Publication date
US20180069022A1 (en) 2018-03-08
CN105448938B (zh) 2019-06-25
CN105448938A (zh) 2016-03-30

Similar Documents

Publication Publication Date Title
WO2017128555A1 (zh) 薄膜晶体管基板及其制造方法
US10205027B2 (en) Coplanar double gate electrode oxide thin film transistor and manufacture method thereof
US9355838B2 (en) Oxide TFT and manufacturing method thereof
JP6092260B2 (ja) アレイ基板の製造方法及びアレイ基板、ディスプレー
US9741751B2 (en) Array substrate fabricating method
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
WO2016029541A1 (zh) 薄膜晶体管及其的制备方法、阵列基板和显示装置
US11054707B2 (en) Method of manufacturing via hole, method of manufacturing array substrate, and array substrate
US9704998B2 (en) Thin film transistor and method of manufacturing the same, display substrate, and display apparatus
WO2021138931A1 (zh) 阵列基板及其制备方法、显示面板
US20180114854A1 (en) Metal oxide thin film transistor and method of preparing the same
US20150295094A1 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
JP2015501549A (ja) 薄膜トランジスターアレイ基板
WO2020232964A1 (zh) 一种薄膜晶体管基板的制备方法
WO2016090807A1 (zh) 阵列基板及其制作方法、显示装置
WO2017128554A1 (zh) Tft阵列基板及其制造方法
WO2013181905A1 (zh) 晶体管、阵列基板及其制造方法、液晶面板和显示装置
WO2019095408A1 (zh) 阵列基板及其制作方法、显示面板
WO2016201610A1 (zh) 金属氧化物薄膜晶体管及制备方法、显示面板和显示器
US10249654B1 (en) Manufacturing method of top-gate TFT and top-gate TFT
WO2017024718A1 (zh) 薄膜晶体管的制作方法和阵列基板的制作方法
WO2019015004A1 (zh) 一种阵列基板、显示装置及其制作方法
US10510899B2 (en) Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel
US10411132B2 (en) Thin film transistor and method for manufacturing the same
WO2014153853A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15113822

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16887437

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16887437

Country of ref document: EP

Kind code of ref document: A1