CN105448938B - 薄膜晶体管基板及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010409 thin film Substances 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- -1 Nitrogen ion Chemical class 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 126
- 229910044991 metal oxide Inorganic materials 0.000 description 7
- 150000004706 metal oxides Chemical class 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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Abstract
本发明提供一种薄膜晶体管基板及其制造方法。该方法包括：在基底上形成栅电极；在基底上形成栅极绝缘层以覆盖栅电极；在栅极绝缘层上形成半导体层；对半导体层进行等离子化，以形成具有预定厚度的欧姆接触层；在栅极绝缘层上形成金属层以覆盖欧姆接触层；对金属层和欧姆接触层进行图案化，以形成源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域；在源电极、漏电极和暴露的半导体层上形成钝化层；在钝化层中形成用于暴露漏电极的接触孔；在钝化层上形成像素电极，像素电极通过接触孔连接到漏电极。根据本发明的制造薄膜晶体管基板的方法，不需要在半导体层与源电极和漏电极之间增设蚀刻阻挡层，因此降低了生产成本，简化了制造工艺。
Description
技术领域
本发明属于晶圆制造和平板显示技术领域。具体地讲，涉及一种薄膜晶体管(TFT)基板及其制造方法。
背景技术
通常，薄膜晶体管(TFT)中的半导体层由金属氧化物薄膜构成，而金属氧化物薄膜对酸非常敏感，即便是弱酸也能够快速地腐蚀氧化物半导体层，从而在氧化物半导体层上刻蚀金属源电极和漏电极时很容易破坏氧化物半导体层本身。
此外，由于氧化物半导体层较薄(通常在30nm至50nm之间)，即使采用浓度在500:1稀释的氢氟酸(HF)中，只需几秒钟就能够刻蚀氧化物半导体层。在现有技术中，通常会在氧化物半导体层与源电极和漏极之间增设一层蚀刻阻挡层(ESL)来保护底部的氧化物半导体层免受用来形成源电极和漏电极的蚀刻液的影响，但是额外制作一层蚀刻阻挡层需要额外增加一道光刻制程，一道光刻制程包括成膜、曝光、显影、蚀刻、剥离等工序，因而会大大增加了生产成本，降低了生产良率。
发明内容
为了解决上述现有技术的不足，本发明提供一种不需要额外增加蚀刻阻挡层的薄膜晶体管基板及其制造方法。
根据本发明的一方面，提供一种制造薄膜晶体管基板的方法，所述方法包括：在基底上形成栅电极；在基底上形成栅极绝缘层以覆盖栅电极；在栅极绝缘层上形成半导体层；对半导体层进行等离子化，以形成具有预定厚度的欧姆接触层；在栅极绝缘层上形成金属层以覆盖欧姆接触层；对金属层和欧姆接触层进行图案化，以形成源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域；在源电极、漏电极和暴露的半导体层上形成钝化层；在钝化层中形成用于暴露漏电极的接触孔；在钝化层上形成像素电极，像素电极通过接触孔连接到漏电极。
根据本发明的示例性实施例，对半导体层进行等离子化的步骤可以包括：在250℃至500℃的条件下对半导体层进行活化；利用氩/氮离子对半导体层的表面进行等离子化处理，以形成具有预定厚度的欧姆接触层。
根据本发明的示例性实施例，对金属层和欧姆接触层进行图案化的步骤可以包括：采用干蚀刻法对金属层的一部分进行蚀刻，之后利用含有H2O2的蚀刻液对剩余的金属层和欧姆接触层进行蚀刻，从而得到源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域。
根据本发明的示例性实施例，金属层可以包括Mo和Al中的至少一种。
根据本发明的示例性实施例，栅电极可以包括Mo和Al中的至少一种。
根据本发明的示例性实施例，栅极绝缘层可以包括氧化硅层或氧化硅层与氮化硅层的复合层。
根据本发明的示例性实施例，钝化层可以包括氧化硅层，或者以从下到上的顺序堆叠的氧化硅层和氮化硅层的复合层。
根据本发明的示例性实施例，像素电极可以包括ITO。
根据本发明的示例性实施例，半导体层可以包括氧化铟镓锌。
根据本发明的另一方面，提供一种薄膜晶体管基板，所述薄膜晶体管基板包括：栅电极，形成在基底上；栅极绝缘层，形成在基底上以覆盖栅电极；半导体层，形成在栅极绝缘层上；源电极和漏电极，形成在半导体层的两侧上；欧姆接触层，形成在源电极与半导体层之间以及漏电极与半导体层之间；钝化层，形成在半导体层、源电极和漏电极上；像素电极，形成在钝化层上并连接到漏电极。
根据本发明的制造薄膜晶体管基板的方法，不需要在半导体层与源电极和漏电极之间增设蚀刻阻挡层，因此降低了生产成本，简化了制造工艺。此外，根据本发明的方法，能够避免金属刻蚀液对金属氧化物的刻蚀。此外，根据本发明的方法，能够在半导体层与源电极和漏电极之间形成良好的欧姆接触。
附图说明
图1至图6示出了根据本发明的示例性实施例的制造薄膜晶体管基板的流程示意图。
具体实施方式
下面将参照附图详细地描述本发明的示例性实施例。
以下将结合附图来详细描述本发明的示例性实施例，然而，附图只是示意性地示出了本发明的具体示例，且不具有限制作用。然而，本领域技术人员应理解的是，在不脱离本发明的权利要求所限定的保护范围的情况下，可以对其进行各种修改和变形。
在下文中，将通过参照附图解释本发明的示例性实施例来详细描述本发明。
图1至图6示出了根据本发明的示例性实施例的制造薄膜晶体管基板的流程示意图。
如图1中所示，在基底100上形成栅电极110。基底100可以由含有SiO2作为主要成分的透明玻璃材料形成，但是不限于此。
通常，通过物理气相沉积(PVD)法在基底100上形成栅电极110。具体地讲，采用PVD法在基底100上沉积金属氧化物，之后执行黄光工艺和刻蚀工艺来形成具有预定图案的栅电极110。
栅电极110可以包括Al和Mo中的至少一种，然而，本发明并不限于此，也可以包括其它适合的金属材料。在本发明的一个示例性实施例中，栅电极110的厚度可以为2000埃至5500埃。
接着，如图2中所示，在基底100上形成栅极绝缘层120以覆盖栅电极110。具体地讲，通过等离子增强化学气相沉积法在基底100上沉积金属层，接着执行黄光工艺和刻蚀工艺来得到栅极绝缘层120。在本发明的示例性实施例中，栅极绝缘层120可以形成为氧化硅(SiOx)的单层或者氧化硅(SiOx)和氮化硅(SiNx)的复合层。此外，在本发明的非限制性实施例中，栅极绝缘层120的厚度可以为1500埃至4000埃，然而，本发明不限于此。
然后，如图3中所示，在栅极绝缘层120上形成半导体层130和欧姆接触层140。具体地讲，首先在栅极绝缘层120上沉积金属氧化物，然后执行黄光工艺和刻蚀工艺来得到具有预定图案的半导体层130，之后在空气或氧化的环境下，在250℃～500℃的温度下对半导体层130的表面进行活化，接着通过干蚀刻法(Dry Etch)或CVD机台使用氩(Ar)/氮(N2)离子对半导体层130的表面进行等离子化(Plasma)处理，从而将半导体层130的一部分转化为具有预定厚度的欧姆接触层140。
在本发明的示例性实施例中，半导体层130可以包括氧化铟镓锌(IGZO)，然而，本发明不限于此，可以选用任何适合的金属氧化物。在本发明的一个示例性实施例中，半导体层110的厚度可以为400埃至1500埃；欧姆接触层的厚度可以为10埃至300埃。
接着，如图4中所示，在栅极绝缘层120上形成金属层以覆盖欧姆接触层140，接着对金属层进行图案化，来形成源电极S和漏电极D并且暴露半导体层130的在源电极S和漏电极D之间的区域。具体地讲，首先，在栅极绝缘层120上沉积金属层，然后对金属层的一部分进行干蚀刻(Dry Etch)，之后利用含有H2O2的蚀刻液对金属层的剩余部分和欧姆接触层进行蚀刻，以形成源电极S和漏电极D并且暴露半导体层130的在源电极S和漏电极D之间的区域。
在本发明中，采用终点监控(EPD)模式控制干蚀刻的程度，以提高制作精度。在本发明的示例性实施例中，金属层包括Al和Mo中的至少一种。在本发明中，金属层优选地包括Al和Mo，并且Mo接触欧姆接触层。
在本发明中，通过氩/氮离子对半导体层的表面进行等离子化处理，氩/氮离子在能量的作用下轰击半导体层的表面的氧导致半导体层中的铟的含量增加，使得半导体层的表面的电阻降低，得到相对的欧姆接触层，之后利用干蚀刻对形成在欧姆接触层上的金属层进行蚀刻，再利用含有过氧化氢的蚀刻液对剩余的金属层以及欧姆接触层进行蚀刻，从而得到源电极和漏电极以及缺陷较少的有源层。
然后，参照图5，在源电极S、漏电极D和暴露的半导体层上形成钝化层150，并且在钝化层150中形成接触孔H。具体地讲，通过等离子增强化学气相沉积法在源电极S、漏电极D和暴露的半导体层上形成钝化层150，之后执行黄光工艺和刻蚀工艺在钝化层150中形成接触孔H。在本发明的示例性实施例中，钝化层包括氧化硅层或者包括氮化硅层和氧化硅层的复合层，并且在包括氮化硅层和氧化硅层的复合层时，氧化硅层与半导体层130接触。在本发明的非限制性实施例中，钝化层的厚度可以为1500埃至4000埃，然而本发明不限于此。
然后，参照图6，在钝化层150上形成像素电极160，并且像素电极160通过接触孔H连接到漏电极D。在本发明中，可以通过PVD法沉积ITO，然后执行黄光工艺和刻蚀工艺来形成像素电极160。在本发明中，像素电极不限于ITO，也可以是其它透明导体。在本发明的示例性实施例中，像素电极160的厚度可以为300埃至1000埃，然而，本发明不限于此。
根据本发明的制造薄膜晶体管基板的方法，不需要在半导体层与源电极和漏电极之间增设蚀刻阻挡层，因此降低了生产成本，简化了制造工艺。
此外，根据本发明的方法，能够避免金属刻蚀液对金属氧化物的刻蚀。
此外，根据本发明的方法，能够在半导体层与源电极和漏电极之间形成良好的欧姆接触。
以上描述了根据本发明的示例性实施例的制造薄膜晶体管的方法，但本发明的保护范围并不限制于上述特定实施例。
Claims (7)
1.一种制造薄膜晶体管基板的方法，其特征在于，所述方法包括如下步骤：
在基底上形成栅电极；
在基底上形成栅极绝缘层以覆盖栅电极；
在栅极绝缘层上形成半导体层；
对半导体层进行等离子化，以形成具有预定厚度的欧姆接触层；
在栅极绝缘层上形成金属层以覆盖欧姆接触层；
对金属层和欧姆接触层进行图案化，以形成源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域；
在源电极、漏电极和暴露的半导体层上形成钝化层；
在钝化层中形成用于暴露漏电极的接触孔；
在钝化层上形成像素电极，像素电极通过接触孔连接到漏电极；
其中，对金属层和欧姆接触层进行图案化的步骤包括：采用干蚀刻法对金属层的一部分进行蚀刻，之后利用含有H2O2的蚀刻液对剩余的金属层和欧姆接触层进行蚀刻，从而得到源电极和漏电极并且暴露半导体层的在源电极和漏电极之间的区域，对半导体层进行等离子化的步骤包括：
在空气或氧化的环境下，在250℃至500℃的条件下对半导体层进行活化；
利用氩/氮离子对半导体层的表面进行等离子化处理，以形成具有预定厚度的欧姆接触层。
2.根据权利要求1所述的方法，其特征在于，金属层包括Mo和Al中的至少一种。
3.根据权利要求1所述的方法，其特征在于，栅电极包括Mo和Al中的至少一种。
4.根据权利要求1所述的方法，其特征在于，栅极绝缘层包括氧化硅层或氧化硅层与氮化硅层的复合层。
5.根据权利要求1所述的方法，其特征在于，钝化层包括氧化硅层，或者以从下到上的顺序堆叠的氧化硅层和氮化硅层的复合层。
6.根据权利要求1所述的方法，其特征在于，像素电极包括ITO。
7.根据权利要求1所述的方法，其特征在于，半导体层包括氧化铟镓锌。
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